488 changes: 427 additions & 61 deletions llvm/test/CodeGen/AArch64/combine-comparisons-by-cse.ll
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140 changes: 103 additions & 37 deletions llvm/test/CodeGen/AArch64/cond-br-tuning.ll
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Original file line number Diff line number Diff line change
@@ -1,14 +1,23 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -debugify-and-strip-all-safe < %s -O3 -mtriple=aarch64-eabi -verify-machineinstrs | FileCheck %s

target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-linaro-linux-gnueabi"

; CMN is an alias of ADDS.
; CHECK-LABEL: test_add_cbz:
; CHECK: cmn w0, w1
; CHECK: b.eq
; CHECK: ret

define void @test_add_cbz(i32 %a, i32 %b, i32* %ptr) {
; CHECK-LABEL: test_add_cbz:
; CHECK: // %bb.0:
; CHECK-NEXT: cmn w0, w1
; CHECK-NEXT: b.eq .LBB0_2
; CHECK-NEXT: // %bb.1: // %L1
; CHECK-NEXT: str wzr, [x2]
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB0_2: // %L2
; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: str w8, [x2]
; CHECK-NEXT: ret
%c = add nsw i32 %a, %b
%d = icmp ne i32 %c, 0
br i1 %d, label %L1, label %L2
Expand All @@ -20,11 +29,17 @@ L2:
ret void
}

; CHECK-LABEL: test_add_cbz_multiple_use:
; CHECK: adds
; CHECK: b.eq
; CHECK: ret
define void @test_add_cbz_multiple_use(i32 %a, i32 %b, i32* %ptr) {
; CHECK-LABEL: test_add_cbz_multiple_use:
; CHECK: // %bb.0:
; CHECK-NEXT: adds w8, w0, w1
; CHECK-NEXT: b.eq .LBB1_2
; CHECK-NEXT: // %bb.1: // %L1
; CHECK-NEXT: str wzr, [x2]
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB1_2: // %L2
; CHECK-NEXT: str w8, [x2]
; CHECK-NEXT: ret
%c = add nsw i32 %a, %b
%d = icmp ne i32 %c, 0
br i1 %d, label %L1, label %L2
Expand All @@ -36,10 +51,18 @@ L2:
ret void
}

; CHECK-LABEL: test_add_cbz_64:
; CHECK: cmn x0, x1
; CHECK: b.eq
define void @test_add_cbz_64(i64 %a, i64 %b, i64* %ptr) {
; CHECK-LABEL: test_add_cbz_64:
; CHECK: // %bb.0:
; CHECK-NEXT: cmn x0, x1
; CHECK-NEXT: b.eq .LBB2_2
; CHECK-NEXT: // %bb.1: // %L1
; CHECK-NEXT: str xzr, [x2]
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB2_2: // %L2
; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: str x8, [x2]
; CHECK-NEXT: ret
%c = add nsw i64 %a, %b
%d = icmp ne i64 %c, 0
br i1 %d, label %L1, label %L2
Expand All @@ -51,10 +74,18 @@ L2:
ret void
}

; CHECK-LABEL: test_and_cbz:
; CHECK: tst w0, #0x6
; CHECK: b.eq
define void @test_and_cbz(i32 %a, i32* %ptr) {
; CHECK-LABEL: test_and_cbz:
; CHECK: // %bb.0:
; CHECK-NEXT: tst w0, #0x6
; CHECK-NEXT: b.eq .LBB3_2
; CHECK-NEXT: // %bb.1: // %L1
; CHECK-NEXT: str wzr, [x1]
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB3_2: // %L2
; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: str w8, [x1]
; CHECK-NEXT: ret
%c = and i32 %a, 6
%d = icmp ne i32 %c, 0
br i1 %d, label %L1, label %L2
Expand All @@ -66,10 +97,18 @@ L2:
ret void
}

; CHECK-LABEL: test_bic_cbnz:
; CHECK: bics wzr, w1, w0
; CHECK: b.ne
define void @test_bic_cbnz(i32 %a, i32 %b, i32* %ptr) {
; CHECK-LABEL: test_bic_cbnz:
; CHECK: // %bb.0:
; CHECK-NEXT: bics wzr, w1, w0
; CHECK-NEXT: b.ne .LBB4_2
; CHECK-NEXT: // %bb.1: // %L1
; CHECK-NEXT: str wzr, [x2]
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB4_2: // %L2
; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: str w8, [x2]
; CHECK-NEXT: ret
%c = and i32 %a, %b
%d = icmp eq i32 %c, %b
br i1 %d, label %L1, label %L2
Expand All @@ -81,11 +120,15 @@ L2:
ret void
}

; CHECK-LABEL: test_add_tbz:
; CHECK: adds
; CHECK: b.pl
; CHECK: ret
define void @test_add_tbz(i32 %a, i32 %b, i32* %ptr) {
; CHECK-LABEL: test_add_tbz:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adds w8, w0, w1
; CHECK-NEXT: b.pl .LBB5_2
; CHECK-NEXT: // %bb.1: // %L1
; CHECK-NEXT: str w8, [x2]
; CHECK-NEXT: .LBB5_2: // %L2
; CHECK-NEXT: ret
entry:
%add = add nsw i32 %a, %b
%cmp36 = icmp sge i32 %add, 0
Expand All @@ -97,11 +140,15 @@ L2:
ret void
}

; CHECK-LABEL: test_subs_tbz:
; CHECK: subs
; CHECK: b.pl
; CHECK: ret
define void @test_subs_tbz(i32 %a, i32 %b, i32* %ptr) {
; CHECK-LABEL: test_subs_tbz:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: subs w8, w0, w1
; CHECK-NEXT: b.pl .LBB6_2
; CHECK-NEXT: // %bb.1: // %L1
; CHECK-NEXT: str w8, [x2]
; CHECK-NEXT: .LBB6_2: // %L2
; CHECK-NEXT: ret
entry:
%sub = sub nsw i32 %a, %b
%cmp36 = icmp sge i32 %sub, 0
Expand All @@ -113,11 +160,15 @@ L2:
ret void
}

; CHECK-LABEL: test_add_tbnz
; CHECK: adds
; CHECK: b.mi
; CHECK: ret
define void @test_add_tbnz(i32 %a, i32 %b, i32* %ptr) {
; CHECK-LABEL: test_add_tbnz:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adds w8, w0, w1
; CHECK-NEXT: b.mi .LBB7_2
; CHECK-NEXT: // %bb.1: // %L1
; CHECK-NEXT: str w8, [x2]
; CHECK-NEXT: .LBB7_2: // %L2
; CHECK-NEXT: ret
entry:
%add = add nsw i32 %a, %b
%cmp36 = icmp slt i32 %add, 0
Expand All @@ -129,11 +180,15 @@ L2:
ret void
}

; CHECK-LABEL: test_subs_tbnz
; CHECK: subs
; CHECK: b.mi
; CHECK: ret
define void @test_subs_tbnz(i32 %a, i32 %b, i32* %ptr) {
; CHECK-LABEL: test_subs_tbnz:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: subs w8, w0, w1
; CHECK-NEXT: b.mi .LBB8_2
; CHECK-NEXT: // %bb.1: // %L1
; CHECK-NEXT: str w8, [x2]
; CHECK-NEXT: .LBB8_2: // %L2
; CHECK-NEXT: ret
entry:
%sub = sub nsw i32 %a, %b
%cmp36 = icmp slt i32 %sub, 0
Expand All @@ -149,11 +204,22 @@ declare void @foo()
declare void @bar(i32)

; Don't transform since the call will clobber the NZCV bits.
; CHECK-LABEL: test_call_clobber:
; CHECK: and w[[DST:[0-9]+]], w1, #0x6
; CHECK: bl bar
; CHECK: cbnz w[[DST]]
define void @test_call_clobber(i32 %unused, i32 %a) {
; CHECK-LABEL: test_call_clobber:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: and w19, w1, #0x6
; CHECK-NEXT: mov w0, w19
; CHECK-NEXT: bl bar
; CHECK-NEXT: cbnz w19, .LBB9_2
; CHECK-NEXT: // %bb.1: // %if.end
; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB9_2: // %if.then
; CHECK-NEXT: bl foo
entry:
%c = and i32 %a, 6
call void @bar(i32 %c)
Expand Down
129 changes: 103 additions & 26 deletions llvm/test/CodeGen/AArch64/fast-isel-branch-cond-split.ll
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Original file line number Diff line number Diff line change
@@ -1,9 +1,23 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s

; CHECK-LABEL: test_or
; CHECK: cbnz w0, {{LBB[0-9]+_2}}
; CHECK: cbz w1, {{LBB[0-9]+_1}}
define i64 @test_or(i32 %a, i32 %b) {
; CHECK-LABEL: test_or:
; CHECK: ; %bb.0: ; %bb1
; CHECK-NEXT: cbnz w0, LBB0_2
; CHECK-NEXT: LBB0_1: ; %bb3
; CHECK-NEXT: mov x0, xzr
; CHECK-NEXT: ret
; CHECK-NEXT: LBB0_2: ; %bb1.cond.split
; CHECK-NEXT: cbz w1, LBB0_1
; CHECK-NEXT: ; %bb.3: ; %bb4
; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w30, -8
; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: bl _bar
; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
; CHECK-NEXT: ret
bb1:
%0 = icmp eq i32 %a, 0
%1 = icmp eq i32 %b, 0
Expand All @@ -18,10 +32,23 @@ bb4:
ret i64 %2
}

; CHECK-LABEL: test_or_select
; CHECK: cbnz w0, {{LBB[0-9]+_2}}
; CHECK: cbz w1, {{LBB[0-9]+_1}}
define i64 @test_or_select(i32 %a, i32 %b) {
; CHECK-LABEL: test_or_select:
; CHECK: ; %bb.0: ; %bb1
; CHECK-NEXT: cbnz w0, LBB1_2
; CHECK-NEXT: LBB1_1: ; %bb3
; CHECK-NEXT: mov x0, xzr
; CHECK-NEXT: ret
; CHECK-NEXT: LBB1_2: ; %bb1.cond.split
; CHECK-NEXT: cbz w1, LBB1_1
; CHECK-NEXT: ; %bb.3: ; %bb4
; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w30, -8
; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: bl _bar
; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
; CHECK-NEXT: ret
bb1:
%0 = icmp eq i32 %a, 0
%1 = icmp eq i32 %b, 0
Expand All @@ -36,10 +63,23 @@ bb4:
ret i64 %2
}

; CHECK-LABEL: test_and
; CHECK: cbnz w0, {{LBB[0-9]+_2}}
; CHECK: cbz w1, {{LBB[0-9]+_1}}
define i64 @test_and(i32 %a, i32 %b) {
; CHECK-LABEL: test_and:
; CHECK: ; %bb.0: ; %bb1
; CHECK-NEXT: cbnz w0, LBB2_2
; CHECK-NEXT: LBB2_1: ; %bb3
; CHECK-NEXT: mov x0, xzr
; CHECK-NEXT: ret
; CHECK-NEXT: LBB2_2: ; %bb1.cond.split
; CHECK-NEXT: cbz w1, LBB2_1
; CHECK-NEXT: ; %bb.3: ; %bb4
; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w30, -8
; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: bl _bar
; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
; CHECK-NEXT: ret
bb1:
%0 = icmp ne i32 %a, 0
%1 = icmp ne i32 %b, 0
Expand All @@ -54,10 +94,23 @@ bb4:
ret i64 %2
}

; CHECK-LABEL: test_and_select
; CHECK: cbnz w0, {{LBB[0-9]+_2}}
; CHECK: cbz w1, {{LBB[0-9]+_1}}
define i64 @test_and_select(i32 %a, i32 %b) {
; CHECK-LABEL: test_and_select:
; CHECK: ; %bb.0: ; %bb1
; CHECK-NEXT: cbnz w0, LBB3_2
; CHECK-NEXT: LBB3_1: ; %bb3
; CHECK-NEXT: mov x0, xzr
; CHECK-NEXT: ret
; CHECK-NEXT: LBB3_2: ; %bb1.cond.split
; CHECK-NEXT: cbz w1, LBB3_1
; CHECK-NEXT: ; %bb.3: ; %bb4
; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w30, -8
; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: bl _bar
; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
; CHECK-NEXT: ret
bb1:
%0 = icmp ne i32 %a, 0
%1 = icmp ne i32 %b, 0
Expand All @@ -74,14 +127,26 @@ bb4:

; If the branch is unpredictable, don't add another branch.

; CHECK-LABEL: test_or_unpredictable
; CHECK: cmp w0, #0
; CHECK-NEXT: cset w8, eq
; CHECK-NEXT: cmp w1, #0
; CHECK-NEXT: cset w9, eq
; CHECK-NEXT: orr w8, w8, w9
; CHECK-NEXT: tbnz w8, #0,
define i64 @test_or_unpredictable(i32 %a, i32 %b) {
; CHECK-LABEL: test_or_unpredictable:
; CHECK: ; %bb.0: ; %bb1
; CHECK-NEXT: cmp w0, #0 ; =0
; CHECK-NEXT: cset w8, eq
; CHECK-NEXT: cmp w1, #0 ; =0
; CHECK-NEXT: cset w9, eq
; CHECK-NEXT: orr w8, w8, w9
; CHECK-NEXT: tbnz w8, #0, LBB4_2
; CHECK-NEXT: ; %bb.1: ; %bb4
; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w30, -8
; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: bl _bar
; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
; CHECK-NEXT: ret
; CHECK-NEXT: LBB4_2: ; %bb3
; CHECK-NEXT: mov x0, xzr
; CHECK-NEXT: ret
bb1:
%0 = icmp eq i32 %a, 0
%1 = icmp eq i32 %b, 0
Expand All @@ -96,14 +161,26 @@ bb4:
ret i64 %2
}

; CHECK-LABEL: test_and_unpredictable
; CHECK: cmp w0, #0
; CHECK-NEXT: cset w8, ne
; CHECK-NEXT: cmp w1, #0
; CHECK-NEXT: cset w9, ne
; CHECK-NEXT: and w8, w8, w9
; CHECK-NEXT: tbz w8, #0,
define i64 @test_and_unpredictable(i32 %a, i32 %b) {
; CHECK-LABEL: test_and_unpredictable:
; CHECK: ; %bb.0: ; %bb1
; CHECK-NEXT: cmp w0, #0 ; =0
; CHECK-NEXT: cset w8, ne
; CHECK-NEXT: cmp w1, #0 ; =0
; CHECK-NEXT: cset w9, ne
; CHECK-NEXT: and w8, w8, w9
; CHECK-NEXT: tbz w8, #0, LBB5_2
; CHECK-NEXT: ; %bb.1: ; %bb4
; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w30, -8
; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: bl _bar
; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
; CHECK-NEXT: ret
; CHECK-NEXT: LBB5_2: ; %bb3
; CHECK-NEXT: mov x0, xzr
; CHECK-NEXT: ret
bb1:
%0 = icmp ne i32 %a, 0
%1 = icmp ne i32 %b, 0
Expand Down
158 changes: 116 additions & 42 deletions llvm/test/CodeGen/AArch64/logical_shifted_reg.ll
View file
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s

@var1_32 = global i32 0
Expand All @@ -8,77 +9,109 @@

define void @logical_32bit() minsize {
; CHECK-LABEL: logical_32bit:
; CHECK: // %bb.0:
; CHECK-NEXT: str x19, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w19, -16
; CHECK-NEXT: adrp x8, :got:var1_32
; CHECK-NEXT: adrp x9, :got:var2_32
; CHECK-NEXT: ldr x8, [x8, :got_lo12:var1_32]
; CHECK-NEXT: ldr x9, [x9, :got_lo12:var2_32]
; CHECK-NEXT: ldr w10, [x8]
; CHECK-NEXT: ldr w9, [x9]
; CHECK-NEXT: and w11, w10, w9
; CHECK-NEXT: bic w12, w10, w9
; CHECK-NEXT: orr w13, w10, w9
; CHECK-NEXT: orn w14, w10, w9
; CHECK-NEXT: eor w15, w10, w9
; CHECK-NEXT: eon w16, w9, w10
; CHECK-NEXT: and w17, w10, w9, lsl #31
; CHECK-NEXT: bic w18, w10, w9, lsl #31
; CHECK-NEXT: orr w0, w10, w9, lsl #31
; CHECK-NEXT: orn w1, w10, w9, lsl #31
; CHECK-NEXT: eor w2, w10, w9, lsl #31
; CHECK-NEXT: eon w3, w10, w9, lsl #31
; CHECK-NEXT: bic w4, w10, w9, asr #10
; CHECK-NEXT: eor w5, w10, w9, asr #10
; CHECK-NEXT: orn w6, w10, w9, lsr #1
; CHECK-NEXT: eor w7, w10, w9, lsr #1
; CHECK-NEXT: eon w19, w10, w9, ror #20
; CHECK-NEXT: and w9, w10, w9, ror #20
; CHECK-NEXT: str w11, [x8]
; CHECK-NEXT: str w12, [x8]
; CHECK-NEXT: str w13, [x8]
; CHECK-NEXT: str w14, [x8]
; CHECK-NEXT: str w15, [x8]
; CHECK-NEXT: str w16, [x8]
; CHECK-NEXT: str w17, [x8]
; CHECK-NEXT: str w18, [x8]
; CHECK-NEXT: str w0, [x8]
; CHECK-NEXT: str w1, [x8]
; CHECK-NEXT: str w2, [x8]
; CHECK-NEXT: str w3, [x8]
; CHECK-NEXT: str w4, [x8]
; CHECK-NEXT: str w5, [x8]
; CHECK-NEXT: str w6, [x8]
; CHECK-NEXT: str w7, [x8]
; CHECK-NEXT: str w19, [x8]
; CHECK-NEXT: str w9, [x8]
; CHECK-NEXT: ldr x19, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
%val1 = load i32, i32* @var1_32
%val2 = load i32, i32* @var2_32

; First check basic and/bic/or/orn/eor/eon patterns with no shift
%neg_val2 = xor i32 -1, %val2

%and_noshift = and i32 %val1, %val2
; CHECK: and {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
store volatile i32 %and_noshift, i32* @var1_32
%bic_noshift = and i32 %neg_val2, %val1
; CHECK: bic {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
store volatile i32 %bic_noshift, i32* @var1_32

%or_noshift = or i32 %val1, %val2
; CHECK: orr {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
store volatile i32 %or_noshift, i32* @var1_32
%orn_noshift = or i32 %neg_val2, %val1
; CHECK: orn {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
store volatile i32 %orn_noshift, i32* @var1_32

%xor_noshift = xor i32 %val1, %val2
; CHECK: eor {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
store volatile i32 %xor_noshift, i32* @var1_32
%xorn_noshift = xor i32 %neg_val2, %val1
; CHECK: eon {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
store volatile i32 %xorn_noshift, i32* @var1_32

; Check the maximum shift on each
%operand_lsl31 = shl i32 %val2, 31
%neg_operand_lsl31 = xor i32 -1, %operand_lsl31

%and_lsl31 = and i32 %val1, %operand_lsl31
; CHECK: and {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #31
store volatile i32 %and_lsl31, i32* @var1_32
%bic_lsl31 = and i32 %val1, %neg_operand_lsl31
; CHECK: bic {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #31
store volatile i32 %bic_lsl31, i32* @var1_32

%or_lsl31 = or i32 %val1, %operand_lsl31
; CHECK: orr {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #31
store volatile i32 %or_lsl31, i32* @var1_32
%orn_lsl31 = or i32 %val1, %neg_operand_lsl31
; CHECK: orn {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #31
store volatile i32 %orn_lsl31, i32* @var1_32

%xor_lsl31 = xor i32 %val1, %operand_lsl31
; CHECK: eor {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #31
store volatile i32 %xor_lsl31, i32* @var1_32
%xorn_lsl31 = xor i32 %val1, %neg_operand_lsl31
; CHECK: eon {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #31
store volatile i32 %xorn_lsl31, i32* @var1_32

; Check other shifts on a subset
%operand_asr10 = ashr i32 %val2, 10
%neg_operand_asr10 = xor i32 -1, %operand_asr10

%bic_asr10 = and i32 %val1, %neg_operand_asr10
; CHECK: bic {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, asr #10
store volatile i32 %bic_asr10, i32* @var1_32
%xor_asr10 = xor i32 %val1, %operand_asr10
; CHECK: eor {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, asr #10
store volatile i32 %xor_asr10, i32* @var1_32

%operand_lsr1 = lshr i32 %val2, 1
%neg_operand_lsr1 = xor i32 -1, %operand_lsr1

%orn_lsr1 = or i32 %val1, %neg_operand_lsr1
; CHECK: orn {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsr #1
store volatile i32 %orn_lsr1, i32* @var1_32
%xor_lsr1 = xor i32 %val1, %operand_lsr1
; CHECK: eor {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsr #1
store volatile i32 %xor_lsr1, i32* @var1_32

%operand_ror20_big = shl i32 %val2, 12
Expand All @@ -87,88 +120,118 @@ define void @logical_32bit() minsize {
%neg_operand_ror20 = xor i32 -1, %operand_ror20

%xorn_ror20 = xor i32 %val1, %neg_operand_ror20
; CHECK: eon {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, ror #20
store volatile i32 %xorn_ror20, i32* @var1_32
%and_ror20 = and i32 %val1, %operand_ror20
; CHECK: and {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, ror #20
store volatile i32 %and_ror20, i32* @var1_32

ret void
}

define void @logical_64bit() minsize {
; CHECK-LABEL: logical_64bit:
; CHECK: // %bb.0:
; CHECK-NEXT: str x19, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w19, -16
; CHECK-NEXT: adrp x8, :got:var1_64
; CHECK-NEXT: adrp x9, :got:var2_64
; CHECK-NEXT: ldr x8, [x8, :got_lo12:var1_64]
; CHECK-NEXT: ldr x9, [x9, :got_lo12:var2_64]
; CHECK-NEXT: ldr x10, [x8]
; CHECK-NEXT: ldr x9, [x9]
; CHECK-NEXT: and x11, x10, x9
; CHECK-NEXT: bic x12, x10, x9
; CHECK-NEXT: orr x13, x10, x9
; CHECK-NEXT: orn x14, x10, x9
; CHECK-NEXT: eor x15, x10, x9
; CHECK-NEXT: eon x16, x9, x10
; CHECK-NEXT: and x17, x10, x9, lsl #63
; CHECK-NEXT: bic x18, x10, x9, lsl #63
; CHECK-NEXT: orr x0, x10, x9, lsl #63
; CHECK-NEXT: orn x1, x10, x9, lsl #63
; CHECK-NEXT: eor x2, x10, x9, lsl #63
; CHECK-NEXT: eon x3, x10, x9, lsl #63
; CHECK-NEXT: bic x4, x10, x9, asr #10
; CHECK-NEXT: eor x5, x10, x9, asr #10
; CHECK-NEXT: orn x6, x10, x9, lsr #1
; CHECK-NEXT: eor x7, x10, x9, lsr #1
; CHECK-NEXT: eon x19, x10, x9, ror #20
; CHECK-NEXT: and x9, x10, x9, ror #20
; CHECK-NEXT: str x11, [x8]
; CHECK-NEXT: str x12, [x8]
; CHECK-NEXT: str x13, [x8]
; CHECK-NEXT: str x14, [x8]
; CHECK-NEXT: str x15, [x8]
; CHECK-NEXT: str x16, [x8]
; CHECK-NEXT: str x17, [x8]
; CHECK-NEXT: str x18, [x8]
; CHECK-NEXT: str x0, [x8]
; CHECK-NEXT: str x1, [x8]
; CHECK-NEXT: str x2, [x8]
; CHECK-NEXT: str x3, [x8]
; CHECK-NEXT: str x4, [x8]
; CHECK-NEXT: str x5, [x8]
; CHECK-NEXT: str x6, [x8]
; CHECK-NEXT: str x7, [x8]
; CHECK-NEXT: str x19, [x8]
; CHECK-NEXT: str x9, [x8]
; CHECK-NEXT: ldr x19, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
%val1 = load i64, i64* @var1_64
%val2 = load i64, i64* @var2_64

; First check basic and/bic/or/orn/eor/eon patterns with no shift
%neg_val2 = xor i64 -1, %val2

%and_noshift = and i64 %val1, %val2
; CHECK: and {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
store volatile i64 %and_noshift, i64* @var1_64
%bic_noshift = and i64 %neg_val2, %val1
; CHECK: bic {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
store volatile i64 %bic_noshift, i64* @var1_64

%or_noshift = or i64 %val1, %val2
; CHECK: orr {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
store volatile i64 %or_noshift, i64* @var1_64
%orn_noshift = or i64 %neg_val2, %val1
; CHECK: orn {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
store volatile i64 %orn_noshift, i64* @var1_64

%xor_noshift = xor i64 %val1, %val2
; CHECK: eor {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
store volatile i64 %xor_noshift, i64* @var1_64
%xorn_noshift = xor i64 %neg_val2, %val1
; CHECK: eon {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
store volatile i64 %xorn_noshift, i64* @var1_64

; Check the maximum shift on each
%operand_lsl63 = shl i64 %val2, 63
%neg_operand_lsl63 = xor i64 -1, %operand_lsl63

%and_lsl63 = and i64 %val1, %operand_lsl63
; CHECK: and {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #63
store volatile i64 %and_lsl63, i64* @var1_64
%bic_lsl63 = and i64 %val1, %neg_operand_lsl63
; CHECK: bic {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #63
store volatile i64 %bic_lsl63, i64* @var1_64

%or_lsl63 = or i64 %val1, %operand_lsl63
; CHECK: orr {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #63
store volatile i64 %or_lsl63, i64* @var1_64
%orn_lsl63 = or i64 %val1, %neg_operand_lsl63
; CHECK: orn {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #63
store volatile i64 %orn_lsl63, i64* @var1_64

%xor_lsl63 = xor i64 %val1, %operand_lsl63
; CHECK: eor {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #63
store volatile i64 %xor_lsl63, i64* @var1_64
%xorn_lsl63 = xor i64 %val1, %neg_operand_lsl63
; CHECK: eon {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #63
store volatile i64 %xorn_lsl63, i64* @var1_64

; Check other shifts on a subset
%operand_asr10 = ashr i64 %val2, 10
%neg_operand_asr10 = xor i64 -1, %operand_asr10

%bic_asr10 = and i64 %val1, %neg_operand_asr10
; CHECK: bic {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, asr #10
store volatile i64 %bic_asr10, i64* @var1_64
%xor_asr10 = xor i64 %val1, %operand_asr10
; CHECK: eor {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, asr #10
store volatile i64 %xor_asr10, i64* @var1_64

%operand_lsr1 = lshr i64 %val2, 1
%neg_operand_lsr1 = xor i64 -1, %operand_lsr1

%orn_lsr1 = or i64 %val1, %neg_operand_lsr1
; CHECK: orn {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsr #1
store volatile i64 %orn_lsr1, i64* @var1_64
%xor_lsr1 = xor i64 %val1, %operand_lsr1
; CHECK: eor {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsr #1
store volatile i64 %xor_lsr1, i64* @var1_64

; Construct a rotate-right from a bunch of other logical
Expand All @@ -180,37 +243,48 @@ define void @logical_64bit() minsize {
%neg_operand_ror20 = xor i64 -1, %operand_ror20

%xorn_ror20 = xor i64 %val1, %neg_operand_ror20
; CHECK: eon {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, ror #20
store volatile i64 %xorn_ror20, i64* @var1_64
%and_ror20 = and i64 %val1, %operand_ror20
; CHECK: and {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, ror #20
store volatile i64 %and_ror20, i64* @var1_64

ret void
}

define void @flag_setting() {
; CHECK-LABEL: flag_setting:
; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, :got:var1_64
; CHECK-NEXT: adrp x10, :got:var2_64
; CHECK-NEXT: ldr x8, [x8, :got_lo12:var1_64]
; CHECK-NEXT: ldr x10, [x10, :got_lo12:var2_64]
; CHECK-NEXT: ldr x9, [x8]
; CHECK-NEXT: ldr x10, [x10]
; CHECK-NEXT: tst x9, x10
; CHECK-NEXT: b.gt .LBB2_4
; CHECK-NEXT: // %bb.1: // %test2
; CHECK-NEXT: tst x9, x10, lsl #63
; CHECK-NEXT: b.lt .LBB2_4
; CHECK-NEXT: // %bb.2: // %test3
; CHECK-NEXT: tst x9, x10, asr #12
; CHECK-NEXT: b.gt .LBB2_4
; CHECK-NEXT: // %bb.3: // %other_exit
; CHECK-NEXT: str x9, [x8]
; CHECK-NEXT: .LBB2_4: // %ret
; CHECK-NEXT: ret
%val1 = load i64, i64* @var1_64
%val2 = load i64, i64* @var2_64

; CHECK: tst {{x[0-9]+}}, {{x[0-9]+}}
; CHECK: b.gt .L
%simple_and = and i64 %val1, %val2
%tst1 = icmp sgt i64 %simple_and, 0
br i1 %tst1, label %ret, label %test2, !prof !1

test2:
; CHECK: tst {{x[0-9]+}}, {{x[0-9]+}}, lsl #63
; CHECK: b.lt .L
%shifted_op = shl i64 %val2, 63
%shifted_and = and i64 %val1, %shifted_op
%tst2 = icmp slt i64 %shifted_and, 0
br i1 %tst2, label %ret, label %test3, !prof !1

test3:
; CHECK: tst {{x[0-9]+}}, {{x[0-9]+}}, asr #12
; CHECK: b.gt .L
%asr_op = ashr i64 %val2, 12
%asr_and = and i64 %asr_op, %val1
%tst3 = icmp sgt i64 %asr_and, 0
Expand Down
27 changes: 23 additions & 4 deletions llvm/test/CodeGen/AArch64/optimize-cond-branch.ll
View file
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -o - %s | FileCheck %s
target triple = "arm64--"

Expand All @@ -8,11 +9,29 @@ target triple = "arm64--"
; Writing a stable/simple test is tricky since most tbz instructions are already
; formed in SelectionDAG, optimizeCondBranch() only triggers if the and
; instruction is in a different block than the conditional jump.
;
; CHECK-LABEL: func
; CHECK-NOT: and
; CHECK: tbz

define void @func() {
; CHECK-LABEL: func:
; CHECK: // %bb.0:
; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: cbnz w8, .LBB0_3
; CHECK-NEXT: // %bb.1: // %b1
; CHECK-NEXT: cbz wzr, .LBB0_4
; CHECK-NEXT: // %bb.2: // %b3
; CHECK-NEXT: ldr w8, [x8]
; CHECK-NEXT: tbz w8, #8, .LBB0_5
; CHECK-NEXT: .LBB0_3: // %b7
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: b extfunc
; CHECK-NEXT: .LBB0_4: // %b2
; CHECK-NEXT: bl extfunc
; CHECK-NEXT: cbnz w0, .LBB0_3
; CHECK-NEXT: .LBB0_5: // %b8
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
%c0 = icmp sgt i64 0, 0
br i1 %c0, label %b1, label %b6

Expand Down
10 changes: 8 additions & 2 deletions llvm/test/CodeGen/ARM/ifcvt-callback.ll
View file
Original file line number Diff line number Diff line change
@@ -1,12 +1,18 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumb-- %s -o - | FileCheck %s

; This test checks that if-conversion pass is unconditionally added to the pass
; pipeline and is conditionally executed based on the per-function targert-cpu
; attribute.

; CHECK: ite eq

define i32 @test_ifcvt(i32 %a, i32 %b) #0 {
; CHECK-LABEL: test_ifcvt:
; CHECK: @ %bb.0:
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: ite eq
; CHECK-NEXT: subeq r0, r1, #1
; CHECK-NEXT: addne r0, r1, #1
; CHECK-NEXT: bx lr
%tmp2 = icmp eq i32 %a, 0
br i1 %tmp2, label %cond_false, label %cond_true

Expand Down
16 changes: 12 additions & 4 deletions llvm/test/CodeGen/ARM/ifcvt1.ll
View file
Original file line number Diff line number Diff line change
@@ -1,21 +1,29 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s -check-prefix=A8
; RUN: llc -mtriple=arm-eabi -mcpu=swift %s -o - | FileCheck %s -check-prefix=SWIFT

define i32 @t1(i32 %a, i32 %b) {
; A8-LABEL: t1:
; A8: @ %bb.0:
; A8-NEXT: cmp r0, #0
; A8-NEXT: subeq r0, r1, #1
; A8-NEXT: addne r0, r1, #1
; A8-NEXT: bx lr
;
; SWIFT-LABEL: t1:
; SWIFT: @ %bb.0:
; SWIFT-NEXT: cmp r0, #0
; SWIFT-NEXT: sub r0, r1, #1
; SWIFT-NEXT: addne r0, r1, #1
; SWIFT-NEXT: bx lr
%tmp2 = icmp eq i32 %a, 0
br i1 %tmp2, label %cond_false, label %cond_true

cond_true:
; A8: subeq r0, r1, #1
; SWIFT: sub r0, r1, #1
%tmp5 = add i32 %b, 1
ret i32 %tmp5

cond_false:
; A8: addne r0, r1, #1
; SWIFT: addne r0, r1, #1
%tmp7 = add i32 %b, -1
ret i32 %tmp7
}
39 changes: 26 additions & 13 deletions llvm/test/CodeGen/ARM/ifcvt3.ll
View file
Original file line number Diff line number Diff line change
@@ -1,21 +1,41 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s
; RUN: llc -mtriple=arm-eabi -mattr=+v4t %s -o - | FileCheck %s -check-prefix CHECK-V4-CMP
; RUN: llc -mtriple=arm-eabi -mattr=+v4t %s -o - | FileCheck %s -check-prefix CHECK-V4-BX

define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) {
; CHECK-LABEL: t1:
; CHECK: cmp r2, #7
; CHECK: cmpne r2, #1
; CHECK: @ %bb.0:
; CHECK-NEXT: cmp r2, #7
; CHECK-NEXT: cmpne r2, #1
; CHECK-NEXT: addne r0, r1, r0
; CHECK-NEXT: addeq r0, r0, r1
; CHECK-NEXT: addeq r0, r0, #1
; CHECK-NEXT: bx lr
;
; CHECK-V4-CMP-LABEL: t1:
; CHECK-V4-CMP: @ %bb.0:
; CHECK-V4-CMP-NEXT: cmp r2, #7
; CHECK-V4-CMP-NEXT: cmpne r2, #1
; CHECK-V4-CMP-NEXT: addne r0, r1, r0
; CHECK-V4-CMP-NEXT: addeq r0, r0, r1
; CHECK-V4-CMP-NEXT: addeq r0, r0, #1
; CHECK-V4-CMP-NEXT: bx lr
;
; CHECK-V4-BX-LABEL: t1:
; CHECK-V4-BX: @ %bb.0:
; CHECK-V4-BX-NEXT: cmp r2, #7
; CHECK-V4-BX-NEXT: cmpne r2, #1
; CHECK-V4-BX-NEXT: addne r0, r1, r0
; CHECK-V4-BX-NEXT: addeq r0, r0, r1
; CHECK-V4-BX-NEXT: addeq r0, r0, #1
; CHECK-V4-BX-NEXT: bx lr
switch i32 %c, label %cond_next [
i32 1, label %cond_true
i32 7, label %cond_true
]

cond_true:
; CHECK: addne r0
; CHECK: addeq r0
; CHECK: addeq r0
; CHECK: bx
%tmp12 = add i32 %a, 1
%tmp1518 = add i32 %tmp12, %b
ret i32 %tmp1518
Expand All @@ -24,10 +44,3 @@ cond_next:
%tmp15 = add i32 %b, %a
ret i32 %tmp15
}

; CHECK-V4-CMP: cmpne
; CHECK-V4-CMP-NOT: cmpne

; CHECK-V4-BX: bx
; CHECK-V4-BX-NOT: bx

27 changes: 21 additions & 6 deletions llvm/test/CodeGen/ARM/load-global2.ll
View file
Original file line number Diff line number Diff line change
@@ -1,23 +1,38 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; PR35221. Test that external global address is not reloaded from GOT in each BB.
; RUN: llc < %s -mtriple=armv7-linux-gnueabi -relocation-model=pic | FileCheck %s -check-prefix=LINUX-PIC

@x = external global i8, align 1

define signext i8 @foo() {
; LINUX-PIC-LABEL: foo:
; LINUX-PIC: @ %bb.0: @ %entry
; LINUX-PIC-NEXT: .save {r4, lr}
; LINUX-PIC-NEXT: push {r4, lr}
; LINUX-PIC-NEXT: ldr r4, .LCPI0_0
; LINUX-PIC-NEXT: .LPC0_0:
; LINUX-PIC-NEXT: ldr r4, [pc, r4]
; LINUX-PIC-NEXT: ldrb r0, [r4]
; LINUX-PIC-NEXT: cmp r0, #0
; LINUX-PIC-NEXT: movne r0, #0
; LINUX-PIC-NEXT: popne {r4, pc}
; LINUX-PIC-NEXT: .LBB0_1: @ %bb1
; LINUX-PIC-NEXT: bl bar
; LINUX-PIC-NEXT: ldrsb r0, [r4]
; LINUX-PIC-NEXT: pop {r4, pc}
; LINUX-PIC-NEXT: .p2align 2
; LINUX-PIC-NEXT: @ %bb.2:
; LINUX-PIC-NEXT: .LCPI0_0:
; LINUX-PIC-NEXT: .Ltmp0:
; LINUX-PIC-NEXT: .long x(GOT_PREL)-((.LPC0_0+8)-.Ltmp0)
entry:
; LINUX-PIC: ldr r[[A:.]], .LCPI0_0
; LINUX-PIC: ldr r[[B:.]], [pc, r[[A]]]
; LINUX-PIC: ldrb r{{.}}, [r[[B]]]
%0 = load i8, i8* @x
%tobool = icmp eq i8 %0, 0
br i1 %tobool, label %bb1, label %bb2

bb1:
call void @bar()
; No more pc-relative loads! Reuse r[[B]].
; LINUX-PIC: bl bar
; LINUX-PIC-NOT: ldr{{.*}}[pc,
; LINUX-PIC: ldrsb r{{.}}, [r[[B]]]
%1 = load i8, i8* @x
ret i8 %1

Expand Down
250 changes: 221 additions & 29 deletions llvm/test/CodeGen/ARM/smml.ll
View file
Original file line number Diff line number Diff line change
@@ -1,24 +1,75 @@
; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-V4
; RUN: llc -mtriple=armv6-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-V6
; RUN: llc -mtriple=armv7-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-V6
; RUN: llc -mtriple=thumb-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-THUMB
; RUN: llc -mtriple=thumbv6-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-THUMB
; RUN: llc -mtriple=thumbv6t2-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-THUMBV6T2
; RUN: llc -mtriple=thumbv7-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-THUMBV6T2
; RUN: llc -mtriple=thumbv7m-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-V4
; RUN: llc -mtriple=thumbv7em-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-THUMBV6T2
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s --check-prefixes=CHECK-V4
; RUN: llc -mtriple=armv6-eabi %s -o - | FileCheck %s --check-prefixes=CHECK-V6
; RUN: llc -mtriple=armv7-eabi %s -o - | FileCheck %s --check-prefixes=CHECK-V6
; RUN: llc -mtriple=thumb-eabi %s -o - | FileCheck %s --check-prefixes=CHECK-THUMB
; RUN: llc -mtriple=thumbv6-eabi %s -o - | FileCheck %s --check-prefixes=CHECK-THUMBV6
; RUN: llc -mtriple=thumbv6t2-eabi %s -o - | FileCheck %s --check-prefixes=CHECK-THUMBV6T2
; RUN: llc -mtriple=thumbv7-eabi %s -o - | FileCheck %s --check-prefixes=CHECK-THUMBV6T2
; RUN: llc -mtriple=thumbv7m-eabi %s -o - | FileCheck %s --check-prefixes=CHECK-V4-THUMBV7M
; RUN: llc -mtriple=thumbv7em-eabi %s -o - | FileCheck %s --check-prefixes=CHECK-THUMBV6T2

; Next test would previously trigger an assertion responsible for verification of
; call site info state.
; RUN: llc -stop-after=if-converter -debug-entry-values -mtriple=thumbv6t2-eabi %s -o -| FileCheck %s -check-prefix=CHECK-CALLSITE
; CHECK-CALLSITE: name: test_used_flags
; CHECK-CALLSITE: callSites:


define i32 @Test0(i32 %a, i32 %b, i32 %c) nounwind readnone ssp {
; CHECK-V4-LABEL: Test0:
; CHECK-V4: @ %bb.0: @ %entry
; CHECK-V4-NEXT: smull r3, r12, r2, r1
; CHECK-V4-NEXT: sub r0, r0, r12
; CHECK-V4-NEXT: mov pc, lr
;
; CHECK-V6-LABEL: Test0:
; CHECK-V6: @ %bb.0: @ %entry
; CHECK-V6-NEXT: smmul r1, r2, r1
; CHECK-V6-NEXT: sub r0, r0, r1
; CHECK-V6-NEXT: bx lr
;
; CHECK-THUMB-LABEL: Test0:
; CHECK-THUMB: @ %bb.0: @ %entry
; CHECK-THUMB-NEXT: .save {r4, r5, r7, lr}
; CHECK-THUMB-NEXT: push {r4, r5, r7, lr}
; CHECK-THUMB-NEXT: movs r5, r1
; CHECK-THUMB-NEXT: movs r4, r0
; CHECK-THUMB-NEXT: asrs r1, r2, #31
; CHECK-THUMB-NEXT: asrs r3, r5, #31
; CHECK-THUMB-NEXT: movs r0, r2
; CHECK-THUMB-NEXT: movs r2, r5
; CHECK-THUMB-NEXT: bl __aeabi_lmul
; CHECK-THUMB-NEXT: subs r0, r4, r1
; CHECK-THUMB-NEXT: pop {r4, r5, r7}
; CHECK-THUMB-NEXT: pop {r1}
; CHECK-THUMB-NEXT: bx r1
;
; CHECK-THUMBV6-LABEL: Test0:
; CHECK-THUMBV6: @ %bb.0: @ %entry
; CHECK-THUMBV6-NEXT: .save {r4, r5, r7, lr}
; CHECK-THUMBV6-NEXT: push {r4, r5, r7, lr}
; CHECK-THUMBV6-NEXT: mov r5, r1
; CHECK-THUMBV6-NEXT: mov r4, r0
; CHECK-THUMBV6-NEXT: asrs r1, r2, #31
; CHECK-THUMBV6-NEXT: asrs r3, r5, #31
; CHECK-THUMBV6-NEXT: mov r0, r2
; CHECK-THUMBV6-NEXT: mov r2, r5
; CHECK-THUMBV6-NEXT: bl __aeabi_lmul
; CHECK-THUMBV6-NEXT: subs r0, r4, r1
; CHECK-THUMBV6-NEXT: pop {r4, r5, r7, pc}
;
; CHECK-THUMBV6T2-LABEL: Test0:
; CHECK-THUMBV6T2: @ %bb.0: @ %entry
; CHECK-THUMBV6T2-NEXT: smmul r1, r2, r1
; CHECK-THUMBV6T2-NEXT: subs r0, r0, r1
; CHECK-THUMBV6T2-NEXT: bx lr
;
; CHECK-V4-THUMBV7M-LABEL: Test0:
; CHECK-V4-THUMBV7M: @ %bb.0: @ %entry
; CHECK-V4-THUMBV7M-NEXT: smull r1, r2, r2, r1
; CHECK-V4-THUMBV7M-NEXT: subs r0, r0, r2
; CHECK-V4-THUMBV7M-NEXT: bx lr
entry:
; CHECK-LABEL: Test0
; CHECK-NOT: smmls
%conv4 = zext i32 %a to i64
%conv1 = sext i32 %b to i64
%conv2 = sext i32 %c to i64
Expand All @@ -30,11 +81,63 @@ entry:
}

define i32 @Test1(i32 %a, i32 %b, i32 %c) {
;CHECK-LABEL: Test1
;CHECK-V4-NOT: smmls
;CHECK-THUMB-NOT: smmls
;CHECK-V6: smmls r0, [[Rn:r[1-2]]], [[Rm:r[1-2]]], r0
;CHECK-THUMBV6T2: smmls r0, [[Rn:r[1-2]]], [[Rm:r[1-2]]], r0
; CHECK-V4-LABEL: Test1:
; CHECK-V4: @ %bb.0: @ %entry
; CHECK-V4-NEXT: smull r3, r12, r2, r1
; CHECK-V4-NEXT: rsbs r1, r3, #0
; CHECK-V4-NEXT: sbc r0, r0, r12
; CHECK-V4-NEXT: mov pc, lr
;
; CHECK-V6-LABEL: Test1:
; CHECK-V6: @ %bb.0: @ %entry
; CHECK-V6-NEXT: smmls r0, r2, r1, r0
; CHECK-V6-NEXT: bx lr
;
; CHECK-THUMB-LABEL: Test1:
; CHECK-THUMB: @ %bb.0: @ %entry
; CHECK-THUMB-NEXT: .save {r4, r5, r7, lr}
; CHECK-THUMB-NEXT: push {r4, r5, r7, lr}
; CHECK-THUMB-NEXT: movs r5, r1
; CHECK-THUMB-NEXT: movs r4, r0
; CHECK-THUMB-NEXT: asrs r1, r2, #31
; CHECK-THUMB-NEXT: asrs r3, r5, #31
; CHECK-THUMB-NEXT: movs r0, r2
; CHECK-THUMB-NEXT: movs r2, r5
; CHECK-THUMB-NEXT: bl __aeabi_lmul
; CHECK-THUMB-NEXT: rsbs r0, r0, #0
; CHECK-THUMB-NEXT: sbcs r4, r1
; CHECK-THUMB-NEXT: movs r0, r4
; CHECK-THUMB-NEXT: pop {r4, r5, r7}
; CHECK-THUMB-NEXT: pop {r1}
; CHECK-THUMB-NEXT: bx r1
;
; CHECK-THUMBV6-LABEL: Test1:
; CHECK-THUMBV6: @ %bb.0: @ %entry
; CHECK-THUMBV6-NEXT: .save {r4, r5, r7, lr}
; CHECK-THUMBV6-NEXT: push {r4, r5, r7, lr}
; CHECK-THUMBV6-NEXT: mov r5, r1
; CHECK-THUMBV6-NEXT: mov r4, r0
; CHECK-THUMBV6-NEXT: asrs r1, r2, #31
; CHECK-THUMBV6-NEXT: asrs r3, r5, #31
; CHECK-THUMBV6-NEXT: mov r0, r2
; CHECK-THUMBV6-NEXT: mov r2, r5
; CHECK-THUMBV6-NEXT: bl __aeabi_lmul
; CHECK-THUMBV6-NEXT: rsbs r0, r0, #0
; CHECK-THUMBV6-NEXT: sbcs r4, r1
; CHECK-THUMBV6-NEXT: mov r0, r4
; CHECK-THUMBV6-NEXT: pop {r4, r5, r7, pc}
;
; CHECK-THUMBV6T2-LABEL: Test1:
; CHECK-THUMBV6T2: @ %bb.0: @ %entry
; CHECK-THUMBV6T2-NEXT: smmls r0, r2, r1, r0
; CHECK-THUMBV6T2-NEXT: bx lr
;
; CHECK-V4-THUMBV7M-LABEL: Test1:
; CHECK-V4-THUMBV7M: @ %bb.0: @ %entry
; CHECK-V4-THUMBV7M-NEXT: smull r1, r2, r2, r1
; CHECK-V4-THUMBV7M-NEXT: rsbs r1, r1, #0
; CHECK-V4-THUMBV7M-NEXT: sbcs r0, r2
; CHECK-V4-THUMBV7M-NEXT: bx lr
entry:
%conv = sext i32 %b to i64
%conv1 = sext i32 %c to i64
Expand All @@ -49,18 +152,107 @@ entry:

declare void @opaque(i32)
define void @test_used_flags(i32 %in1, i32 %in2) {
; CHECK-LABEL: test_used_flags:
; CHECK-THUMB: movs r2, #0
; CHECK-THUMB: rsbs r0, r0, #0
; CHECK-THUMB: sbcs r2, r1
; CHECK-THUMB: bge
; CHECK-V6: smull [[PROD_LO:r[0-9]+]], [[PROD_HI:r[0-9]+]], r0, r1
; CHECK-V6: rsbs {{.*}}, [[PROD_LO]], #0
; CHECK-V6: rscs {{.*}}, [[PROD_HI]], #0
; CHECK-THUMBV6T2: smull [[PROD_LO:r[0-9]+]], [[PROD_HI:r[0-9]+]], r0, r1
; CHECK-THUMBV6T2: movs [[ZERO:r[0-9]+]], #0
; CHECK-THUMBV6T2: rsbs {{.*}}, [[PROD_LO]], #0
; CHECK-THUMBV6T2: sbcs.w {{.*}}, [[ZERO]], [[PROD_HI]]
; CHECK-V4-LABEL: test_used_flags:
; CHECK-V4: @ %bb.0:
; CHECK-V4-NEXT: .save {r11, lr}
; CHECK-V4-NEXT: push {r11, lr}
; CHECK-V4-NEXT: smull r2, r3, r0, r1
; CHECK-V4-NEXT: rsbs r0, r2, #0
; CHECK-V4-NEXT: rscs r0, r3, #0
; CHECK-V4-NEXT: movge r0, #42
; CHECK-V4-NEXT: movlt r0, #56
; CHECK-V4-NEXT: bl opaque
; CHECK-V4-NEXT: pop {r11, lr}
; CHECK-V4-NEXT: mov pc, lr
;
; CHECK-V6-LABEL: test_used_flags:
; CHECK-V6: @ %bb.0:
; CHECK-V6-NEXT: .save {r11, lr}
; CHECK-V6-NEXT: push {r11, lr}
; CHECK-V6-NEXT: smull r0, r1, r0, r1
; CHECK-V6-NEXT: rsbs r0, r0, #0
; CHECK-V6-NEXT: rscs r0, r1, #0
; CHECK-V6-NEXT: bge .LBB2_2
; CHECK-V6-NEXT: @ %bb.1: @ %false
; CHECK-V6-NEXT: mov r0, #56
; CHECK-V6-NEXT: bl opaque
; CHECK-V6-NEXT: pop {r11, pc}
; CHECK-V6-NEXT: .LBB2_2: @ %true
; CHECK-V6-NEXT: mov r0, #42
; CHECK-V6-NEXT: bl opaque
; CHECK-V6-NEXT: pop {r11, pc}
;
; CHECK-THUMB-LABEL: test_used_flags:
; CHECK-THUMB: @ %bb.0:
; CHECK-THUMB-NEXT: .save {r7, lr}
; CHECK-THUMB-NEXT: push {r7, lr}
; CHECK-THUMB-NEXT: movs r2, r1
; CHECK-THUMB-NEXT: asrs r1, r0, #31
; CHECK-THUMB-NEXT: asrs r3, r2, #31
; CHECK-THUMB-NEXT: bl __aeabi_lmul
; CHECK-THUMB-NEXT: movs r2, #0
; CHECK-THUMB-NEXT: rsbs r0, r0, #0
; CHECK-THUMB-NEXT: sbcs r2, r1
; CHECK-THUMB-NEXT: bge .LBB2_2
; CHECK-THUMB-NEXT: @ %bb.1: @ %false
; CHECK-THUMB-NEXT: movs r0, #56
; CHECK-THUMB-NEXT: b .LBB2_3
; CHECK-THUMB-NEXT: .LBB2_2: @ %true
; CHECK-THUMB-NEXT: movs r0, #42
; CHECK-THUMB-NEXT: .LBB2_3: @ %true
; CHECK-THUMB-NEXT: bl opaque
; CHECK-THUMB-NEXT: pop {r7}
; CHECK-THUMB-NEXT: pop {r0}
; CHECK-THUMB-NEXT: bx r0
;
; CHECK-THUMBV6-LABEL: test_used_flags:
; CHECK-THUMBV6: @ %bb.0:
; CHECK-THUMBV6-NEXT: .save {r7, lr}
; CHECK-THUMBV6-NEXT: push {r7, lr}
; CHECK-THUMBV6-NEXT: mov r2, r1
; CHECK-THUMBV6-NEXT: asrs r1, r0, #31
; CHECK-THUMBV6-NEXT: asrs r3, r2, #31
; CHECK-THUMBV6-NEXT: bl __aeabi_lmul
; CHECK-THUMBV6-NEXT: movs r2, #0
; CHECK-THUMBV6-NEXT: rsbs r0, r0, #0
; CHECK-THUMBV6-NEXT: sbcs r2, r1
; CHECK-THUMBV6-NEXT: bge .LBB2_2
; CHECK-THUMBV6-NEXT: @ %bb.1: @ %false
; CHECK-THUMBV6-NEXT: movs r0, #56
; CHECK-THUMBV6-NEXT: bl opaque
; CHECK-THUMBV6-NEXT: pop {r7, pc}
; CHECK-THUMBV6-NEXT: .LBB2_2: @ %true
; CHECK-THUMBV6-NEXT: movs r0, #42
; CHECK-THUMBV6-NEXT: bl opaque
; CHECK-THUMBV6-NEXT: pop {r7, pc}
;
; CHECK-THUMBV6T2-LABEL: test_used_flags:
; CHECK-THUMBV6T2: @ %bb.0:
; CHECK-THUMBV6T2-NEXT: .save {r7, lr}
; CHECK-THUMBV6T2-NEXT: push {r7, lr}
; CHECK-THUMBV6T2-NEXT: smull r0, r1, r0, r1
; CHECK-THUMBV6T2-NEXT: movs r2, #0
; CHECK-THUMBV6T2-NEXT: rsbs r0, r0, #0
; CHECK-THUMBV6T2-NEXT: sbcs.w r0, r2, r1
; CHECK-THUMBV6T2-NEXT: ite lt
; CHECK-THUMBV6T2-NEXT: movlt r0, #56
; CHECK-THUMBV6T2-NEXT: movge r0, #42
; CHECK-THUMBV6T2-NEXT: bl opaque
; CHECK-THUMBV6T2-NEXT: pop {r7, pc}
;
; CHECK-V4-THUMBV7M-LABEL: test_used_flags:
; CHECK-V4-THUMBV7M: @ %bb.0:
; CHECK-V4-THUMBV7M-NEXT: .save {r7, lr}
; CHECK-V4-THUMBV7M-NEXT: push {r7, lr}
; CHECK-V4-THUMBV7M-NEXT: smull r0, r1, r0, r1
; CHECK-V4-THUMBV7M-NEXT: movs r2, #0
; CHECK-V4-THUMBV7M-NEXT: rsbs r0, r0, #0
; CHECK-V4-THUMBV7M-NEXT: sbcs.w r0, r2, r1
; CHECK-V4-THUMBV7M-NEXT: ite lt
; CHECK-V4-THUMBV7M-NEXT: movlt r0, #56
; CHECK-V4-THUMBV7M-NEXT: movge r0, #42
; CHECK-V4-THUMBV7M-NEXT: bl opaque
; CHECK-V4-THUMBV7M-NEXT: pop {r7, pc}
%in1.64 = sext i32 %in1 to i64
%in2.64 = sext i32 %in2 to i64
%mul = mul nsw i64 %in1.64, %in2.64
Expand Down
371 changes: 273 additions & 98 deletions llvm/test/CodeGen/ARM/speculation-hardening-sls.ll
View file

Large diffs are not rendered by default.

19 changes: 17 additions & 2 deletions llvm/test/CodeGen/Hexagon/dont_rotate_pregs_at_O2.ll
View file
Original file line number Diff line number Diff line change
@@ -1,8 +1,23 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=hexagon -O2 < %s | FileCheck %s

; CHECK-NOT: p1 =

define i32 @f0(i32 %a0, i32 %a1) #0 {
; CHECK-LABEL: f0:
; CHECK: .cfi_startproc
; CHECK-NEXT: // %bb.0: // %b0
; CHECK-NEXT: {
; CHECK-NEXT: p0 = cmp.gt(r1,r0)
; CHECK-NEXT: if (p0.new) r0 = #0
; CHECK-NEXT: if (p0.new) jumpr:nt r31
; CHECK-NEXT: }
; CHECK-NEXT: .LBB0_1: // %b2
; CHECK-NEXT: {
; CHECK-NEXT: p0 = cmp.gt(r1,#99)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: r0 = mux(p0,##321,#123)
; CHECK-NEXT: jumpr r31
; CHECK-NEXT: }
b0:
%v0 = icmp slt i32 %a0, %a1
br i1 %v0, label %b1, label %b2
Expand Down
29 changes: 24 additions & 5 deletions llvm/test/CodeGen/Hexagon/noFalignAfterCallAtO2.ll
View file
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=hexagon -O2 < %s | FileCheck %s

; Check that we don't generate .falign directives after function calls at O2.
Expand All @@ -7,12 +8,30 @@
declare i32 @f0()

; We don't want faligns after the calls to foo.
; CHECK: call f0
; CHECK-NOT: falign
; CHECK: call f0
; CHECK-NOT: falign
; CHECK: dealloc_return

define i32 @f1(i32 %a0) #0 {
; CHECK-LABEL: f1:
; CHECK: // %bb.0: // %b0
; CHECK-NEXT: {
; CHECK-NEXT: if (!p0.new) r0 = add(r0,#5)
; CHECK-NEXT: p0 = cmp.eq(r0,#0)
; CHECK-NEXT: if (!p0.new) jumpr:nt r31
; CHECK-NEXT: }
; CHECK-NEXT: .LBB0_1: // %b1
; CHECK-NEXT: {
; CHECK-NEXT: call f0
; CHECK-NEXT: memd(r29+#-16) = r17:16
; CHECK-NEXT: allocframe(#8)
; CHECK-NEXT: } // 8-byte Folded Spill
; CHECK-NEXT: {
; CHECK-NEXT: call f0
; CHECK-NEXT: r16 = r0
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: r0 = add(r16,r0)
; CHECK-NEXT: r17:16 = memd(r29+#0)
; CHECK-NEXT: dealloc_return
; CHECK-NEXT: } // 8-byte Folded Reload
b0:
%v0 = icmp eq i32 %a0, 0
br i1 %v0, label %b1, label %b2
Expand Down
34 changes: 33 additions & 1 deletion llvm/test/CodeGen/Thumb2/tpsoft.ll
View file
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc %s -mtriple=thumbv7-linux-gnueabi -o - | \
; RUN: FileCheck -check-prefix=ELFASM %s
; RUN: llc %s -mtriple=thumbebv7-linux-gnueabi -o - | \
Expand All @@ -15,6 +16,38 @@
@b = external global [10 x i8]

define arm_aapcs_vfpcc i32 @main() nounwind {
; ELFASM-LABEL: main:
; ELFASM: @ %bb.0: @ %entry
; ELFASM-NEXT: .save {r7, lr}
; ELFASM-NEXT: push {r7, lr}
; ELFASM-NEXT: ldr r0, .LCPI0_0
; ELFASM-NEXT: .LPC0_0:
; ELFASM-NEXT: add r0, pc
; ELFASM-NEXT: ldr r1, [r0]
; ELFASM-NEXT: bl __aeabi_read_tp
; ELFASM-NEXT: ldr r0, [r0, r1]
; ELFASM-NEXT: cmp r0, #13
; ELFASM-NEXT: beq .LBB0_3
; ELFASM-NEXT: @ %bb.1: @ %entry
; ELFASM-NEXT: cmp r0, #12
; ELFASM-NEXT: itt ne
; ELFASM-NEXT: movne.w r0, #-1
; ELFASM-NEXT: popne {r7, pc}
; ELFASM-NEXT: .LBB0_2: @ %bb
; ELFASM-NEXT: movw r0, :lower16:a
; ELFASM-NEXT: movt r0, :upper16:a
; ELFASM-NEXT: pop.w {r7, lr}
; ELFASM-NEXT: b foo
; ELFASM-NEXT: .LBB0_3: @ %bb1
; ELFASM-NEXT: movw r0, :lower16:b
; ELFASM-NEXT: movt r0, :upper16:b
; ELFASM-NEXT: pop.w {r7, lr}
; ELFASM-NEXT: b bar
; ELFASM-NEXT: .p2align 2
; ELFASM-NEXT: @ %bb.4:
; ELFASM-NEXT: .LCPI0_0:
; ELFASM-NEXT: .Ltmp0:
; ELFASM-NEXT: .long i(GOTTPOFF)-((.LPC0_0+4)-.Ltmp0)
entry:
%0 = load i32, i32* @i, align 4
switch i32 %0, label %bb2 [
Expand All @@ -25,7 +58,6 @@ entry:
bb: ; preds = %entry
%1 = tail call arm_aapcs_vfpcc i32 @foo(i8* @a) nounwind
ret i32 %1
; ELFASM: bl __aeabi_read_tp


; ELFOBJ: Sections [
Expand Down
77 changes: 66 additions & 11 deletions llvm/test/CodeGen/Thumb2/v8_IT_4.ll
View file
Original file line number Diff line number Diff line change
@@ -1,7 +1,8 @@
; RUN: llc < %s -mtriple=thumbv8-eabi -float-abi=hard | FileCheck %s
; RUN: llc < %s -mtriple=thumbv7-eabi -float-abi=hard -arm-restrict-it | FileCheck %s
; RUN: llc < %s -mtriple=thumbv8-eabi -float-abi=hard -regalloc=basic | FileCheck %s
; RUN: llc < %s -mtriple=thumbv7-eabi -float-abi=hard -regalloc=basic -arm-restrict-it | FileCheck %s
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=thumbv8-eabi -float-abi=hard | FileCheck --check-prefixes=P01 %s
; RUN: llc < %s -mtriple=thumbv7-eabi -float-abi=hard -arm-restrict-it | FileCheck --check-prefixes=P01 %s
; RUN: llc < %s -mtriple=thumbv8-eabi -float-abi=hard -regalloc=basic | FileCheck --check-prefixes=P23 %s
; RUN: llc < %s -mtriple=thumbv7-eabi -float-abi=hard -regalloc=basic -arm-restrict-it | FileCheck --check-prefixes=P23 %s

%"struct.__gnu_cxx::__normal_iterator<char*,std::basic_string<char, std::char_traits<char>, std::allocator<char> > >" = type { i8* }
%"struct.__gnu_cxx::new_allocator<char>" = type <{ i8 }>
Expand All @@ -11,13 +12,67 @@


define weak arm_aapcs_vfpcc i32 @_ZNKSs7compareERKSs(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this, %"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %__str) {
; CHECK-LABEL: _ZNKSs7compareERKSs:
; CHECK: cbz r0,
; CHECK-NEXT: %bb1
; CHECK-NEXT: pop.w
; CHECK-NEXT: %bb
; CHECK-NEXT: sub{{(.w)?}} r0, r{{[0-9]+}}, r{{[0-9]+}}
; CHECK-NEXT: pop.w
; P01-LABEL: _ZNKSs7compareERKSs:
; P01: @ %bb.0: @ %entry
; P01-NEXT: .save {r4, r5, r6, r7, r8, lr}
; P01-NEXT: push.w {r4, r5, r6, r7, r8, lr}
; P01-NEXT: mov r6, r1
; P01-NEXT: mov r7, r0
; P01-NEXT: bl _ZNKSs4sizeEv
; P01-NEXT: mov r8, r0
; P01-NEXT: mov r0, r6
; P01-NEXT: bl _ZNKSs4sizeEv
; P01-NEXT: mov r4, r8
; P01-NEXT: cmp r0, r8
; P01-NEXT: mov r5, r0
; P01-NEXT: it lo
; P01-NEXT: movlo r4, r0
; P01-NEXT: mov r0, r7
; P01-NEXT: bl _ZNKSs7_M_dataEv
; P01-NEXT: mov r7, r0
; P01-NEXT: mov r0, r6
; P01-NEXT: bl _ZNKSs4dataEv
; P01-NEXT: mov r1, r0
; P01-NEXT: mov r0, r7
; P01-NEXT: mov r2, r4
; P01-NEXT: bl memcmp
; P01-NEXT: cbz r0, .LBB0_2
; P01-NEXT: @ %bb.1: @ %bb1
; P01-NEXT: pop.w {r4, r5, r6, r7, r8, pc}
; P01-NEXT: .LBB0_2: @ %bb
; P01-NEXT: sub.w r0, r8, r5
; P01-NEXT: pop.w {r4, r5, r6, r7, r8, pc}
;
; P23-LABEL: _ZNKSs7compareERKSs:
; P23: @ %bb.0: @ %entry
; P23-NEXT: .save {r4, r5, r6, r7, r8, lr}
; P23-NEXT: push.w {r4, r5, r6, r7, r8, lr}
; P23-NEXT: mov r7, r1
; P23-NEXT: mov r5, r0
; P23-NEXT: bl _ZNKSs4sizeEv
; P23-NEXT: mov r8, r0
; P23-NEXT: mov r0, r7
; P23-NEXT: bl _ZNKSs4sizeEv
; P23-NEXT: mov r4, r8
; P23-NEXT: cmp r0, r8
; P23-NEXT: mov r6, r0
; P23-NEXT: it lo
; P23-NEXT: movlo r4, r0
; P23-NEXT: mov r0, r5
; P23-NEXT: bl _ZNKSs7_M_dataEv
; P23-NEXT: mov r5, r0
; P23-NEXT: mov r0, r7
; P23-NEXT: bl _ZNKSs4dataEv
; P23-NEXT: mov r1, r0
; P23-NEXT: mov r0, r5
; P23-NEXT: mov r2, r4
; P23-NEXT: bl memcmp
; P23-NEXT: cbz r0, .LBB0_2
; P23-NEXT: @ %bb.1: @ %bb1
; P23-NEXT: pop.w {r4, r5, r6, r7, r8, pc}
; P23-NEXT: .LBB0_2: @ %bb
; P23-NEXT: sub.w r0, r8, r6
; P23-NEXT: pop.w {r4, r5, r6, r7, r8, pc}
entry:
%0 = tail call arm_aapcs_vfpcc i32 @_ZNKSs4sizeEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this) ; <i32> [#uses=3]
%1 = tail call arm_aapcs_vfpcc i32 @_ZNKSs4sizeEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %__str) ; <i32> [#uses=3]
Expand Down
5 changes: 3 additions & 2 deletions llvm/utils/UpdateTestChecks/common.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -291,11 +291,12 @@ def __str__(self):
return self.scrub

class FunctionTestBuilder:
def __init__(self, run_list, flags, scrubber_args):
def __init__(self, run_list, flags, scrubber_args, path):
self._verbose = flags.verbose
self._record_args = flags.function_signature
self._check_attributes = flags.check_attributes
self._scrubber_args = scrubber_args
self._path = path
# Strip double-quotes if input was read by UTC_ARGS
self._replace_value_regex = list(map(lambda x: x.strip('"'), flags.replace_value_regex))
self._func_dict = {}
Expand All @@ -309,7 +310,7 @@ def __init__(self, run_list, flags, scrubber_args):

def finish_and_get_func_dict(self):
for prefix in self._get_failed_prefixes():
warn('Prefix %s had conflicting output from different RUN lines for all functions' % (prefix,))
warn('Prefix %s had conflicting output from different RUN lines for all functions in test %s' % (prefix,self._path,))
return self._func_dict

def func_order(self):
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3 changes: 2 additions & 1 deletion llvm/utils/update_analyze_test_checks.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -115,7 +115,8 @@ def main():
'function_signature': False,
'check_attributes': False,
'replace_value_regex': []}),
scrubber_args = [])
scrubber_args = [],
path=test)

for prefixes, opt_args in prefix_list:
common.debug('Extracted opt cmd:', opt_basename, opt_args, file=sys.stderr)
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3 changes: 2 additions & 1 deletion llvm/utils/update_cc_test_checks.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -275,7 +275,8 @@ def main():
builder = common.FunctionTestBuilder(
run_list=filecheck_run_list,
flags=ti.args,
scrubber_args=[])
scrubber_args=[],
path=ti.path)

for prefixes, args, extra_commands, triple_in_cmd in run_list:
# Execute non-filechecked runline.
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3 changes: 2 additions & 1 deletion llvm/utils/update_llc_test_checks.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -114,7 +114,8 @@ def main():
'function_signature': False,
'check_attributes': False,
'replace_value_regex': []}),
scrubber_args=[ti.args])
scrubber_args=[ti.args],
path=ti.path)

for prefixes, llc_tool, llc_args, preprocess_cmd, triple_in_cmd, march_in_cmd in run_list:
common.debug('Extracted LLC cmd:', llc_tool, llc_args)
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3 changes: 2 additions & 1 deletion llvm/utils/update_test_checks.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -113,7 +113,8 @@ def main():
builder = common.FunctionTestBuilder(
run_list=prefix_list,
flags=ti.args,
scrubber_args=[])
scrubber_args=[],
path=ti.path)

for prefixes, opt_args, preprocess_cmd in prefix_list:
common.debug('Extracted opt cmd: ' + opt_basename + ' ' + opt_args)
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