132 changes: 59 additions & 73 deletions llvm/test/CodeGen/AArch64/sve-fptosi-sat.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -508,19 +508,17 @@ declare <vscale x 4 x i64> @llvm.fptosi.sat.nxv4f16.nxv4i64(<vscale x 4 x half>)
define <vscale x 2 x i32> @test_signed_v2f16_v2i32(<vscale x 2 x half> %f) {
; CHECK-LABEL: test_signed_v2f16_v2i32:
; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI14_0
; CHECK-NEXT: add x8, x8, :lo12:.LCPI14_0
; CHECK-NEXT: mov w8, #64511
; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: mov z3.d, #0xffffffff80000000
; CHECK-NEXT: ld1rh { z1.d }, p0/z, [x8]
; CHECK-NEXT: adrp x8, .LCPI14_1
; CHECK-NEXT: add x8, x8, :lo12:.LCPI14_1
; CHECK-NEXT: ld1rh { z2.d }, p0/z, [x8]
; CHECK-NEXT: mov z2.d, #0xffffffff80000000
; CHECK-NEXT: mov z1.h, w8
; CHECK-NEXT: mov w8, #31743
; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, z1.h
; CHECK-NEXT: movprfx z1, z0
; CHECK-NEXT: fcvtzs z1.d, p0/m, z0.h
; CHECK-NEXT: not p1.b, p0/z, p1.b
; CHECK-NEXT: mov z1.d, p1/m, z3.d
; CHECK-NEXT: mov z1.d, p1/m, z2.d
; CHECK-NEXT: mov z2.h, w8
; CHECK-NEXT: fcmgt p1.h, p0/z, z0.h, z2.h
; CHECK-NEXT: mov z2.d, #0x7fffffff
; CHECK-NEXT: mov z1.d, p1/m, z2.d
Expand All @@ -535,23 +533,21 @@ define <vscale x 2 x i32> @test_signed_v2f16_v2i32(<vscale x 2 x half> %f) {
define <vscale x 4 x i32> @test_signed_v4f16_v4i32(<vscale x 4 x half> %f) {
; CHECK-LABEL: test_signed_v4f16_v4i32:
; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI15_0
; CHECK-NEXT: add x8, x8, :lo12:.LCPI15_0
; CHECK-NEXT: mov w8, #64511
; CHECK-NEXT: mov w9, #-2147483648
; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: adrp x9, .LCPI15_1
; CHECK-NEXT: add x9, x9, :lo12:.LCPI15_1
; CHECK-NEXT: ld1rh { z1.s }, p0/z, [x8]
; CHECK-NEXT: mov w8, #-2147483648
; CHECK-NEXT: ld1rh { z2.s }, p0/z, [x9]
; CHECK-NEXT: mov z3.s, w8
; CHECK-NEXT: mov w8, #2147483647
; CHECK-NEXT: mov z1.h, w8
; CHECK-NEXT: mov w8, #31743
; CHECK-NEXT: mov z2.s, w9
; CHECK-NEXT: mov w9, #2147483647
; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, z1.h
; CHECK-NEXT: movprfx z1, z0
; CHECK-NEXT: fcvtzs z1.s, p0/m, z0.h
; CHECK-NEXT: not p1.b, p0/z, p1.b
; CHECK-NEXT: mov z1.s, p1/m, z3.s
; CHECK-NEXT: fcmgt p1.h, p0/z, z0.h, z2.h
; CHECK-NEXT: mov z2.s, w8
; CHECK-NEXT: mov z3.h, w8
; CHECK-NEXT: mov z1.s, p1/m, z2.s
; CHECK-NEXT: fcmgt p1.h, p0/z, z0.h, z3.h
; CHECK-NEXT: mov z2.s, w9
; CHECK-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h
; CHECK-NEXT: mov z1.s, p1/m, z2.s
; CHECK-NEXT: mov z1.s, p0/m, #0 // =0x0
Expand All @@ -564,31 +560,29 @@ define <vscale x 4 x i32> @test_signed_v4f16_v4i32(<vscale x 4 x half> %f) {
define <vscale x 8 x i32> @test_signed_v8f16_v8i32(<vscale x 8 x half> %f) {
; CHECK-LABEL: test_signed_v8f16_v8i32:
; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI16_0
; CHECK-NEXT: add x8, x8, :lo12:.LCPI16_0
; CHECK-NEXT: mov w8, #64511
; CHECK-NEXT: mov w9, #-2147483648
; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: adrp x9, .LCPI16_1
; CHECK-NEXT: add x9, x9, :lo12:.LCPI16_1
; CHECK-NEXT: uunpklo z2.s, z0.h
; CHECK-NEXT: ld1rh { z1.s }, p0/z, [x8]
; CHECK-NEXT: mov w8, #-2147483648
; CHECK-NEXT: uunpkhi z6.s, z0.h
; CHECK-NEXT: ld1rh { z3.s }, p0/z, [x9]
; CHECK-NEXT: movprfx z4, z2
; CHECK-NEXT: fcvtzs z4.s, p0/m, z2.h
; CHECK-NEXT: mov z5.s, w8
; CHECK-NEXT: mov w8, #2147483647
; CHECK-NEXT: mov z1.h, w8
; CHECK-NEXT: mov w8, #31743
; CHECK-NEXT: mov z3.s, w9
; CHECK-NEXT: mov w9, #2147483647
; CHECK-NEXT: fcmge p1.h, p0/z, z2.h, z1.h
; CHECK-NEXT: fcmge p2.h, p0/z, z6.h, z1.h
; CHECK-NEXT: not p1.b, p0/z, p1.b
; CHECK-NEXT: mov z5.h, w8
; CHECK-NEXT: not p2.b, p0/z, p2.b
; CHECK-NEXT: mov z4.s, p1/m, z5.s
; CHECK-NEXT: fcmgt p1.h, p0/z, z2.h, z3.h
; CHECK-NEXT: mov z7.s, w8
; CHECK-NEXT: mov z4.s, p1/m, z3.s
; CHECK-NEXT: fcmgt p1.h, p0/z, z2.h, z5.h
; CHECK-NEXT: mov z7.s, w9
; CHECK-NEXT: movprfx z0, z6
; CHECK-NEXT: fcvtzs z0.s, p0/m, z6.h
; CHECK-NEXT: sel z1.s, p2, z5.s, z0.s
; CHECK-NEXT: fcmgt p2.h, p0/z, z6.h, z3.h
; CHECK-NEXT: sel z1.s, p2, z3.s, z0.s
; CHECK-NEXT: fcmgt p2.h, p0/z, z6.h, z5.h
; CHECK-NEXT: sel z0.s, p1, z7.s, z4.s
; CHECK-NEXT: mov z1.s, p2/m, z7.s
; CHECK-NEXT: fcmuo p1.h, p0/z, z2.h, z2.h
Expand All @@ -603,23 +597,21 @@ define <vscale x 8 x i32> @test_signed_v8f16_v8i32(<vscale x 8 x half> %f) {
define <vscale x 4 x i16> @test_signed_v4f16_v4i16(<vscale x 4 x half> %f) {
; CHECK-LABEL: test_signed_v4f16_v4i16:
; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI17_0
; CHECK-NEXT: add x8, x8, :lo12:.LCPI17_0
; CHECK-NEXT: mov w8, #63488
; CHECK-NEXT: mov w9, #30719
; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: ld1rh { z1.s }, p0/z, [x8]
; CHECK-NEXT: adrp x8, .LCPI17_1
; CHECK-NEXT: add x8, x8, :lo12:.LCPI17_1
; CHECK-NEXT: ld1rh { z2.s }, p0/z, [x8]
; CHECK-NEXT: mov z1.h, w8
; CHECK-NEXT: mov w8, #32767
; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, z1.h
; CHECK-NEXT: movprfx z1, z0
; CHECK-NEXT: fcvtzs z1.s, p0/m, z0.h
; CHECK-NEXT: not p1.b, p0/z, p1.b
; CHECK-NEXT: mov z2.h, w9
; CHECK-NEXT: mov z1.s, p1/m, #-32768 // =0xffffffffffff8000
; CHECK-NEXT: fcmgt p1.h, p0/z, z0.h, z2.h
; CHECK-NEXT: mov z2.s, w8
; CHECK-NEXT: mov z1.s, p1/m, z2.s
; CHECK-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h
; CHECK-NEXT: mov z1.s, p1/m, z2.s
; CHECK-NEXT: mov z1.s, p0/m, #0 // =0x0
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: ret
Expand All @@ -630,23 +622,21 @@ define <vscale x 4 x i16> @test_signed_v4f16_v4i16(<vscale x 4 x half> %f) {
define <vscale x 8 x i16> @test_signed_v8f16_v8i16(<vscale x 8 x half> %f) {
; CHECK-LABEL: test_signed_v8f16_v8i16:
; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI18_0
; CHECK-NEXT: add x8, x8, :lo12:.LCPI18_0
; CHECK-NEXT: mov w8, #63488
; CHECK-NEXT: mov w9, #30719
; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: ld1rh { z1.h }, p0/z, [x8]
; CHECK-NEXT: adrp x8, .LCPI18_1
; CHECK-NEXT: add x8, x8, :lo12:.LCPI18_1
; CHECK-NEXT: ld1rh { z2.h }, p0/z, [x8]
; CHECK-NEXT: mov z1.h, w8
; CHECK-NEXT: mov w8, #32767
; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, z1.h
; CHECK-NEXT: movprfx z1, z0
; CHECK-NEXT: fcvtzs z1.h, p0/m, z0.h
; CHECK-NEXT: not p1.b, p0/z, p1.b
; CHECK-NEXT: mov z2.h, w9
; CHECK-NEXT: mov z1.h, p1/m, #-32768 // =0xffffffffffff8000
; CHECK-NEXT: fcmgt p1.h, p0/z, z0.h, z2.h
; CHECK-NEXT: mov z2.h, w8
; CHECK-NEXT: mov z1.h, p1/m, z2.h
; CHECK-NEXT: fcmuo p0.h, p0/z, z0.h, z0.h
; CHECK-NEXT: mov z1.h, p1/m, z2.h
; CHECK-NEXT: mov z1.h, p0/m, #0 // =0x0
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: ret
Expand All @@ -657,19 +647,17 @@ define <vscale x 8 x i16> @test_signed_v8f16_v8i16(<vscale x 8 x half> %f) {
define <vscale x 2 x i64> @test_signed_v2f16_v2i64(<vscale x 2 x half> %f) {
; CHECK-LABEL: test_signed_v2f16_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI19_0
; CHECK-NEXT: add x8, x8, :lo12:.LCPI19_0
; CHECK-NEXT: mov w8, #64511
; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: mov z3.d, #0x8000000000000000
; CHECK-NEXT: ld1rh { z1.d }, p0/z, [x8]
; CHECK-NEXT: adrp x8, .LCPI19_1
; CHECK-NEXT: add x8, x8, :lo12:.LCPI19_1
; CHECK-NEXT: ld1rh { z2.d }, p0/z, [x8]
; CHECK-NEXT: mov z2.d, #0x8000000000000000
; CHECK-NEXT: mov z1.h, w8
; CHECK-NEXT: mov w8, #31743
; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, z1.h
; CHECK-NEXT: movprfx z1, z0
; CHECK-NEXT: fcvtzs z1.d, p0/m, z0.h
; CHECK-NEXT: not p1.b, p0/z, p1.b
; CHECK-NEXT: mov z1.d, p1/m, z3.d
; CHECK-NEXT: mov z1.d, p1/m, z2.d
; CHECK-NEXT: mov z2.h, w8
; CHECK-NEXT: fcmgt p1.h, p0/z, z0.h, z2.h
; CHECK-NEXT: mov z2.d, #0x7fffffffffffffff
; CHECK-NEXT: mov z1.d, p1/m, z2.d
Expand All @@ -684,32 +672,30 @@ define <vscale x 2 x i64> @test_signed_v2f16_v2i64(<vscale x 2 x half> %f) {
define <vscale x 4 x i64> @test_signed_v4f16_v4i64(<vscale x 4 x half> %f) {
; CHECK-LABEL: test_signed_v4f16_v4i64:
; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI20_0
; CHECK-NEXT: add x8, x8, :lo12:.LCPI20_0
; CHECK-NEXT: mov w8, #64511
; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: uunpklo z4.d, z0.s
; CHECK-NEXT: mov z3.d, #0x8000000000000000
; CHECK-NEXT: uunpklo z3.d, z0.s
; CHECK-NEXT: mov w9, #31743
; CHECK-NEXT: mov z2.d, #0x8000000000000000
; CHECK-NEXT: uunpkhi z5.d, z0.s
; CHECK-NEXT: ld1rh { z1.d }, p0/z, [x8]
; CHECK-NEXT: adrp x8, .LCPI20_1
; CHECK-NEXT: add x8, x8, :lo12:.LCPI20_1
; CHECK-NEXT: mov z6.d, #0x7fffffffffffffff
; CHECK-NEXT: ld1rh { z2.d }, p0/z, [x8]
; CHECK-NEXT: fcmge p1.h, p0/z, z4.h, z1.h
; CHECK-NEXT: movprfx z0, z4
; CHECK-NEXT: fcvtzs z0.d, p0/m, z4.h
; CHECK-NEXT: mov z1.h, w8
; CHECK-NEXT: movprfx z0, z3
; CHECK-NEXT: fcvtzs z0.d, p0/m, z3.h
; CHECK-NEXT: fcmge p1.h, p0/z, z3.h, z1.h
; CHECK-NEXT: mov z4.h, w9
; CHECK-NEXT: not p1.b, p0/z, p1.b
; CHECK-NEXT: mov z0.d, p1/m, z3.d
; CHECK-NEXT: fcmgt p2.h, p0/z, z3.h, z4.h
; CHECK-NEXT: mov z0.d, p1/m, z2.d
; CHECK-NEXT: fcmge p1.h, p0/z, z5.h, z1.h
; CHECK-NEXT: movprfx z1, z5
; CHECK-NEXT: fcvtzs z1.d, p0/m, z5.h
; CHECK-NEXT: not p1.b, p0/z, p1.b
; CHECK-NEXT: fcmgt p2.h, p0/z, z4.h, z2.h
; CHECK-NEXT: mov z1.d, p1/m, z3.d
; CHECK-NEXT: fcmgt p1.h, p0/z, z5.h, z2.h
; CHECK-NEXT: mov z6.d, #0x7fffffffffffffff
; CHECK-NEXT: mov z1.d, p1/m, z2.d
; CHECK-NEXT: fcmgt p1.h, p0/z, z5.h, z4.h
; CHECK-NEXT: mov z0.d, p2/m, z6.d
; CHECK-NEXT: mov z1.d, p1/m, z6.d
; CHECK-NEXT: fcmuo p1.h, p0/z, z4.h, z4.h
; CHECK-NEXT: fcmuo p1.h, p0/z, z3.h, z3.h
; CHECK-NEXT: fcmuo p0.h, p0/z, z5.h, z5.h
; CHECK-NEXT: mov z0.d, p1/m, #0 // =0x0
; CHECK-NEXT: mov z1.d, p0/m, #0 // =0x0
Expand Down
111 changes: 51 additions & 60 deletions llvm/test/CodeGen/AArch64/sve-fptoui-sat.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -400,18 +400,16 @@ declare <vscale x 4 x i64> @llvm.fptoui.sat.nxv4f16.nxv4i64(<vscale x 4 x half>)
define <vscale x 2 x i32> @test_signed_v2f16_v2i32(<vscale x 2 x half> %f) {
; CHECK-LABEL: test_signed_v2f16_v2i32:
; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI14_0
; CHECK-NEXT: add x8, x8, :lo12:.LCPI14_0
; CHECK-NEXT: mov w8, #31743
; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, #0.0
; CHECK-NEXT: ld1rh { z1.d }, p0/z, [x8]
; CHECK-NEXT: movprfx z2, z0
; CHECK-NEXT: fcvtzu z2.d, p0/m, z0.h
; CHECK-NEXT: not p1.b, p0/z, p1.b
; CHECK-NEXT: mov z2.d, p1/m, #0 // =0x0
; CHECK-NEXT: fcmgt p0.h, p0/z, z0.h, z1.h
; CHECK-NEXT: mov z0.d, #0xffffffff
; CHECK-NEXT: sel z0.d, p0, z0.d, z2.d
; CHECK-NEXT: mov z1.h, w8
; CHECK-NEXT: fcmgt p2.h, p0/z, z0.h, z1.h
; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.h
; CHECK-NEXT: not p0.b, p0/z, p1.b
; CHECK-NEXT: mov z1.d, #0xffffffff
; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
; CHECK-NEXT: mov z0.d, p2/m, z1.d
; CHECK-NEXT: ret
%x = call <vscale x 2 x i32> @llvm.fptoui.sat.nxv2f16.nxv2i32(<vscale x 2 x half> %f)
ret <vscale x 2 x i32> %x
Expand All @@ -420,14 +418,13 @@ define <vscale x 2 x i32> @test_signed_v2f16_v2i32(<vscale x 2 x half> %f) {
define <vscale x 4 x i32> @test_signed_v4f16_v4i32(<vscale x 4 x half> %f) {
; CHECK-LABEL: test_signed_v4f16_v4i32:
; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI15_0
; CHECK-NEXT: add x8, x8, :lo12:.LCPI15_0
; CHECK-NEXT: mov w8, #31743
; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, #0.0
; CHECK-NEXT: ld1rh { z2.s }, p0/z, [x8]
; CHECK-NEXT: movprfx z1, z0
; CHECK-NEXT: fcvtzu z1.s, p0/m, z0.h
; CHECK-NEXT: not p1.b, p0/z, p1.b
; CHECK-NEXT: mov z2.h, w8
; CHECK-NEXT: mov z1.s, p1/m, #0 // =0x0
; CHECK-NEXT: fcmgt p0.h, p0/z, z0.h, z2.h
; CHECK-NEXT: mov z1.s, p0/m, #-1 // =0xffffffffffffffff
Expand All @@ -440,24 +437,23 @@ define <vscale x 4 x i32> @test_signed_v4f16_v4i32(<vscale x 4 x half> %f) {
define <vscale x 8 x i32> @test_signed_v8f16_v8i32(<vscale x 8 x half> %f) {
; CHECK-LABEL: test_signed_v8f16_v8i32:
; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI16_0
; CHECK-NEXT: add x8, x8, :lo12:.LCPI16_0
; CHECK-NEXT: mov w8, #31743
; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: uunpklo z3.s, z0.h
; CHECK-NEXT: uunpkhi z4.s, z0.h
; CHECK-NEXT: fcmge p1.h, p0/z, z3.h, #0.0
; CHECK-NEXT: ld1rh { z2.s }, p0/z, [x8]
; CHECK-NEXT: fcmge p2.h, p0/z, z4.h, #0.0
; CHECK-NEXT: movprfx z0, z3
; CHECK-NEXT: fcvtzu z0.s, p0/m, z3.h
; CHECK-NEXT: movprfx z1, z4
; CHECK-NEXT: fcvtzu z1.s, p0/m, z4.h
; CHECK-NEXT: not p1.b, p0/z, p1.b
; CHECK-NEXT: uunpklo z1.s, z0.h
; CHECK-NEXT: uunpkhi z3.s, z0.h
; CHECK-NEXT: fcmge p2.h, p0/z, z1.h, #0.0
; CHECK-NEXT: movprfx z0, z1
; CHECK-NEXT: fcvtzu z0.s, p0/m, z1.h
; CHECK-NEXT: not p2.b, p0/z, p2.b
; CHECK-NEXT: mov z2.h, w8
; CHECK-NEXT: mov z0.s, p2/m, #0 // =0x0
; CHECK-NEXT: fcmge p2.h, p0/z, z3.h, #0.0
; CHECK-NEXT: fcmgt p1.h, p0/z, z1.h, z2.h
; CHECK-NEXT: movprfx z1, z3
; CHECK-NEXT: fcvtzu z1.s, p0/m, z3.h
; CHECK-NEXT: not p2.b, p0/z, p2.b
; CHECK-NEXT: mov z0.s, p1/m, #0 // =0x0
; CHECK-NEXT: fcmgt p0.h, p0/z, z3.h, z2.h
; CHECK-NEXT: mov z1.s, p2/m, #0 // =0x0
; CHECK-NEXT: fcmgt p1.h, p0/z, z3.h, z2.h
; CHECK-NEXT: fcmgt p0.h, p0/z, z4.h, z2.h
; CHECK-NEXT: mov z0.s, p1/m, #-1 // =0xffffffffffffffff
; CHECK-NEXT: mov z1.s, p0/m, #-1 // =0xffffffffffffffff
; CHECK-NEXT: ret
Expand All @@ -468,19 +464,17 @@ define <vscale x 8 x i32> @test_signed_v8f16_v8i32(<vscale x 8 x half> %f) {
define <vscale x 4 x i16> @test_signed_v4f16_v4i16(<vscale x 4 x half> %f) {
; CHECK-LABEL: test_signed_v4f16_v4i16:
; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI17_0
; CHECK-NEXT: add x8, x8, :lo12:.LCPI17_0
; CHECK-NEXT: mov w8, #31743
; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: mov w9, #65535
; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, #0.0
; CHECK-NEXT: ld1rh { z1.s }, p0/z, [x8]
; CHECK-NEXT: mov w8, #65535
; CHECK-NEXT: movprfx z2, z0
; CHECK-NEXT: fcvtzu z2.s, p0/m, z0.h
; CHECK-NEXT: not p1.b, p0/z, p1.b
; CHECK-NEXT: mov z2.s, p1/m, #0 // =0x0
; CHECK-NEXT: fcmgt p0.h, p0/z, z0.h, z1.h
; CHECK-NEXT: mov z0.s, w8
; CHECK-NEXT: sel z0.s, p0, z0.s, z2.s
; CHECK-NEXT: mov z1.h, w8
; CHECK-NEXT: fcmgt p2.h, p0/z, z0.h, z1.h
; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.h
; CHECK-NEXT: not p0.b, p0/z, p1.b
; CHECK-NEXT: mov z1.s, w9
; CHECK-NEXT: mov z0.s, p0/m, #0 // =0x0
; CHECK-NEXT: mov z0.s, p2/m, z1.s
; CHECK-NEXT: ret
%x = call <vscale x 4 x i16> @llvm.fptoui.sat.nxv4f16.nxv4i16(<vscale x 4 x half> %f)
ret <vscale x 4 x i16> %x
Expand All @@ -489,14 +483,13 @@ define <vscale x 4 x i16> @test_signed_v4f16_v4i16(<vscale x 4 x half> %f) {
define <vscale x 8 x i16> @test_signed_v8f16_v8i16(<vscale x 8 x half> %f) {
; CHECK-LABEL: test_signed_v8f16_v8i16:
; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI18_0
; CHECK-NEXT: add x8, x8, :lo12:.LCPI18_0
; CHECK-NEXT: mov w8, #31743
; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, #0.0
; CHECK-NEXT: ld1rh { z2.h }, p0/z, [x8]
; CHECK-NEXT: movprfx z1, z0
; CHECK-NEXT: fcvtzu z1.h, p0/m, z0.h
; CHECK-NEXT: not p1.b, p0/z, p1.b
; CHECK-NEXT: mov z2.h, w8
; CHECK-NEXT: mov z1.h, p1/m, #0 // =0x0
; CHECK-NEXT: fcmgt p0.h, p0/z, z0.h, z2.h
; CHECK-NEXT: mov z1.h, p0/m, #-1 // =0xffffffffffffffff
Expand All @@ -509,14 +502,13 @@ define <vscale x 8 x i16> @test_signed_v8f16_v8i16(<vscale x 8 x half> %f) {
define <vscale x 2 x i64> @test_signed_v2f16_v2i64(<vscale x 2 x half> %f) {
; CHECK-LABEL: test_signed_v2f16_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI19_0
; CHECK-NEXT: add x8, x8, :lo12:.LCPI19_0
; CHECK-NEXT: mov w8, #31743
; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, #0.0
; CHECK-NEXT: ld1rh { z2.d }, p0/z, [x8]
; CHECK-NEXT: movprfx z1, z0
; CHECK-NEXT: fcvtzu z1.d, p0/m, z0.h
; CHECK-NEXT: not p1.b, p0/z, p1.b
; CHECK-NEXT: mov z2.h, w8
; CHECK-NEXT: mov z1.d, p1/m, #0 // =0x0
; CHECK-NEXT: fcmgt p0.h, p0/z, z0.h, z2.h
; CHECK-NEXT: mov z1.d, p0/m, #-1 // =0xffffffffffffffff
Expand All @@ -529,24 +521,23 @@ define <vscale x 2 x i64> @test_signed_v2f16_v2i64(<vscale x 2 x half> %f) {
define <vscale x 4 x i64> @test_signed_v4f16_v4i64(<vscale x 4 x half> %f) {
; CHECK-LABEL: test_signed_v4f16_v4i64:
; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI20_0
; CHECK-NEXT: add x8, x8, :lo12:.LCPI20_0
; CHECK-NEXT: mov w8, #31743
; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: uunpklo z3.d, z0.s
; CHECK-NEXT: uunpkhi z4.d, z0.s
; CHECK-NEXT: fcmge p1.h, p0/z, z3.h, #0.0
; CHECK-NEXT: ld1rh { z2.d }, p0/z, [x8]
; CHECK-NEXT: fcmge p2.h, p0/z, z4.h, #0.0
; CHECK-NEXT: movprfx z0, z3
; CHECK-NEXT: fcvtzu z0.d, p0/m, z3.h
; CHECK-NEXT: movprfx z1, z4
; CHECK-NEXT: fcvtzu z1.d, p0/m, z4.h
; CHECK-NEXT: not p1.b, p0/z, p1.b
; CHECK-NEXT: uunpklo z1.d, z0.s
; CHECK-NEXT: uunpkhi z3.d, z0.s
; CHECK-NEXT: fcmge p2.h, p0/z, z1.h, #0.0
; CHECK-NEXT: movprfx z0, z1
; CHECK-NEXT: fcvtzu z0.d, p0/m, z1.h
; CHECK-NEXT: not p2.b, p0/z, p2.b
; CHECK-NEXT: mov z2.h, w8
; CHECK-NEXT: mov z0.d, p2/m, #0 // =0x0
; CHECK-NEXT: fcmge p2.h, p0/z, z3.h, #0.0
; CHECK-NEXT: fcmgt p1.h, p0/z, z1.h, z2.h
; CHECK-NEXT: movprfx z1, z3
; CHECK-NEXT: fcvtzu z1.d, p0/m, z3.h
; CHECK-NEXT: not p2.b, p0/z, p2.b
; CHECK-NEXT: mov z0.d, p1/m, #0 // =0x0
; CHECK-NEXT: fcmgt p0.h, p0/z, z3.h, z2.h
; CHECK-NEXT: mov z1.d, p2/m, #0 // =0x0
; CHECK-NEXT: fcmgt p1.h, p0/z, z3.h, z2.h
; CHECK-NEXT: fcmgt p0.h, p0/z, z4.h, z2.h
; CHECK-NEXT: mov z0.d, p1/m, #-1 // =0xffffffffffffffff
; CHECK-NEXT: mov z1.d, p0/m, #-1 // =0xffffffffffffffff
; CHECK-NEXT: ret
Expand Down