44 changes: 22 additions & 22 deletions llvm/test/CodeGen/RISCV/float-select-fcmp.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -240,14 +240,14 @@ define float @select_fcmp_ord(float %a, float %b) nounwind {
define float @select_fcmp_ueq(float %a, float %b) nounwind {
; RV32IF-LABEL: select_fcmp_ueq:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: fmv.w.x ft1, a1
; RV32IF-NEXT: feq.s a0, ft1, ft1
; RV32IF-NEXT: feq.s a1, ft0, ft0
; RV32IF-NEXT: and a0, a1, a0
; RV32IF-NEXT: seqz a0, a0
; RV32IF-NEXT: feq.s a1, ft0, ft1
; RV32IF-NEXT: or a0, a1, a0
; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: feq.s a0, ft0, ft1
; RV32IF-NEXT: feq.s a1, ft1, ft1
; RV32IF-NEXT: feq.s a2, ft0, ft0
; RV32IF-NEXT: and a1, a2, a1
; RV32IF-NEXT: seqz a1, a1
; RV32IF-NEXT: or a0, a0, a1
; RV32IF-NEXT: bnez a0, .LBB8_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fmv.s ft0, ft1
Expand All @@ -257,14 +257,14 @@ define float @select_fcmp_ueq(float %a, float %b) nounwind {
;
; RV64IF-LABEL: select_fcmp_ueq:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: fmv.w.x ft1, a1
; RV64IF-NEXT: feq.s a0, ft1, ft1
; RV64IF-NEXT: feq.s a1, ft0, ft0
; RV64IF-NEXT: and a0, a1, a0
; RV64IF-NEXT: seqz a0, a0
; RV64IF-NEXT: feq.s a1, ft0, ft1
; RV64IF-NEXT: or a0, a1, a0
; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: feq.s a0, ft0, ft1
; RV64IF-NEXT: feq.s a1, ft1, ft1
; RV64IF-NEXT: feq.s a2, ft0, ft0
; RV64IF-NEXT: and a1, a2, a1
; RV64IF-NEXT: seqz a1, a1
; RV64IF-NEXT: or a0, a0, a1
; RV64IF-NEXT: bnez a0, .LBB8_2
; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: fmv.s ft0, ft1
Expand Down Expand Up @@ -486,24 +486,24 @@ define i32 @i32_select_fcmp_oeq(float %a, float %b, i32 %c, i32 %d) nounwind {
; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, a1
; RV32IF-NEXT: fmv.w.x ft1, a0
; RV32IF-NEXT: feq.s a0, ft1, ft0
; RV32IF-NEXT: bnez a0, .LBB16_2
; RV32IF-NEXT: feq.s a1, ft1, ft0
; RV32IF-NEXT: mv a0, a2
; RV32IF-NEXT: bnez a1, .LBB16_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: mv a2, a3
; RV32IF-NEXT: mv a0, a3
; RV32IF-NEXT: .LBB16_2:
; RV32IF-NEXT: mv a0, a2
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: i32_select_fcmp_oeq:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a1
; RV64IF-NEXT: fmv.w.x ft1, a0
; RV64IF-NEXT: feq.s a0, ft1, ft0
; RV64IF-NEXT: bnez a0, .LBB16_2
; RV64IF-NEXT: feq.s a1, ft1, ft0
; RV64IF-NEXT: mv a0, a2
; RV64IF-NEXT: bnez a1, .LBB16_2
; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: mv a2, a3
; RV64IF-NEXT: mv a0, a3
; RV64IF-NEXT: .LBB16_2:
; RV64IF-NEXT: mv a0, a2
; RV64IF-NEXT: ret
%1 = fcmp oeq float %a, %b
%2 = select i1 %1, i32 %c, i32 %d
Expand Down
86 changes: 43 additions & 43 deletions llvm/test/CodeGen/RISCV/fp128.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -13,28 +13,28 @@ define i32 @test_load_and_cmp() nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -48
; RV32I-NEXT: sw ra, 44(sp)
; RV32I-NEXT: lui a0, %hi(y)
; RV32I-NEXT: lw a1, %lo(y)(a0)
; RV32I-NEXT: sw a1, 8(sp)
; RV32I-NEXT: lui a1, %hi(x)
; RV32I-NEXT: lw a2, %lo(x)(a1)
; RV32I-NEXT: sw a2, 24(sp)
; RV32I-NEXT: addi a0, a0, %lo(y)
; RV32I-NEXT: lw a2, 12(a0)
; RV32I-NEXT: sw a2, 20(sp)
; RV32I-NEXT: lw a2, 8(a0)
; RV32I-NEXT: sw a2, 16(sp)
; RV32I-NEXT: lw a0, 4(a0)
; RV32I-NEXT: sw a0, 12(sp)
; RV32I-NEXT: addi a0, a1, %lo(x)
; RV32I-NEXT: lw a1, 12(a0)
; RV32I-NEXT: lui a0, %hi(x)
; RV32I-NEXT: addi a1, a0, %lo(x)
; RV32I-NEXT: lw a6, 4(a1)
; RV32I-NEXT: lw a7, 8(a1)
; RV32I-NEXT: lw a1, 12(a1)
; RV32I-NEXT: lw a0, %lo(x)(a0)
; RV32I-NEXT: lui a4, %hi(y)
; RV32I-NEXT: addi a5, a4, %lo(y)
; RV32I-NEXT: lw a2, 4(a5)
; RV32I-NEXT: lw a3, 8(a5)
; RV32I-NEXT: lw a5, 12(a5)
; RV32I-NEXT: lw a4, %lo(y)(a4)
; RV32I-NEXT: sw a4, 8(sp)
; RV32I-NEXT: sw a0, 24(sp)
; RV32I-NEXT: sw a5, 20(sp)
; RV32I-NEXT: sw a3, 16(sp)
; RV32I-NEXT: sw a2, 12(sp)
; RV32I-NEXT: sw a1, 36(sp)
; RV32I-NEXT: lw a1, 8(a0)
; RV32I-NEXT: sw a1, 32(sp)
; RV32I-NEXT: lw a0, 4(a0)
; RV32I-NEXT: sw a0, 28(sp)
; RV32I-NEXT: sw a7, 32(sp)
; RV32I-NEXT: addi a0, sp, 24
; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: sw a6, 28(sp)
; RV32I-NEXT: call __netf2
; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: lw ra, 44(sp)
Expand All @@ -52,39 +52,39 @@ define i32 @test_add_and_fptosi() nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -80
; RV32I-NEXT: sw ra, 76(sp)
; RV32I-NEXT: lui a0, %hi(y)
; RV32I-NEXT: lw a1, %lo(y)(a0)
; RV32I-NEXT: sw a1, 24(sp)
; RV32I-NEXT: lui a1, %hi(x)
; RV32I-NEXT: lw a2, %lo(x)(a1)
; RV32I-NEXT: sw a2, 40(sp)
; RV32I-NEXT: addi a0, a0, %lo(y)
; RV32I-NEXT: lw a2, 12(a0)
; RV32I-NEXT: sw a2, 36(sp)
; RV32I-NEXT: lw a2, 8(a0)
; RV32I-NEXT: lui a0, %hi(x)
; RV32I-NEXT: addi a1, a0, %lo(x)
; RV32I-NEXT: lw a6, 4(a1)
; RV32I-NEXT: lw a7, 8(a1)
; RV32I-NEXT: lw a1, 12(a1)
; RV32I-NEXT: lw a0, %lo(x)(a0)
; RV32I-NEXT: lui a4, %hi(y)
; RV32I-NEXT: addi a5, a4, %lo(y)
; RV32I-NEXT: lw a3, 4(a5)
; RV32I-NEXT: lw a2, 8(a5)
; RV32I-NEXT: lw a5, 12(a5)
; RV32I-NEXT: lw a4, %lo(y)(a4)
; RV32I-NEXT: sw a4, 24(sp)
; RV32I-NEXT: sw a0, 40(sp)
; RV32I-NEXT: sw a5, 36(sp)
; RV32I-NEXT: sw a2, 32(sp)
; RV32I-NEXT: lw a0, 4(a0)
; RV32I-NEXT: sw a0, 28(sp)
; RV32I-NEXT: addi a0, a1, %lo(x)
; RV32I-NEXT: lw a1, 12(a0)
; RV32I-NEXT: sw a3, 28(sp)
; RV32I-NEXT: sw a1, 52(sp)
; RV32I-NEXT: lw a1, 8(a0)
; RV32I-NEXT: sw a1, 48(sp)
; RV32I-NEXT: lw a0, 4(a0)
; RV32I-NEXT: sw a0, 44(sp)
; RV32I-NEXT: sw a7, 48(sp)
; RV32I-NEXT: addi a0, sp, 56
; RV32I-NEXT: addi a1, sp, 40
; RV32I-NEXT: addi a2, sp, 24
; RV32I-NEXT: sw a6, 44(sp)
; RV32I-NEXT: call __addtf3
; RV32I-NEXT: lw a0, 68(sp)
; RV32I-NEXT: sw a0, 20(sp)
; RV32I-NEXT: lw a0, 64(sp)
; RV32I-NEXT: sw a0, 16(sp)
; RV32I-NEXT: lw a1, 56(sp)
; RV32I-NEXT: lw a0, 60(sp)
; RV32I-NEXT: lw a2, 64(sp)
; RV32I-NEXT: lw a3, 68(sp)
; RV32I-NEXT: sw a3, 20(sp)
; RV32I-NEXT: sw a2, 16(sp)
; RV32I-NEXT: sw a0, 12(sp)
; RV32I-NEXT: lw a0, 56(sp)
; RV32I-NEXT: sw a0, 8(sp)
; RV32I-NEXT: addi a0, sp, 8
; RV32I-NEXT: sw a1, 8(sp)
; RV32I-NEXT: call __fixtfsi
; RV32I-NEXT: lw ra, 76(sp)
; RV32I-NEXT: addi sp, sp, 80
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/RISCV/frame-info.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -38,12 +38,12 @@ define void @foo(i32 signext %size) {
; RV64-NEXT: .cfi_offset s0, -16
; RV64-NEXT: addi s0, sp, 16
; RV64-NEXT: .cfi_def_cfa s0, 0
; RV64-NEXT: addi a1, zero, 1
; RV64-NEXT: slli a1, a1, 33
; RV64-NEXT: addi a1, a1, -16
; RV64-NEXT: slli a0, a0, 32
; RV64-NEXT: srli a0, a0, 32
; RV64-NEXT: addi a0, a0, 15
; RV64-NEXT: addi a1, zero, 1
; RV64-NEXT: slli a1, a1, 33
; RV64-NEXT: addi a1, a1, -16
; RV64-NEXT: and a0, a0, a1
; RV64-NEXT: sub a0, sp, a0
; RV64-NEXT: mv sp, a0
Expand Down
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/RISCV/get-setcc-result-type.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -6,21 +6,21 @@ define void @getSetCCResultType(<4 x i32>* %p, <4 x i32>* %q) nounwind {
; RV32I-LABEL: getSetCCResultType:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: lw a1, 12(a0)
; RV32I-NEXT: lw a2, 8(a0)
; RV32I-NEXT: lw a3, 4(a0)
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: seqz a3, a3
; RV32I-NEXT: seqz a4, a4
; RV32I-NEXT: neg a4, a4
; RV32I-NEXT: neg a3, a3
; RV32I-NEXT: neg a2, a2
; RV32I-NEXT: neg a1, a1
; RV32I-NEXT: sw a1, 12(a0)
; RV32I-NEXT: lw a1, 8(a0)
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: neg a1, a1
; RV32I-NEXT: sw a1, 8(a0)
; RV32I-NEXT: lw a1, 4(a0)
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: neg a1, a1
; RV32I-NEXT: sw a1, 4(a0)
; RV32I-NEXT: lw a1, 0(a0)
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: neg a1, a1
; RV32I-NEXT: sw a1, 0(a0)
; RV32I-NEXT: sw a2, 8(a0)
; RV32I-NEXT: sw a3, 4(a0)
; RV32I-NEXT: sw a4, 0(a0)
; RV32I-NEXT: ret
entry:
%0 = load <4 x i32>, <4 x i32>* %p, align 16
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -12,10 +12,10 @@ define dso_local void @multiple_stores() local_unnamed_addr nounwind {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lui a0, %hi(s)
; CHECK-NEXT: addi a0, a0, %lo(s)
; CHECK-NEXT: addi a1, zero, 20
; CHECK-NEXT: sw a1, 164(a0)
; CHECK-NEXT: addi a1, zero, 10
; CHECK-NEXT: sw a1, 160(a0)
; CHECK-NEXT: addi a1, zero, 20
; CHECK-NEXT: sw a1, 164(a0)
; CHECK-NEXT: ret
entry:
store i32 10, i32* getelementptr inbounds (%struct.S, %struct.S* @s, i32 0, i32 1), align 4
Expand Down
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/RISCV/imm-cse.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -10,19 +10,19 @@
define void @imm32_cse() nounwind {
; RV32I-LABEL: imm32_cse:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a0, 1
; RV32I-NEXT: addi a0, a0, 1
; RV32I-NEXT: lui a1, %hi(src)
; RV32I-NEXT: lw a2, %lo(src)(a1)
; RV32I-NEXT: add a2, a2, a0
; RV32I-NEXT: lui a3, %hi(dst)
; RV32I-NEXT: sw a2, %lo(dst)(a3)
; RV32I-NEXT: lw a2, %lo(src)(a1)
; RV32I-NEXT: add a2, a2, a0
; RV32I-NEXT: lui a0, %hi(src)
; RV32I-NEXT: lw a1, %lo(src)(a0)
; RV32I-NEXT: lui a2, 1
; RV32I-NEXT: addi a2, a2, 1
; RV32I-NEXT: sw a2, %lo(dst)(a3)
; RV32I-NEXT: lw a1, %lo(src)(a1)
; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: add a1, a1, a2
; RV32I-NEXT: lui a3, %hi(dst)
; RV32I-NEXT: sw a1, %lo(dst)(a3)
; RV32I-NEXT: lw a1, %lo(src)(a0)
; RV32I-NEXT: add a1, a1, a2
; RV32I-NEXT: addi a1, a1, 1
; RV32I-NEXT: sw a1, %lo(dst)(a3)
; RV32I-NEXT: lw a0, %lo(src)(a0)
; RV32I-NEXT: add a0, a0, a2
; RV32I-NEXT: addi a0, a0, 2
; RV32I-NEXT: sw a0, %lo(dst)(a3)
; RV32I-NEXT: ret
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/imm.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -142,8 +142,8 @@ define i64 @imm64_2() nounwind {
define i64 @imm64_3() nounwind {
; RV32I-LABEL: imm64_3:
; RV32I: # %bb.0:
; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: addi a1, zero, 1
; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: ret
;
; RV64I-LABEL: imm64_3:
Expand All @@ -157,8 +157,8 @@ define i64 @imm64_3() nounwind {
define i64 @imm64_4() nounwind {
; RV32I-LABEL: imm64_4:
; RV32I: # %bb.0:
; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: ret
;
; RV64I-LABEL: imm64_4:
Expand All @@ -172,8 +172,8 @@ define i64 @imm64_4() nounwind {
define i64 @imm64_5() nounwind {
; RV32I-LABEL: imm64_5:
; RV32I: # %bb.0:
; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: ret
;
; RV64I-LABEL: imm64_5:
Expand Down Expand Up @@ -249,7 +249,7 @@ define i64 @imm64_9() nounwind {
; RV32I-LABEL: imm64_9:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a0, zero, -1
; RV32I-NEXT: addi a1, zero, -1
; RV32I-NEXT: addi a1, zero, -1
; RV32I-NEXT: ret
;
; RV64I-LABEL: imm64_9:
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/indirectbr.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@ define i32 @indirectbr(i8* %target) nounwind {
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: jr a0
; RV32I-NEXT: .LBB0_1:
; RV32I-NEXT: .LBB0_1: # %test_label
; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
Expand All @@ -26,7 +26,7 @@ define i32 @indirectbr_with_offset(i8* %a) nounwind {
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: jr 1380(a0)
; RV32I-NEXT: .LBB1_1:
; RV32I-NEXT: .LBB1_1: # %test_label
; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -26,11 +26,11 @@ define double @constraint_f_double(double %a) nounwind {
;
; RV64F-LABEL: constraint_f_double:
; RV64F: # %bb.0:
; RV64F-NEXT: fmv.d.x ft0, a0
; RV64F-NEXT: lui a0, %hi(gd)
; RV64F-NEXT: fld ft1, %lo(gd)(a0)
; RV64F-NEXT: lui a1, %hi(gd)
; RV64F-NEXT: fld ft0, %lo(gd)(a1)
; RV64F-NEXT: fmv.d.x ft1, a0
; RV64F-NEXT: #APP
; RV64F-NEXT: fadd.d ft0, ft0, ft1
; RV64F-NEXT: fadd.d ft0, ft1, ft0
; RV64F-NEXT: #NO_APP
; RV64F-NEXT: fmv.x.d a0, ft0
; RV64F-NEXT: ret
Expand Down Expand Up @@ -59,9 +59,9 @@ define double @constraint_f_double_abi_name(double %a) nounwind {
;
; RV64F-LABEL: constraint_f_double_abi_name:
; RV64F: # %bb.0:
; RV64F-NEXT: lui a1, %hi(gd)
; RV64F-NEXT: fld fs0, %lo(gd)(a1)
; RV64F-NEXT: fmv.d.x fa1, a0
; RV64F-NEXT: lui a0, %hi(gd)
; RV64F-NEXT: fld fs0, %lo(gd)(a0)
; RV64F-NEXT: #APP
; RV64F-NEXT: fadd.d ft0, fa1, fs0
; RV64F-NEXT: #NO_APP
Expand Down
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -9,22 +9,22 @@
define float @constraint_f_float(float %a) nounwind {
; RV32F-LABEL: constraint_f_float:
; RV32F: # %bb.0:
; RV32F-NEXT: fmv.w.x ft0, a0
; RV32F-NEXT: lui a0, %hi(gf)
; RV32F-NEXT: flw ft1, %lo(gf)(a0)
; RV32F-NEXT: lui a1, %hi(gf)
; RV32F-NEXT: flw ft0, %lo(gf)(a1)
; RV32F-NEXT: fmv.w.x ft1, a0
; RV32F-NEXT: #APP
; RV32F-NEXT: fadd.s ft0, ft0, ft1
; RV32F-NEXT: fadd.s ft0, ft1, ft0
; RV32F-NEXT: #NO_APP
; RV32F-NEXT: fmv.x.w a0, ft0
; RV32F-NEXT: ret
;
; RV64F-LABEL: constraint_f_float:
; RV64F: # %bb.0:
; RV64F-NEXT: fmv.w.x ft0, a0
; RV64F-NEXT: lui a0, %hi(gf)
; RV64F-NEXT: flw ft1, %lo(gf)(a0)
; RV64F-NEXT: lui a1, %hi(gf)
; RV64F-NEXT: flw ft0, %lo(gf)(a1)
; RV64F-NEXT: fmv.w.x ft1, a0
; RV64F-NEXT: #APP
; RV64F-NEXT: fadd.s ft0, ft0, ft1
; RV64F-NEXT: fadd.s ft0, ft1, ft0
; RV64F-NEXT: #NO_APP
; RV64F-NEXT: fmv.x.w a0, ft0
; RV64F-NEXT: ret
Expand All @@ -36,9 +36,9 @@ define float @constraint_f_float(float %a) nounwind {
define float @constraint_f_float_abi_name(float %a) nounwind {
; RV32F-LABEL: constraint_f_float_abi_name:
; RV32F: # %bb.0:
; RV32F-NEXT: lui a1, %hi(gf)
; RV32F-NEXT: flw fs0, %lo(gf)(a1)
; RV32F-NEXT: fmv.w.x fa0, a0
; RV32F-NEXT: lui a0, %hi(gf)
; RV32F-NEXT: flw fs0, %lo(gf)(a0)
; RV32F-NEXT: #APP
; RV32F-NEXT: fadd.s ft0, fa0, fs0
; RV32F-NEXT: #NO_APP
Expand All @@ -47,9 +47,9 @@ define float @constraint_f_float_abi_name(float %a) nounwind {
;
; RV64F-LABEL: constraint_f_float_abi_name:
; RV64F: # %bb.0:
; RV64F-NEXT: lui a1, %hi(gf)
; RV64F-NEXT: flw fs0, %lo(gf)(a1)
; RV64F-NEXT: fmv.w.x fa0, a0
; RV64F-NEXT: lui a0, %hi(gf)
; RV64F-NEXT: flw fs0, %lo(gf)(a0)
; RV64F-NEXT: #APP
; RV64F-NEXT: fadd.s ft0, fa0, fs0
; RV64F-NEXT: #NO_APP
Expand Down
48 changes: 24 additions & 24 deletions llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -213,11 +213,11 @@ define void @foo_float() nounwind #0 {
; CHECK-RV32IF-NEXT: sw a0, 12(sp)
; CHECK-RV32IF-NEXT: fsw ft0, 8(sp)
; CHECK-RV32IF-NEXT: fsw ft1, 4(sp)
; CHECK-RV32IF-NEXT: lui a0, %hi(f)
; CHECK-RV32IF-NEXT: flw ft0, %lo(f)(a0)
; CHECK-RV32IF-NEXT: lui a0, %hi(e)
; CHECK-RV32IF-NEXT: flw ft1, %lo(e)(a0)
; CHECK-RV32IF-NEXT: fadd.s ft0, ft1, ft0
; CHECK-RV32IF-NEXT: flw ft0, %lo(e)(a0)
; CHECK-RV32IF-NEXT: lui a0, %hi(f)
; CHECK-RV32IF-NEXT: flw ft1, %lo(f)(a0)
; CHECK-RV32IF-NEXT: fadd.s ft0, ft0, ft1
; CHECK-RV32IF-NEXT: lui a0, %hi(d)
; CHECK-RV32IF-NEXT: fsw ft0, %lo(d)(a0)
; CHECK-RV32IF-NEXT: flw ft1, 4(sp)
Expand All @@ -232,11 +232,11 @@ define void @foo_float() nounwind #0 {
; CHECK-RV32IFD-NEXT: sw a0, 28(sp)
; CHECK-RV32IFD-NEXT: fsd ft0, 16(sp)
; CHECK-RV32IFD-NEXT: fsd ft1, 8(sp)
; CHECK-RV32IFD-NEXT: lui a0, %hi(f)
; CHECK-RV32IFD-NEXT: flw ft0, %lo(f)(a0)
; CHECK-RV32IFD-NEXT: lui a0, %hi(e)
; CHECK-RV32IFD-NEXT: flw ft1, %lo(e)(a0)
; CHECK-RV32IFD-NEXT: fadd.s ft0, ft1, ft0
; CHECK-RV32IFD-NEXT: flw ft0, %lo(e)(a0)
; CHECK-RV32IFD-NEXT: lui a0, %hi(f)
; CHECK-RV32IFD-NEXT: flw ft1, %lo(f)(a0)
; CHECK-RV32IFD-NEXT: fadd.s ft0, ft0, ft1
; CHECK-RV32IFD-NEXT: lui a0, %hi(d)
; CHECK-RV32IFD-NEXT: fsw ft0, %lo(d)(a0)
; CHECK-RV32IFD-NEXT: fld ft1, 8(sp)
Expand Down Expand Up @@ -312,11 +312,11 @@ define void @foo_fp_float() nounwind #1 {
; CHECK-RV32IF-NEXT: fsw ft0, 16(sp)
; CHECK-RV32IF-NEXT: fsw ft1, 12(sp)
; CHECK-RV32IF-NEXT: addi s0, sp, 32
; CHECK-RV32IF-NEXT: lui a0, %hi(f)
; CHECK-RV32IF-NEXT: flw ft0, %lo(f)(a0)
; CHECK-RV32IF-NEXT: lui a0, %hi(e)
; CHECK-RV32IF-NEXT: flw ft1, %lo(e)(a0)
; CHECK-RV32IF-NEXT: fadd.s ft0, ft1, ft0
; CHECK-RV32IF-NEXT: flw ft0, %lo(e)(a0)
; CHECK-RV32IF-NEXT: lui a0, %hi(f)
; CHECK-RV32IF-NEXT: flw ft1, %lo(f)(a0)
; CHECK-RV32IF-NEXT: fadd.s ft0, ft0, ft1
; CHECK-RV32IF-NEXT: lui a0, %hi(d)
; CHECK-RV32IF-NEXT: fsw ft0, %lo(d)(a0)
; CHECK-RV32IF-NEXT: flw ft1, 12(sp)
Expand All @@ -336,11 +336,11 @@ define void @foo_fp_float() nounwind #1 {
; CHECK-RV32IFD-NEXT: fsd ft0, 8(sp)
; CHECK-RV32IFD-NEXT: fsd ft1, 0(sp)
; CHECK-RV32IFD-NEXT: addi s0, sp, 32
; CHECK-RV32IFD-NEXT: lui a0, %hi(f)
; CHECK-RV32IFD-NEXT: flw ft0, %lo(f)(a0)
; CHECK-RV32IFD-NEXT: lui a0, %hi(e)
; CHECK-RV32IFD-NEXT: flw ft1, %lo(e)(a0)
; CHECK-RV32IFD-NEXT: fadd.s ft0, ft1, ft0
; CHECK-RV32IFD-NEXT: flw ft0, %lo(e)(a0)
; CHECK-RV32IFD-NEXT: lui a0, %hi(f)
; CHECK-RV32IFD-NEXT: flw ft1, %lo(f)(a0)
; CHECK-RV32IFD-NEXT: fadd.s ft0, ft0, ft1
; CHECK-RV32IFD-NEXT: lui a0, %hi(d)
; CHECK-RV32IFD-NEXT: fsw ft0, %lo(d)(a0)
; CHECK-RV32IFD-NEXT: fld ft1, 0(sp)
Expand Down Expand Up @@ -534,11 +534,11 @@ define void @foo_double() nounwind #0 {
; CHECK-RV32IFD-NEXT: sw a0, 28(sp)
; CHECK-RV32IFD-NEXT: fsd ft0, 16(sp)
; CHECK-RV32IFD-NEXT: fsd ft1, 8(sp)
; CHECK-RV32IFD-NEXT: lui a0, %hi(i)
; CHECK-RV32IFD-NEXT: fld ft0, %lo(i)(a0)
; CHECK-RV32IFD-NEXT: lui a0, %hi(h)
; CHECK-RV32IFD-NEXT: fld ft1, %lo(h)(a0)
; CHECK-RV32IFD-NEXT: fadd.d ft0, ft1, ft0
; CHECK-RV32IFD-NEXT: fld ft0, %lo(h)(a0)
; CHECK-RV32IFD-NEXT: lui a0, %hi(i)
; CHECK-RV32IFD-NEXT: fld ft1, %lo(i)(a0)
; CHECK-RV32IFD-NEXT: fadd.d ft0, ft0, ft1
; CHECK-RV32IFD-NEXT: lui a0, %hi(g)
; CHECK-RV32IFD-NEXT: fsd ft0, %lo(g)(a0)
; CHECK-RV32IFD-NEXT: fld ft1, 8(sp)
Expand Down Expand Up @@ -738,11 +738,11 @@ define void @foo_fp_double() nounwind #1 {
; CHECK-RV32IFD-NEXT: fsd ft0, 8(sp)
; CHECK-RV32IFD-NEXT: fsd ft1, 0(sp)
; CHECK-RV32IFD-NEXT: addi s0, sp, 32
; CHECK-RV32IFD-NEXT: lui a0, %hi(i)
; CHECK-RV32IFD-NEXT: fld ft0, %lo(i)(a0)
; CHECK-RV32IFD-NEXT: lui a0, %hi(h)
; CHECK-RV32IFD-NEXT: fld ft1, %lo(h)(a0)
; CHECK-RV32IFD-NEXT: fadd.d ft0, ft1, ft0
; CHECK-RV32IFD-NEXT: fld ft0, %lo(h)(a0)
; CHECK-RV32IFD-NEXT: lui a0, %hi(i)
; CHECK-RV32IFD-NEXT: fld ft1, %lo(i)(a0)
; CHECK-RV32IFD-NEXT: fadd.d ft0, ft0, ft1
; CHECK-RV32IFD-NEXT: lui a0, %hi(g)
; CHECK-RV32IFD-NEXT: fsd ft0, %lo(g)(a0)
; CHECK-RV32IFD-NEXT: fld ft1, 0(sp)
Expand Down
38 changes: 19 additions & 19 deletions llvm/test/CodeGen/RISCV/legalize-fneg.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,9 +15,9 @@ define void @test1(float* %a, float* %b) nounwind {
;
; RV64-LABEL: test1:
; RV64: # %bb.0: # %entry
; RV64-NEXT: lw a1, 0(a1)
; RV64-NEXT: addi a2, zero, 1
; RV64-NEXT: slli a2, a2, 31
; RV64-NEXT: lw a1, 0(a1)
; RV64-NEXT: xor a1, a1, a2
; RV64-NEXT: sw a1, 0(a0)
; RV64-NEXT: ret
Expand All @@ -33,17 +33,17 @@ define void @test2(double* %a, double* %b) nounwind {
; RV32: # %bb.0: # %entry
; RV32-NEXT: lw a2, 4(a1)
; RV32-NEXT: lw a1, 0(a1)
; RV32-NEXT: lui a3, 524288
; RV32-NEXT: xor a2, a2, a3
; RV32-NEXT: sw a1, 0(a0)
; RV32-NEXT: lui a1, 524288
; RV32-NEXT: xor a1, a2, a1
; RV32-NEXT: sw a1, 4(a0)
; RV32-NEXT: sw a2, 4(a0)
; RV32-NEXT: ret
;
; RV64-LABEL: test2:
; RV64: # %bb.0: # %entry
; RV64-NEXT: ld a1, 0(a1)
; RV64-NEXT: addi a2, zero, -1
; RV64-NEXT: slli a2, a2, 63
; RV64-NEXT: ld a1, 0(a1)
; RV64-NEXT: xor a1, a1, a2
; RV64-NEXT: sd a1, 0(a0)
; RV64-NEXT: ret
Expand All @@ -57,27 +57,27 @@ entry:
define void @test3(fp128* %a, fp128* %b) nounwind {
; RV32-LABEL: test3:
; RV32: # %bb.0: # %entry
; RV32-NEXT: lw a2, 12(a1)
; RV32-NEXT: lw a3, 4(a1)
; RV32-NEXT: lw a4, 0(a1)
; RV32-NEXT: lw a1, 8(a1)
; RV32-NEXT: sw a1, 8(a0)
; RV32-NEXT: sw a4, 0(a0)
; RV32-NEXT: sw a3, 4(a0)
; RV32-NEXT: lui a1, 524288
; RV32-NEXT: xor a1, a2, a1
; RV32-NEXT: sw a1, 12(a0)
; RV32-NEXT: lw a2, 4(a1)
; RV32-NEXT: lw a3, 12(a1)
; RV32-NEXT: lw a4, 8(a1)
; RV32-NEXT: lw a1, 0(a1)
; RV32-NEXT: lui a5, 524288
; RV32-NEXT: xor a3, a3, a5
; RV32-NEXT: sw a4, 8(a0)
; RV32-NEXT: sw a1, 0(a0)
; RV32-NEXT: sw a2, 4(a0)
; RV32-NEXT: sw a3, 12(a0)
; RV32-NEXT: ret
;
; RV64-LABEL: test3:
; RV64: # %bb.0: # %entry
; RV64-NEXT: ld a2, 8(a1)
; RV64-NEXT: ld a1, 0(a1)
; RV64-NEXT: addi a3, zero, -1
; RV64-NEXT: slli a3, a3, 63
; RV64-NEXT: xor a2, a2, a3
; RV64-NEXT: sd a1, 0(a0)
; RV64-NEXT: addi a1, zero, -1
; RV64-NEXT: slli a1, a1, 63
; RV64-NEXT: xor a1, a2, a1
; RV64-NEXT: sd a1, 8(a0)
; RV64-NEXT: sd a2, 8(a0)
; RV64-NEXT: ret
entry:
%0 = load fp128, fp128* %b
Expand Down
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/RISCV/lsr-legaladdimm.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11,21 +11,21 @@
define i32 @main() nounwind {
; RV32I-LABEL: main:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: lui a0, %hi(b)
; RV32I-NEXT: addi a0, a0, %lo(b)
; RV32I-NEXT: lui a1, %hi(a)
; RV32I-NEXT: addi a1, a1, %lo(a)
; RV32I-NEXT: lui a2, 1
; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: lui a1, %hi(b)
; RV32I-NEXT: addi a1, a1, %lo(b)
; RV32I-NEXT: lui a2, %hi(a)
; RV32I-NEXT: addi a2, a2, %lo(a)
; RV32I-NEXT: lui a3, 1
; RV32I-NEXT: .LBB0_1: # %for.body
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: addi a4, a3, -2048
; RV32I-NEXT: sw a4, 0(a1)
; RV32I-NEXT: addi a4, a0, -2048
; RV32I-NEXT: sw a4, 0(a2)
; RV32I-NEXT: sw a0, 0(a1)
; RV32I-NEXT: addi a0, a0, 1
; RV32I-NEXT: addi a1, a1, 4
; RV32I-NEXT: sw a3, 0(a0)
; RV32I-NEXT: addi a0, a0, 4
; RV32I-NEXT: addi a3, a3, 1
; RV32I-NEXT: bne a3, a2, .LBB0_1
; RV32I-NEXT: addi a2, a2, 4
; RV32I-NEXT: bne a0, a3, .LBB0_1
; RV32I-NEXT: # %bb.2: # %for.end
; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: ret
Expand Down
45 changes: 24 additions & 21 deletions llvm/test/CodeGen/RISCV/mem.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,8 +7,9 @@
define i32 @lb(i8 *%a) nounwind {
; RV32I-LABEL: lb:
; RV32I: # %bb.0:
; RV32I-NEXT: lb a1, 0(a0)
; RV32I-NEXT: lb a0, 1(a0)
; RV32I-NEXT: lb a1, 1(a0)
; RV32I-NEXT: lb a0, 0(a0)
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: ret
%1 = getelementptr i8, i8* %a, i32 1
%2 = load i8, i8* %1
Expand All @@ -21,8 +22,9 @@ define i32 @lb(i8 *%a) nounwind {
define i32 @lh(i16 *%a) nounwind {
; RV32I-LABEL: lh:
; RV32I: # %bb.0:
; RV32I-NEXT: lh a1, 0(a0)
; RV32I-NEXT: lh a0, 4(a0)
; RV32I-NEXT: lh a1, 4(a0)
; RV32I-NEXT: lh a0, 0(a0)
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: ret
%1 = getelementptr i16, i16* %a, i32 2
%2 = load i16, i16* %1
Expand All @@ -35,8 +37,9 @@ define i32 @lh(i16 *%a) nounwind {
define i32 @lw(i32 *%a) nounwind {
; RV32I-LABEL: lw:
; RV32I: # %bb.0:
; RV32I-NEXT: lw a1, 0(a0)
; RV32I-NEXT: lw a0, 12(a0)
; RV32I-NEXT: lw a1, 12(a0)
; RV32I-NEXT: lw a0, 0(a0)
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: ret
%1 = getelementptr i32, i32* %a, i32 3
%2 = load i32, i32* %1
Expand All @@ -47,9 +50,9 @@ define i32 @lw(i32 *%a) nounwind {
define i32 @lbu(i8 *%a) nounwind {
; RV32I-LABEL: lbu:
; RV32I: # %bb.0:
; RV32I-NEXT: lbu a1, 0(a0)
; RV32I-NEXT: lbu a0, 4(a0)
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: lbu a1, 4(a0)
; RV32I-NEXT: lbu a0, 0(a0)
; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: ret
%1 = getelementptr i8, i8* %a, i32 4
%2 = load i8, i8* %1
Expand All @@ -63,9 +66,9 @@ define i32 @lbu(i8 *%a) nounwind {
define i32 @lhu(i16 *%a) nounwind {
; RV32I-LABEL: lhu:
; RV32I: # %bb.0:
; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lhu a0, 10(a0)
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: lhu a1, 10(a0)
; RV32I-NEXT: lhu a0, 0(a0)
; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: ret
%1 = getelementptr i16, i16* %a, i32 5
%2 = load i16, i16* %1
Expand All @@ -81,8 +84,8 @@ define i32 @lhu(i16 *%a) nounwind {
define void @sb(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: sb:
; RV32I: # %bb.0:
; RV32I-NEXT: sb a1, 6(a0)
; RV32I-NEXT: sb a1, 0(a0)
; RV32I-NEXT: sb a1, 6(a0)
; RV32I-NEXT: ret
store i8 %b, i8* %a
%1 = getelementptr i8, i8* %a, i32 6
Expand All @@ -93,8 +96,8 @@ define void @sb(i8 *%a, i8 %b) nounwind {
define void @sh(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: sh:
; RV32I: # %bb.0:
; RV32I-NEXT: sh a1, 14(a0)
; RV32I-NEXT: sh a1, 0(a0)
; RV32I-NEXT: sh a1, 14(a0)
; RV32I-NEXT: ret
store i16 %b, i16* %a
%1 = getelementptr i16, i16* %a, i32 7
Expand All @@ -105,8 +108,8 @@ define void @sh(i16 *%a, i16 %b) nounwind {
define void @sw(i32 *%a, i32 %b) nounwind {
; RV32I-LABEL: sw:
; RV32I: # %bb.0:
; RV32I-NEXT: sw a1, 32(a0)
; RV32I-NEXT: sw a1, 0(a0)
; RV32I-NEXT: sw a1, 32(a0)
; RV32I-NEXT: ret
store i32 %b, i32* %a
%1 = getelementptr i32, i32* %a, i32 8
Expand All @@ -118,10 +121,10 @@ define void @sw(i32 *%a, i32 %b) nounwind {
define i32 @load_sext_zext_anyext_i1(i1 *%a) nounwind {
; RV32I-LABEL: load_sext_zext_anyext_i1:
; RV32I: # %bb.0:
; RV32I-NEXT: lb a1, 0(a0)
; RV32I-NEXT: lbu a1, 1(a0)
; RV32I-NEXT: lbu a0, 2(a0)
; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lbu a2, 2(a0)
; RV32I-NEXT: lb a0, 0(a0)
; RV32I-NEXT: sub a0, a2, a1
; RV32I-NEXT: ret
; sextload i1
%1 = getelementptr i1, i1* %a, i32 1
Expand All @@ -140,10 +143,10 @@ define i32 @load_sext_zext_anyext_i1(i1 *%a) nounwind {
define i16 @load_sext_zext_anyext_i1_i16(i1 *%a) nounwind {
; RV32I-LABEL: load_sext_zext_anyext_i1_i16:
; RV32I: # %bb.0:
; RV32I-NEXT: lb a1, 0(a0)
; RV32I-NEXT: lbu a1, 1(a0)
; RV32I-NEXT: lbu a0, 2(a0)
; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lbu a2, 2(a0)
; RV32I-NEXT: lb a0, 0(a0)
; RV32I-NEXT: sub a0, a2, a1
; RV32I-NEXT: ret
; sextload i1
%1 = getelementptr i1, i1* %a, i32 1
Expand Down
58 changes: 31 additions & 27 deletions llvm/test/CodeGen/RISCV/mem64.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,8 +7,9 @@
define i64 @lb(i8 *%a) nounwind {
; RV64I-LABEL: lb:
; RV64I: # %bb.0:
; RV64I-NEXT: lb a1, 0(a0)
; RV64I-NEXT: lb a0, 1(a0)
; RV64I-NEXT: lb a1, 1(a0)
; RV64I-NEXT: lb a0, 0(a0)
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ret
%1 = getelementptr i8, i8* %a, i32 1
%2 = load i8, i8* %1
Expand All @@ -21,8 +22,9 @@ define i64 @lb(i8 *%a) nounwind {
define i64 @lh(i16 *%a) nounwind {
; RV64I-LABEL: lh:
; RV64I: # %bb.0:
; RV64I-NEXT: lh a1, 0(a0)
; RV64I-NEXT: lh a0, 4(a0)
; RV64I-NEXT: lh a1, 4(a0)
; RV64I-NEXT: lh a0, 0(a0)
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ret
%1 = getelementptr i16, i16* %a, i32 2
%2 = load i16, i16* %1
Expand All @@ -35,8 +37,9 @@ define i64 @lh(i16 *%a) nounwind {
define i64 @lw(i32 *%a) nounwind {
; RV64I-LABEL: lw:
; RV64I: # %bb.0:
; RV64I-NEXT: lw a1, 0(a0)
; RV64I-NEXT: lw a0, 12(a0)
; RV64I-NEXT: lw a1, 12(a0)
; RV64I-NEXT: lw a0, 0(a0)
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ret
%1 = getelementptr i32, i32* %a, i32 3
%2 = load i32, i32* %1
Expand All @@ -49,9 +52,9 @@ define i64 @lw(i32 *%a) nounwind {
define i64 @lbu(i8 *%a) nounwind {
; RV64I-LABEL: lbu:
; RV64I: # %bb.0:
; RV64I-NEXT: lbu a1, 0(a0)
; RV64I-NEXT: lbu a0, 4(a0)
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: lbu a1, 4(a0)
; RV64I-NEXT: lbu a0, 0(a0)
; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: ret
%1 = getelementptr i8, i8* %a, i32 4
%2 = load i8, i8* %1
Expand All @@ -65,9 +68,9 @@ define i64 @lbu(i8 *%a) nounwind {
define i64 @lhu(i16 *%a) nounwind {
; RV64I-LABEL: lhu:
; RV64I: # %bb.0:
; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lhu a0, 10(a0)
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: lhu a1, 10(a0)
; RV64I-NEXT: lhu a0, 0(a0)
; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: ret
%1 = getelementptr i16, i16* %a, i32 5
%2 = load i16, i16* %1
Expand All @@ -81,9 +84,9 @@ define i64 @lhu(i16 *%a) nounwind {
define i64 @lwu(i32 *%a) nounwind {
; RV64I-LABEL: lwu:
; RV64I: # %bb.0:
; RV64I-NEXT: lwu a1, 0(a0)
; RV64I-NEXT: lwu a0, 24(a0)
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: lwu a1, 24(a0)
; RV64I-NEXT: lwu a0, 0(a0)
; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: ret
%1 = getelementptr i32, i32* %a, i32 6
%2 = load i32, i32* %1
Expand All @@ -99,8 +102,8 @@ define i64 @lwu(i32 *%a) nounwind {
define void @sb(i8 *%a, i8 %b) nounwind {
; RV64I-LABEL: sb:
; RV64I: # %bb.0:
; RV64I-NEXT: sb a1, 7(a0)
; RV64I-NEXT: sb a1, 0(a0)
; RV64I-NEXT: sb a1, 7(a0)
; RV64I-NEXT: ret
store i8 %b, i8* %a
%1 = getelementptr i8, i8* %a, i32 7
Expand All @@ -111,8 +114,8 @@ define void @sb(i8 *%a, i8 %b) nounwind {
define void @sh(i16 *%a, i16 %b) nounwind {
; RV64I-LABEL: sh:
; RV64I: # %bb.0:
; RV64I-NEXT: sh a1, 16(a0)
; RV64I-NEXT: sh a1, 0(a0)
; RV64I-NEXT: sh a1, 16(a0)
; RV64I-NEXT: ret
store i16 %b, i16* %a
%1 = getelementptr i16, i16* %a, i32 8
Expand All @@ -123,8 +126,8 @@ define void @sh(i16 *%a, i16 %b) nounwind {
define void @sw(i32 *%a, i32 %b) nounwind {
; RV64I-LABEL: sw:
; RV64I: # %bb.0:
; RV64I-NEXT: sw a1, 36(a0)
; RV64I-NEXT: sw a1, 0(a0)
; RV64I-NEXT: sw a1, 36(a0)
; RV64I-NEXT: ret
store i32 %b, i32* %a
%1 = getelementptr i32, i32* %a, i32 9
Expand All @@ -137,8 +140,9 @@ define void @sw(i32 *%a, i32 %b) nounwind {
define i64 @ld(i64 *%a) nounwind {
; RV64I-LABEL: ld:
; RV64I: # %bb.0:
; RV64I-NEXT: ld a1, 0(a0)
; RV64I-NEXT: ld a0, 80(a0)
; RV64I-NEXT: ld a1, 80(a0)
; RV64I-NEXT: ld a0, 0(a0)
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ret
%1 = getelementptr i64, i64* %a, i32 10
%2 = load i64, i64* %1
Expand All @@ -149,8 +153,8 @@ define i64 @ld(i64 *%a) nounwind {
define void @sd(i64 *%a, i64 %b) nounwind {
; RV64I-LABEL: sd:
; RV64I: # %bb.0:
; RV64I-NEXT: sd a1, 88(a0)
; RV64I-NEXT: sd a1, 0(a0)
; RV64I-NEXT: sd a1, 88(a0)
; RV64I-NEXT: ret
store i64 %b, i64* %a
%1 = getelementptr i64, i64* %a, i32 11
Expand All @@ -162,10 +166,10 @@ define void @sd(i64 *%a, i64 %b) nounwind {
define i64 @load_sext_zext_anyext_i1(i1 *%a) nounwind {
; RV64I-LABEL: load_sext_zext_anyext_i1:
; RV64I: # %bb.0:
; RV64I-NEXT: lb a1, 0(a0)
; RV64I-NEXT: lbu a1, 1(a0)
; RV64I-NEXT: lbu a0, 2(a0)
; RV64I-NEXT: sub a0, a0, a1
; RV64I-NEXT: lbu a2, 2(a0)
; RV64I-NEXT: lb a0, 0(a0)
; RV64I-NEXT: sub a0, a2, a1
; RV64I-NEXT: ret
; sextload i1
%1 = getelementptr i1, i1* %a, i32 1
Expand All @@ -184,10 +188,10 @@ define i64 @load_sext_zext_anyext_i1(i1 *%a) nounwind {
define i16 @load_sext_zext_anyext_i1_i16(i1 *%a) nounwind {
; RV64I-LABEL: load_sext_zext_anyext_i1_i16:
; RV64I: # %bb.0:
; RV64I-NEXT: lb a1, 0(a0)
; RV64I-NEXT: lbu a1, 1(a0)
; RV64I-NEXT: lbu a0, 2(a0)
; RV64I-NEXT: sub a0, a0, a1
; RV64I-NEXT: lbu a2, 2(a0)
; RV64I-NEXT: lb a0, 0(a0)
; RV64I-NEXT: sub a0, a2, a1
; RV64I-NEXT: ret
; sextload i1
%1 = getelementptr i1, i1* %a, i32 1
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/mul.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -247,8 +247,8 @@ define i32 @mulhs(i32 %a, i32 %b) nounwind {
;
; RV64IM-LABEL: mulhs:
; RV64IM: # %bb.0:
; RV64IM-NEXT: sext.w a1, a1
; RV64IM-NEXT: sext.w a0, a0
; RV64IM-NEXT: sext.w a1, a1
; RV64IM-NEXT: mul a0, a0, a1
; RV64IM-NEXT: srli a0, a0, 32
; RV64IM-NEXT: ret
Expand Down
54 changes: 27 additions & 27 deletions llvm/test/CodeGen/RISCV/remat.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -37,39 +37,39 @@ define i32 @test() nounwind {
; RV32I-NEXT: sw s9, 20(sp)
; RV32I-NEXT: sw s10, 16(sp)
; RV32I-NEXT: sw s11, 12(sp)
; RV32I-NEXT: lui s9, %hi(a)
; RV32I-NEXT: lw a0, %lo(a)(s9)
; RV32I-NEXT: lui s6, %hi(a)
; RV32I-NEXT: lw a0, %lo(a)(s6)
; RV32I-NEXT: beqz a0, .LBB0_11
; RV32I-NEXT: # %bb.1: # %for.body.preheader
; RV32I-NEXT: lui s2, %hi(l)
; RV32I-NEXT: lui s3, %hi(k)
; RV32I-NEXT: lui s4, %hi(j)
; RV32I-NEXT: lui s6, %hi(i)
; RV32I-NEXT: lui s5, %hi(h)
; RV32I-NEXT: lui s7, %hi(g)
; RV32I-NEXT: lui s8, %hi(f)
; RV32I-NEXT: lui s1, %hi(e)
; RV32I-NEXT: lui s0, %hi(d)
; RV32I-NEXT: lui s5, %hi(i)
; RV32I-NEXT: lui s1, %hi(d)
; RV32I-NEXT: lui s0, %hi(e)
; RV32I-NEXT: lui s7, %hi(f)
; RV32I-NEXT: lui s8, %hi(g)
; RV32I-NEXT: lui s9, %hi(h)
; RV32I-NEXT: lui s10, %hi(c)
; RV32I-NEXT: lui s11, %hi(b)
; RV32I-NEXT: lw a1, %lo(l)(s2)
; RV32I-NEXT: bnez a1, .LBB0_4
; RV32I-NEXT: j .LBB0_5
; RV32I-NEXT: .LBB0_2: # %for.inc
; RV32I-NEXT: # in Loop: Header=BB0_5 Depth=1
; RV32I-NEXT: lw a0, %lo(a)(s9)
; RV32I-NEXT: lw a0, %lo(a)(s6)
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: sw a0, %lo(a)(s9)
; RV32I-NEXT: sw a0, %lo(a)(s6)
; RV32I-NEXT: beqz a0, .LBB0_11
; RV32I-NEXT: # %bb.3: # %for.body
; RV32I-NEXT: # in Loop: Header=BB0_5 Depth=1
; RV32I-NEXT: lw a1, %lo(l)(s2)
; RV32I-NEXT: beqz a1, .LBB0_5
; RV32I-NEXT: .LBB0_4: # %if.then
; RV32I-NEXT: lw a4, %lo(e)(s1)
; RV32I-NEXT: lw a3, %lo(d)(s0)
; RV32I-NEXT: lw a2, %lo(c)(s10)
; RV32I-NEXT: lw a1, %lo(b)(s11)
; RV32I-NEXT: lw a2, %lo(c)(s10)
; RV32I-NEXT: lw a3, %lo(d)(s1)
; RV32I-NEXT: lw a4, %lo(e)(s0)
; RV32I-NEXT: addi a5, zero, 32
; RV32I-NEXT: call foo
; RV32I-NEXT: .LBB0_5: # %if.end
Expand All @@ -78,11 +78,11 @@ define i32 @test() nounwind {
; RV32I-NEXT: beqz a0, .LBB0_7
; RV32I-NEXT: # %bb.6: # %if.then3
; RV32I-NEXT: # in Loop: Header=BB0_5 Depth=1
; RV32I-NEXT: lw a4, %lo(f)(s8)
; RV32I-NEXT: lw a3, %lo(e)(s1)
; RV32I-NEXT: lw a2, %lo(d)(s0)
; RV32I-NEXT: lw a1, %lo(c)(s10)
; RV32I-NEXT: lw a0, %lo(b)(s11)
; RV32I-NEXT: lw a1, %lo(c)(s10)
; RV32I-NEXT: lw a2, %lo(d)(s1)
; RV32I-NEXT: lw a3, %lo(e)(s0)
; RV32I-NEXT: lw a4, %lo(f)(s7)
; RV32I-NEXT: addi a5, zero, 64
; RV32I-NEXT: call foo
; RV32I-NEXT: .LBB0_7: # %if.end5
Expand All @@ -91,24 +91,24 @@ define i32 @test() nounwind {
; RV32I-NEXT: beqz a0, .LBB0_9
; RV32I-NEXT: # %bb.8: # %if.then7
; RV32I-NEXT: # in Loop: Header=BB0_5 Depth=1
; RV32I-NEXT: lw a4, %lo(g)(s7)
; RV32I-NEXT: lw a3, %lo(f)(s8)
; RV32I-NEXT: lw a2, %lo(e)(s1)
; RV32I-NEXT: lw a1, %lo(d)(s0)
; RV32I-NEXT: lw a0, %lo(c)(s10)
; RV32I-NEXT: lw a1, %lo(d)(s1)
; RV32I-NEXT: lw a2, %lo(e)(s0)
; RV32I-NEXT: lw a3, %lo(f)(s7)
; RV32I-NEXT: lw a4, %lo(g)(s8)
; RV32I-NEXT: addi a5, zero, 32
; RV32I-NEXT: call foo
; RV32I-NEXT: .LBB0_9: # %if.end9
; RV32I-NEXT: # in Loop: Header=BB0_5 Depth=1
; RV32I-NEXT: lw a0, %lo(i)(s6)
; RV32I-NEXT: lw a0, %lo(i)(s5)
; RV32I-NEXT: beqz a0, .LBB0_2
; RV32I-NEXT: # %bb.10: # %if.then11
; RV32I-NEXT: # in Loop: Header=BB0_5 Depth=1
; RV32I-NEXT: lw a4, %lo(h)(s5)
; RV32I-NEXT: lw a3, %lo(g)(s7)
; RV32I-NEXT: lw a2, %lo(f)(s8)
; RV32I-NEXT: lw a1, %lo(e)(s1)
; RV32I-NEXT: lw a0, %lo(d)(s0)
; RV32I-NEXT: lw a0, %lo(d)(s1)
; RV32I-NEXT: lw a1, %lo(e)(s0)
; RV32I-NEXT: lw a2, %lo(f)(s7)
; RV32I-NEXT: lw a3, %lo(g)(s8)
; RV32I-NEXT: lw a4, %lo(h)(s9)
; RV32I-NEXT: addi a5, zero, 32
; RV32I-NEXT: call foo
; RV32I-NEXT: j .LBB0_2
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/RISCV/rv64f-float-convert.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -113,9 +113,9 @@ define zeroext i32 @bcvt_f32_to_zext_i32(float %a, float %b) nounwind {
define float @bcvt_i64_to_f32_via_i32(i64 %a, i64 %b) nounwind {
; RV64IF-LABEL: bcvt_i64_to_f32_via_i32:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a1
; RV64IF-NEXT: fmv.w.x ft1, a0
; RV64IF-NEXT: fadd.s ft0, ft1, ft0
; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: fmv.w.x ft1, a1
; RV64IF-NEXT: fadd.s ft0, ft0, ft1
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
%1 = trunc i64 %a to i32
Expand Down
14 changes: 7 additions & 7 deletions llvm/test/CodeGen/RISCV/rv64i-complex-float.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,16 +13,16 @@ define i64 @complex_float_add(i64 %a.coerce, i64 %b.coerce) nounwind {
; CHECK-NEXT: sd s0, 16(sp)
; CHECK-NEXT: sd s1, 8(sp)
; CHECK-NEXT: sd s2, 0(sp)
; CHECK-NEXT: mv s0, a1
; CHECK-NEXT: mv s1, a0
; CHECK-NEXT: srli s2, a0, 32
; CHECK-NEXT: srli s1, a1, 32
; CHECK-NEXT: call __addsf3
; CHECK-NEXT: mv s2, a0
; CHECK-NEXT: srli a0, s1, 32
; CHECK-NEXT: srli a1, s0, 32
; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: mv a0, s2
; CHECK-NEXT: mv a1, s1
; CHECK-NEXT: call __addsf3
; CHECK-NEXT: slli a1, s2, 32
; CHECK-NEXT: srli a1, a1, 32
; CHECK-NEXT: slli a0, a0, 32
; CHECK-NEXT: slli a1, s0, 32
; CHECK-NEXT: srli a1, a1, 32
; CHECK-NEXT: or a0, a0, a1
; CHECK-NEXT: ld s2, 0(sp)
; CHECK-NEXT: ld s1, 8(sp)
Expand Down
36 changes: 18 additions & 18 deletions llvm/test/CodeGen/RISCV/rv64i-w-insts-legalization.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,17 +8,17 @@ define signext i32 @addw(i32 signext %s, i32 signext %n, i32 signext %k) nounwin
; CHECK-NEXT: # %bb.1: # %for.body.preheader
; CHECK-NEXT: not a2, a0
; CHECK-NEXT: add a2, a2, a1
; CHECK-NEXT: addi a3, a0, 1
; CHECK-NEXT: mul a3, a2, a3
; CHECK-NEXT: slli a2, a2, 32
; CHECK-NEXT: srli a2, a2, 32
; CHECK-NEXT: sub a1, a1, a0
; CHECK-NEXT: addi a1, a1, -2
; CHECK-NEXT: slli a1, a1, 32
; CHECK-NEXT: srli a1, a1, 32
; CHECK-NEXT: slli a3, a2, 32
; CHECK-NEXT: srli a3, a3, 32
; CHECK-NEXT: mul a1, a3, a1
; CHECK-NEXT: addi a3, a0, 1
; CHECK-NEXT: mul a2, a2, a3
; CHECK-NEXT: add a0, a2, a0
; CHECK-NEXT: mul a1, a2, a1
; CHECK-NEXT: srli a1, a1, 1
; CHECK-NEXT: add a0, a3, a0
; CHECK-NEXT: addw a0, a0, a1
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB0_2:
Expand Down Expand Up @@ -54,18 +54,18 @@ define signext i32 @subw(i32 signext %s, i32 signext %n, i32 signext %k) nounwin
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: bge a0, a1, .LBB1_2
; CHECK-NEXT: # %bb.1: # %for.body.preheader
; CHECK-NEXT: sub a2, a1, a0
; CHECK-NEXT: addi a2, a2, -2
; CHECK-NEXT: slli a2, a2, 32
; CHECK-NEXT: srli a2, a2, 32
; CHECK-NEXT: not a3, a0
; CHECK-NEXT: add a1, a3, a1
; CHECK-NEXT: slli a4, a1, 32
; CHECK-NEXT: srli a4, a4, 32
; CHECK-NEXT: mul a2, a4, a2
; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sub a0, a1, a0
; CHECK-NEXT: srli a1, a2, 1
; CHECK-NEXT: not a2, a0
; CHECK-NEXT: add a3, a2, a1
; CHECK-NEXT: mul a2, a3, a2
; CHECK-NEXT: slli a3, a3, 32
; CHECK-NEXT: srli a3, a3, 32
; CHECK-NEXT: sub a1, a1, a0
; CHECK-NEXT: addi a1, a1, -2
; CHECK-NEXT: slli a1, a1, 32
; CHECK-NEXT: srli a1, a1, 32
; CHECK-NEXT: mul a1, a3, a1
; CHECK-NEXT: srli a1, a1, 1
; CHECK-NEXT: sub a0, a2, a0
; CHECK-NEXT: subw a0, a0, a1
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB1_2:
Expand Down
146 changes: 86 additions & 60 deletions llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -40,27 +40,41 @@ define i128 @cmovcc128(i64 signext %a, i128 %b, i128 %c) nounwind {
; RV32I-LABEL: cmovcc128:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: xori a1, a1, 123
; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: beqz a1, .LBB1_2
; RV32I-NEXT: or a2, a1, a2
; RV32I-NEXT: mv a1, a3
; RV32I-NEXT: beqz a2, .LBB1_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: mv a1, a4
; RV32I-NEXT: .LBB1_2: # %entry
; RV32I-NEXT: lw a6, 0(a1)
; RV32I-NEXT: beqz a2, .LBB1_6
; RV32I-NEXT: # %bb.3: # %entry
; RV32I-NEXT: addi a1, a4, 4
; RV32I-NEXT: addi a2, a4, 8
; RV32I-NEXT: addi a5, a4, 12
; RV32I-NEXT: mv a3, a4
; RV32I-NEXT: j .LBB1_3
; RV32I-NEXT: .LBB1_2:
; RV32I-NEXT: lw a5, 0(a1)
; RV32I-NEXT: bnez a2, .LBB1_7
; RV32I-NEXT: .LBB1_4:
; RV32I-NEXT: addi a1, a3, 8
; RV32I-NEXT: lw a1, 0(a1)
; RV32I-NEXT: bnez a2, .LBB1_8
; RV32I-NEXT: .LBB1_5:
; RV32I-NEXT: addi a2, a3, 12
; RV32I-NEXT: j .LBB1_9
; RV32I-NEXT: .LBB1_6:
; RV32I-NEXT: addi a1, a3, 4
; RV32I-NEXT: addi a2, a3, 8
; RV32I-NEXT: addi a5, a3, 12
; RV32I-NEXT: .LBB1_3: # %entry
; RV32I-NEXT: lw a4, 0(a5)
; RV32I-NEXT: sw a4, 12(a0)
; RV32I-NEXT: lw a2, 0(a2)
; RV32I-NEXT: sw a2, 8(a0)
; RV32I-NEXT: lw a5, 0(a1)
; RV32I-NEXT: beqz a2, .LBB1_4
; RV32I-NEXT: .LBB1_7: # %entry
; RV32I-NEXT: addi a1, a4, 8
; RV32I-NEXT: lw a1, 0(a1)
; RV32I-NEXT: sw a1, 4(a0)
; RV32I-NEXT: lw a1, 0(a3)
; RV32I-NEXT: sw a1, 0(a0)
; RV32I-NEXT: beqz a2, .LBB1_5
; RV32I-NEXT: .LBB1_8: # %entry
; RV32I-NEXT: addi a2, a4, 12
; RV32I-NEXT: .LBB1_9: # %entry
; RV32I-NEXT: lw a2, 0(a2)
; RV32I-NEXT: sw a2, 12(a0)
; RV32I-NEXT: sw a1, 8(a0)
; RV32I-NEXT: sw a5, 4(a0)
; RV32I-NEXT: sw a6, 0(a0)
; RV32I-NEXT: ret
;
; RV64I-LABEL: cmovcc128:
Expand All @@ -83,24 +97,24 @@ entry:
define i64 @cmov64(i1 %a, i64 %b, i64 %c) nounwind {
; RV32I-LABEL: cmov64:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: bnez a0, .LBB2_2
; RV32I-NEXT: andi a5, a0, 1
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: bnez a5, .LBB2_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: mv a1, a3
; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: .LBB2_2: # %entry
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: mv a1, a2
; RV32I-NEXT: ret
;
; RV64I-LABEL: cmov64:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: bnez a0, .LBB2_2
; RV64I-NEXT: andi a3, a0, 1
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: bnez a3, .LBB2_2
; RV64I-NEXT: # %bb.1: # %entry
; RV64I-NEXT: mv a1, a2
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: .LBB2_2: # %entry
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ret
entry:
%cond = select i1 %a, i64 %b, i64 %c
Expand All @@ -110,38 +124,52 @@ entry:
define i128 @cmov128(i1 %a, i128 %b, i128 %c) nounwind {
; RV32I-LABEL: cmov128:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: andi a1, a1, 1
; RV32I-NEXT: bnez a1, .LBB3_2
; RV32I-NEXT: andi a4, a1, 1
; RV32I-NEXT: mv a1, a2
; RV32I-NEXT: bnez a4, .LBB3_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: mv a1, a3
; RV32I-NEXT: .LBB3_2: # %entry
; RV32I-NEXT: lw a6, 0(a1)
; RV32I-NEXT: bnez a4, .LBB3_6
; RV32I-NEXT: # %bb.3: # %entry
; RV32I-NEXT: addi a1, a3, 4
; RV32I-NEXT: addi a4, a3, 8
; RV32I-NEXT: addi a5, a3, 12
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: j .LBB3_3
; RV32I-NEXT: .LBB3_2:
; RV32I-NEXT: lw a5, 0(a1)
; RV32I-NEXT: beqz a4, .LBB3_7
; RV32I-NEXT: .LBB3_4:
; RV32I-NEXT: addi a1, a2, 8
; RV32I-NEXT: lw a1, 0(a1)
; RV32I-NEXT: beqz a4, .LBB3_8
; RV32I-NEXT: .LBB3_5:
; RV32I-NEXT: addi a2, a2, 12
; RV32I-NEXT: j .LBB3_9
; RV32I-NEXT: .LBB3_6:
; RV32I-NEXT: addi a1, a2, 4
; RV32I-NEXT: addi a4, a2, 8
; RV32I-NEXT: addi a5, a2, 12
; RV32I-NEXT: .LBB3_3: # %entry
; RV32I-NEXT: lw a3, 0(a5)
; RV32I-NEXT: sw a3, 12(a0)
; RV32I-NEXT: lw a3, 0(a4)
; RV32I-NEXT: sw a3, 8(a0)
; RV32I-NEXT: lw a5, 0(a1)
; RV32I-NEXT: bnez a4, .LBB3_4
; RV32I-NEXT: .LBB3_7: # %entry
; RV32I-NEXT: addi a1, a3, 8
; RV32I-NEXT: lw a1, 0(a1)
; RV32I-NEXT: sw a1, 4(a0)
; RV32I-NEXT: lw a1, 0(a2)
; RV32I-NEXT: sw a1, 0(a0)
; RV32I-NEXT: bnez a4, .LBB3_5
; RV32I-NEXT: .LBB3_8: # %entry
; RV32I-NEXT: addi a2, a3, 12
; RV32I-NEXT: .LBB3_9: # %entry
; RV32I-NEXT: lw a2, 0(a2)
; RV32I-NEXT: sw a2, 12(a0)
; RV32I-NEXT: sw a1, 8(a0)
; RV32I-NEXT: sw a5, 4(a0)
; RV32I-NEXT: sw a6, 0(a0)
; RV32I-NEXT: ret
;
; RV64I-LABEL: cmov128:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: bnez a0, .LBB3_2
; RV64I-NEXT: andi a5, a0, 1
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: bnez a5, .LBB3_2
; RV64I-NEXT: # %bb.1: # %entry
; RV64I-NEXT: mv a1, a3
; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: mv a2, a4
; RV64I-NEXT: .LBB3_2: # %entry
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: mv a1, a2
; RV64I-NEXT: ret
entry:
Expand Down Expand Up @@ -280,39 +308,37 @@ entry:
define i32 @cmovdiffcc(i1 %a, i1 %b, i32 %c, i32 %d, i32 %e, i32 %f) nounwind {
; RV32I-LABEL: cmovdiffcc:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: andi a1, a1, 1
; RV32I-NEXT: beqz a1, .LBB7_3
; RV32I-NEXT: beqz a0, .LBB7_3
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: beqz a0, .LBB7_4
; RV32I-NEXT: beqz a1, .LBB7_4
; RV32I-NEXT: .LBB7_2: # %entry
; RV32I-NEXT: add a0, a2, a4
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB7_3: # %entry
; RV32I-NEXT: mv a4, a5
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: bnez a0, .LBB7_2
; RV32I-NEXT: .LBB7_4: # %entry
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bnez a1, .LBB7_2
; RV32I-NEXT: .LBB7_4: # %entry
; RV32I-NEXT: mv a4, a5
; RV32I-NEXT: add a0, a2, a4
; RV32I-NEXT: ret
;
; RV64I-LABEL: cmovdiffcc:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: andi a1, a1, 1
; RV64I-NEXT: beqz a1, .LBB7_3
; RV64I-NEXT: beqz a0, .LBB7_3
; RV64I-NEXT: # %bb.1: # %entry
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: beqz a0, .LBB7_4
; RV64I-NEXT: beqz a1, .LBB7_4
; RV64I-NEXT: .LBB7_2: # %entry
; RV64I-NEXT: addw a0, a2, a4
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB7_3: # %entry
; RV64I-NEXT: mv a4, a5
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: bnez a0, .LBB7_2
; RV64I-NEXT: .LBB7_4: # %entry
; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bnez a1, .LBB7_2
; RV64I-NEXT: .LBB7_4: # %entry
; RV64I-NEXT: mv a4, a5
; RV64I-NEXT: addw a0, a2, a4
; RV64I-NEXT: ret
entry:
Expand Down
28 changes: 14 additions & 14 deletions llvm/test/CodeGen/RISCV/setcc-logic.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,17 +7,17 @@
define i1 @and_icmp_eq(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
; RV32I-LABEL: and_icmp_eq:
; RV32I: # %bb.0:
; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: xor a1, a2, a3
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: ret
;
; RV64I-LABEL: and_icmp_eq:
; RV64I: # %bb.0:
; RV64I-NEXT: xor a2, a2, a3
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: xor a1, a2, a3
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: seqz a0, a0
Expand All @@ -31,17 +31,17 @@ define i1 @and_icmp_eq(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
define i1 @or_icmp_ne(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
; RV32I-LABEL: or_icmp_ne:
; RV32I: # %bb.0:
; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: xor a1, a2, a3
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: ret
;
; RV64I-LABEL: or_icmp_ne:
; RV64I: # %bb.0:
; RV64I-NEXT: xor a2, a2, a3
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: xor a1, a2, a3
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: snez a0, a0
Expand Down Expand Up @@ -102,22 +102,22 @@ define i1 @and_icmps_const_1bit_diff(i32 %x) nounwind {
define i1 @and_icmps_const_not1bit_diff(i32 %x) nounwind {
; RV32I-LABEL: and_icmps_const_not1bit_diff:
; RV32I: # %bb.0:
; RV32I-NEXT: xori a1, a0, 92
; RV32I-NEXT: xori a1, a0, 44
; RV32I-NEXT: snez a1, a1
; RV32I-NEXT: xori a0, a0, 44
; RV32I-NEXT: xori a0, a0, 92
; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: ret
;
; RV64I-LABEL: and_icmps_const_not1bit_diff:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: xori a1, a0, 92
; RV64I-NEXT: xori a1, a0, 44
; RV64I-NEXT: snez a1, a1
; RV64I-NEXT: xori a0, a0, 44
; RV64I-NEXT: xori a0, a0, 92
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: ret
%a = icmp ne i32 %x, 44
%b = icmp ne i32 %x, 92
Expand Down
114 changes: 59 additions & 55 deletions llvm/test/CodeGen/RISCV/shifts.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -17,13 +17,14 @@ define i64 @lshr64(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB0_2:
; RV32I-NEXT: srl a0, a0, a2
; RV32I-NEXT: addi a3, zero, 31
; RV32I-NEXT: sub a3, a3, a2
; RV32I-NEXT: slli a4, a1, 1
; RV32I-NEXT: sll a3, a4, a3
; RV32I-NEXT: srl a0, a0, a2
; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: srl a1, a1, a2
; RV32I-NEXT: srl a2, a1, a2
; RV32I-NEXT: mv a1, a2
; RV32I-NEXT: ret
;
; RV64I-LABEL: lshr64:
Expand Down Expand Up @@ -62,11 +63,11 @@ define i64 @ashr64(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: srai a1, a1, 31
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB2_2:
; RV32I-NEXT: srl a0, a0, a2
; RV32I-NEXT: addi a3, zero, 31
; RV32I-NEXT: sub a3, a3, a2
; RV32I-NEXT: slli a4, a1, 1
; RV32I-NEXT: sll a3, a4, a3
; RV32I-NEXT: srl a0, a0, a2
; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: sra a1, a1, a2
; RV32I-NEXT: ret
Expand Down Expand Up @@ -107,13 +108,14 @@ define i64 @shl64(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB4_2:
; RV32I-NEXT: sll a1, a1, a2
; RV32I-NEXT: addi a3, zero, 31
; RV32I-NEXT: sub a3, a3, a2
; RV32I-NEXT: srli a4, a0, 1
; RV32I-NEXT: srl a3, a4, a3
; RV32I-NEXT: sll a1, a1, a2
; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: sll a0, a0, a2
; RV32I-NEXT: sll a2, a0, a2
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
; RV64I-LABEL: shl64:
Expand Down Expand Up @@ -148,27 +150,27 @@ define i128 @lshr128(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: addi sp, sp, -48
; RV32I-NEXT: sw ra, 44(sp)
; RV32I-NEXT: sw s0, 40(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a0, 12(a1)
; RV32I-NEXT: sw a0, 20(sp)
; RV32I-NEXT: lw a0, 8(a1)
; RV32I-NEXT: sw a0, 16(sp)
; RV32I-NEXT: lw a0, 4(a1)
; RV32I-NEXT: sw a0, 12(sp)
; RV32I-NEXT: lw a0, 0(a1)
; RV32I-NEXT: sw a0, 8(sp)
; RV32I-NEXT: lw a2, 0(a2)
; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: lw a4, 4(a1)
; RV32I-NEXT: lw a5, 8(a1)
; RV32I-NEXT: lw a1, 12(a1)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: sw a1, 20(sp)
; RV32I-NEXT: sw a5, 16(sp)
; RV32I-NEXT: sw a4, 12(sp)
; RV32I-NEXT: addi a0, sp, 24
; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: sw a3, 8(sp)
; RV32I-NEXT: call __lshrti3
; RV32I-NEXT: lw a0, 36(sp)
; RV32I-NEXT: lw a1, 32(sp)
; RV32I-NEXT: lw a2, 28(sp)
; RV32I-NEXT: lw a3, 24(sp)
; RV32I-NEXT: sw a0, 12(s0)
; RV32I-NEXT: lw a0, 32(sp)
; RV32I-NEXT: sw a0, 8(s0)
; RV32I-NEXT: lw a0, 28(sp)
; RV32I-NEXT: sw a0, 4(s0)
; RV32I-NEXT: lw a0, 24(sp)
; RV32I-NEXT: sw a0, 0(s0)
; RV32I-NEXT: sw a1, 8(s0)
; RV32I-NEXT: sw a2, 4(s0)
; RV32I-NEXT: sw a3, 0(s0)
; RV32I-NEXT: lw s0, 40(sp)
; RV32I-NEXT: lw ra, 44(sp)
; RV32I-NEXT: addi sp, sp, 48
Expand All @@ -183,13 +185,14 @@ define i128 @lshr128(i128 %a, i128 %b) nounwind {
; RV64I-NEXT: mv a1, zero
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB6_2:
; RV64I-NEXT: srl a0, a0, a2
; RV64I-NEXT: addi a3, zero, 63
; RV64I-NEXT: sub a3, a3, a2
; RV64I-NEXT: slli a4, a1, 1
; RV64I-NEXT: sll a3, a4, a3
; RV64I-NEXT: srl a0, a0, a2
; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: srl a1, a1, a2
; RV64I-NEXT: srl a2, a1, a2
; RV64I-NEXT: mv a1, a2
; RV64I-NEXT: ret
%1 = lshr i128 %a, %b
ret i128 %1
Expand All @@ -201,27 +204,27 @@ define i128 @ashr128(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: addi sp, sp, -48
; RV32I-NEXT: sw ra, 44(sp)
; RV32I-NEXT: sw s0, 40(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a0, 12(a1)
; RV32I-NEXT: sw a0, 20(sp)
; RV32I-NEXT: lw a0, 8(a1)
; RV32I-NEXT: sw a0, 16(sp)
; RV32I-NEXT: lw a0, 4(a1)
; RV32I-NEXT: sw a0, 12(sp)
; RV32I-NEXT: lw a0, 0(a1)
; RV32I-NEXT: sw a0, 8(sp)
; RV32I-NEXT: lw a2, 0(a2)
; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: lw a4, 4(a1)
; RV32I-NEXT: lw a5, 8(a1)
; RV32I-NEXT: lw a1, 12(a1)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: sw a1, 20(sp)
; RV32I-NEXT: sw a5, 16(sp)
; RV32I-NEXT: sw a4, 12(sp)
; RV32I-NEXT: addi a0, sp, 24
; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: sw a3, 8(sp)
; RV32I-NEXT: call __ashrti3
; RV32I-NEXT: lw a0, 36(sp)
; RV32I-NEXT: lw a1, 32(sp)
; RV32I-NEXT: lw a2, 28(sp)
; RV32I-NEXT: lw a3, 24(sp)
; RV32I-NEXT: sw a0, 12(s0)
; RV32I-NEXT: lw a0, 32(sp)
; RV32I-NEXT: sw a0, 8(s0)
; RV32I-NEXT: lw a0, 28(sp)
; RV32I-NEXT: sw a0, 4(s0)
; RV32I-NEXT: lw a0, 24(sp)
; RV32I-NEXT: sw a0, 0(s0)
; RV32I-NEXT: sw a1, 8(s0)
; RV32I-NEXT: sw a2, 4(s0)
; RV32I-NEXT: sw a3, 0(s0)
; RV32I-NEXT: lw s0, 40(sp)
; RV32I-NEXT: lw ra, 44(sp)
; RV32I-NEXT: addi sp, sp, 48
Expand All @@ -236,11 +239,11 @@ define i128 @ashr128(i128 %a, i128 %b) nounwind {
; RV64I-NEXT: srai a1, a1, 63
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB7_2:
; RV64I-NEXT: srl a0, a0, a2
; RV64I-NEXT: addi a3, zero, 63
; RV64I-NEXT: sub a3, a3, a2
; RV64I-NEXT: slli a4, a1, 1
; RV64I-NEXT: sll a3, a4, a3
; RV64I-NEXT: srl a0, a0, a2
; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: sra a1, a1, a2
; RV64I-NEXT: ret
Expand All @@ -254,27 +257,27 @@ define i128 @shl128(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: addi sp, sp, -48
; RV32I-NEXT: sw ra, 44(sp)
; RV32I-NEXT: sw s0, 40(sp)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lw a0, 12(a1)
; RV32I-NEXT: sw a0, 20(sp)
; RV32I-NEXT: lw a0, 8(a1)
; RV32I-NEXT: sw a0, 16(sp)
; RV32I-NEXT: lw a0, 4(a1)
; RV32I-NEXT: sw a0, 12(sp)
; RV32I-NEXT: lw a0, 0(a1)
; RV32I-NEXT: sw a0, 8(sp)
; RV32I-NEXT: lw a2, 0(a2)
; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: lw a4, 4(a1)
; RV32I-NEXT: lw a5, 8(a1)
; RV32I-NEXT: lw a1, 12(a1)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: sw a1, 20(sp)
; RV32I-NEXT: sw a5, 16(sp)
; RV32I-NEXT: sw a4, 12(sp)
; RV32I-NEXT: addi a0, sp, 24
; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: sw a3, 8(sp)
; RV32I-NEXT: call __ashlti3
; RV32I-NEXT: lw a0, 36(sp)
; RV32I-NEXT: lw a1, 32(sp)
; RV32I-NEXT: lw a2, 28(sp)
; RV32I-NEXT: lw a3, 24(sp)
; RV32I-NEXT: sw a0, 12(s0)
; RV32I-NEXT: lw a0, 32(sp)
; RV32I-NEXT: sw a0, 8(s0)
; RV32I-NEXT: lw a0, 28(sp)
; RV32I-NEXT: sw a0, 4(s0)
; RV32I-NEXT: lw a0, 24(sp)
; RV32I-NEXT: sw a0, 0(s0)
; RV32I-NEXT: sw a1, 8(s0)
; RV32I-NEXT: sw a2, 4(s0)
; RV32I-NEXT: sw a3, 0(s0)
; RV32I-NEXT: lw s0, 40(sp)
; RV32I-NEXT: lw ra, 44(sp)
; RV32I-NEXT: addi sp, sp, 48
Expand All @@ -289,13 +292,14 @@ define i128 @shl128(i128 %a, i128 %b) nounwind {
; RV64I-NEXT: mv a0, zero
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB8_2:
; RV64I-NEXT: sll a1, a1, a2
; RV64I-NEXT: addi a3, zero, 63
; RV64I-NEXT: sub a3, a3, a2
; RV64I-NEXT: srli a4, a0, 1
; RV64I-NEXT: srl a3, a4, a3
; RV64I-NEXT: sll a1, a1, a2
; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: sll a0, a0, a2
; RV64I-NEXT: sll a2, a0, a2
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: ret
%1 = shl i128 %a, %b
ret i128 %1
Expand Down
58 changes: 29 additions & 29 deletions llvm/test/CodeGen/RISCV/split-offsets.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11,33 +11,33 @@
define void @test1([65536 x i32]** %sp, [65536 x i32]* %t, i32 %n) {
; RV32I-LABEL: test1:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: lw a0, 0(a0)
; RV32I-NEXT: lui a2, 20
; RV32I-NEXT: addi a2, a2, -1920
; RV32I-NEXT: lw a0, 0(a0)
; RV32I-NEXT: add a1, a1, a2
; RV32I-NEXT: add a0, a0, a2
; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: sw a2, 0(a0)
; RV32I-NEXT: addi a3, zero, 1
; RV32I-NEXT: sw a3, 4(a0)
; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: sw a4, 0(a0)
; RV32I-NEXT: add a0, a1, a2
; RV32I-NEXT: sw a4, 4(a0)
; RV32I-NEXT: sw a3, 0(a0)
; RV32I-NEXT: sw a3, 0(a1)
; RV32I-NEXT: sw a2, 4(a1)
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret
;
; RV64I-LABEL: test1:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: ld a0, 0(a0)
; RV64I-NEXT: lui a2, 20
; RV64I-NEXT: addiw a2, a2, -1920
; RV64I-NEXT: ld a0, 0(a0)
; RV64I-NEXT: add a1, a1, a2
; RV64I-NEXT: add a0, a0, a2
; RV64I-NEXT: addi a2, zero, 2
; RV64I-NEXT: sw a2, 0(a0)
; RV64I-NEXT: addi a3, zero, 1
; RV64I-NEXT: sw a3, 4(a0)
; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: sw a4, 0(a0)
; RV64I-NEXT: add a0, a1, a2
; RV64I-NEXT: sw a4, 4(a0)
; RV64I-NEXT: sw a3, 0(a0)
; RV64I-NEXT: sw a3, 0(a1)
; RV64I-NEXT: sw a2, 4(a1)
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret
entry:
Expand All @@ -57,20 +57,20 @@ entry:
define void @test2([65536 x i32]** %sp, [65536 x i32]* %t, i32 %n) {
; RV32I-LABEL: test2:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: lui a3, 20
; RV32I-NEXT: addi a3, a3, -1920
; RV32I-NEXT: lw a0, 0(a0)
; RV32I-NEXT: add a0, a0, a3
; RV32I-NEXT: add a1, a1, a3
; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: lw a4, 0(a0)
; RV32I-NEXT: lui a0, 20
; RV32I-NEXT: addi a5, a0, -1920
; RV32I-NEXT: add a0, a1, a5
; RV32I-NEXT: add a1, a4, a5
; RV32I-NEXT: bge a3, a2, .LBB1_2
; RV32I-NEXT: .LBB1_1: # %while_body
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: sw a3, 4(a0)
; RV32I-NEXT: addi a4, a3, 1
; RV32I-NEXT: sw a4, 0(a0)
; RV32I-NEXT: sw a3, 4(a1)
; RV32I-NEXT: sw a4, 0(a1)
; RV32I-NEXT: sw a3, 4(a1)
; RV32I-NEXT: sw a4, 0(a0)
; RV32I-NEXT: sw a3, 4(a0)
; RV32I-NEXT: mv a3, a4
; RV32I-NEXT: blt a3, a2, .LBB1_1
; RV32I-NEXT: .LBB1_2: # %while_end
Expand All @@ -79,22 +79,22 @@ define void @test2([65536 x i32]** %sp, [65536 x i32]* %t, i32 %n) {
;
; RV64I-LABEL: test2:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: lui a3, 20
; RV64I-NEXT: addiw a3, a3, -1920
; RV64I-NEXT: ld a0, 0(a0)
; RV64I-NEXT: add a0, a0, a3
; RV64I-NEXT: add a1, a1, a3
; RV64I-NEXT: sext.w a2, a2
; RV64I-NEXT: mv a3, zero
; RV64I-NEXT: ld a4, 0(a0)
; RV64I-NEXT: lui a0, 20
; RV64I-NEXT: addiw a5, a0, -1920
; RV64I-NEXT: add a0, a1, a5
; RV64I-NEXT: add a1, a4, a5
; RV64I-NEXT: sext.w a2, a2
; RV64I-NEXT: sext.w a4, a3
; RV64I-NEXT: bge a4, a2, .LBB1_2
; RV64I-NEXT: .LBB1_1: # %while_body
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: sw a3, 4(a0)
; RV64I-NEXT: addi a4, a3, 1
; RV64I-NEXT: sw a4, 0(a0)
; RV64I-NEXT: sw a3, 4(a1)
; RV64I-NEXT: sw a4, 0(a1)
; RV64I-NEXT: sw a3, 4(a1)
; RV64I-NEXT: sw a4, 0(a0)
; RV64I-NEXT: sw a3, 4(a0)
; RV64I-NEXT: mv a3, a4
; RV64I-NEXT: sext.w a4, a3
; RV64I-NEXT: blt a4, a2, .LBB1_1
Expand Down
200 changes: 101 additions & 99 deletions llvm/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,111 +4,113 @@
define { i128, i8 } @muloti_test(i128 %l, i128 %r) #0 {
; RISCV32-LABEL: muloti_test:
; RISCV32: # %bb.0: # %start
; RISCV32-NEXT: addi sp, sp, -80
; RISCV32-NEXT: sw ra, 76(sp)
; RISCV32-NEXT: sw s0, 72(sp)
; RISCV32-NEXT: sw s1, 68(sp)
; RISCV32-NEXT: sw s2, 64(sp)
; RISCV32-NEXT: sw s3, 60(sp)
; RISCV32-NEXT: sw s4, 56(sp)
; RISCV32-NEXT: sw s5, 52(sp)
; RISCV32-NEXT: sw s6, 48(sp)
; RISCV32-NEXT: mv s1, a2
; RISCV32-NEXT: mv s0, a1
; RISCV32-NEXT: mv s2, a0
; RISCV32-NEXT: sw zero, 12(sp)
; RISCV32-NEXT: sw zero, 8(sp)
; RISCV32-NEXT: sw zero, 28(sp)
; RISCV32-NEXT: sw zero, 24(sp)
; RISCV32-NEXT: lw s3, 4(a2)
; RISCV32-NEXT: sw s3, 4(sp)
; RISCV32-NEXT: lw s5, 0(a2)
; RISCV32-NEXT: sw s5, 0(sp)
; RISCV32-NEXT: lw s4, 4(a1)
; RISCV32-NEXT: sw s4, 20(sp)
; RISCV32-NEXT: lw s6, 0(a1)
; RISCV32-NEXT: sw s6, 16(sp)
; RISCV32-NEXT: addi a0, sp, 32
; RISCV32-NEXT: addi a1, sp, 16
; RISCV32-NEXT: mv a2, sp
; RISCV32-NEXT: addi sp, sp, -96
; RISCV32-NEXT: sw ra, 92(sp)
; RISCV32-NEXT: sw s0, 88(sp)
; RISCV32-NEXT: sw s1, 84(sp)
; RISCV32-NEXT: sw s2, 80(sp)
; RISCV32-NEXT: sw s3, 76(sp)
; RISCV32-NEXT: sw s4, 72(sp)
; RISCV32-NEXT: sw s5, 68(sp)
; RISCV32-NEXT: sw s6, 64(sp)
; RISCV32-NEXT: sw s7, 60(sp)
; RISCV32-NEXT: sw s8, 56(sp)
; RISCV32-NEXT: lw s2, 12(a1)
; RISCV32-NEXT: lw s6, 8(a1)
; RISCV32-NEXT: lw s3, 12(a2)
; RISCV32-NEXT: lw s7, 8(a2)
; RISCV32-NEXT: lw s0, 0(a1)
; RISCV32-NEXT: lw s8, 4(a1)
; RISCV32-NEXT: lw s1, 0(a2)
; RISCV32-NEXT: lw s5, 4(a2)
; RISCV32-NEXT: mv s4, a0
; RISCV32-NEXT: sw zero, 20(sp)
; RISCV32-NEXT: sw zero, 16(sp)
; RISCV32-NEXT: sw zero, 36(sp)
; RISCV32-NEXT: sw zero, 32(sp)
; RISCV32-NEXT: sw s5, 12(sp)
; RISCV32-NEXT: sw s1, 8(sp)
; RISCV32-NEXT: sw s8, 28(sp)
; RISCV32-NEXT: addi a0, sp, 40
; RISCV32-NEXT: addi a1, sp, 24
; RISCV32-NEXT: addi a2, sp, 8
; RISCV32-NEXT: sw s0, 24(sp)
; RISCV32-NEXT: call __multi3
; RISCV32-NEXT: lw a0, 12(s0)
; RISCV32-NEXT: lw a1, 8(s0)
; RISCV32-NEXT: mul a2, s3, a1
; RISCV32-NEXT: mul a3, a0, s5
; RISCV32-NEXT: add a4, a3, a2
; RISCV32-NEXT: lw a2, 12(s1)
; RISCV32-NEXT: lw a3, 8(s1)
; RISCV32-NEXT: mul a5, s4, a3
; RISCV32-NEXT: mul s1, a2, s6
; RISCV32-NEXT: add a5, s1, a5
; RISCV32-NEXT: mul s1, a3, s6
; RISCV32-NEXT: mul s0, a1, s5
; RISCV32-NEXT: add s1, s0, s1
; RISCV32-NEXT: sltu s0, s1, s0
; RISCV32-NEXT: mulhu a6, a3, s6
; RISCV32-NEXT: add t1, a6, a5
; RISCV32-NEXT: mulhu t2, a1, s5
; RISCV32-NEXT: add t3, t2, a4
; RISCV32-NEXT: add a5, t3, t1
; RISCV32-NEXT: add a5, a5, s0
; RISCV32-NEXT: lw s0, 44(sp)
; RISCV32-NEXT: add a5, s0, a5
; RISCV32-NEXT: lw a4, 40(sp)
; RISCV32-NEXT: add a7, a4, s1
; RISCV32-NEXT: sltu t0, a7, a4
; RISCV32-NEXT: add a5, a5, t0
; RISCV32-NEXT: beq a5, s0, .LBB0_2
; RISCV32-NEXT: mul a0, s8, s7
; RISCV32-NEXT: mul a1, s3, s0
; RISCV32-NEXT: add a0, a1, a0
; RISCV32-NEXT: mulhu a5, s7, s0
; RISCV32-NEXT: add a0, a5, a0
; RISCV32-NEXT: mul a1, s5, s6
; RISCV32-NEXT: mul a2, s2, s1
; RISCV32-NEXT: add a1, a2, a1
; RISCV32-NEXT: mulhu t0, s6, s1
; RISCV32-NEXT: add t1, t0, a1
; RISCV32-NEXT: add a6, t1, a0
; RISCV32-NEXT: mul a1, s7, s0
; RISCV32-NEXT: mul a3, s6, s1
; RISCV32-NEXT: add a4, a3, a1
; RISCV32-NEXT: lw a1, 52(sp)
; RISCV32-NEXT: lw a2, 48(sp)
; RISCV32-NEXT: sltu a3, a4, a3
; RISCV32-NEXT: add a3, a6, a3
; RISCV32-NEXT: add a3, a1, a3
; RISCV32-NEXT: add a6, a2, a4
; RISCV32-NEXT: sltu a2, a6, a2
; RISCV32-NEXT: add a7, a3, a2
; RISCV32-NEXT: beq a7, a1, .LBB0_2
; RISCV32-NEXT: # %bb.1: # %start
; RISCV32-NEXT: sltu t0, a5, s0
; RISCV32-NEXT: sltu a2, a7, a1
; RISCV32-NEXT: .LBB0_2: # %start
; RISCV32-NEXT: snez a4, s3
; RISCV32-NEXT: snez s1, a0
; RISCV32-NEXT: and a4, s1, a4
; RISCV32-NEXT: snez s1, s4
; RISCV32-NEXT: snez s0, a2
; RISCV32-NEXT: and s1, s0, s1
; RISCV32-NEXT: mulhu s0, a2, s6
; RISCV32-NEXT: snez s0, s0
; RISCV32-NEXT: or s1, s1, s0
; RISCV32-NEXT: mulhu s0, a0, s5
; RISCV32-NEXT: snez s0, s0
; RISCV32-NEXT: or a4, a4, s0
; RISCV32-NEXT: sltu t2, t3, t2
; RISCV32-NEXT: mulhu s0, s3, a1
; RISCV32-NEXT: snez s0, s0
; RISCV32-NEXT: or t3, a4, s0
; RISCV32-NEXT: sltu s0, t1, a6
; RISCV32-NEXT: mulhu a4, s4, a3
; RISCV32-NEXT: sltu a0, a0, a5
; RISCV32-NEXT: snez a1, s8
; RISCV32-NEXT: snez a3, s3
; RISCV32-NEXT: and a1, a3, a1
; RISCV32-NEXT: mulhu a3, s3, s0
; RISCV32-NEXT: snez a3, a3
; RISCV32-NEXT: or a1, a1, a3
; RISCV32-NEXT: mulhu a3, s8, s7
; RISCV32-NEXT: snez a3, a3
; RISCV32-NEXT: or a1, a1, a3
; RISCV32-NEXT: or a0, a1, a0
; RISCV32-NEXT: sltu a1, t1, t0
; RISCV32-NEXT: snez a3, s5
; RISCV32-NEXT: snez a4, s2
; RISCV32-NEXT: and a3, a4, a3
; RISCV32-NEXT: mulhu a4, s2, s1
; RISCV32-NEXT: snez a4, a4
; RISCV32-NEXT: or a3, a3, a4
; RISCV32-NEXT: mulhu a4, s5, s6
; RISCV32-NEXT: snez a4, a4
; RISCV32-NEXT: or a3, a3, a4
; RISCV32-NEXT: or a1, a3, a1
; RISCV32-NEXT: or a3, s7, s3
; RISCV32-NEXT: snez a3, a3
; RISCV32-NEXT: or a4, s6, s2
; RISCV32-NEXT: snez a4, a4
; RISCV32-NEXT: or a4, s1, a4
; RISCV32-NEXT: lw s1, 36(sp)
; RISCV32-NEXT: sw s1, 4(s2)
; RISCV32-NEXT: lw s1, 32(sp)
; RISCV32-NEXT: sw s1, 0(s2)
; RISCV32-NEXT: sw a7, 8(s2)
; RISCV32-NEXT: sw a5, 12(s2)
; RISCV32-NEXT: or a4, a4, s0
; RISCV32-NEXT: or a5, t3, t2
; RISCV32-NEXT: and a3, a4, a3
; RISCV32-NEXT: or a1, a3, a1
; RISCV32-NEXT: or a0, a1, a0
; RISCV32-NEXT: or a1, a3, a2
; RISCV32-NEXT: snez a1, a1
; RISCV32-NEXT: snez a0, a0
; RISCV32-NEXT: and a0, a0, a1
; RISCV32-NEXT: or a0, a0, a5
; RISCV32-NEXT: or a0, a0, a4
; RISCV32-NEXT: or a0, a0, t0
; RISCV32-NEXT: lw a1, 44(sp)
; RISCV32-NEXT: lw a3, 40(sp)
; RISCV32-NEXT: or a0, a0, a2
; RISCV32-NEXT: andi a0, a0, 1
; RISCV32-NEXT: sb a0, 16(s2)
; RISCV32-NEXT: lw s6, 48(sp)
; RISCV32-NEXT: lw s5, 52(sp)
; RISCV32-NEXT: lw s4, 56(sp)
; RISCV32-NEXT: lw s3, 60(sp)
; RISCV32-NEXT: lw s2, 64(sp)
; RISCV32-NEXT: lw s1, 68(sp)
; RISCV32-NEXT: lw s0, 72(sp)
; RISCV32-NEXT: lw ra, 76(sp)
; RISCV32-NEXT: addi sp, sp, 80
; RISCV32-NEXT: sw a1, 4(s4)
; RISCV32-NEXT: sw a3, 0(s4)
; RISCV32-NEXT: sw a6, 8(s4)
; RISCV32-NEXT: sw a7, 12(s4)
; RISCV32-NEXT: sb a0, 16(s4)
; RISCV32-NEXT: lw s8, 56(sp)
; RISCV32-NEXT: lw s7, 60(sp)
; RISCV32-NEXT: lw s6, 64(sp)
; RISCV32-NEXT: lw s5, 68(sp)
; RISCV32-NEXT: lw s4, 72(sp)
; RISCV32-NEXT: lw s3, 76(sp)
; RISCV32-NEXT: lw s2, 80(sp)
; RISCV32-NEXT: lw s1, 84(sp)
; RISCV32-NEXT: lw s0, 88(sp)
; RISCV32-NEXT: lw ra, 92(sp)
; RISCV32-NEXT: addi sp, sp, 96
; RISCV32-NEXT: ret
start:
%0 = tail call { i128, i1 } @llvm.umul.with.overflow.i128(i128 %l, i128 %r) #2
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258 changes: 129 additions & 129 deletions llvm/test/CodeGen/RISCV/vararg.ll
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Large diffs are not rendered by default.

8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -45,10 +45,10 @@ define i32 @test_zext_i16() nounwind {
; RV32I-LABEL: test_zext_i16:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: lui a0, %hi(shorts)
; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi a1, a1, -120
; RV32I-NEXT: lhu a2, %lo(shorts)(a0)
; RV32I-NEXT: bne a2, a1, .LBB1_3
; RV32I-NEXT: lhu a1, %lo(shorts)(a0)
; RV32I-NEXT: lui a2, 16
; RV32I-NEXT: addi a2, a2, -120
; RV32I-NEXT: bne a1, a2, .LBB1_3
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: addi a0, a0, %lo(shorts)
; RV32I-NEXT: lhu a0, 2(a0)
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