62 changes: 31 additions & 31 deletions llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f-rv64.ll
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s
; RUN: < %s | FileCheck %s
declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16(
<vscale x 1 x half>,
i64);
Expand All @@ -10,7 +10,7 @@ define <vscale x 1 x i16> @intrinsic_vfcvt_rtz.x.f.v_nxv1i16_nxv1f16(<vscale x 1
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16(
<vscale x 1 x half> %0,
Expand All @@ -30,7 +30,7 @@ define <vscale x 1 x i16> @intrinsic_vfcvt_mask_rtz.x.f.v_nxv1i16_nxv1f16(<vscal
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv1i16.nxv1f16(
<vscale x 1 x i16> %0,
Expand All @@ -50,7 +50,7 @@ define <vscale x 2 x i16> @intrinsic_vfcvt_rtz.x.f.v_nxv2i16_nxv2f16(<vscale x 2
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16(
<vscale x 2 x half> %0,
Expand All @@ -70,7 +70,7 @@ define <vscale x 2 x i16> @intrinsic_vfcvt_mask_rtz.x.f.v_nxv2i16_nxv2f16(<vscal
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv2i16.nxv2f16(
<vscale x 2 x i16> %0,
Expand All @@ -90,7 +90,7 @@ define <vscale x 4 x i16> @intrinsic_vfcvt_rtz.x.f.v_nxv4i16_nxv4f16(<vscale x 4
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16(
<vscale x 4 x half> %0,
Expand All @@ -110,7 +110,7 @@ define <vscale x 4 x i16> @intrinsic_vfcvt_mask_rtz.x.f.v_nxv4i16_nxv4f16(<vscal
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv4i16.nxv4f16(
<vscale x 4 x i16> %0,
Expand All @@ -130,7 +130,7 @@ define <vscale x 8 x i16> @intrinsic_vfcvt_rtz.x.f.v_nxv8i16_nxv8f16(<vscale x 8
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16(
<vscale x 8 x half> %0,
Expand All @@ -150,7 +150,7 @@ define <vscale x 8 x i16> @intrinsic_vfcvt_mask_rtz.x.f.v_nxv8i16_nxv8f16(<vscal
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv8i16.nxv8f16(
<vscale x 8 x i16> %0,
Expand All @@ -170,7 +170,7 @@ define <vscale x 16 x i16> @intrinsic_vfcvt_rtz.x.f.v_nxv16i16_nxv16f16(<vscale
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16(
<vscale x 16 x half> %0,
Expand All @@ -190,7 +190,7 @@ define <vscale x 16 x i16> @intrinsic_vfcvt_mask_rtz.x.f.v_nxv16i16_nxv16f16(<vs
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv16i16.nxv16f16(
<vscale x 16 x i16> %0,
Expand All @@ -210,7 +210,7 @@ define <vscale x 32 x i16> @intrinsic_vfcvt_rtz.x.f.v_nxv32i16_nxv32f16(<vscale
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16(
<vscale x 32 x half> %0,
Expand All @@ -230,7 +230,7 @@ define <vscale x 32 x i16> @intrinsic_vfcvt_mask_rtz.x.f.v_nxv32i16_nxv32f16(<vs
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv32i16.nxv32f16(
<vscale x 32 x i16> %0,
Expand All @@ -250,7 +250,7 @@ define <vscale x 1 x i32> @intrinsic_vfcvt_rtz.x.f.v_nxv1i32_nxv1f32(<vscale x 1
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i32.nxv1f32(
<vscale x 1 x float> %0,
Expand All @@ -270,7 +270,7 @@ define <vscale x 1 x i32> @intrinsic_vfcvt_mask_rtz.x.f.v_nxv1i32_nxv1f32(<vscal
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv1i32.nxv1f32(
<vscale x 1 x i32> %0,
Expand All @@ -290,7 +290,7 @@ define <vscale x 2 x i32> @intrinsic_vfcvt_rtz.x.f.v_nxv2i32_nxv2f32(<vscale x 2
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i32.nxv2f32(
<vscale x 2 x float> %0,
Expand All @@ -310,7 +310,7 @@ define <vscale x 2 x i32> @intrinsic_vfcvt_mask_rtz.x.f.v_nxv2i32_nxv2f32(<vscal
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv2i32.nxv2f32(
<vscale x 2 x i32> %0,
Expand All @@ -330,7 +330,7 @@ define <vscale x 4 x i32> @intrinsic_vfcvt_rtz.x.f.v_nxv4i32_nxv4f32(<vscale x 4
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i32.nxv4f32(
<vscale x 4 x float> %0,
Expand All @@ -350,7 +350,7 @@ define <vscale x 4 x i32> @intrinsic_vfcvt_mask_rtz.x.f.v_nxv4i32_nxv4f32(<vscal
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv4i32.nxv4f32(
<vscale x 4 x i32> %0,
Expand All @@ -370,7 +370,7 @@ define <vscale x 8 x i32> @intrinsic_vfcvt_rtz.x.f.v_nxv8i32_nxv8f32(<vscale x 8
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i32.nxv8f32(
<vscale x 8 x float> %0,
Expand All @@ -390,7 +390,7 @@ define <vscale x 8 x i32> @intrinsic_vfcvt_mask_rtz.x.f.v_nxv8i32_nxv8f32(<vscal
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv8i32.nxv8f32(
<vscale x 8 x i32> %0,
Expand All @@ -410,7 +410,7 @@ define <vscale x 16 x i32> @intrinsic_vfcvt_rtz.x.f.v_nxv16i32_nxv16f32(<vscale
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i32.nxv16f32(
<vscale x 16 x float> %0,
Expand All @@ -430,7 +430,7 @@ define <vscale x 16 x i32> @intrinsic_vfcvt_mask_rtz.x.f.v_nxv16i32_nxv16f32(<vs
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv16i32.nxv16f32(
<vscale x 16 x i32> %0,
Expand All @@ -450,7 +450,7 @@ define <vscale x 1 x i64> @intrinsic_vfcvt_rtz.x.f.v_nxv1i64_nxv1f64(<vscale x 1
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i64.nxv1f64(
<vscale x 1 x double> %0,
Expand All @@ -470,7 +470,7 @@ define <vscale x 1 x i64> @intrinsic_vfcvt_mask_rtz.x.f.v_nxv1i64_nxv1f64(<vscal
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv1i64.nxv1f64(
<vscale x 1 x i64> %0,
Expand All @@ -490,7 +490,7 @@ define <vscale x 2 x i64> @intrinsic_vfcvt_rtz.x.f.v_nxv2i64_nxv2f64(<vscale x 2
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i64.nxv2f64(
<vscale x 2 x double> %0,
Expand All @@ -510,7 +510,7 @@ define <vscale x 2 x i64> @intrinsic_vfcvt_mask_rtz.x.f.v_nxv2i64_nxv2f64(<vscal
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv2i64.nxv2f64(
<vscale x 2 x i64> %0,
Expand All @@ -530,7 +530,7 @@ define <vscale x 4 x i64> @intrinsic_vfcvt_rtz.x.f.v_nxv4i64_nxv4f64(<vscale x 4
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i64.nxv4f64(
<vscale x 4 x double> %0,
Expand All @@ -550,7 +550,7 @@ define <vscale x 4 x i64> @intrinsic_vfcvt_mask_rtz.x.f.v_nxv4i64_nxv4f64(<vscal
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv4i64.nxv4f64(
<vscale x 4 x i64> %0,
Expand All @@ -570,7 +570,7 @@ define <vscale x 8 x i64> @intrinsic_vfcvt_rtz.x.f.v_nxv8i64_nxv8f64(<vscale x 8
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i64.nxv8f64(
<vscale x 8 x double> %0,
Expand All @@ -590,7 +590,7 @@ define <vscale x 8 x i64> @intrinsic_vfcvt_mask_rtz.x.f.v_nxv8i64_nxv8f64(<vscal
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv8i64.nxv8f64(
<vscale x 8 x i64> %0,
Expand Down
62 changes: 31 additions & 31 deletions llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f-rv32.ll
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s
; RUN: < %s | FileCheck %s
declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16(
<vscale x 1 x half>,
i32);
Expand All @@ -10,7 +10,7 @@ define <vscale x 1 x i16> @intrinsic_vfcvt_rtz.xu.f.v_nxv1i16_nxv1f16(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16(
<vscale x 1 x half> %0,
Expand All @@ -30,7 +30,7 @@ define <vscale x 1 x i16> @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv1i16_nxv1f16(<vsca
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv1i16.nxv1f16(
<vscale x 1 x i16> %0,
Expand All @@ -50,7 +50,7 @@ define <vscale x 2 x i16> @intrinsic_vfcvt_rtz.xu.f.v_nxv2i16_nxv2f16(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16(
<vscale x 2 x half> %0,
Expand All @@ -70,7 +70,7 @@ define <vscale x 2 x i16> @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv2i16_nxv2f16(<vsca
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv2i16.nxv2f16(
<vscale x 2 x i16> %0,
Expand All @@ -90,7 +90,7 @@ define <vscale x 4 x i16> @intrinsic_vfcvt_rtz.xu.f.v_nxv4i16_nxv4f16(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16(
<vscale x 4 x half> %0,
Expand All @@ -110,7 +110,7 @@ define <vscale x 4 x i16> @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv4i16_nxv4f16(<vsca
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv4i16.nxv4f16(
<vscale x 4 x i16> %0,
Expand All @@ -130,7 +130,7 @@ define <vscale x 8 x i16> @intrinsic_vfcvt_rtz.xu.f.v_nxv8i16_nxv8f16(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16(
<vscale x 8 x half> %0,
Expand All @@ -150,7 +150,7 @@ define <vscale x 8 x i16> @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv8i16_nxv8f16(<vsca
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv8i16.nxv8f16(
<vscale x 8 x i16> %0,
Expand All @@ -170,7 +170,7 @@ define <vscale x 16 x i16> @intrinsic_vfcvt_rtz.xu.f.v_nxv16i16_nxv16f16(<vscale
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16(
<vscale x 16 x half> %0,
Expand All @@ -190,7 +190,7 @@ define <vscale x 16 x i16> @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv16i16_nxv16f16(<v
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv16i16.nxv16f16(
<vscale x 16 x i16> %0,
Expand All @@ -210,7 +210,7 @@ define <vscale x 32 x i16> @intrinsic_vfcvt_rtz.xu.f.v_nxv32i16_nxv32f16(<vscale
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv32i16.nxv32f16(
<vscale x 32 x half> %0,
Expand All @@ -230,7 +230,7 @@ define <vscale x 32 x i16> @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv32i16_nxv32f16(<v
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv32i16.nxv32f16(
<vscale x 32 x i16> %0,
Expand All @@ -250,7 +250,7 @@ define <vscale x 1 x i32> @intrinsic_vfcvt_rtz.xu.f.v_nxv1i32_nxv1f32(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i32.nxv1f32(
<vscale x 1 x float> %0,
Expand All @@ -270,7 +270,7 @@ define <vscale x 1 x i32> @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv1i32_nxv1f32(<vsca
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv1i32.nxv1f32(
<vscale x 1 x i32> %0,
Expand All @@ -290,7 +290,7 @@ define <vscale x 2 x i32> @intrinsic_vfcvt_rtz.xu.f.v_nxv2i32_nxv2f32(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i32.nxv2f32(
<vscale x 2 x float> %0,
Expand All @@ -310,7 +310,7 @@ define <vscale x 2 x i32> @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv2i32_nxv2f32(<vsca
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv2i32.nxv2f32(
<vscale x 2 x i32> %0,
Expand All @@ -330,7 +330,7 @@ define <vscale x 4 x i32> @intrinsic_vfcvt_rtz.xu.f.v_nxv4i32_nxv4f32(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i32.nxv4f32(
<vscale x 4 x float> %0,
Expand All @@ -350,7 +350,7 @@ define <vscale x 4 x i32> @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv4i32_nxv4f32(<vsca
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv4i32.nxv4f32(
<vscale x 4 x i32> %0,
Expand All @@ -370,7 +370,7 @@ define <vscale x 8 x i32> @intrinsic_vfcvt_rtz.xu.f.v_nxv8i32_nxv8f32(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i32.nxv8f32(
<vscale x 8 x float> %0,
Expand All @@ -390,7 +390,7 @@ define <vscale x 8 x i32> @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv8i32_nxv8f32(<vsca
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv8i32.nxv8f32(
<vscale x 8 x i32> %0,
Expand All @@ -410,7 +410,7 @@ define <vscale x 16 x i32> @intrinsic_vfcvt_rtz.xu.f.v_nxv16i32_nxv16f32(<vscale
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i32.nxv16f32(
<vscale x 16 x float> %0,
Expand All @@ -430,7 +430,7 @@ define <vscale x 16 x i32> @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv16i32_nxv16f32(<v
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv16i32.nxv16f32(
<vscale x 16 x i32> %0,
Expand All @@ -450,7 +450,7 @@ define <vscale x 1 x i64> @intrinsic_vfcvt_rtz.xu.f.v_nxv1i64_nxv1f64(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i64.nxv1f64(
<vscale x 1 x double> %0,
Expand All @@ -470,7 +470,7 @@ define <vscale x 1 x i64> @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv1i64_nxv1f64(<vsca
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv1i64.nxv1f64(
<vscale x 1 x i64> %0,
Expand All @@ -490,7 +490,7 @@ define <vscale x 2 x i64> @intrinsic_vfcvt_rtz.xu.f.v_nxv2i64_nxv2f64(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i64.nxv2f64(
<vscale x 2 x double> %0,
Expand All @@ -510,7 +510,7 @@ define <vscale x 2 x i64> @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv2i64_nxv2f64(<vsca
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv2i64.nxv2f64(
<vscale x 2 x i64> %0,
Expand All @@ -530,7 +530,7 @@ define <vscale x 4 x i64> @intrinsic_vfcvt_rtz.xu.f.v_nxv4i64_nxv4f64(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i64.nxv4f64(
<vscale x 4 x double> %0,
Expand All @@ -550,7 +550,7 @@ define <vscale x 4 x i64> @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv4i64_nxv4f64(<vsca
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv4i64.nxv4f64(
<vscale x 4 x i64> %0,
Expand All @@ -570,7 +570,7 @@ define <vscale x 8 x i64> @intrinsic_vfcvt_rtz.xu.f.v_nxv8i64_nxv8f64(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i64.nxv8f64(
<vscale x 8 x double> %0,
Expand All @@ -590,7 +590,7 @@ define <vscale x 8 x i64> @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv8i64_nxv8f64(<vsca
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv8i64.nxv8f64(
<vscale x 8 x i64> %0,
Expand Down
62 changes: 31 additions & 31 deletions llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f-rv64.ll
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s
; RUN: < %s | FileCheck %s
declare <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16(
<vscale x 1 x half>,
i64);
Expand All @@ -10,7 +10,7 @@ define <vscale x 1 x i16> @intrinsic_vfcvt_rtz.xu.f.v_nxv1i16_nxv1f16(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16(
<vscale x 1 x half> %0,
Expand All @@ -30,7 +30,7 @@ define <vscale x 1 x i16> @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv1i16_nxv1f16(<vsca
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv1i16.nxv1f16(
<vscale x 1 x i16> %0,
Expand All @@ -50,7 +50,7 @@ define <vscale x 2 x i16> @intrinsic_vfcvt_rtz.xu.f.v_nxv2i16_nxv2f16(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16(
<vscale x 2 x half> %0,
Expand All @@ -70,7 +70,7 @@ define <vscale x 2 x i16> @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv2i16_nxv2f16(<vsca
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv2i16.nxv2f16(
<vscale x 2 x i16> %0,
Expand All @@ -90,7 +90,7 @@ define <vscale x 4 x i16> @intrinsic_vfcvt_rtz.xu.f.v_nxv4i16_nxv4f16(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16(
<vscale x 4 x half> %0,
Expand All @@ -110,7 +110,7 @@ define <vscale x 4 x i16> @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv4i16_nxv4f16(<vsca
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv4i16.nxv4f16(
<vscale x 4 x i16> %0,
Expand All @@ -130,7 +130,7 @@ define <vscale x 8 x i16> @intrinsic_vfcvt_rtz.xu.f.v_nxv8i16_nxv8f16(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16(
<vscale x 8 x half> %0,
Expand All @@ -150,7 +150,7 @@ define <vscale x 8 x i16> @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv8i16_nxv8f16(<vsca
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv8i16.nxv8f16(
<vscale x 8 x i16> %0,
Expand All @@ -170,7 +170,7 @@ define <vscale x 16 x i16> @intrinsic_vfcvt_rtz.xu.f.v_nxv16i16_nxv16f16(<vscale
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16(
<vscale x 16 x half> %0,
Expand All @@ -190,7 +190,7 @@ define <vscale x 16 x i16> @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv16i16_nxv16f16(<v
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv16i16.nxv16f16(
<vscale x 16 x i16> %0,
Expand All @@ -210,7 +210,7 @@ define <vscale x 32 x i16> @intrinsic_vfcvt_rtz.xu.f.v_nxv32i16_nxv32f16(<vscale
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv32i16.nxv32f16(
<vscale x 32 x half> %0,
Expand All @@ -230,7 +230,7 @@ define <vscale x 32 x i16> @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv32i16_nxv32f16(<v
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv32i16.nxv32f16(
<vscale x 32 x i16> %0,
Expand All @@ -250,7 +250,7 @@ define <vscale x 1 x i32> @intrinsic_vfcvt_rtz.xu.f.v_nxv1i32_nxv1f32(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i32.nxv1f32(
<vscale x 1 x float> %0,
Expand All @@ -270,7 +270,7 @@ define <vscale x 1 x i32> @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv1i32_nxv1f32(<vsca
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv1i32.nxv1f32(
<vscale x 1 x i32> %0,
Expand All @@ -290,7 +290,7 @@ define <vscale x 2 x i32> @intrinsic_vfcvt_rtz.xu.f.v_nxv2i32_nxv2f32(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i32.nxv2f32(
<vscale x 2 x float> %0,
Expand All @@ -310,7 +310,7 @@ define <vscale x 2 x i32> @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv2i32_nxv2f32(<vsca
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv2i32.nxv2f32(
<vscale x 2 x i32> %0,
Expand All @@ -330,7 +330,7 @@ define <vscale x 4 x i32> @intrinsic_vfcvt_rtz.xu.f.v_nxv4i32_nxv4f32(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i32.nxv4f32(
<vscale x 4 x float> %0,
Expand All @@ -350,7 +350,7 @@ define <vscale x 4 x i32> @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv4i32_nxv4f32(<vsca
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv4i32.nxv4f32(
<vscale x 4 x i32> %0,
Expand All @@ -370,7 +370,7 @@ define <vscale x 8 x i32> @intrinsic_vfcvt_rtz.xu.f.v_nxv8i32_nxv8f32(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i32.nxv8f32(
<vscale x 8 x float> %0,
Expand All @@ -390,7 +390,7 @@ define <vscale x 8 x i32> @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv8i32_nxv8f32(<vsca
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv8i32.nxv8f32(
<vscale x 8 x i32> %0,
Expand All @@ -410,7 +410,7 @@ define <vscale x 16 x i32> @intrinsic_vfcvt_rtz.xu.f.v_nxv16i32_nxv16f32(<vscale
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i32.nxv16f32(
<vscale x 16 x float> %0,
Expand All @@ -430,7 +430,7 @@ define <vscale x 16 x i32> @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv16i32_nxv16f32(<v
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv16i32.nxv16f32(
<vscale x 16 x i32> %0,
Expand All @@ -450,7 +450,7 @@ define <vscale x 1 x i64> @intrinsic_vfcvt_rtz.xu.f.v_nxv1i64_nxv1f64(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i64.nxv1f64(
<vscale x 1 x double> %0,
Expand All @@ -470,7 +470,7 @@ define <vscale x 1 x i64> @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv1i64_nxv1f64(<vsca
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv1i64.nxv1f64(
<vscale x 1 x i64> %0,
Expand All @@ -490,7 +490,7 @@ define <vscale x 2 x i64> @intrinsic_vfcvt_rtz.xu.f.v_nxv2i64_nxv2f64(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i64.nxv2f64(
<vscale x 2 x double> %0,
Expand All @@ -510,7 +510,7 @@ define <vscale x 2 x i64> @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv2i64_nxv2f64(<vsca
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv2i64.nxv2f64(
<vscale x 2 x i64> %0,
Expand All @@ -530,7 +530,7 @@ define <vscale x 4 x i64> @intrinsic_vfcvt_rtz.xu.f.v_nxv4i64_nxv4f64(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i64.nxv4f64(
<vscale x 4 x double> %0,
Expand All @@ -550,7 +550,7 @@ define <vscale x 4 x i64> @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv4i64_nxv4f64(<vsca
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv4i64.nxv4f64(
<vscale x 4 x i64> %0,
Expand All @@ -570,7 +570,7 @@ define <vscale x 8 x i64> @intrinsic_vfcvt_rtz.xu.f.v_nxv8i64_nxv8f64(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i64.nxv8f64(
<vscale x 8 x double> %0,
Expand All @@ -590,7 +590,7 @@ define <vscale x 8 x i64> @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv8i64_nxv8f64(<vsca
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv8i64.nxv8f64(
<vscale x 8 x i64> %0,
Expand Down
62 changes: 31 additions & 31 deletions llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f-rv32.ll
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s
; RUN: < %s | FileCheck %s
declare <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16(
<vscale x 1 x half>,
i32);
Expand All @@ -10,7 +10,7 @@ define <vscale x 1 x i16> @intrinsic_vfcvt_x.f.v_nxv1i16_nxv1f16(<vscale x 1 x h
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16(
<vscale x 1 x half> %0,
Expand All @@ -30,7 +30,7 @@ define <vscale x 1 x i16> @intrinsic_vfcvt_mask_x.f.v_nxv1i16_nxv1f16(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv1i16.nxv1f16(
<vscale x 1 x i16> %0,
Expand All @@ -50,7 +50,7 @@ define <vscale x 2 x i16> @intrinsic_vfcvt_x.f.v_nxv2i16_nxv2f16(<vscale x 2 x h
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16(
<vscale x 2 x half> %0,
Expand All @@ -70,7 +70,7 @@ define <vscale x 2 x i16> @intrinsic_vfcvt_mask_x.f.v_nxv2i16_nxv2f16(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv2i16.nxv2f16(
<vscale x 2 x i16> %0,
Expand All @@ -90,7 +90,7 @@ define <vscale x 4 x i16> @intrinsic_vfcvt_x.f.v_nxv4i16_nxv4f16(<vscale x 4 x h
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16(
<vscale x 4 x half> %0,
Expand All @@ -110,7 +110,7 @@ define <vscale x 4 x i16> @intrinsic_vfcvt_mask_x.f.v_nxv4i16_nxv4f16(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv4i16.nxv4f16(
<vscale x 4 x i16> %0,
Expand All @@ -130,7 +130,7 @@ define <vscale x 8 x i16> @intrinsic_vfcvt_x.f.v_nxv8i16_nxv8f16(<vscale x 8 x h
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16(
<vscale x 8 x half> %0,
Expand All @@ -150,7 +150,7 @@ define <vscale x 8 x i16> @intrinsic_vfcvt_mask_x.f.v_nxv8i16_nxv8f16(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv8i16.nxv8f16(
<vscale x 8 x i16> %0,
Expand All @@ -170,7 +170,7 @@ define <vscale x 16 x i16> @intrinsic_vfcvt_x.f.v_nxv16i16_nxv16f16(<vscale x 16
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16(
<vscale x 16 x half> %0,
Expand All @@ -190,7 +190,7 @@ define <vscale x 16 x i16> @intrinsic_vfcvt_mask_x.f.v_nxv16i16_nxv16f16(<vscale
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv16i16.nxv16f16(
<vscale x 16 x i16> %0,
Expand All @@ -210,7 +210,7 @@ define <vscale x 32 x i16> @intrinsic_vfcvt_x.f.v_nxv32i16_nxv32f16(<vscale x 32
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16(
<vscale x 32 x half> %0,
Expand All @@ -230,7 +230,7 @@ define <vscale x 32 x i16> @intrinsic_vfcvt_mask_x.f.v_nxv32i16_nxv32f16(<vscale
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv32i16.nxv32f16(
<vscale x 32 x i16> %0,
Expand All @@ -250,7 +250,7 @@ define <vscale x 1 x i32> @intrinsic_vfcvt_x.f.v_nxv1i32_nxv1f32(<vscale x 1 x f
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfcvt.x.f.v.nxv1i32.nxv1f32(
<vscale x 1 x float> %0,
Expand All @@ -270,7 +270,7 @@ define <vscale x 1 x i32> @intrinsic_vfcvt_mask_x.f.v_nxv1i32_nxv1f32(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv1i32.nxv1f32(
<vscale x 1 x i32> %0,
Expand All @@ -290,7 +290,7 @@ define <vscale x 2 x i32> @intrinsic_vfcvt_x.f.v_nxv2i32_nxv2f32(<vscale x 2 x f
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfcvt.x.f.v.nxv2i32.nxv2f32(
<vscale x 2 x float> %0,
Expand All @@ -310,7 +310,7 @@ define <vscale x 2 x i32> @intrinsic_vfcvt_mask_x.f.v_nxv2i32_nxv2f32(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv2i32.nxv2f32(
<vscale x 2 x i32> %0,
Expand All @@ -330,7 +330,7 @@ define <vscale x 4 x i32> @intrinsic_vfcvt_x.f.v_nxv4i32_nxv4f32(<vscale x 4 x f
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfcvt.x.f.v.nxv4i32.nxv4f32(
<vscale x 4 x float> %0,
Expand All @@ -350,7 +350,7 @@ define <vscale x 4 x i32> @intrinsic_vfcvt_mask_x.f.v_nxv4i32_nxv4f32(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv4i32.nxv4f32(
<vscale x 4 x i32> %0,
Expand All @@ -370,7 +370,7 @@ define <vscale x 8 x i32> @intrinsic_vfcvt_x.f.v_nxv8i32_nxv8f32(<vscale x 8 x f
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfcvt.x.f.v.nxv8i32.nxv8f32(
<vscale x 8 x float> %0,
Expand All @@ -390,7 +390,7 @@ define <vscale x 8 x i32> @intrinsic_vfcvt_mask_x.f.v_nxv8i32_nxv8f32(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv8i32.nxv8f32(
<vscale x 8 x i32> %0,
Expand All @@ -410,7 +410,7 @@ define <vscale x 16 x i32> @intrinsic_vfcvt_x.f.v_nxv16i32_nxv16f32(<vscale x 16
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vfcvt.x.f.v.nxv16i32.nxv16f32(
<vscale x 16 x float> %0,
Expand All @@ -430,7 +430,7 @@ define <vscale x 16 x i32> @intrinsic_vfcvt_mask_x.f.v_nxv16i32_nxv16f32(<vscale
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv16i32.nxv16f32(
<vscale x 16 x i32> %0,
Expand All @@ -450,7 +450,7 @@ define <vscale x 1 x i64> @intrinsic_vfcvt_x.f.v_nxv1i64_nxv1f64(<vscale x 1 x d
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vfcvt.x.f.v.nxv1i64.nxv1f64(
<vscale x 1 x double> %0,
Expand All @@ -470,7 +470,7 @@ define <vscale x 1 x i64> @intrinsic_vfcvt_mask_x.f.v_nxv1i64_nxv1f64(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv1i64.nxv1f64(
<vscale x 1 x i64> %0,
Expand All @@ -490,7 +490,7 @@ define <vscale x 2 x i64> @intrinsic_vfcvt_x.f.v_nxv2i64_nxv2f64(<vscale x 2 x d
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vfcvt.x.f.v.nxv2i64.nxv2f64(
<vscale x 2 x double> %0,
Expand All @@ -510,7 +510,7 @@ define <vscale x 2 x i64> @intrinsic_vfcvt_mask_x.f.v_nxv2i64_nxv2f64(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv2i64.nxv2f64(
<vscale x 2 x i64> %0,
Expand All @@ -530,7 +530,7 @@ define <vscale x 4 x i64> @intrinsic_vfcvt_x.f.v_nxv4i64_nxv4f64(<vscale x 4 x d
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vfcvt.x.f.v.nxv4i64.nxv4f64(
<vscale x 4 x double> %0,
Expand All @@ -550,7 +550,7 @@ define <vscale x 4 x i64> @intrinsic_vfcvt_mask_x.f.v_nxv4i64_nxv4f64(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv4i64.nxv4f64(
<vscale x 4 x i64> %0,
Expand All @@ -570,7 +570,7 @@ define <vscale x 8 x i64> @intrinsic_vfcvt_x.f.v_nxv8i64_nxv8f64(<vscale x 8 x d
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vfcvt.x.f.v.nxv8i64.nxv8f64(
<vscale x 8 x double> %0,
Expand All @@ -590,7 +590,7 @@ define <vscale x 8 x i64> @intrinsic_vfcvt_mask_x.f.v_nxv8i64_nxv8f64(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv8i64.nxv8f64(
<vscale x 8 x i64> %0,
Expand Down
62 changes: 31 additions & 31 deletions llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f-rv64.ll
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s
; RUN: < %s | FileCheck %s
declare <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16(
<vscale x 1 x half>,
i64);
Expand All @@ -10,7 +10,7 @@ define <vscale x 1 x i16> @intrinsic_vfcvt_x.f.v_nxv1i16_nxv1f16(<vscale x 1 x h
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16(
<vscale x 1 x half> %0,
Expand All @@ -30,7 +30,7 @@ define <vscale x 1 x i16> @intrinsic_vfcvt_mask_x.f.v_nxv1i16_nxv1f16(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv1i16.nxv1f16(
<vscale x 1 x i16> %0,
Expand All @@ -50,7 +50,7 @@ define <vscale x 2 x i16> @intrinsic_vfcvt_x.f.v_nxv2i16_nxv2f16(<vscale x 2 x h
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16(
<vscale x 2 x half> %0,
Expand All @@ -70,7 +70,7 @@ define <vscale x 2 x i16> @intrinsic_vfcvt_mask_x.f.v_nxv2i16_nxv2f16(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv2i16.nxv2f16(
<vscale x 2 x i16> %0,
Expand All @@ -90,7 +90,7 @@ define <vscale x 4 x i16> @intrinsic_vfcvt_x.f.v_nxv4i16_nxv4f16(<vscale x 4 x h
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16(
<vscale x 4 x half> %0,
Expand All @@ -110,7 +110,7 @@ define <vscale x 4 x i16> @intrinsic_vfcvt_mask_x.f.v_nxv4i16_nxv4f16(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv4i16.nxv4f16(
<vscale x 4 x i16> %0,
Expand All @@ -130,7 +130,7 @@ define <vscale x 8 x i16> @intrinsic_vfcvt_x.f.v_nxv8i16_nxv8f16(<vscale x 8 x h
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16(
<vscale x 8 x half> %0,
Expand All @@ -150,7 +150,7 @@ define <vscale x 8 x i16> @intrinsic_vfcvt_mask_x.f.v_nxv8i16_nxv8f16(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv8i16.nxv8f16(
<vscale x 8 x i16> %0,
Expand All @@ -170,7 +170,7 @@ define <vscale x 16 x i16> @intrinsic_vfcvt_x.f.v_nxv16i16_nxv16f16(<vscale x 16
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16(
<vscale x 16 x half> %0,
Expand All @@ -190,7 +190,7 @@ define <vscale x 16 x i16> @intrinsic_vfcvt_mask_x.f.v_nxv16i16_nxv16f16(<vscale
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv16i16.nxv16f16(
<vscale x 16 x i16> %0,
Expand All @@ -210,7 +210,7 @@ define <vscale x 32 x i16> @intrinsic_vfcvt_x.f.v_nxv32i16_nxv32f16(<vscale x 32
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16(
<vscale x 32 x half> %0,
Expand All @@ -230,7 +230,7 @@ define <vscale x 32 x i16> @intrinsic_vfcvt_mask_x.f.v_nxv32i16_nxv32f16(<vscale
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vfcvt.x.f.v.mask.nxv32i16.nxv32f16(
<vscale x 32 x i16> %0,
Expand All @@ -250,7 +250,7 @@ define <vscale x 1 x i32> @intrinsic_vfcvt_x.f.v_nxv1i32_nxv1f32(<vscale x 1 x f
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfcvt.x.f.v.nxv1i32.nxv1f32(
<vscale x 1 x float> %0,
Expand All @@ -270,7 +270,7 @@ define <vscale x 1 x i32> @intrinsic_vfcvt_mask_x.f.v_nxv1i32_nxv1f32(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv1i32.nxv1f32(
<vscale x 1 x i32> %0,
Expand All @@ -290,7 +290,7 @@ define <vscale x 2 x i32> @intrinsic_vfcvt_x.f.v_nxv2i32_nxv2f32(<vscale x 2 x f
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfcvt.x.f.v.nxv2i32.nxv2f32(
<vscale x 2 x float> %0,
Expand All @@ -310,7 +310,7 @@ define <vscale x 2 x i32> @intrinsic_vfcvt_mask_x.f.v_nxv2i32_nxv2f32(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv2i32.nxv2f32(
<vscale x 2 x i32> %0,
Expand All @@ -330,7 +330,7 @@ define <vscale x 4 x i32> @intrinsic_vfcvt_x.f.v_nxv4i32_nxv4f32(<vscale x 4 x f
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfcvt.x.f.v.nxv4i32.nxv4f32(
<vscale x 4 x float> %0,
Expand All @@ -350,7 +350,7 @@ define <vscale x 4 x i32> @intrinsic_vfcvt_mask_x.f.v_nxv4i32_nxv4f32(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv4i32.nxv4f32(
<vscale x 4 x i32> %0,
Expand All @@ -370,7 +370,7 @@ define <vscale x 8 x i32> @intrinsic_vfcvt_x.f.v_nxv8i32_nxv8f32(<vscale x 8 x f
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfcvt.x.f.v.nxv8i32.nxv8f32(
<vscale x 8 x float> %0,
Expand All @@ -390,7 +390,7 @@ define <vscale x 8 x i32> @intrinsic_vfcvt_mask_x.f.v_nxv8i32_nxv8f32(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv8i32.nxv8f32(
<vscale x 8 x i32> %0,
Expand All @@ -410,7 +410,7 @@ define <vscale x 16 x i32> @intrinsic_vfcvt_x.f.v_nxv16i32_nxv16f32(<vscale x 16
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vfcvt.x.f.v.nxv16i32.nxv16f32(
<vscale x 16 x float> %0,
Expand All @@ -430,7 +430,7 @@ define <vscale x 16 x i32> @intrinsic_vfcvt_mask_x.f.v_nxv16i32_nxv16f32(<vscale
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vfcvt.x.f.v.mask.nxv16i32.nxv16f32(
<vscale x 16 x i32> %0,
Expand All @@ -450,7 +450,7 @@ define <vscale x 1 x i64> @intrinsic_vfcvt_x.f.v_nxv1i64_nxv1f64(<vscale x 1 x d
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vfcvt.x.f.v.nxv1i64.nxv1f64(
<vscale x 1 x double> %0,
Expand All @@ -470,7 +470,7 @@ define <vscale x 1 x i64> @intrinsic_vfcvt_mask_x.f.v_nxv1i64_nxv1f64(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv1i64.nxv1f64(
<vscale x 1 x i64> %0,
Expand All @@ -490,7 +490,7 @@ define <vscale x 2 x i64> @intrinsic_vfcvt_x.f.v_nxv2i64_nxv2f64(<vscale x 2 x d
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vfcvt.x.f.v.nxv2i64.nxv2f64(
<vscale x 2 x double> %0,
Expand All @@ -510,7 +510,7 @@ define <vscale x 2 x i64> @intrinsic_vfcvt_mask_x.f.v_nxv2i64_nxv2f64(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv2i64.nxv2f64(
<vscale x 2 x i64> %0,
Expand All @@ -530,7 +530,7 @@ define <vscale x 4 x i64> @intrinsic_vfcvt_x.f.v_nxv4i64_nxv4f64(<vscale x 4 x d
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vfcvt.x.f.v.nxv4i64.nxv4f64(
<vscale x 4 x double> %0,
Expand All @@ -550,7 +550,7 @@ define <vscale x 4 x i64> @intrinsic_vfcvt_mask_x.f.v_nxv4i64_nxv4f64(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv4i64.nxv4f64(
<vscale x 4 x i64> %0,
Expand All @@ -570,7 +570,7 @@ define <vscale x 8 x i64> @intrinsic_vfcvt_x.f.v_nxv8i64_nxv8f64(<vscale x 8 x d
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vfcvt.x.f.v.nxv8i64.nxv8f64(
<vscale x 8 x double> %0,
Expand All @@ -590,7 +590,7 @@ define <vscale x 8 x i64> @intrinsic_vfcvt_mask_x.f.v_nxv8i64_nxv8f64(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu
; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vfcvt.x.f.v.mask.nxv8i64.nxv8f64(
<vscale x 8 x i64> %0,
Expand Down
62 changes: 31 additions & 31 deletions llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f-rv32.ll
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s
; RUN: < %s | FileCheck %s
declare <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16(
<vscale x 1 x half>,
i32);
Expand All @@ -10,7 +10,7 @@ define <vscale x 1 x i16> @intrinsic_vfcvt_xu.f.v_nxv1i16_nxv1f16(<vscale x 1 x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16(
<vscale x 1 x half> %0,
Expand All @@ -30,7 +30,7 @@ define <vscale x 1 x i16> @intrinsic_vfcvt_mask_xu.f.v_nxv1i16_nxv1f16(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i16.nxv1f16(
<vscale x 1 x i16> %0,
Expand All @@ -50,7 +50,7 @@ define <vscale x 2 x i16> @intrinsic_vfcvt_xu.f.v_nxv2i16_nxv2f16(<vscale x 2 x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16(
<vscale x 2 x half> %0,
Expand All @@ -70,7 +70,7 @@ define <vscale x 2 x i16> @intrinsic_vfcvt_mask_xu.f.v_nxv2i16_nxv2f16(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i16.nxv2f16(
<vscale x 2 x i16> %0,
Expand All @@ -90,7 +90,7 @@ define <vscale x 4 x i16> @intrinsic_vfcvt_xu.f.v_nxv4i16_nxv4f16(<vscale x 4 x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16(
<vscale x 4 x half> %0,
Expand All @@ -110,7 +110,7 @@ define <vscale x 4 x i16> @intrinsic_vfcvt_mask_xu.f.v_nxv4i16_nxv4f16(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i16.nxv4f16(
<vscale x 4 x i16> %0,
Expand All @@ -130,7 +130,7 @@ define <vscale x 8 x i16> @intrinsic_vfcvt_xu.f.v_nxv8i16_nxv8f16(<vscale x 8 x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16(
<vscale x 8 x half> %0,
Expand All @@ -150,7 +150,7 @@ define <vscale x 8 x i16> @intrinsic_vfcvt_mask_xu.f.v_nxv8i16_nxv8f16(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i16.nxv8f16(
<vscale x 8 x i16> %0,
Expand All @@ -170,7 +170,7 @@ define <vscale x 16 x i16> @intrinsic_vfcvt_xu.f.v_nxv16i16_nxv16f16(<vscale x 1
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16(
<vscale x 16 x half> %0,
Expand All @@ -190,7 +190,7 @@ define <vscale x 16 x i16> @intrinsic_vfcvt_mask_xu.f.v_nxv16i16_nxv16f16(<vscal
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv16i16.nxv16f16(
<vscale x 16 x i16> %0,
Expand All @@ -210,7 +210,7 @@ define <vscale x 32 x i16> @intrinsic_vfcvt_xu.f.v_nxv32i16_nxv32f16(<vscale x 3
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv32i16.nxv32f16(
<vscale x 32 x half> %0,
Expand All @@ -230,7 +230,7 @@ define <vscale x 32 x i16> @intrinsic_vfcvt_mask_xu.f.v_nxv32i16_nxv32f16(<vscal
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv32i16.nxv32f16(
<vscale x 32 x i16> %0,
Expand All @@ -250,7 +250,7 @@ define <vscale x 1 x i32> @intrinsic_vfcvt_xu.f.v_nxv1i32_nxv1f32(<vscale x 1 x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv1i32.nxv1f32(
<vscale x 1 x float> %0,
Expand All @@ -270,7 +270,7 @@ define <vscale x 1 x i32> @intrinsic_vfcvt_mask_xu.f.v_nxv1i32_nxv1f32(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i32.nxv1f32(
<vscale x 1 x i32> %0,
Expand All @@ -290,7 +290,7 @@ define <vscale x 2 x i32> @intrinsic_vfcvt_xu.f.v_nxv2i32_nxv2f32(<vscale x 2 x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv2i32.nxv2f32(
<vscale x 2 x float> %0,
Expand All @@ -310,7 +310,7 @@ define <vscale x 2 x i32> @intrinsic_vfcvt_mask_xu.f.v_nxv2i32_nxv2f32(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i32.nxv2f32(
<vscale x 2 x i32> %0,
Expand All @@ -330,7 +330,7 @@ define <vscale x 4 x i32> @intrinsic_vfcvt_xu.f.v_nxv4i32_nxv4f32(<vscale x 4 x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv4i32.nxv4f32(
<vscale x 4 x float> %0,
Expand All @@ -350,7 +350,7 @@ define <vscale x 4 x i32> @intrinsic_vfcvt_mask_xu.f.v_nxv4i32_nxv4f32(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i32.nxv4f32(
<vscale x 4 x i32> %0,
Expand All @@ -370,7 +370,7 @@ define <vscale x 8 x i32> @intrinsic_vfcvt_xu.f.v_nxv8i32_nxv8f32(<vscale x 8 x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv8i32.nxv8f32(
<vscale x 8 x float> %0,
Expand All @@ -390,7 +390,7 @@ define <vscale x 8 x i32> @intrinsic_vfcvt_mask_xu.f.v_nxv8i32_nxv8f32(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i32.nxv8f32(
<vscale x 8 x i32> %0,
Expand All @@ -410,7 +410,7 @@ define <vscale x 16 x i32> @intrinsic_vfcvt_xu.f.v_nxv16i32_nxv16f32(<vscale x 1
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv16i32.nxv16f32(
<vscale x 16 x float> %0,
Expand All @@ -430,7 +430,7 @@ define <vscale x 16 x i32> @intrinsic_vfcvt_mask_xu.f.v_nxv16i32_nxv16f32(<vscal
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv16i32.nxv16f32(
<vscale x 16 x i32> %0,
Expand All @@ -450,7 +450,7 @@ define <vscale x 1 x i64> @intrinsic_vfcvt_xu.f.v_nxv1i64_nxv1f64(<vscale x 1 x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv1i64.nxv1f64(
<vscale x 1 x double> %0,
Expand All @@ -470,7 +470,7 @@ define <vscale x 1 x i64> @intrinsic_vfcvt_mask_xu.f.v_nxv1i64_nxv1f64(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i64.nxv1f64(
<vscale x 1 x i64> %0,
Expand All @@ -490,7 +490,7 @@ define <vscale x 2 x i64> @intrinsic_vfcvt_xu.f.v_nxv2i64_nxv2f64(<vscale x 2 x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv2i64.nxv2f64(
<vscale x 2 x double> %0,
Expand All @@ -510,7 +510,7 @@ define <vscale x 2 x i64> @intrinsic_vfcvt_mask_xu.f.v_nxv2i64_nxv2f64(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i64.nxv2f64(
<vscale x 2 x i64> %0,
Expand All @@ -530,7 +530,7 @@ define <vscale x 4 x i64> @intrinsic_vfcvt_xu.f.v_nxv4i64_nxv4f64(<vscale x 4 x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv4i64.nxv4f64(
<vscale x 4 x double> %0,
Expand All @@ -550,7 +550,7 @@ define <vscale x 4 x i64> @intrinsic_vfcvt_mask_xu.f.v_nxv4i64_nxv4f64(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i64.nxv4f64(
<vscale x 4 x i64> %0,
Expand All @@ -570,7 +570,7 @@ define <vscale x 8 x i64> @intrinsic_vfcvt_xu.f.v_nxv8i64_nxv8f64(<vscale x 8 x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv8i64.nxv8f64(
<vscale x 8 x double> %0,
Expand All @@ -590,7 +590,7 @@ define <vscale x 8 x i64> @intrinsic_vfcvt_mask_xu.f.v_nxv8i64_nxv8f64(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i64.nxv8f64(
<vscale x 8 x i64> %0,
Expand Down
62 changes: 31 additions & 31 deletions llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f-rv64.ll
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s
; RUN: < %s | FileCheck %s
declare <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16(
<vscale x 1 x half>,
i64);
Expand All @@ -10,7 +10,7 @@ define <vscale x 1 x i16> @intrinsic_vfcvt_xu.f.v_nxv1i16_nxv1f16(<vscale x 1 x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16(
<vscale x 1 x half> %0,
Expand All @@ -30,7 +30,7 @@ define <vscale x 1 x i16> @intrinsic_vfcvt_mask_xu.f.v_nxv1i16_nxv1f16(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i16.nxv1f16(
<vscale x 1 x i16> %0,
Expand All @@ -50,7 +50,7 @@ define <vscale x 2 x i16> @intrinsic_vfcvt_xu.f.v_nxv2i16_nxv2f16(<vscale x 2 x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16(
<vscale x 2 x half> %0,
Expand All @@ -70,7 +70,7 @@ define <vscale x 2 x i16> @intrinsic_vfcvt_mask_xu.f.v_nxv2i16_nxv2f16(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i16.nxv2f16(
<vscale x 2 x i16> %0,
Expand All @@ -90,7 +90,7 @@ define <vscale x 4 x i16> @intrinsic_vfcvt_xu.f.v_nxv4i16_nxv4f16(<vscale x 4 x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16(
<vscale x 4 x half> %0,
Expand All @@ -110,7 +110,7 @@ define <vscale x 4 x i16> @intrinsic_vfcvt_mask_xu.f.v_nxv4i16_nxv4f16(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i16.nxv4f16(
<vscale x 4 x i16> %0,
Expand All @@ -130,7 +130,7 @@ define <vscale x 8 x i16> @intrinsic_vfcvt_xu.f.v_nxv8i16_nxv8f16(<vscale x 8 x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16(
<vscale x 8 x half> %0,
Expand All @@ -150,7 +150,7 @@ define <vscale x 8 x i16> @intrinsic_vfcvt_mask_xu.f.v_nxv8i16_nxv8f16(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i16.nxv8f16(
<vscale x 8 x i16> %0,
Expand All @@ -170,7 +170,7 @@ define <vscale x 16 x i16> @intrinsic_vfcvt_xu.f.v_nxv16i16_nxv16f16(<vscale x 1
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16(
<vscale x 16 x half> %0,
Expand All @@ -190,7 +190,7 @@ define <vscale x 16 x i16> @intrinsic_vfcvt_mask_xu.f.v_nxv16i16_nxv16f16(<vscal
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv16i16.nxv16f16(
<vscale x 16 x i16> %0,
Expand All @@ -210,7 +210,7 @@ define <vscale x 32 x i16> @intrinsic_vfcvt_xu.f.v_nxv32i16_nxv32f16(<vscale x 3
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv32i16.nxv32f16(
<vscale x 32 x half> %0,
Expand All @@ -230,7 +230,7 @@ define <vscale x 32 x i16> @intrinsic_vfcvt_mask_xu.f.v_nxv32i16_nxv32f16(<vscal
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vfcvt.xu.f.v.mask.nxv32i16.nxv32f16(
<vscale x 32 x i16> %0,
Expand All @@ -250,7 +250,7 @@ define <vscale x 1 x i32> @intrinsic_vfcvt_xu.f.v_nxv1i32_nxv1f32(<vscale x 1 x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv1i32.nxv1f32(
<vscale x 1 x float> %0,
Expand All @@ -270,7 +270,7 @@ define <vscale x 1 x i32> @intrinsic_vfcvt_mask_xu.f.v_nxv1i32_nxv1f32(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i32.nxv1f32(
<vscale x 1 x i32> %0,
Expand All @@ -290,7 +290,7 @@ define <vscale x 2 x i32> @intrinsic_vfcvt_xu.f.v_nxv2i32_nxv2f32(<vscale x 2 x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv2i32.nxv2f32(
<vscale x 2 x float> %0,
Expand All @@ -310,7 +310,7 @@ define <vscale x 2 x i32> @intrinsic_vfcvt_mask_xu.f.v_nxv2i32_nxv2f32(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i32.nxv2f32(
<vscale x 2 x i32> %0,
Expand All @@ -330,7 +330,7 @@ define <vscale x 4 x i32> @intrinsic_vfcvt_xu.f.v_nxv4i32_nxv4f32(<vscale x 4 x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv4i32.nxv4f32(
<vscale x 4 x float> %0,
Expand All @@ -350,7 +350,7 @@ define <vscale x 4 x i32> @intrinsic_vfcvt_mask_xu.f.v_nxv4i32_nxv4f32(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i32.nxv4f32(
<vscale x 4 x i32> %0,
Expand All @@ -370,7 +370,7 @@ define <vscale x 8 x i32> @intrinsic_vfcvt_xu.f.v_nxv8i32_nxv8f32(<vscale x 8 x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv8i32.nxv8f32(
<vscale x 8 x float> %0,
Expand All @@ -390,7 +390,7 @@ define <vscale x 8 x i32> @intrinsic_vfcvt_mask_xu.f.v_nxv8i32_nxv8f32(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i32.nxv8f32(
<vscale x 8 x i32> %0,
Expand All @@ -410,7 +410,7 @@ define <vscale x 16 x i32> @intrinsic_vfcvt_xu.f.v_nxv16i32_nxv16f32(<vscale x 1
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vfcvt.xu.f.v.nxv16i32.nxv16f32(
<vscale x 16 x float> %0,
Expand All @@ -430,7 +430,7 @@ define <vscale x 16 x i32> @intrinsic_vfcvt_mask_xu.f.v_nxv16i32_nxv16f32(<vscal
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vfcvt.xu.f.v.mask.nxv16i32.nxv16f32(
<vscale x 16 x i32> %0,
Expand All @@ -450,7 +450,7 @@ define <vscale x 1 x i64> @intrinsic_vfcvt_xu.f.v_nxv1i64_nxv1f64(<vscale x 1 x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv1i64.nxv1f64(
<vscale x 1 x double> %0,
Expand All @@ -470,7 +470,7 @@ define <vscale x 1 x i64> @intrinsic_vfcvt_mask_xu.f.v_nxv1i64_nxv1f64(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i64.nxv1f64(
<vscale x 1 x i64> %0,
Expand All @@ -490,7 +490,7 @@ define <vscale x 2 x i64> @intrinsic_vfcvt_xu.f.v_nxv2i64_nxv2f64(<vscale x 2 x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv2i64.nxv2f64(
<vscale x 2 x double> %0,
Expand All @@ -510,7 +510,7 @@ define <vscale x 2 x i64> @intrinsic_vfcvt_mask_xu.f.v_nxv2i64_nxv2f64(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v10, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i64.nxv2f64(
<vscale x 2 x i64> %0,
Expand All @@ -530,7 +530,7 @@ define <vscale x 4 x i64> @intrinsic_vfcvt_xu.f.v_nxv4i64_nxv4f64(<vscale x 4 x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv4i64.nxv4f64(
<vscale x 4 x double> %0,
Expand All @@ -550,7 +550,7 @@ define <vscale x 4 x i64> @intrinsic_vfcvt_mask_xu.f.v_nxv4i64_nxv4f64(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v12, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i64.nxv4f64(
<vscale x 4 x i64> %0,
Expand All @@ -570,7 +570,7 @@ define <vscale x 8 x i64> @intrinsic_vfcvt_xu.f.v_nxv8i64_nxv8f64(<vscale x 8 x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v8
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vfcvt.xu.f.v.nxv8i64.nxv8f64(
<vscale x 8 x double> %0,
Expand All @@ -590,7 +590,7 @@ define <vscale x 8 x i64> @intrinsic_vfcvt_mask_xu.f.v_nxv8i64_nxv8f64(<vscale x
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu
; CHECK-NEXT: vfcvt.xu.f.v v8, v16, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i64.nxv8f64(
<vscale x 8 x i64> %0,
Expand Down
122 changes: 61 additions & 61 deletions llvm/test/CodeGen/RISCV/rvv/vfdiv-rv32.ll
View file

Large diffs are not rendered by default.

122 changes: 61 additions & 61 deletions llvm/test/CodeGen/RISCV/rvv/vfdiv-rv64.ll
View file

Large diffs are not rendered by default.

30 changes: 15 additions & 15 deletions llvm/test/CodeGen/RISCV/rvv/vfirst-rv32.ll
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s
; RUN: < %s | FileCheck %s
declare i32 @llvm.riscv.vfirst.i32.nxv1i1(
<vscale x 1 x i1>,
i32);
Expand All @@ -10,7 +10,7 @@ define i32 @intrinsic_vfirst_m_i32_nxv1i1(<vscale x 1 x i1> %0, i32 %1) nounwind
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu
; CHECK-NEXT: vfirst.m a0, v0
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vfirst.i32.nxv1i1(
<vscale x 1 x i1> %0,
Expand All @@ -31,7 +31,7 @@ define i32 @intrinsic_vfirst_mask_m_i32_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vfirst.m a0, v25, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vfirst.mask.i32.nxv1i1(
<vscale x 1 x i1> %0,
Expand All @@ -50,7 +50,7 @@ define i32 @intrinsic_vfirst_m_i32_nxv2i1(<vscale x 2 x i1> %0, i32 %1) nounwind
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu
; CHECK-NEXT: vfirst.m a0, v0
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vfirst.i32.nxv2i1(
<vscale x 2 x i1> %0,
Expand All @@ -71,7 +71,7 @@ define i32 @intrinsic_vfirst_mask_m_i32_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vfirst.m a0, v25, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vfirst.mask.i32.nxv2i1(
<vscale x 2 x i1> %0,
Expand All @@ -90,7 +90,7 @@ define i32 @intrinsic_vfirst_m_i32_nxv4i1(<vscale x 4 x i1> %0, i32 %1) nounwind
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu
; CHECK-NEXT: vfirst.m a0, v0
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vfirst.i32.nxv4i1(
<vscale x 4 x i1> %0,
Expand All @@ -111,7 +111,7 @@ define i32 @intrinsic_vfirst_mask_m_i32_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vfirst.m a0, v25, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vfirst.mask.i32.nxv4i1(
<vscale x 4 x i1> %0,
Expand All @@ -130,7 +130,7 @@ define i32 @intrinsic_vfirst_m_i32_nxv8i1(<vscale x 8 x i1> %0, i32 %1) nounwind
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vfirst.m a0, v0
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vfirst.i32.nxv8i1(
<vscale x 8 x i1> %0,
Expand All @@ -151,7 +151,7 @@ define i32 @intrinsic_vfirst_mask_m_i32_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vfirst.m a0, v25, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vfirst.mask.i32.nxv8i1(
<vscale x 8 x i1> %0,
Expand All @@ -170,7 +170,7 @@ define i32 @intrinsic_vfirst_m_i32_nxv16i1(<vscale x 16 x i1> %0, i32 %1) nounwi
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu
; CHECK-NEXT: vfirst.m a0, v0
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vfirst.i32.nxv16i1(
<vscale x 16 x i1> %0,
Expand All @@ -191,7 +191,7 @@ define i32 @intrinsic_vfirst_mask_m_i32_nxv16i1(<vscale x 16 x i1> %0, <vscale x
; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vfirst.m a0, v25, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vfirst.mask.i32.nxv16i1(
<vscale x 16 x i1> %0,
Expand All @@ -210,7 +210,7 @@ define i32 @intrinsic_vfirst_m_i32_nxv32i1(<vscale x 32 x i1> %0, i32 %1) nounwi
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu
; CHECK-NEXT: vfirst.m a0, v0
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vfirst.i32.nxv32i1(
<vscale x 32 x i1> %0,
Expand All @@ -231,7 +231,7 @@ define i32 @intrinsic_vfirst_mask_m_i32_nxv32i1(<vscale x 32 x i1> %0, <vscale x
; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vfirst.m a0, v25, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vfirst.mask.i32.nxv32i1(
<vscale x 32 x i1> %0,
Expand All @@ -250,7 +250,7 @@ define i32 @intrinsic_vfirst_m_i32_nxv64i1(<vscale x 64 x i1> %0, i32 %1) nounwi
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu
; CHECK-NEXT: vfirst.m a0, v0
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vfirst.i32.nxv64i1(
<vscale x 64 x i1> %0,
Expand All @@ -271,7 +271,7 @@ define i32 @intrinsic_vfirst_mask_m_i32_nxv64i1(<vscale x 64 x i1> %0, <vscale x
; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vfirst.m a0, v25, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call i32 @llvm.riscv.vfirst.mask.i32.nxv64i1(
<vscale x 64 x i1> %0,
Expand Down
30 changes: 15 additions & 15 deletions llvm/test/CodeGen/RISCV/rvv/vfirst-rv64.ll
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s
; RUN: < %s | FileCheck %s
declare i64 @llvm.riscv.vfirst.i64.nxv1i1(
<vscale x 1 x i1>,
i64);
Expand All @@ -10,7 +10,7 @@ define i64 @intrinsic_vfirst_m_i64_nxv1i1(<vscale x 1 x i1> %0, i64 %1) nounwind
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu
; CHECK-NEXT: vfirst.m a0, v0
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vfirst.i64.nxv1i1(
<vscale x 1 x i1> %0,
Expand All @@ -31,7 +31,7 @@ define i64 @intrinsic_vfirst_mask_m_i64_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vfirst.m a0, v25, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vfirst.mask.i64.nxv1i1(
<vscale x 1 x i1> %0,
Expand All @@ -50,7 +50,7 @@ define i64 @intrinsic_vfirst_m_i64_nxv2i1(<vscale x 2 x i1> %0, i64 %1) nounwind
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu
; CHECK-NEXT: vfirst.m a0, v0
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vfirst.i64.nxv2i1(
<vscale x 2 x i1> %0,
Expand All @@ -71,7 +71,7 @@ define i64 @intrinsic_vfirst_mask_m_i64_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vfirst.m a0, v25, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vfirst.mask.i64.nxv2i1(
<vscale x 2 x i1> %0,
Expand All @@ -90,7 +90,7 @@ define i64 @intrinsic_vfirst_m_i64_nxv4i1(<vscale x 4 x i1> %0, i64 %1) nounwind
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu
; CHECK-NEXT: vfirst.m a0, v0
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vfirst.i64.nxv4i1(
<vscale x 4 x i1> %0,
Expand All @@ -111,7 +111,7 @@ define i64 @intrinsic_vfirst_mask_m_i64_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vfirst.m a0, v25, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vfirst.mask.i64.nxv4i1(
<vscale x 4 x i1> %0,
Expand All @@ -130,7 +130,7 @@ define i64 @intrinsic_vfirst_m_i64_nxv8i1(<vscale x 8 x i1> %0, i64 %1) nounwind
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vfirst.m a0, v0
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vfirst.i64.nxv8i1(
<vscale x 8 x i1> %0,
Expand All @@ -151,7 +151,7 @@ define i64 @intrinsic_vfirst_mask_m_i64_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vfirst.m a0, v25, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vfirst.mask.i64.nxv8i1(
<vscale x 8 x i1> %0,
Expand All @@ -170,7 +170,7 @@ define i64 @intrinsic_vfirst_m_i64_nxv16i1(<vscale x 16 x i1> %0, i64 %1) nounwi
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu
; CHECK-NEXT: vfirst.m a0, v0
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vfirst.i64.nxv16i1(
<vscale x 16 x i1> %0,
Expand All @@ -191,7 +191,7 @@ define i64 @intrinsic_vfirst_mask_m_i64_nxv16i1(<vscale x 16 x i1> %0, <vscale x
; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vfirst.m a0, v25, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vfirst.mask.i64.nxv16i1(
<vscale x 16 x i1> %0,
Expand All @@ -210,7 +210,7 @@ define i64 @intrinsic_vfirst_m_i64_nxv32i1(<vscale x 32 x i1> %0, i64 %1) nounwi
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu
; CHECK-NEXT: vfirst.m a0, v0
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vfirst.i64.nxv32i1(
<vscale x 32 x i1> %0,
Expand All @@ -231,7 +231,7 @@ define i64 @intrinsic_vfirst_mask_m_i64_nxv32i1(<vscale x 32 x i1> %0, <vscale x
; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vfirst.m a0, v25, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vfirst.mask.i64.nxv32i1(
<vscale x 32 x i1> %0,
Expand All @@ -250,7 +250,7 @@ define i64 @intrinsic_vfirst_m_i64_nxv64i1(<vscale x 64 x i1> %0, i64 %1) nounwi
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu
; CHECK-NEXT: vfirst.m a0, v0
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vfirst.i64.nxv64i1(
<vscale x 64 x i1> %0,
Expand All @@ -271,7 +271,7 @@ define i64 @intrinsic_vfirst_mask_m_i64_nxv64i1(<vscale x 64 x i1> %0, <vscale x
; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vfirst.m a0, v25, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
; CHECK-NEXT: ret
entry:
%a = call i64 @llvm.riscv.vfirst.mask.i64.nxv64i1(
<vscale x 64 x i1> %0,
Expand Down
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