144 changes: 60 additions & 84 deletions llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1154,10 +1154,9 @@ define i64 @vreduce_add_nxv1i64(<vscale x 1 x i64> %v) {
; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vredsum.vs v25, v8, v25
; CHECK-NEXT: vmv.x.s a0, v25
; CHECK-NEXT: addi a1, zero, 1
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vsrl.vx v25, v25, a2
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetivli a2, 1, e64,m1,ta,mu
; CHECK-NEXT: vsrl.vx v25, v25, a1
; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; CHECK-NEXT: vmv.x.s a1, v25
; CHECK-NEXT: ret
Expand All @@ -1174,10 +1173,9 @@ define i64 @vreduce_umax_nxv1i64(<vscale x 1 x i64> %v) {
; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vredmaxu.vs v25, v8, v25
; CHECK-NEXT: vmv.x.s a0, v25
; CHECK-NEXT: addi a1, zero, 1
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vsrl.vx v25, v25, a2
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetivli a2, 1, e64,m1,ta,mu
; CHECK-NEXT: vsrl.vx v25, v25, a1
; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; CHECK-NEXT: vmv.x.s a1, v25
; CHECK-NEXT: ret
Expand All @@ -1201,8 +1199,7 @@ define i64 @vreduce_smax_nxv1i64(<vscale x 1 x i64> %v) {
; CHECK-NEXT: vor.vv v25, v26, v25
; CHECK-NEXT: vredmax.vs v25, v8, v25
; CHECK-NEXT: vmv.x.s a0, v25
; CHECK-NEXT: addi a2, zero, 1
; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu
; CHECK-NEXT: vsetivli a2, 1, e64,m1,ta,mu
; CHECK-NEXT: vsrl.vx v25, v25, a1
; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; CHECK-NEXT: vmv.x.s a1, v25
Expand All @@ -1220,10 +1217,9 @@ define i64 @vreduce_umin_nxv1i64(<vscale x 1 x i64> %v) {
; CHECK-NEXT: vmv.v.i v25, -1
; CHECK-NEXT: vredminu.vs v25, v8, v25
; CHECK-NEXT: vmv.x.s a0, v25
; CHECK-NEXT: addi a1, zero, 1
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vsrl.vx v25, v25, a2
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetivli a2, 1, e64,m1,ta,mu
; CHECK-NEXT: vsrl.vx v25, v25, a1
; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; CHECK-NEXT: vmv.x.s a1, v25
; CHECK-NEXT: ret
Expand All @@ -1248,8 +1244,7 @@ define i64 @vreduce_smin_nxv1i64(<vscale x 1 x i64> %v) {
; CHECK-NEXT: vor.vv v25, v25, v26
; CHECK-NEXT: vredmin.vs v25, v8, v25
; CHECK-NEXT: vmv.x.s a0, v25
; CHECK-NEXT: addi a2, zero, 1
; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu
; CHECK-NEXT: vsetivli a2, 1, e64,m1,ta,mu
; CHECK-NEXT: vsrl.vx v25, v25, a1
; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; CHECK-NEXT: vmv.x.s a1, v25
Expand All @@ -1267,10 +1262,9 @@ define i64 @vreduce_and_nxv1i64(<vscale x 1 x i64> %v) {
; CHECK-NEXT: vmv.v.i v25, -1
; CHECK-NEXT: vredand.vs v25, v8, v25
; CHECK-NEXT: vmv.x.s a0, v25
; CHECK-NEXT: addi a1, zero, 1
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vsrl.vx v25, v25, a2
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetivli a2, 1, e64,m1,ta,mu
; CHECK-NEXT: vsrl.vx v25, v25, a1
; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; CHECK-NEXT: vmv.x.s a1, v25
; CHECK-NEXT: ret
Expand All @@ -1287,10 +1281,9 @@ define i64 @vreduce_or_nxv1i64(<vscale x 1 x i64> %v) {
; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vredor.vs v25, v8, v25
; CHECK-NEXT: vmv.x.s a0, v25
; CHECK-NEXT: addi a1, zero, 1
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vsrl.vx v25, v25, a2
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetivli a2, 1, e64,m1,ta,mu
; CHECK-NEXT: vsrl.vx v25, v25, a1
; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; CHECK-NEXT: vmv.x.s a1, v25
; CHECK-NEXT: ret
Expand All @@ -1307,10 +1300,9 @@ define i64 @vreduce_xor_nxv1i64(<vscale x 1 x i64> %v) {
; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vredxor.vs v25, v8, v25
; CHECK-NEXT: vmv.x.s a0, v25
; CHECK-NEXT: addi a1, zero, 1
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vsrl.vx v25, v25, a2
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetivli a2, 1, e64,m1,ta,mu
; CHECK-NEXT: vsrl.vx v25, v25, a1
; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; CHECK-NEXT: vmv.x.s a1, v25
; CHECK-NEXT: ret
Expand All @@ -1329,10 +1321,9 @@ define i64 @vreduce_add_nxv2i64(<vscale x 2 x i64> %v) {
; CHECK-NEXT: vredsum.vs v25, v8, v25
; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; CHECK-NEXT: vmv.x.s a0, v25
; CHECK-NEXT: addi a1, zero, 1
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vsrl.vx v25, v25, a2
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetivli a2, 1, e64,m1,ta,mu
; CHECK-NEXT: vsrl.vx v25, v25, a1
; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; CHECK-NEXT: vmv.x.s a1, v25
; CHECK-NEXT: ret
Expand All @@ -1351,10 +1342,9 @@ define i64 @vreduce_umax_nxv2i64(<vscale x 2 x i64> %v) {
; CHECK-NEXT: vredmaxu.vs v25, v8, v25
; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; CHECK-NEXT: vmv.x.s a0, v25
; CHECK-NEXT: addi a1, zero, 1
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vsrl.vx v25, v25, a2
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetivli a2, 1, e64,m1,ta,mu
; CHECK-NEXT: vsrl.vx v25, v25, a1
; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; CHECK-NEXT: vmv.x.s a1, v25
; CHECK-NEXT: ret
Expand All @@ -1380,8 +1370,7 @@ define i64 @vreduce_smax_nxv2i64(<vscale x 2 x i64> %v) {
; CHECK-NEXT: vredmax.vs v25, v8, v25
; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; CHECK-NEXT: vmv.x.s a0, v25
; CHECK-NEXT: addi a2, zero, 1
; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu
; CHECK-NEXT: vsetivli a2, 1, e64,m1,ta,mu
; CHECK-NEXT: vsrl.vx v25, v25, a1
; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; CHECK-NEXT: vmv.x.s a1, v25
Expand All @@ -1401,10 +1390,9 @@ define i64 @vreduce_umin_nxv2i64(<vscale x 2 x i64> %v) {
; CHECK-NEXT: vredminu.vs v25, v8, v25
; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; CHECK-NEXT: vmv.x.s a0, v25
; CHECK-NEXT: addi a1, zero, 1
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vsrl.vx v25, v25, a2
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetivli a2, 1, e64,m1,ta,mu
; CHECK-NEXT: vsrl.vx v25, v25, a1
; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; CHECK-NEXT: vmv.x.s a1, v25
; CHECK-NEXT: ret
Expand All @@ -1431,8 +1419,7 @@ define i64 @vreduce_smin_nxv2i64(<vscale x 2 x i64> %v) {
; CHECK-NEXT: vredmin.vs v25, v8, v25
; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; CHECK-NEXT: vmv.x.s a0, v25
; CHECK-NEXT: addi a2, zero, 1
; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu
; CHECK-NEXT: vsetivli a2, 1, e64,m1,ta,mu
; CHECK-NEXT: vsrl.vx v25, v25, a1
; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; CHECK-NEXT: vmv.x.s a1, v25
Expand All @@ -1452,10 +1439,9 @@ define i64 @vreduce_and_nxv2i64(<vscale x 2 x i64> %v) {
; CHECK-NEXT: vredand.vs v25, v8, v25
; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; CHECK-NEXT: vmv.x.s a0, v25
; CHECK-NEXT: addi a1, zero, 1
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vsrl.vx v25, v25, a2
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetivli a2, 1, e64,m1,ta,mu
; CHECK-NEXT: vsrl.vx v25, v25, a1
; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; CHECK-NEXT: vmv.x.s a1, v25
; CHECK-NEXT: ret
Expand All @@ -1474,10 +1460,9 @@ define i64 @vreduce_or_nxv2i64(<vscale x 2 x i64> %v) {
; CHECK-NEXT: vredor.vs v25, v8, v25
; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; CHECK-NEXT: vmv.x.s a0, v25
; CHECK-NEXT: addi a1, zero, 1
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vsrl.vx v25, v25, a2
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetivli a2, 1, e64,m1,ta,mu
; CHECK-NEXT: vsrl.vx v25, v25, a1
; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; CHECK-NEXT: vmv.x.s a1, v25
; CHECK-NEXT: ret
Expand All @@ -1496,10 +1481,9 @@ define i64 @vreduce_xor_nxv2i64(<vscale x 2 x i64> %v) {
; CHECK-NEXT: vredxor.vs v25, v8, v25
; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; CHECK-NEXT: vmv.x.s a0, v25
; CHECK-NEXT: addi a1, zero, 1
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vsrl.vx v25, v25, a2
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetivli a2, 1, e64,m1,ta,mu
; CHECK-NEXT: vsrl.vx v25, v25, a1
; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; CHECK-NEXT: vmv.x.s a1, v25
; CHECK-NEXT: ret
Expand All @@ -1518,10 +1502,9 @@ define i64 @vreduce_add_nxv4i64(<vscale x 4 x i64> %v) {
; CHECK-NEXT: vredsum.vs v25, v8, v25
; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; CHECK-NEXT: vmv.x.s a0, v25
; CHECK-NEXT: addi a1, zero, 1
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vsrl.vx v25, v25, a2
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetivli a2, 1, e64,m1,ta,mu
; CHECK-NEXT: vsrl.vx v25, v25, a1
; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; CHECK-NEXT: vmv.x.s a1, v25
; CHECK-NEXT: ret
Expand All @@ -1540,10 +1523,9 @@ define i64 @vreduce_umax_nxv4i64(<vscale x 4 x i64> %v) {
; CHECK-NEXT: vredmaxu.vs v25, v8, v25
; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; CHECK-NEXT: vmv.x.s a0, v25
; CHECK-NEXT: addi a1, zero, 1
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vsrl.vx v25, v25, a2
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetivli a2, 1, e64,m1,ta,mu
; CHECK-NEXT: vsrl.vx v25, v25, a1
; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; CHECK-NEXT: vmv.x.s a1, v25
; CHECK-NEXT: ret
Expand All @@ -1569,8 +1551,7 @@ define i64 @vreduce_smax_nxv4i64(<vscale x 4 x i64> %v) {
; CHECK-NEXT: vredmax.vs v25, v8, v25
; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; CHECK-NEXT: vmv.x.s a0, v25
; CHECK-NEXT: addi a2, zero, 1
; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu
; CHECK-NEXT: vsetivli a2, 1, e64,m1,ta,mu
; CHECK-NEXT: vsrl.vx v25, v25, a1
; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; CHECK-NEXT: vmv.x.s a1, v25
Expand All @@ -1590,10 +1571,9 @@ define i64 @vreduce_umin_nxv4i64(<vscale x 4 x i64> %v) {
; CHECK-NEXT: vredminu.vs v25, v8, v25
; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; CHECK-NEXT: vmv.x.s a0, v25
; CHECK-NEXT: addi a1, zero, 1
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vsrl.vx v25, v25, a2
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetivli a2, 1, e64,m1,ta,mu
; CHECK-NEXT: vsrl.vx v25, v25, a1
; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; CHECK-NEXT: vmv.x.s a1, v25
; CHECK-NEXT: ret
Expand All @@ -1620,8 +1600,7 @@ define i64 @vreduce_smin_nxv4i64(<vscale x 4 x i64> %v) {
; CHECK-NEXT: vredmin.vs v25, v8, v25
; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; CHECK-NEXT: vmv.x.s a0, v25
; CHECK-NEXT: addi a2, zero, 1
; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu
; CHECK-NEXT: vsetivli a2, 1, e64,m1,ta,mu
; CHECK-NEXT: vsrl.vx v25, v25, a1
; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; CHECK-NEXT: vmv.x.s a1, v25
Expand All @@ -1641,10 +1620,9 @@ define i64 @vreduce_and_nxv4i64(<vscale x 4 x i64> %v) {
; CHECK-NEXT: vredand.vs v25, v8, v25
; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; CHECK-NEXT: vmv.x.s a0, v25
; CHECK-NEXT: addi a1, zero, 1
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vsrl.vx v25, v25, a2
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetivli a2, 1, e64,m1,ta,mu
; CHECK-NEXT: vsrl.vx v25, v25, a1
; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; CHECK-NEXT: vmv.x.s a1, v25
; CHECK-NEXT: ret
Expand All @@ -1663,10 +1641,9 @@ define i64 @vreduce_or_nxv4i64(<vscale x 4 x i64> %v) {
; CHECK-NEXT: vredor.vs v25, v8, v25
; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; CHECK-NEXT: vmv.x.s a0, v25
; CHECK-NEXT: addi a1, zero, 1
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vsrl.vx v25, v25, a2
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetivli a2, 1, e64,m1,ta,mu
; CHECK-NEXT: vsrl.vx v25, v25, a1
; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; CHECK-NEXT: vmv.x.s a1, v25
; CHECK-NEXT: ret
Expand All @@ -1685,10 +1662,9 @@ define i64 @vreduce_xor_nxv4i64(<vscale x 4 x i64> %v) {
; CHECK-NEXT: vredxor.vs v25, v8, v25
; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; CHECK-NEXT: vmv.x.s a0, v25
; CHECK-NEXT: addi a1, zero, 1
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vsrl.vx v25, v25, a2
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetivli a2, 1, e64,m1,ta,mu
; CHECK-NEXT: vsrl.vx v25, v25, a1
; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; CHECK-NEXT: vmv.x.s a1, v25
; CHECK-NEXT: ret
Expand Down
50 changes: 18 additions & 32 deletions llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11,11 +11,10 @@ declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlseg2.mask.nxv16i
define <vscale x 16 x i16> @test_vlseg2_mask_nxv16i16(i16* %base, <vscale x 16 x i1> %mask) {
; CHECK-LABEL: test_vlseg2_mask_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mv a1, zero
; CHECK-NEXT: vsetvli a2, a1, e16,m4,ta,mu
; CHECK-NEXT: vsetivli a1, 0, e16,m4,ta,mu
; CHECK-NEXT: vlseg2e16.v v4, (a0)
; CHECK-NEXT: vmv4r.v v8, v4
; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
; CHECK-NEXT: vsetivli a1, 0, e16,m4,tu,mu
; CHECK-NEXT: vlseg2e16.v v4, (a0), v0.t
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret
Expand All @@ -33,11 +32,10 @@ declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.mask.nxv16
define <vscale x 16 x i16> @test_vlsseg2_mask_nxv16i16(i16* %base, i64 %offset, <vscale x 16 x i1> %mask) {
; CHECK-LABEL: test_vlsseg2_mask_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mv a2, zero
; CHECK-NEXT: vsetvli a3, a2, e16,m4,ta,mu
; CHECK-NEXT: vsetivli a2, 0, e16,m4,ta,mu
; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1
; CHECK-NEXT: vmv4r.v v8, v4
; CHECK-NEXT: vsetvli a2, a2, e16,m4,tu,mu
; CHECK-NEXT: vsetivli a2, 0, e16,m4,tu,mu
; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1, v0.t
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret
Expand All @@ -54,11 +52,10 @@ declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vloxseg2.mask.nxv1
define <vscale x 16 x i16> @test_vloxseg2_mask_nxv16i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask) {
; CHECK-LABEL: test_vloxseg2_mask_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mv a1, zero
; CHECK-NEXT: vsetvli a2, a1, e16,m4,ta,mu
; CHECK-NEXT: vsetivli a1, 0, e16,m4,ta,mu
; CHECK-NEXT: vloxseg2ei16.v v12, (a0), v8
; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
; CHECK-NEXT: vsetivli a1, 0, e16,m4,tu,mu
; CHECK-NEXT: vloxseg2ei16.v v12, (a0), v8, v0.t
; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
Expand All @@ -76,11 +73,10 @@ declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv1
define <vscale x 16 x i16> @test_vluxseg2_mask_nxv16i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask) {
; CHECK-LABEL: test_vluxseg2_mask_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mv a1, zero
; CHECK-NEXT: vsetvli a2, a1, e16,m4,ta,mu
; CHECK-NEXT: vsetivli a1, 0, e16,m4,ta,mu
; CHECK-NEXT: vluxseg2ei16.v v12, (a0), v8
; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
; CHECK-NEXT: vsetivli a1, 0, e16,m4,tu,mu
; CHECK-NEXT: vluxseg2ei16.v v12, (a0), v8, v0.t
; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
Expand All @@ -98,8 +94,7 @@ declare {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.mask
define <vscale x 16 x i16> @test_vlseg2ff_nxv16i16(i16* %base, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mv a2, zero
; CHECK-NEXT: vsetvli a2, a2, e16,m4,ta,mu
; CHECK-NEXT: vsetivli a2, 0, e16,m4,ta,mu
; CHECK-NEXT: vlseg2e16ff.v v4, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a1)
Expand All @@ -117,8 +112,7 @@ define <vscale x 16 x i16> @test_vlseg2ff_mask_nxv16i16(<vscale x 16 x i16> %val
; CHECK-LABEL: test_vlseg2ff_mask_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv4r.v v4, v8
; CHECK-NEXT: mv a2, zero
; CHECK-NEXT: vsetvli a2, a2, e16,m4,tu,mu
; CHECK-NEXT: vsetivli a2, 0, e16,m4,tu,mu
; CHECK-NEXT: vlseg2e16ff.v v4, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a1)
Expand All @@ -140,8 +134,7 @@ define void @test_vsseg2_nxv16i16(<vscale x 16 x i16> %val, i16* %base) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: mv a1, zero
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vsetivli a1, 0, e16,m4,ta,mu
; CHECK-NEXT: vsseg2e16.v v8, (a0)
; CHECK-NEXT: ret
entry:
Expand All @@ -154,8 +147,7 @@ define void @test_vsseg2_mask_nxv16i16(<vscale x 16 x i16> %val, i16* %base, <vs
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: mv a1, zero
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vsetivli a1, 0, e16,m4,ta,mu
; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t
; CHECK-NEXT: ret
entry:
Expand All @@ -171,8 +163,7 @@ define void @test_vssseg2_nxv16i16(<vscale x 16 x i16> %val, i16* %base, i64 %of
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: mv a2, zero
; CHECK-NEXT: vsetvli a2, a2, e16,m4,ta,mu
; CHECK-NEXT: vsetivli a2, 0, e16,m4,ta,mu
; CHECK-NEXT: vssseg2e16.v v8, (a0), a1
; CHECK-NEXT: ret
entry:
Expand All @@ -185,8 +176,7 @@ define void @test_vssseg2_mask_nxv16i16(<vscale x 16 x i16> %val, i16* %base, i6
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: mv a2, zero
; CHECK-NEXT: vsetvli a2, a2, e16,m4,ta,mu
; CHECK-NEXT: vsetivli a2, 0, e16,m4,ta,mu
; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t
; CHECK-NEXT: ret
entry:
Expand All @@ -203,8 +193,7 @@ define void @test_vsoxseg2_nxv16i16_nxv16i16(<vscale x 16 x i16> %val, i16* %bas
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
; CHECK-NEXT: vmv4r.v v28, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: mv a1, zero
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vsetivli a1, 0, e16,m4,ta,mu
; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v28
; CHECK-NEXT: ret
entry:
Expand All @@ -218,8 +207,7 @@ define void @test_vsoxseg2_mask_nxv16i16_nxv16i16(<vscale x 16 x i16> %val, i16*
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
; CHECK-NEXT: vmv4r.v v28, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: mv a1, zero
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vsetivli a1, 0, e16,m4,ta,mu
; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v28, v0.t
; CHECK-NEXT: ret
entry:
Expand All @@ -236,8 +224,7 @@ define void @test_vsuxseg2_nxv16i16_nxv16i16(<vscale x 16 x i16> %val, i16* %bas
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
; CHECK-NEXT: vmv4r.v v28, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: mv a1, zero
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vsetivli a1, 0, e16,m4,ta,mu
; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v28
; CHECK-NEXT: ret
entry:
Expand All @@ -251,8 +238,7 @@ define void @test_vsuxseg2_mask_nxv16i16_nxv16i16(<vscale x 16 x i16> %val, i16*
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
; CHECK-NEXT: vmv4r.v v28, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: mv a1, zero
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vsetivli a1, 0, e16,m4,ta,mu
; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v28, v0.t
; CHECK-NEXT: ret
entry:
Expand Down