113 changes: 113 additions & 0 deletions llvm/test/MC/AArch64/SME2/st1d.s
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --mattr=-sme2 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST


st1d {z0.d, z8.d}, pn8, [x0, x0, lsl #3] // 10100001-00100000-01100000-00000000
// CHECK-INST: st1d { z0.d, z8.d }, pn8, [x0, x0, lsl #3]
// CHECK-ENCODING: [0x00,0x60,0x20,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a1206000 <unknown>

st1d {z21.d, z29.d}, pn13, [x10, x21, lsl #3] // 10100001-00110101-01110101-01010101
// CHECK-INST: st1d { z21.d, z29.d }, pn13, [x10, x21, lsl #3]
// CHECK-ENCODING: [0x55,0x75,0x35,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a1357555 <unknown>

st1d {z23.d, z31.d}, pn11, [x13, x8, lsl #3] // 10100001-00101000-01101101-10110111
// CHECK-INST: st1d { z23.d, z31.d }, pn11, [x13, x8, lsl #3]
// CHECK-ENCODING: [0xb7,0x6d,0x28,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a1286db7 <unknown>

st1d {z23.d, z31.d}, pn15, [sp, xzr, lsl #3] // 10100001-00111111-01111111-11110111
// CHECK-INST: st1d { z23.d, z31.d }, pn15, [sp, xzr, lsl #3]
// CHECK-ENCODING: [0xf7,0x7f,0x3f,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a13f7ff7 <unknown>


st1d {z0.d, z8.d}, pn8, [x0] // 10100001-01100000-01100000-00000000
// CHECK-INST: st1d { z0.d, z8.d }, pn8, [x0]
// CHECK-ENCODING: [0x00,0x60,0x60,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a1606000 <unknown>

st1d {z21.d, z29.d}, pn13, [x10, #10, mul vl] // 10100001-01100101-01110101-01010101
// CHECK-INST: st1d { z21.d, z29.d }, pn13, [x10, #10, mul vl]
// CHECK-ENCODING: [0x55,0x75,0x65,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a1657555 <unknown>

st1d {z23.d, z31.d}, pn11, [x13, #-16, mul vl] // 10100001-01101000-01101101-10110111
// CHECK-INST: st1d { z23.d, z31.d }, pn11, [x13, #-16, mul vl]
// CHECK-ENCODING: [0xb7,0x6d,0x68,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a1686db7 <unknown>

st1d {z23.d, z31.d}, pn15, [sp, #-2, mul vl] // 10100001-01101111-01111111-11110111
// CHECK-INST: st1d { z23.d, z31.d }, pn15, [sp, #-2, mul vl]
// CHECK-ENCODING: [0xf7,0x7f,0x6f,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a16f7ff7 <unknown>


st1d {z0.d, z4.d, z8.d, z12.d}, pn8, [x0, x0, lsl #3] // 10100001-00100000-11100000-00000000
// CHECK-INST: st1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0, x0, lsl #3]
// CHECK-ENCODING: [0x00,0xe0,0x20,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a120e000 <unknown>

st1d {z17.d, z21.d, z25.d, z29.d}, pn13, [x10, x21, lsl #3] // 10100001-00110101-11110101-01010001
// CHECK-INST: st1d { z17.d, z21.d, z25.d, z29.d }, pn13, [x10, x21, lsl #3]
// CHECK-ENCODING: [0x51,0xf5,0x35,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a135f551 <unknown>

st1d {z19.d, z23.d, z27.d, z31.d}, pn11, [x13, x8, lsl #3] // 10100001-00101000-11101101-10110011
// CHECK-INST: st1d { z19.d, z23.d, z27.d, z31.d }, pn11, [x13, x8, lsl #3]
// CHECK-ENCODING: [0xb3,0xed,0x28,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a128edb3 <unknown>

st1d {z19.d, z23.d, z27.d, z31.d}, pn15, [sp, xzr, lsl #3] // 10100001-00111111-11111111-11110011
// CHECK-INST: st1d { z19.d, z23.d, z27.d, z31.d }, pn15, [sp, xzr, lsl #3]
// CHECK-ENCODING: [0xf3,0xff,0x3f,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a13ffff3 <unknown>


st1d {z0.d, z4.d, z8.d, z12.d}, pn8, [x0] // 10100001-01100000-11100000-00000000
// CHECK-INST: st1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0]
// CHECK-ENCODING: [0x00,0xe0,0x60,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a160e000 <unknown>

st1d {z17.d, z21.d, z25.d, z29.d}, pn13, [x10, #20, mul vl] // 10100001-01100101-11110101-01010001
// CHECK-INST: st1d { z17.d, z21.d, z25.d, z29.d }, pn13, [x10, #20, mul vl]
// CHECK-ENCODING: [0x51,0xf5,0x65,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a165f551 <unknown>

st1d {z19.d, z23.d, z27.d, z31.d}, pn11, [x13, #-32, mul vl] // 10100001-01101000-11101101-10110011
// CHECK-INST: st1d { z19.d, z23.d, z27.d, z31.d }, pn11, [x13, #-32, mul vl]
// CHECK-ENCODING: [0xb3,0xed,0x68,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a168edb3 <unknown>

st1d {z19.d, z23.d, z27.d, z31.d}, pn15, [sp, #-4, mul vl] // 10100001-01101111-11111111-11110011
// CHECK-INST: st1d { z19.d, z23.d, z27.d, z31.d }, pn15, [sp, #-4, mul vl]
// CHECK-ENCODING: [0xf3,0xff,0x6f,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a16ffff3 <unknown>

115 changes: 115 additions & 0 deletions llvm/test/MC/AArch64/SME2/st1h.s
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2 --no-print-imm-hex - \
// RUN: | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --mattr=-sme2 --no-print-imm-hex - \
// RUN: |FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST


st1h {z0.h, z8.h}, pn8, [x0, x0, lsl #1] // 10100001-00100000-00100000-00000000
// CHECK-INST: st1h { z0.h, z8.h }, pn8, [x0, x0, lsl #1]
// CHECK-ENCODING: [0x00,0x20,0x20,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a1202000 <unknown>

st1h {z21.h, z29.h}, pn13, [x10, x21, lsl #1] // 10100001-00110101-00110101-01010101
// CHECK-INST: st1h { z21.h, z29.h }, pn13, [x10, x21, lsl #1]
// CHECK-ENCODING: [0x55,0x35,0x35,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a1353555 <unknown>

st1h {z23.h, z31.h}, pn11, [x13, x8, lsl #1] // 10100001-00101000-00101101-10110111
// CHECK-INST: st1h { z23.h, z31.h }, pn11, [x13, x8, lsl #1]
// CHECK-ENCODING: [0xb7,0x2d,0x28,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a1282db7 <unknown>

st1h {z23.h, z31.h}, pn15, [sp, xzr, lsl #1] // 10100001-00111111-00111111-11110111
// CHECK-INST: st1h { z23.h, z31.h }, pn15, [sp, xzr, lsl #1]
// CHECK-ENCODING: [0xf7,0x3f,0x3f,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a13f3ff7 <unknown>


st1h {z0.h, z8.h}, pn8, [x0] // 10100001-01100000-00100000-00000000
// CHECK-INST: st1h { z0.h, z8.h }, pn8, [x0]
// CHECK-ENCODING: [0x00,0x20,0x60,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a1602000 <unknown>

st1h {z21.h, z29.h}, pn13, [x10, #10, mul vl] // 10100001-01100101-00110101-01010101
// CHECK-INST: st1h { z21.h, z29.h }, pn13, [x10, #10, mul vl]
// CHECK-ENCODING: [0x55,0x35,0x65,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a1653555 <unknown>

st1h {z23.h, z31.h}, pn11, [x13, #-16, mul vl] // 10100001-01101000-00101101-10110111
// CHECK-INST: st1h { z23.h, z31.h }, pn11, [x13, #-16, mul vl]
// CHECK-ENCODING: [0xb7,0x2d,0x68,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a1682db7 <unknown>

st1h {z23.h, z31.h}, pn15, [sp, #-2, mul vl] // 10100001-01101111-00111111-11110111
// CHECK-INST: st1h { z23.h, z31.h }, pn15, [sp, #-2, mul vl]
// CHECK-ENCODING: [0xf7,0x3f,0x6f,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a16f3ff7 <unknown>


st1h {z0.h, z4.h, z8.h, z12.h}, pn8, [x0, x0, lsl #1] // 10100001-00100000-10100000-00000000
// CHECK-INST: st1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0, x0, lsl #1]
// CHECK-ENCODING: [0x00,0xa0,0x20,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a120a000 <unknown>

st1h {z17.h, z21.h, z25.h, z29.h}, pn13, [x10, x21, lsl #1] // 10100001-00110101-10110101-01010001
// CHECK-INST: st1h { z17.h, z21.h, z25.h, z29.h }, pn13, [x10, x21, lsl #1]
// CHECK-ENCODING: [0x51,0xb5,0x35,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a135b551 <unknown>

st1h {z19.h, z23.h, z27.h, z31.h}, pn11, [x13, x8, lsl #1] // 10100001-00101000-10101101-10110011
// CHECK-INST: st1h { z19.h, z23.h, z27.h, z31.h }, pn11, [x13, x8, lsl #1]
// CHECK-ENCODING: [0xb3,0xad,0x28,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a128adb3 <unknown>

st1h {z19.h, z23.h, z27.h, z31.h}, pn15, [sp, xzr, lsl #1] // 10100001-00111111-10111111-11110011
// CHECK-INST: st1h { z19.h, z23.h, z27.h, z31.h }, pn15, [sp, xzr, lsl #1]
// CHECK-ENCODING: [0xf3,0xbf,0x3f,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a13fbff3 <unknown>


st1h {z0.h, z4.h, z8.h, z12.h}, pn8, [x0] // 10100001-01100000-10100000-00000000
// CHECK-INST: st1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0]
// CHECK-ENCODING: [0x00,0xa0,0x60,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a160a000 <unknown>

st1h {z17.h, z21.h, z25.h, z29.h}, pn13, [x10, #20, mul vl] // 10100001-01100101-10110101-01010001
// CHECK-INST: st1h { z17.h, z21.h, z25.h, z29.h }, pn13, [x10, #20, mul vl]
// CHECK-ENCODING: [0x51,0xb5,0x65,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a165b551 <unknown>

st1h {z19.h, z23.h, z27.h, z31.h}, pn11, [x13, #-32, mul vl] // 10100001-01101000-10101101-10110011
// CHECK-INST: st1h { z19.h, z23.h, z27.h, z31.h }, pn11, [x13, #-32, mul vl]
// CHECK-ENCODING: [0xb3,0xad,0x68,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a168adb3 <unknown>

st1h {z19.h, z23.h, z27.h, z31.h}, pn15, [sp, #-4, mul vl] // 10100001-01101111-10111111-11110011
// CHECK-INST: st1h { z19.h, z23.h, z27.h, z31.h }, pn15, [sp, #-4, mul vl]
// CHECK-ENCODING: [0xf3,0xbf,0x6f,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a16fbff3 <unknown>

115 changes: 115 additions & 0 deletions llvm/test/MC/AArch64/SME2/st1w.s
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2 --no-print-imm-hex - \
// RUN: | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --mattr=-sme2 --no-print-imm-hex - \
// RUN: | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST


st1w {z0.s, z8.s}, pn8, [x0, x0, lsl #2] // 10100001-00100000-01000000-00000000
// CHECK-INST: st1w { z0.s, z8.s }, pn8, [x0, x0, lsl #2]
// CHECK-ENCODING: [0x00,0x40,0x20,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a1204000 <unknown>

st1w {z21.s, z29.s}, pn13, [x10, x21, lsl #2] // 10100001-00110101-01010101-01010101
// CHECK-INST: st1w { z21.s, z29.s }, pn13, [x10, x21, lsl #2]
// CHECK-ENCODING: [0x55,0x55,0x35,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a1355555 <unknown>

st1w {z23.s, z31.s}, pn11, [x13, x8, lsl #2] // 10100001-00101000-01001101-10110111
// CHECK-INST: st1w { z23.s, z31.s }, pn11, [x13, x8, lsl #2]
// CHECK-ENCODING: [0xb7,0x4d,0x28,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a1284db7 <unknown>

st1w {z23.s, z31.s}, pn15, [sp, xzr, lsl #2] // 10100001-00111111-01011111-11110111
// CHECK-INST: st1w { z23.s, z31.s }, pn15, [sp, xzr, lsl #2]
// CHECK-ENCODING: [0xf7,0x5f,0x3f,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a13f5ff7 <unknown>


st1w {z0.s, z8.s}, pn8, [x0] // 10100001-01100000-01000000-00000000
// CHECK-INST: st1w { z0.s, z8.s }, pn8, [x0]
// CHECK-ENCODING: [0x00,0x40,0x60,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a1604000 <unknown>

st1w {z21.s, z29.s}, pn13, [x10, #10, mul vl] // 10100001-01100101-01010101-01010101
// CHECK-INST: st1w { z21.s, z29.s }, pn13, [x10, #10, mul vl]
// CHECK-ENCODING: [0x55,0x55,0x65,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a1655555 <unknown>

st1w {z23.s, z31.s}, pn11, [x13, #-16, mul vl] // 10100001-01101000-01001101-10110111
// CHECK-INST: st1w { z23.s, z31.s }, pn11, [x13, #-16, mul vl]
// CHECK-ENCODING: [0xb7,0x4d,0x68,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a1684db7 <unknown>

st1w {z23.s, z31.s}, pn15, [sp, #-2, mul vl] // 10100001-01101111-01011111-11110111
// CHECK-INST: st1w { z23.s, z31.s }, pn15, [sp, #-2, mul vl]
// CHECK-ENCODING: [0xf7,0x5f,0x6f,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a16f5ff7 <unknown>


st1w {z0.s, z4.s, z8.s, z12.s}, pn8, [x0, x0, lsl #2] // 10100001-00100000-11000000-00000000
// CHECK-INST: st1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0, x0, lsl #2]
// CHECK-ENCODING: [0x00,0xc0,0x20,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a120c000 <unknown>

st1w {z17.s, z21.s, z25.s, z29.s}, pn13, [x10, x21, lsl #2] // 10100001-00110101-11010101-01010001
// CHECK-INST: st1w { z17.s, z21.s, z25.s, z29.s }, pn13, [x10, x21, lsl #2]
// CHECK-ENCODING: [0x51,0xd5,0x35,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a135d551 <unknown>

st1w {z19.s, z23.s, z27.s, z31.s}, pn11, [x13, x8, lsl #2] // 10100001-00101000-11001101-10110011
// CHECK-INST: st1w { z19.s, z23.s, z27.s, z31.s }, pn11, [x13, x8, lsl #2]
// CHECK-ENCODING: [0xb3,0xcd,0x28,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a128cdb3 <unknown>

st1w {z19.s, z23.s, z27.s, z31.s}, pn15, [sp, xzr, lsl #2] // 10100001-00111111-11011111-11110011
// CHECK-INST: st1w { z19.s, z23.s, z27.s, z31.s }, pn15, [sp, xzr, lsl #2]
// CHECK-ENCODING: [0xf3,0xdf,0x3f,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a13fdff3 <unknown>


st1w {z0.s, z4.s, z8.s, z12.s}, pn8, [x0] // 10100001-01100000-11000000-00000000
// CHECK-INST: st1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0]
// CHECK-ENCODING: [0x00,0xc0,0x60,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a160c000 <unknown>

st1w {z17.s, z21.s, z25.s, z29.s}, pn13, [x10, #20, mul vl] // 10100001-01100101-11010101-01010001
// CHECK-INST: st1w { z17.s, z21.s, z25.s, z29.s }, pn13, [x10, #20, mul vl]
// CHECK-ENCODING: [0x51,0xd5,0x65,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a165d551 <unknown>

st1w {z19.s, z23.s, z27.s, z31.s}, pn11, [x13, #-32, mul vl] // 10100001-01101000-11001101-10110011
// CHECK-INST: st1w { z19.s, z23.s, z27.s, z31.s }, pn11, [x13, #-32, mul vl]
// CHECK-ENCODING: [0xb3,0xcd,0x68,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a168cdb3 <unknown>

st1w {z19.s, z23.s, z27.s, z31.s}, pn15, [sp, #-4, mul vl] // 10100001-01101111-11011111-11110011
// CHECK-INST: st1w { z19.s, z23.s, z27.s, z31.s }, pn15, [sp, #-4, mul vl]
// CHECK-ENCODING: [0xf3,0xdf,0x6f,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a16fdff3 <unknown>

113 changes: 113 additions & 0 deletions llvm/test/MC/AArch64/SME2/stnt1b.s
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --mattr=-sme2 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST


stnt1b {z0.b, z8.b}, pn8, [x0, x0] // 10100001-00100000-00000000-00001000
// CHECK-INST: stnt1b { z0.b, z8.b }, pn8, [x0, x0]
// CHECK-ENCODING: [0x08,0x00,0x20,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a1200008 <unknown>

stnt1b {z21.b, z29.b}, pn13, [x10, x21] // 10100001-00110101-00010101-01011101
// CHECK-INST: stnt1b { z21.b, z29.b }, pn13, [x10, x21]
// CHECK-ENCODING: [0x5d,0x15,0x35,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a135155d <unknown>

stnt1b {z23.b, z31.b}, pn11, [x13, x8] // 10100001-00101000-00001101-10111111
// CHECK-INST: stnt1b { z23.b, z31.b }, pn11, [x13, x8]
// CHECK-ENCODING: [0xbf,0x0d,0x28,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a1280dbf <unknown>

stnt1b {z23.b, z31.b}, pn15, [sp, xzr] // 10100001-00111111-00011111-11111111
// CHECK-INST: stnt1b { z23.b, z31.b }, pn15, [sp, xzr]
// CHECK-ENCODING: [0xff,0x1f,0x3f,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a13f1fff <unknown>


stnt1b {z0.b, z8.b}, pn8, [x0] // 10100001-01100000-00000000-00001000
// CHECK-INST: stnt1b { z0.b, z8.b }, pn8, [x0]
// CHECK-ENCODING: [0x08,0x00,0x60,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a1600008 <unknown>

stnt1b {z21.b, z29.b}, pn13, [x10, #10, mul vl] // 10100001-01100101-00010101-01011101
// CHECK-INST: stnt1b { z21.b, z29.b }, pn13, [x10, #10, mul vl]
// CHECK-ENCODING: [0x5d,0x15,0x65,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a165155d <unknown>

stnt1b {z23.b, z31.b}, pn11, [x13, #-16, mul vl] // 10100001-01101000-00001101-10111111
// CHECK-INST: stnt1b { z23.b, z31.b }, pn11, [x13, #-16, mul vl]
// CHECK-ENCODING: [0xbf,0x0d,0x68,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a1680dbf <unknown>

stnt1b {z23.b, z31.b}, pn15, [sp, #-2, mul vl] // 10100001-01101111-00011111-11111111
// CHECK-INST: stnt1b { z23.b, z31.b }, pn15, [sp, #-2, mul vl]
// CHECK-ENCODING: [0xff,0x1f,0x6f,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a16f1fff <unknown>


stnt1b {z0.b, z4.b, z8.b, z12.b}, pn8, [x0, x0] // 10100001-00100000-10000000-00001000
// CHECK-INST: stnt1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0, x0]
// CHECK-ENCODING: [0x08,0x80,0x20,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a1208008 <unknown>

stnt1b {z17.b, z21.b, z25.b, z29.b}, pn13, [x10, x21] // 10100001-00110101-10010101-01011001
// CHECK-INST: stnt1b { z17.b, z21.b, z25.b, z29.b }, pn13, [x10, x21]
// CHECK-ENCODING: [0x59,0x95,0x35,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a1359559 <unknown>

stnt1b {z19.b, z23.b, z27.b, z31.b}, pn11, [x13, x8] // 10100001-00101000-10001101-10111011
// CHECK-INST: stnt1b { z19.b, z23.b, z27.b, z31.b }, pn11, [x13, x8]
// CHECK-ENCODING: [0xbb,0x8d,0x28,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a1288dbb <unknown>

stnt1b {z19.b, z23.b, z27.b, z31.b}, pn15, [sp, xzr] // 10100001-00111111-10011111-11111011
// CHECK-INST: stnt1b { z19.b, z23.b, z27.b, z31.b }, pn15, [sp, xzr]
// CHECK-ENCODING: [0xfb,0x9f,0x3f,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a13f9ffb <unknown>


stnt1b {z0.b, z4.b, z8.b, z12.b}, pn8, [x0] // 10100001-01100000-10000000-00001000
// CHECK-INST: stnt1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0]
// CHECK-ENCODING: [0x08,0x80,0x60,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a1608008 <unknown>

stnt1b {z17.b, z21.b, z25.b, z29.b}, pn13, [x10, #20, mul vl] // 10100001-01100101-10010101-01011001
// CHECK-INST: stnt1b { z17.b, z21.b, z25.b, z29.b }, pn13, [x10, #20, mul vl]
// CHECK-ENCODING: [0x59,0x95,0x65,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a1659559 <unknown>

stnt1b {z19.b, z23.b, z27.b, z31.b}, pn11, [x13, #-32, mul vl] // 10100001-01101000-10001101-10111011
// CHECK-INST: stnt1b { z19.b, z23.b, z27.b, z31.b }, pn11, [x13, #-32, mul vl]
// CHECK-ENCODING: [0xbb,0x8d,0x68,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a1688dbb <unknown>

stnt1b {z19.b, z23.b, z27.b, z31.b}, pn15, [sp, #-4, mul vl] // 10100001-01101111-10011111-11111011
// CHECK-INST: stnt1b { z19.b, z23.b, z27.b, z31.b }, pn15, [sp, #-4, mul vl]
// CHECK-ENCODING: [0xfb,0x9f,0x6f,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a16f9ffb <unknown>

115 changes: 115 additions & 0 deletions llvm/test/MC/AArch64/SME2/stnt1d.s
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2 --no-print-imm-hex - \
// RUN: | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --mattr=-sme2 --no-print-imm-hex - \
// RUN: | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST


stnt1d {z0.d, z8.d}, pn8, [x0, x0, lsl #3] // 10100001-00100000-01100000-00001000
// CHECK-INST: stnt1d { z0.d, z8.d }, pn8, [x0, x0, lsl #3]
// CHECK-ENCODING: [0x08,0x60,0x20,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a1206008 <unknown>

stnt1d {z21.d, z29.d}, pn13, [x10, x21, lsl #3] // 10100001-00110101-01110101-01011101
// CHECK-INST: stnt1d { z21.d, z29.d }, pn13, [x10, x21, lsl #3]
// CHECK-ENCODING: [0x5d,0x75,0x35,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a135755d <unknown>

stnt1d {z23.d, z31.d}, pn11, [x13, x8, lsl #3] // 10100001-00101000-01101101-10111111
// CHECK-INST: stnt1d { z23.d, z31.d }, pn11, [x13, x8, lsl #3]
// CHECK-ENCODING: [0xbf,0x6d,0x28,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a1286dbf <unknown>

stnt1d {z23.d, z31.d}, pn15, [sp, xzr, lsl #3] // 10100001-00111111-01111111-11111111
// CHECK-INST: stnt1d { z23.d, z31.d }, pn15, [sp, xzr, lsl #3]
// CHECK-ENCODING: [0xff,0x7f,0x3f,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a13f7fff <unknown>


stnt1d {z0.d, z8.d}, pn8, [x0] // 10100001-01100000-01100000-00001000
// CHECK-INST: stnt1d { z0.d, z8.d }, pn8, [x0]
// CHECK-ENCODING: [0x08,0x60,0x60,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a1606008 <unknown>

stnt1d {z21.d, z29.d}, pn13, [x10, #10, mul vl] // 10100001-01100101-01110101-01011101
// CHECK-INST: stnt1d { z21.d, z29.d }, pn13, [x10, #10, mul vl]
// CHECK-ENCODING: [0x5d,0x75,0x65,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a165755d <unknown>

stnt1d {z23.d, z31.d}, pn11, [x13, #-16, mul vl] // 10100001-01101000-01101101-10111111
// CHECK-INST: stnt1d { z23.d, z31.d }, pn11, [x13, #-16, mul vl]
// CHECK-ENCODING: [0xbf,0x6d,0x68,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a1686dbf <unknown>

stnt1d {z23.d, z31.d}, pn15, [sp, #-2, mul vl] // 10100001-01101111-01111111-11111111
// CHECK-INST: stnt1d { z23.d, z31.d }, pn15, [sp, #-2, mul vl]
// CHECK-ENCODING: [0xff,0x7f,0x6f,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a16f7fff <unknown>


stnt1d {z0.d, z4.d, z8.d, z12.d}, pn8, [x0, x0, lsl #3] // 10100001-00100000-11100000-00001000
// CHECK-INST: stnt1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0, x0, lsl #3]
// CHECK-ENCODING: [0x08,0xe0,0x20,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a120e008 <unknown>

stnt1d {z17.d, z21.d, z25.d, z29.d}, pn13, [x10, x21, lsl #3] // 10100001-00110101-11110101-01011001
// CHECK-INST: stnt1d { z17.d, z21.d, z25.d, z29.d }, pn13, [x10, x21, lsl #3]
// CHECK-ENCODING: [0x59,0xf5,0x35,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a135f559 <unknown>

stnt1d {z19.d, z23.d, z27.d, z31.d}, pn11, [x13, x8, lsl #3] // 10100001-00101000-11101101-10111011
// CHECK-INST: stnt1d { z19.d, z23.d, z27.d, z31.d }, pn11, [x13, x8, lsl #3]
// CHECK-ENCODING: [0xbb,0xed,0x28,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a128edbb <unknown>

stnt1d {z19.d, z23.d, z27.d, z31.d}, pn15, [sp, xzr, lsl #3] // 10100001-00111111-11111111-11111011
// CHECK-INST: stnt1d { z19.d, z23.d, z27.d, z31.d }, pn15, [sp, xzr, lsl #3]
// CHECK-ENCODING: [0xfb,0xff,0x3f,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a13ffffb <unknown>


stnt1d {z0.d, z4.d, z8.d, z12.d}, pn8, [x0] // 10100001-01100000-11100000-00001000
// CHECK-INST: stnt1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0]
// CHECK-ENCODING: [0x08,0xe0,0x60,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a160e008 <unknown>

stnt1d {z17.d, z21.d, z25.d, z29.d}, pn13, [x10, #20, mul vl] // 10100001-01100101-11110101-01011001
// CHECK-INST: stnt1d { z17.d, z21.d, z25.d, z29.d }, pn13, [x10, #20, mul vl]
// CHECK-ENCODING: [0x59,0xf5,0x65,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a165f559 <unknown>

stnt1d {z19.d, z23.d, z27.d, z31.d}, pn11, [x13, #-32, mul vl] // 10100001-01101000-11101101-10111011
// CHECK-INST: stnt1d { z19.d, z23.d, z27.d, z31.d }, pn11, [x13, #-32, mul vl]
// CHECK-ENCODING: [0xbb,0xed,0x68,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a168edbb <unknown>

stnt1d {z19.d, z23.d, z27.d, z31.d}, pn15, [sp, #-4, mul vl] // 10100001-01101111-11111111-11111011
// CHECK-INST: stnt1d { z19.d, z23.d, z27.d, z31.d }, pn15, [sp, #-4, mul vl]
// CHECK-ENCODING: [0xfb,0xff,0x6f,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a16ffffb <unknown>

113 changes: 113 additions & 0 deletions llvm/test/MC/AArch64/SME2/stnt1h.s
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --mattr=-sme2 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST


stnt1h {z0.h, z8.h}, pn8, [x0, x0, lsl #1] // 10100001-00100000-00100000-00001000
// CHECK-INST: stnt1h { z0.h, z8.h }, pn8, [x0, x0, lsl #1]
// CHECK-ENCODING: [0x08,0x20,0x20,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a1202008 <unknown>

stnt1h {z21.h, z29.h}, pn13, [x10, x21, lsl #1] // 10100001-00110101-00110101-01011101
// CHECK-INST: stnt1h { z21.h, z29.h }, pn13, [x10, x21, lsl #1]
// CHECK-ENCODING: [0x5d,0x35,0x35,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a135355d <unknown>

stnt1h {z23.h, z31.h}, pn11, [x13, x8, lsl #1] // 10100001-00101000-00101101-10111111
// CHECK-INST: stnt1h { z23.h, z31.h }, pn11, [x13, x8, lsl #1]
// CHECK-ENCODING: [0xbf,0x2d,0x28,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a1282dbf <unknown>

stnt1h {z23.h, z31.h}, pn15, [sp, xzr, lsl #1] // 10100001-00111111-00111111-11111111
// CHECK-INST: stnt1h { z23.h, z31.h }, pn15, [sp, xzr, lsl #1]
// CHECK-ENCODING: [0xff,0x3f,0x3f,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a13f3fff <unknown>


stnt1h {z0.h, z8.h}, pn8, [x0] // 10100001-01100000-00100000-00001000
// CHECK-INST: stnt1h { z0.h, z8.h }, pn8, [x0]
// CHECK-ENCODING: [0x08,0x20,0x60,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a1602008 <unknown>

stnt1h {z21.h, z29.h}, pn13, [x10, #10, mul vl] // 10100001-01100101-00110101-01011101
// CHECK-INST: stnt1h { z21.h, z29.h }, pn13, [x10, #10, mul vl]
// CHECK-ENCODING: [0x5d,0x35,0x65,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a165355d <unknown>

stnt1h {z23.h, z31.h}, pn11, [x13, #-16, mul vl] // 10100001-01101000-00101101-10111111
// CHECK-INST: stnt1h { z23.h, z31.h }, pn11, [x13, #-16, mul vl]
// CHECK-ENCODING: [0xbf,0x2d,0x68,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a1682dbf <unknown>

stnt1h {z23.h, z31.h}, pn15, [sp, #-2, mul vl] // 10100001-01101111-00111111-11111111
// CHECK-INST: stnt1h { z23.h, z31.h }, pn15, [sp, #-2, mul vl]
// CHECK-ENCODING: [0xff,0x3f,0x6f,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a16f3fff <unknown>


stnt1h {z0.h, z4.h, z8.h, z12.h}, pn8, [x0, x0, lsl #1] // 10100001-00100000-10100000-00001000
// CHECK-INST: stnt1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0, x0, lsl #1]
// CHECK-ENCODING: [0x08,0xa0,0x20,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a120a008 <unknown>

stnt1h {z17.h, z21.h, z25.h, z29.h}, pn13, [x10, x21, lsl #1] // 10100001-00110101-10110101-01011001
// CHECK-INST: stnt1h { z17.h, z21.h, z25.h, z29.h }, pn13, [x10, x21, lsl #1]
// CHECK-ENCODING: [0x59,0xb5,0x35,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a135b559 <unknown>

stnt1h {z19.h, z23.h, z27.h, z31.h}, pn11, [x13, x8, lsl #1] // 10100001-00101000-10101101-10111011
// CHECK-INST: stnt1h { z19.h, z23.h, z27.h, z31.h }, pn11, [x13, x8, lsl #1]
// CHECK-ENCODING: [0xbb,0xad,0x28,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a128adbb <unknown>

stnt1h {z19.h, z23.h, z27.h, z31.h}, pn15, [sp, xzr, lsl #1] // 10100001-00111111-10111111-11111011
// CHECK-INST: stnt1h { z19.h, z23.h, z27.h, z31.h }, pn15, [sp, xzr, lsl #1]
// CHECK-ENCODING: [0xfb,0xbf,0x3f,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a13fbffb <unknown>


stnt1h {z0.h, z4.h, z8.h, z12.h}, pn8, [x0] // 10100001-01100000-10100000-00001000
// CHECK-INST: stnt1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0]
// CHECK-ENCODING: [0x08,0xa0,0x60,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a160a008 <unknown>

stnt1h {z17.h, z21.h, z25.h, z29.h}, pn13, [x10, #20, mul vl] // 10100001-01100101-10110101-01011001
// CHECK-INST: stnt1h { z17.h, z21.h, z25.h, z29.h }, pn13, [x10, #20, mul vl]
// CHECK-ENCODING: [0x59,0xb5,0x65,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a165b559 <unknown>

stnt1h {z19.h, z23.h, z27.h, z31.h}, pn11, [x13, #-32, mul vl] // 10100001-01101000-10101101-10111011
// CHECK-INST: stnt1h { z19.h, z23.h, z27.h, z31.h }, pn11, [x13, #-32, mul vl]
// CHECK-ENCODING: [0xbb,0xad,0x68,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a168adbb <unknown>

stnt1h {z19.h, z23.h, z27.h, z31.h}, pn15, [sp, #-4, mul vl] // 10100001-01101111-10111111-11111011
// CHECK-INST: stnt1h { z19.h, z23.h, z27.h, z31.h }, pn15, [sp, #-4, mul vl]
// CHECK-ENCODING: [0xfb,0xbf,0x6f,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a16fbffb <unknown>

115 changes: 115 additions & 0 deletions llvm/test/MC/AArch64/SME2/stnt1w.s
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@@ -0,0 +1,115 @@
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2 --no-print-imm-hex - \
// RUN: | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --mattr=-sme2 --no-print-imm-hex - \
// RUN: | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST


stnt1w {z0.s, z8.s}, pn8, [x0, x0, lsl #2] // 10100001-00100000-01000000-00001000
// CHECK-INST: stnt1w { z0.s, z8.s }, pn8, [x0, x0, lsl #2]
// CHECK-ENCODING: [0x08,0x40,0x20,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a1204008 <unknown>

stnt1w {z21.s, z29.s}, pn13, [x10, x21, lsl #2] // 10100001-00110101-01010101-01011101
// CHECK-INST: stnt1w { z21.s, z29.s }, pn13, [x10, x21, lsl #2]
// CHECK-ENCODING: [0x5d,0x55,0x35,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a135555d <unknown>

stnt1w {z23.s, z31.s}, pn11, [x13, x8, lsl #2] // 10100001-00101000-01001101-10111111
// CHECK-INST: stnt1w { z23.s, z31.s }, pn11, [x13, x8, lsl #2]
// CHECK-ENCODING: [0xbf,0x4d,0x28,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a1284dbf <unknown>

stnt1w {z23.s, z31.s}, pn15, [sp, xzr, lsl #2] // 10100001-00111111-01011111-11111111
// CHECK-INST: stnt1w { z23.s, z31.s }, pn15, [sp, xzr, lsl #2]
// CHECK-ENCODING: [0xff,0x5f,0x3f,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a13f5fff <unknown>


stnt1w {z0.s, z8.s}, pn8, [x0] // 10100001-01100000-01000000-00001000
// CHECK-INST: stnt1w { z0.s, z8.s }, pn8, [x0]
// CHECK-ENCODING: [0x08,0x40,0x60,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a1604008 <unknown>

stnt1w {z21.s, z29.s}, pn13, [x10, #10, mul vl] // 10100001-01100101-01010101-01011101
// CHECK-INST: stnt1w { z21.s, z29.s }, pn13, [x10, #10, mul vl]
// CHECK-ENCODING: [0x5d,0x55,0x65,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a165555d <unknown>

stnt1w {z23.s, z31.s}, pn11, [x13, #-16, mul vl] // 10100001-01101000-01001101-10111111
// CHECK-INST: stnt1w { z23.s, z31.s }, pn11, [x13, #-16, mul vl]
// CHECK-ENCODING: [0xbf,0x4d,0x68,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a1684dbf <unknown>

stnt1w {z23.s, z31.s}, pn15, [sp, #-2, mul vl] // 10100001-01101111-01011111-11111111
// CHECK-INST: stnt1w { z23.s, z31.s }, pn15, [sp, #-2, mul vl]
// CHECK-ENCODING: [0xff,0x5f,0x6f,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a16f5fff <unknown>


stnt1w {z0.s, z4.s, z8.s, z12.s}, pn8, [x0, x0, lsl #2] // 10100001-00100000-11000000-00001000
// CHECK-INST: stnt1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0, x0, lsl #2]
// CHECK-ENCODING: [0x08,0xc0,0x20,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a120c008 <unknown>

stnt1w {z17.s, z21.s, z25.s, z29.s}, pn13, [x10, x21, lsl #2] // 10100001-00110101-11010101-01011001
// CHECK-INST: stnt1w { z17.s, z21.s, z25.s, z29.s }, pn13, [x10, x21, lsl #2]
// CHECK-ENCODING: [0x59,0xd5,0x35,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a135d559 <unknown>

stnt1w {z19.s, z23.s, z27.s, z31.s}, pn11, [x13, x8, lsl #2] // 10100001-00101000-11001101-10111011
// CHECK-INST: stnt1w { z19.s, z23.s, z27.s, z31.s }, pn11, [x13, x8, lsl #2]
// CHECK-ENCODING: [0xbb,0xcd,0x28,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a128cdbb <unknown>

stnt1w {z19.s, z23.s, z27.s, z31.s}, pn15, [sp, xzr, lsl #2] // 10100001-00111111-11011111-11111011
// CHECK-INST: stnt1w { z19.s, z23.s, z27.s, z31.s }, pn15, [sp, xzr, lsl #2]
// CHECK-ENCODING: [0xfb,0xdf,0x3f,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a13fdffb <unknown>


stnt1w {z0.s, z4.s, z8.s, z12.s}, pn8, [x0] // 10100001-01100000-11000000-00001000
// CHECK-INST: stnt1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0]
// CHECK-ENCODING: [0x08,0xc0,0x60,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a160c008 <unknown>

stnt1w {z17.s, z21.s, z25.s, z29.s}, pn13, [x10, #20, mul vl] // 10100001-01100101-11010101-01011001
// CHECK-INST: stnt1w { z17.s, z21.s, z25.s, z29.s }, pn13, [x10, #20, mul vl]
// CHECK-ENCODING: [0x59,0xd5,0x65,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a165d559 <unknown>

stnt1w {z19.s, z23.s, z27.s, z31.s}, pn11, [x13, #-32, mul vl] // 10100001-01101000-11001101-10111011
// CHECK-INST: stnt1w { z19.s, z23.s, z27.s, z31.s }, pn11, [x13, #-32, mul vl]
// CHECK-ENCODING: [0xbb,0xcd,0x68,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a168cdbb <unknown>

stnt1w {z19.s, z23.s, z27.s, z31.s}, pn15, [sp, #-4, mul vl] // 10100001-01101111-11011111-11111011
// CHECK-INST: stnt1w { z19.s, z23.s, z27.s, z31.s }, pn15, [sp, #-4, mul vl]
// CHECK-ENCODING: [0xfb,0xdf,0x6f,0xa1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: a16fdffb <unknown>

2 changes: 1 addition & 1 deletion llvm/test/MC/AArch64/SME2/sub-diagnostics.s
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Expand Up @@ -66,7 +66,7 @@ sub za.d[w8, 0, vgx2], {z0.d-z3.d}, z0.d
// Invalid vector list.

sub za.d[w8, 0], {z0.d,z2.d}, {z0.d,z2.d}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sub za.d[w8, 0], {z0.d,z2.d}, {z0.d,z2.d}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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2 changes: 1 addition & 1 deletion llvm/test/MC/AArch64/SVE/ld2b-diagnostics.s
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Expand Up @@ -81,7 +81,7 @@ ld2b { z0.b, z1.h }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

ld2b { z0.b, z2.b }, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ld2b { z0.b, z2.b }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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2 changes: 1 addition & 1 deletion llvm/test/MC/AArch64/SVE/ld2d-diagnostics.s
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Expand Up @@ -86,7 +86,7 @@ ld2d { z0.d, z1.b }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

ld2d { z0.d, z2.d }, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ld2d { z0.d, z2.d }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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2 changes: 1 addition & 1 deletion llvm/test/MC/AArch64/SVE/ld2h-diagnostics.s
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Expand Up @@ -86,7 +86,7 @@ ld2h { z0.h, z1.s }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

ld2h { z0.h, z2.h }, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ld2h { z0.h, z2.h }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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2 changes: 1 addition & 1 deletion llvm/test/MC/AArch64/SVE/ld2w-diagnostics.s
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Expand Up @@ -86,7 +86,7 @@ ld2w { z0.s, z1.d }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

ld2w { z0.s, z2.s }, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ld2w { z0.s, z2.s }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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2 changes: 1 addition & 1 deletion llvm/test/MC/AArch64/SVE/ld3b-diagnostics.s
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Expand Up @@ -81,7 +81,7 @@ ld3b { z0.b, z1.b, z2.h }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

ld3b { z0.b, z1.b, z3.b }, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride
// CHECK-NEXT: ld3b { z0.b, z1.b, z3.b }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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2 changes: 1 addition & 1 deletion llvm/test/MC/AArch64/SVE/ld3d-diagnostics.s
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Expand Up @@ -86,7 +86,7 @@ ld3d { z0.d, z1.d, z2.b }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

ld3d { z0.d, z1.d, z3.d }, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride
// CHECK-NEXT: ld3d { z0.d, z1.d, z3.d }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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2 changes: 1 addition & 1 deletion llvm/test/MC/AArch64/SVE/ld3h-diagnostics.s
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Expand Up @@ -86,7 +86,7 @@ ld3h { z0.h, z1.h, z2.s }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

ld3h { z0.h, z1.h, z3.h }, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride
// CHECK-NEXT: ld3h { z0.h, z1.h, z3.h }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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2 changes: 1 addition & 1 deletion llvm/test/MC/AArch64/SVE/ld3w-diagnostics.s
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Expand Up @@ -86,7 +86,7 @@ ld3w { z0.s, z1.s, z2.d }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

ld3w { z0.s, z1.s, z3.s }, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride
// CHECK-NEXT: ld3w { z0.s, z1.s, z3.s }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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2 changes: 1 addition & 1 deletion llvm/test/MC/AArch64/SVE/ld4b-diagnostics.s
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Original file line number Diff line number Diff line change
Expand Up @@ -81,7 +81,7 @@ ld4b { z0.b, z1.b, z2.b, z3.h }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

ld4b { z0.b, z1.b, z3.b, z5.b }, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride
// CHECK-NEXT: ld4b { z0.b, z1.b, z3.b, z5.b }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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2 changes: 1 addition & 1 deletion llvm/test/MC/AArch64/SVE/ld4d-diagnostics.s
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Original file line number Diff line number Diff line change
Expand Up @@ -86,7 +86,7 @@ ld4d { z0.d, z1.d, z2.d, z3.b }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

ld4d { z0.d, z1.d, z3.d, z5.d }, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride
// CHECK-NEXT: ld4d { z0.d, z1.d, z3.d, z5.d }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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2 changes: 1 addition & 1 deletion llvm/test/MC/AArch64/SVE/ld4h-diagnostics.s
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Expand Up @@ -86,7 +86,7 @@ ld4h { z0.h, z1.h, z2.h, z3.s }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

ld4h { z0.h, z1.h, z3.h, z5.h }, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride
// CHECK-NEXT: ld4h { z0.h, z1.h, z3.h, z5.h }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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2 changes: 1 addition & 1 deletion llvm/test/MC/AArch64/SVE/ld4w-diagnostics.s
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Original file line number Diff line number Diff line change
Expand Up @@ -86,7 +86,7 @@ ld4w { z0.s, z1.s, z2.s, z3.d }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

ld4w { z0.s, z1.s, z3.s, z5.s }, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride
// CHECK-NEXT: ld4w { z0.s, z1.s, z3.s, z5.s }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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2 changes: 1 addition & 1 deletion llvm/test/MC/AArch64/SVE/st2b-diagnostics.s
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Original file line number Diff line number Diff line change
Expand Up @@ -91,7 +91,7 @@ st2b { z0.b, z1.h }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

st2b { z0.b, z2.b }, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: st2b { z0.b, z2.b }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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2 changes: 1 addition & 1 deletion llvm/test/MC/AArch64/SVE/st2d-diagnostics.s
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Original file line number Diff line number Diff line change
Expand Up @@ -96,7 +96,7 @@ st2d { z0.d, z1.b }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

st2d { z0.d, z2.d }, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: st2d { z0.d, z2.d }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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2 changes: 1 addition & 1 deletion llvm/test/MC/AArch64/SVE/st2h-diagnostics.s
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Original file line number Diff line number Diff line change
Expand Up @@ -96,7 +96,7 @@ st2h { z0.h, z1.s }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

st2h { z0.h, z2.h }, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: st2h { z0.h, z2.h }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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2 changes: 1 addition & 1 deletion llvm/test/MC/AArch64/SVE/st2w-diagnostics.s
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Original file line number Diff line number Diff line change
Expand Up @@ -96,7 +96,7 @@ st2w { z0.s, z1.d }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

st2w { z0.s, z2.s }, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: st2w { z0.s, z2.s }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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2 changes: 1 addition & 1 deletion llvm/test/MC/AArch64/SVE/st3b-diagnostics.s
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Original file line number Diff line number Diff line change
Expand Up @@ -91,7 +91,7 @@ st3b { z0.b, z1.b, z2.h }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

st3b { z0.b, z1.b, z3.b }, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride
// CHECK-NEXT: st3b { z0.b, z1.b, z3.b }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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2 changes: 1 addition & 1 deletion llvm/test/MC/AArch64/SVE/st3d-diagnostics.s
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Expand Up @@ -96,7 +96,7 @@ st3d { z0.d, z1.d, z2.b }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

st3d { z0.d, z1.d, z3.d }, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride
// CHECK-NEXT: st3d { z0.d, z1.d, z3.d }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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2 changes: 1 addition & 1 deletion llvm/test/MC/AArch64/SVE/st3h-diagnostics.s
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Expand Up @@ -96,7 +96,7 @@ st3h { z0.h, z1.h, z2.s }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

st3h { z0.h, z1.h, z3.h }, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride
// CHECK-NEXT: st3h { z0.h, z1.h, z3.h }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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2 changes: 1 addition & 1 deletion llvm/test/MC/AArch64/SVE/st3w-diagnostics.s
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Original file line number Diff line number Diff line change
Expand Up @@ -96,7 +96,7 @@ st3w { z0.s, z1.s, z2.d }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

st3w { z0.s, z1.s, z3.s }, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride
// CHECK-NEXT: st3w { z0.s, z1.s, z3.s }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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2 changes: 1 addition & 1 deletion llvm/test/MC/AArch64/SVE/st4b-diagnostics.s
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Original file line number Diff line number Diff line change
Expand Up @@ -91,7 +91,7 @@ st4b { z0.b, z1.b, z2.b, z3.h }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

st4b { z0.b, z1.b, z3.b, z5.b }, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride
// CHECK-NEXT: st4b { z0.b, z1.b, z3.b, z5.b }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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2 changes: 1 addition & 1 deletion llvm/test/MC/AArch64/SVE/st4d-diagnostics.s
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Original file line number Diff line number Diff line change
Expand Up @@ -96,7 +96,7 @@ st4d { z0.d, z1.d, z2.d, z3.b }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

st4d { z0.d, z1.d, z3.d, z5.d }, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride
// CHECK-NEXT: st4d { z0.d, z1.d, z3.d, z5.d }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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2 changes: 1 addition & 1 deletion llvm/test/MC/AArch64/SVE/st4h-diagnostics.s
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Original file line number Diff line number Diff line change
Expand Up @@ -96,7 +96,7 @@ st4h { z0.h, z1.h, z2.h, z3.s }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

st4h { z0.h, z1.h, z3.h, z5.h }, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride
// CHECK-NEXT: st4h { z0.h, z1.h, z3.h, z5.h }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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2 changes: 1 addition & 1 deletion llvm/test/MC/AArch64/SVE/st4w-diagnostics.s
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Original file line number Diff line number Diff line change
Expand Up @@ -96,7 +96,7 @@ st4w { z0.s, z1.s, z2.s, z3.d }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

st4w { z0.s, z1.s, z3.s, z5.s }, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride
// CHECK-NEXT: st4w { z0.s, z1.s, z3.s, z5.s }, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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2 changes: 1 addition & 1 deletion llvm/test/MC/AArch64/SVE2/ext-diagnostics.s
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Original file line number Diff line number Diff line change
Expand Up @@ -58,7 +58,7 @@ ext z0.b, { z1.b, z2.h }, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

ext z0.b, { z1.b, z31.b }, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ext z0.b, { z1.b, z31.b }, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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2 changes: 1 addition & 1 deletion llvm/test/MC/AArch64/SVE2/splice-diagnostics.s
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Original file line number Diff line number Diff line change
Expand Up @@ -34,7 +34,7 @@ splice z0.b, p0, { z1.b, z2.h }
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

splice z0.b, p0, { z1.b, z31.b }
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: splice z0.b, p0, { z1.b, z31.b }
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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2 changes: 1 addition & 1 deletion llvm/test/MC/AArch64/SVE2/tbl-diagnostics.s
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Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,7 @@ tbl z0.d, { z1.d, z2.b }, z3.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

tbl z0.d, { z1.d, z21.d }, z3.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: tbl z0.d, { z1.d, z21.d }, z3.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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4 changes: 2 additions & 2 deletions llvm/test/MC/AArch64/SVE2p1/pext-diagnostics.s
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Original file line number Diff line number Diff line change
Expand Up @@ -4,12 +4,12 @@
// Invalid vector lists

pext {p0.h, p2.h}, pn8[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: pext {p0.h, p2.h}, pn8[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

pext {p15.h, p1.h}, pn8[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: pext {p15.h, p1.h}, pn8[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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2 changes: 1 addition & 1 deletion llvm/test/MC/AArch64/SVE2p1/whilege-diagnostics.s
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Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@ whilege pn7.b, x0, x0, vlx2
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

whilege { p0.b, p2.b }, x13, x8
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilege { p0.b, p2.b }, x13, x8
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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2 changes: 1 addition & 1 deletion llvm/test/MC/AArch64/SVE2p1/whilegt-diagnostics.s
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Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@ whilegt pn7.b, x0, x0, vlx2
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

whilegt { p0.b, p2.b }, x13, x8
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilegt { p0.b, p2.b }, x13, x8
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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2 changes: 1 addition & 1 deletion llvm/test/MC/AArch64/SVE2p1/whilehi-diagnostics.s
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Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@ whilehi pn7.b, x0, x0, vlx2
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

whilehi { p0.b, p2.b }, x13, x8
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilehi { p0.b, p2.b }, x13, x8
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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2 changes: 1 addition & 1 deletion llvm/test/MC/AArch64/SVE2p1/whilehs-diagnostics.s
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Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@ whilehs pn7.b, x0, x0, vlx2
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

whilehs { p0.b, p2.b }, x13, x8
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilehs { p0.b, p2.b }, x13, x8
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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2 changes: 1 addition & 1 deletion llvm/test/MC/AArch64/SVE2p1/whilele-diagnostics.s
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Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@ whilele pn7.b, x0, x0, vlx2
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

whilele { p0.b, p2.b }, x13, x8
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilele { p0.b, p2.b }, x13, x8
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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2 changes: 1 addition & 1 deletion llvm/test/MC/AArch64/SVE2p1/whilelo-diagnostics.s
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Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@ whilelo pn7.b, x0, x0, vlx2
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

whilelo { p0.b, p2.b }, x13, x8
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilelo { p0.b, p2.b }, x13, x8
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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2 changes: 1 addition & 1 deletion llvm/test/MC/AArch64/SVE2p1/whilels-diagnostics.s
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Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@ whilels pn7.b, x0, x0, vlx2
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

whilels { p0.b, p2.b }, x13, x8
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilels { p0.b, p2.b }, x13, x8
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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2 changes: 1 addition & 1 deletion llvm/test/MC/AArch64/SVE2p1/whilelt-diagnostics.s
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Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@ whilelt pn7.b, x0, x0, vlx2
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

whilelt { p0.b, p2.b }, x13, x8
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilelt { p0.b, p2.b }, x13, x8
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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16 changes: 8 additions & 8 deletions llvm/test/MC/AArch64/neon-diagnostics.s
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Original file line number Diff line number Diff line change
Expand Up @@ -3877,7 +3877,7 @@
ld1 {v1.8h-v1.8h}, [x0]
ld1 {v15.8h-v17.4h}, [x15]
ld1 {v0.8b-v2.8b, [x0]
// CHECK-ERROR: error: registers must be sequential
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: ld1 {v0.16b, v2.16b}, [x0]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid number of vectors
Expand Down Expand Up @@ -3907,7 +3907,7 @@
// CHECK-ERROR: error: mismatched register size suffix
// CHECK-ERROR: ld2 {v15.8h, v16.4h}, [x15]
// CHECK-ERROR: ^
// CHECK-ERROR: error: registers must be sequential
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: ld2 {v0.8b, v2.8b}, [x0]
// CHECK-ERROR: ^
// CHECK-ERROR: ld2 {v15.4h, v16.4h, v17.4h}, [x32]
Expand All @@ -3930,7 +3930,7 @@
// CHECK-ERROR: error: mismatched register size suffix
// CHECK-ERROR: ld3 {v0.8b, v1,8b, v2.8b, v3.8b}, [x0]
// CHECK-ERROR: ^
// CHECK-ERROR: error: registers must be sequential
// CHECK-ERROR: error: registers must have the same sequential stride
// CHECK-ERROR: ld3 {v0.8b, v2.8b, v3.8b}, [x0]
// CHECK-ERROR: ^
// CHECK-ERROR: error: mismatched register size suffix
Expand All @@ -3948,7 +3948,7 @@
// CHECK-ERROR: error: mismatched register size suffix
// CHECK-ERROR: ld4 {v15.8h, v16.8h, v17.4h, v18.8h}, [x15]
// CHECK-ERROR: ^
// CHECK-ERROR: error: registers must be sequential
// CHECK-ERROR: error: registers must have the same sequential stride
// CHECK-ERROR: ld4 {v0.8b, v2.8b, v3.8b, v4.8b}, [x0]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid number of vectors
Expand Down Expand Up @@ -3985,7 +3985,7 @@
st1 {v1.8h-v1.8h}, [x0]
st1 {v15.8h-v17.4h}, [x15]
st1 {v0.8b-v2.8b, [x0]
// CHECK-ERROR: error: registers must be sequential
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: st1 {v0.16b, v2.16b}, [x0]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid number of vectors
Expand Down Expand Up @@ -4015,7 +4015,7 @@
// CHECK-ERROR: error: mismatched register size suffix
// CHECK-ERROR: st2 {v15.8h, v16.4h}, [x15]
// CHECK-ERROR: ^
// CHECK-ERROR: error: registers must be sequential
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: st2 {v0.8b, v2.8b}, [x0]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
Expand All @@ -4039,7 +4039,7 @@
// CHECK-ERROR: error: mismatched register size suffix
// CHECK-ERROR: st3 {v0.8b, v1,8b, v2.8b, v3.8b}, [x0]
// CHECK-ERROR: ^
// CHECK-ERROR: error: registers must be sequential
// CHECK-ERROR: error: registers must have the same sequential stride
// CHECK-ERROR: st3 {v0.8b, v2.8b, v3.8b}, [x0]
// CHECK-ERROR: ^
// CHECK-ERROR: error: mismatched register size suffix
Expand All @@ -4057,7 +4057,7 @@
// CHECK-ERROR: error: mismatched register size suffix
// CHECK-ERROR: st4 {v15.8h, v16.8h, v17.4h, v18.8h}, [x15]
// CHECK-ERROR: ^
// CHECK-ERROR: error: registers must be sequential
// CHECK-ERROR: error: registers must have the same sequential stride
// CHECK-ERROR: st4 {v0.8b, v2.8b, v3.8b, v4.8b}, [x0]
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid number of vectors
Expand Down