166 changes: 83 additions & 83 deletions llvm/test/CodeGen/NVPTX/st-param-imm.ll
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/NVPTX/store-undef.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -38,7 +38,7 @@ define void @test_store_param_def(i64 %param0, i32 %param1) {
; CHECK-NEXT: ld.param.u32 %r1, [test_store_param_def_param_1];
; CHECK-NEXT: { // callseq 1, 0
; CHECK-NEXT: .param .align 16 .b8 param0[32];
; CHECK-NEXT: st.param.b64 [param0+0], %rd1;
; CHECK-NEXT: st.param.b64 [param0], %rd1;
; CHECK-NEXT: st.param.v2.b32 [param0+8], {%r2, %r1};
; CHECK-NEXT: st.param.v4.b32 [param0+16], {%r3, %r1, %r4, %r5};
; CHECK-NEXT: call.uni
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/NVPTX/tex-read-cuda.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -58,8 +58,8 @@ define void @baz(ptr %red, i32 %idx) {
; SM20: texfunc,
; SM30: texfunc,
%texcall = tail call float @texfunc(i64 %texHandle)
; SM20: ld.param.f32 %f[[TEXCALL:[0-9]+]], [[[RETVAL]]+0]
; SM30: ld.param.f32 %f[[TEXCALL:[0-9]+]], [[[RETVAL]]+0]
; SM20: ld.param.f32 %f[[TEXCALL:[0-9]+]], [[[RETVAL]]]
; SM30: ld.param.f32 %f[[TEXCALL:[0-9]+]], [[[RETVAL]]]
; SM20: add.rn.f32 %f[[RET2:[0-9]+]], %f[[RED]], %f[[TEXCALL]]
; SM30: add.rn.f32 %f[[RET2:[0-9]+]], %f[[RED]], %f[[TEXCALL]]
%ret2 = fadd float %ret, %texcall
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/NVPTX/tid-range.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ entry:
; CHECK-LABEL: test1(
; CHECK: setp.eq.s32 %p1, %r1, 1;
; CHECK: selp.u32 %[[R:.+]], 1, 0, %p1;
; CHECK: st.param.b32 [func_retval0+0], %[[R]];
; CHECK: st.param.b32 [func_retval0], %[[R]];

declare i32 @llvm.nvvm.read.ptx.sreg.tid.x()

Expand Down
42 changes: 21 additions & 21 deletions llvm/test/CodeGen/NVPTX/unaligned-param-load-store.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -29,7 +29,7 @@
; CHECK-DAG: or.b16 [[P2_1_or:%rs[0-9]+]], [[P2_1_shl]], [[P2_0]];
; CHECK: { // callseq
; CHECK: .param .align 8 .b8 param0[16];
; CHECK-DAG: st.param.b16 [param0+0], [[P0]];
; CHECK-DAG: st.param.b16 [param0], [[P0]];
; CHECK-DAG: st.param.b8 [param0+3], [[P2_1_or]];
; CHECK-DAG: st.param.b8 [param0+4], [[P2_1]];
; CHECK: .param .align 8 .b8 retval0[16];
Expand All @@ -38,11 +38,11 @@
; CHECK-NEXT: (
; CHECK-NEXT: param0
; CHECK-NEXT: );
; CHECK-DAG: ld.param.b16 [[R0:%rs[0-9]+]], [retval0+0];
; CHECK-DAG: ld.param.b16 [[R0:%rs[0-9]+]], [retval0];
; CHECK-DAG: ld.param.b8 [[R2_0:%rs[0-9]+]], [retval0+3];
; CHECK-DAG: ld.param.b8 [[R2_1:%rs[0-9]+]], [retval0+4];
; CHECK: } // callseq
; CHECK-DAG: st.param.b16 [func_retval0+0], [[R0]];
; CHECK-DAG: st.param.b16 [func_retval0], [[R0]];
; CHECK-DAG: shl.b16 [[R2_1_shl:%rs[0-9]+]], [[R2_1]], 8;
; CHECK-DAG: and.b16 [[R2_0_and:%rs[0-9]+]], [[R2_0]], 255;
; CHECK-DAG: or.b16 [[R2:%rs[0-9]+]], [[R2_0_and]], [[R2_1_shl]];
Expand Down Expand Up @@ -74,7 +74,7 @@ define %s_i8i16p @test_s_i8i16p(%s_i8i16p %a) {
; CHECK-DAG: shr.u32 [[P2_2_shr:%r[0-9]+]], [[P2_or_1]], 16;
; CHECK: { // callseq
; CHECK-DAG: .param .align 8 .b8 param0[24];
; CHECK-DAG: st.param.b32 [param0+0], [[P0]];
; CHECK-DAG: st.param.b32 [param0], [[P0]];
; CHECK-DAG: st.param.b8 [param0+5], [[P2]];
; CHECK-DAG: st.param.b8 [param0+6], [[P2_1_shr]];
; CHECK-DAG: st.param.b8 [param0+7], [[P2_2_shr]];
Expand All @@ -85,13 +85,13 @@ define %s_i8i16p @test_s_i8i16p(%s_i8i16p %a) {
; CHECK-NEXT: (
; CHECK-NEXT: param0
; CHECK-NEXT: );
; CHECK-DAG: ld.param.b32 [[R0:%r[0-9]+]], [retval0+0];
; CHECK-DAG: ld.param.b32 [[R0:%r[0-9]+]], [retval0];
; CHECK-DAG: ld.param.b8 [[R2_0:%rs[0-9]+]], [retval0+5];
; CHECK-DAG: ld.param.b8 [[R2_1:%rs[0-9]+]], [retval0+6];
; CHECK-DAG: ld.param.b8 [[R2_2:%rs[0-9]+]], [retval0+7];
; CHECK-DAG: ld.param.b8 [[R2_3:%rs[0-9]+]], [retval0+8];
; CHECK: } // callseq
; CHECK-DAG: st.param.b32 [func_retval0+0], [[R0]];
; CHECK-DAG: st.param.b32 [func_retval0], [[R0]];
; CHECK-DAG: st.param.b8 [func_retval0+5],
; CHECK-DAG: st.param.b8 [func_retval0+6],
; CHECK-DAG: st.param.b8 [func_retval0+7],
Expand Down Expand Up @@ -137,7 +137,7 @@ define %s_i8i32p @test_s_i8i32p(%s_i8i32p %a) {
; CHECK-DAG: bfe.u64 [[P2_bfe_6:%rd[0-9]+]], [[P2_or_5]], 24, 8;
; CHECK: { // callseq
; CHECK: .param .align 8 .b8 param0[32];
; CHECK-DAG: st.param.b64 [param0+0], [[P0]];
; CHECK-DAG: st.param.b64 [param0], [[P0]];
; CHECK-DAG: st.param.b8 [param0+9], [[P2]];
; CHECK-DAG: st.param.b8 [param0+10], [[P2_shr_1]];
; CHECK-DAG: st.param.b8 [param0+11], [[P2_shr_2]];
Expand All @@ -152,7 +152,7 @@ define %s_i8i32p @test_s_i8i32p(%s_i8i32p %a) {
; CHECK-NEXT: (
; CHECK-NEXT: param0
; CHECK-NEXT: );
; CHECK-DAG: ld.param.b64 [[R0:%rd[0-9]+]], [retval0+0];
; CHECK-DAG: ld.param.b64 [[R0:%rd[0-9]+]], [retval0];
; CHECK-DAG: ld.param.b8 [[R2_0:%rs[0-9]+]], [retval0+9];
; CHECK-DAG: ld.param.b8 [[R2_1:%rs[0-9]+]], [retval0+10];
; CHECK-DAG: ld.param.b8 [[R2_2:%rs[0-9]+]], [retval0+11];
Expand All @@ -162,7 +162,7 @@ define %s_i8i32p @test_s_i8i32p(%s_i8i32p %a) {
; CHECK-DAG: ld.param.b8 [[R2_6:%rs[0-9]+]], [retval0+15];
; CHECK-DAG: ld.param.b8 [[R2_7:%rs[0-9]+]], [retval0+16];
; CHECK: } // callseq
; CHECK-DAG: st.param.b64 [func_retval0+0], [[R0]];
; CHECK-DAG: st.param.b64 [func_retval0], [[R0]];
; CHECK-DAG: st.param.b8 [func_retval0+9],
; CHECK-DAG: st.param.b8 [func_retval0+10],
; CHECK-DAG: st.param.b8 [func_retval0+11],
Expand All @@ -188,7 +188,7 @@ define %s_i8i64p @test_s_i8i64p(%s_i8i64p %a) {
; CHECK-DAG: or.b16 [[P2_1_or:%rs[0-9]+]], [[P2_1_shl]], [[P2_0]];
; CHECK: { // callseq
; CHECK: .param .align 8 .b8 param0[16];
; CHECK-DAG: st.param.b16 [param0+0], [[P0]];
; CHECK-DAG: st.param.b16 [param0], [[P0]];
; CHECK-DAG: st.param.b8 [param0+3], [[P2_1_or]];
; CHECK-DAG: st.param.b8 [param0+4], [[P2_1]];
; CHECK: .param .align 8 .b8 retval0[16];
Expand All @@ -197,11 +197,11 @@ define %s_i8i64p @test_s_i8i64p(%s_i8i64p %a) {
; CHECK-NEXT: (
; CHECK-NEXT: param0
; CHECK-NEXT: );
; CHECK-DAG: ld.param.b16 [[R0:%rs[0-9]+]], [retval0+0];
; CHECK-DAG: ld.param.b16 [[R0:%rs[0-9]+]], [retval0];
; CHECK-DAG: ld.param.b8 [[R2I_0:%rs[0-9]+]], [retval0+3];
; CHECK-DAG: ld.param.b8 [[R2I_1:%rs[0-9]+]], [retval0+4];
; CHECK: } // callseq
; CHECK-DAG: st.param.b16 [func_retval0+0], [[R0]];
; CHECK-DAG: st.param.b16 [func_retval0], [[R0]];
; CHECK-DAG: shl.b16 [[R2I_1_shl:%rs[0-9]+]], [[R2I_1]], 8;
; CHECK-DAG: and.b16 [[R2I_0_and:%rs[0-9]+]], [[R2I_0]], 255;
; CHECK-DAG: or.b16 [[R2I:%rs[0-9]+]], [[R2I_0_and]], [[R2I_1_shl]];
Expand Down Expand Up @@ -233,7 +233,7 @@ define %s_i8f16p @test_s_i8f16p(%s_i8f16p %a) {
; CHECK-DAG: shr.u32 [[P2_2_shr:%r[0-9]+]], [[P2_or_1]], 16;
; CHECK: { // callseq
; CHECK-DAG: .param .align 8 .b8 param0[24];
; CHECK-DAG: st.param.b32 [param0+0], [[P0]];
; CHECK-DAG: st.param.b32 [param0], [[P0]];
; CHECK-DAG: st.param.b8 [param0+5], [[P2]];
; CHECK-DAG: st.param.b8 [param0+6], [[P2_1_shr]];
; CHECK-DAG: st.param.b8 [param0+7], [[P2_2_shr]];
Expand All @@ -244,13 +244,13 @@ define %s_i8f16p @test_s_i8f16p(%s_i8f16p %a) {
; CHECK-NEXT: (
; CHECK-NEXT: param0
; CHECK-NEXT: );
; CHECK-DAG: ld.param.b32 [[R0:%r[0-9]+]], [retval0+0];
; CHECK-DAG: ld.param.b32 [[R0:%r[0-9]+]], [retval0];
; CHECK-DAG: ld.param.b8 [[R2_0:%rs[0-9]+]], [retval0+5];
; CHECK-DAG: ld.param.b8 [[R2_1:%rs[0-9]+]], [retval0+6];
; CHECK-DAG: ld.param.b8 [[R2_2:%rs[0-9]+]], [retval0+7];
; CHECK-DAG: ld.param.b8 [[R2_3:%rs[0-9]+]], [retval0+8];
; CHECK: } // callseq
; CHECK-DAG: st.param.b32 [func_retval0+0], [[R0]];
; CHECK-DAG: st.param.b32 [func_retval0], [[R0]];
; CHECK-DAG: st.param.b8 [func_retval0+5],
; CHECK-DAG: st.param.b8 [func_retval0+6],
; CHECK-DAG: st.param.b8 [func_retval0+7],
Expand Down Expand Up @@ -280,7 +280,7 @@ define %s_i8f16x2p @test_s_i8f16x2p(%s_i8f16x2p %a) {
; CHECK-DAG: shr.u32 [[P2_2_shr:%r[0-9]+]], [[P2_or_1]], 16;
; CHECK: { // callseq
; CHECK-DAG: .param .align 8 .b8 param0[24];
; CHECK-DAG: st.param.f32 [param0+0], [[P0]];
; CHECK-DAG: st.param.f32 [param0], [[P0]];
; CHECK-DAG: st.param.b8 [param0+5], [[P2]];
; CHECK-DAG: st.param.b8 [param0+6], [[P2_1_shr]];
; CHECK-DAG: st.param.b8 [param0+7], [[P2_2_shr]];
Expand All @@ -291,13 +291,13 @@ define %s_i8f16x2p @test_s_i8f16x2p(%s_i8f16x2p %a) {
; CHECK-NEXT: (
; CHECK-NEXT: param0
; CHECK-NEXT: );
; CHECK-DAG: ld.param.f32 [[R0:%f[0-9]+]], [retval0+0];
; CHECK-DAG: ld.param.f32 [[R0:%f[0-9]+]], [retval0];
; CHECK-DAG: ld.param.b8 [[R2_0:%rs[0-9]+]], [retval0+5];
; CHECK-DAG: ld.param.b8 [[R2_1:%rs[0-9]+]], [retval0+6];
; CHECK-DAG: ld.param.b8 [[R2_2:%rs[0-9]+]], [retval0+7];
; CHECK-DAG: ld.param.b8 [[R2_3:%rs[0-9]+]], [retval0+8];
; CHECK: } // callseq
; CHECK-DAG: st.param.f32 [func_retval0+0], [[R0]];
; CHECK-DAG: st.param.f32 [func_retval0], [[R0]];
; CHECK-DAG: st.param.b8 [func_retval0+5],
; CHECK-DAG: st.param.b8 [func_retval0+6],
; CHECK-DAG: st.param.b8 [func_retval0+7],
Expand Down Expand Up @@ -343,7 +343,7 @@ define %s_i8f32p @test_s_i8f32p(%s_i8f32p %a) {
; CHECK-DAG: bfe.u64 [[P2_bfe_6:%rd[0-9]+]], [[P2_or_5]], 24, 8;
; CHECK: { // callseq
; CHECK: .param .align 8 .b8 param0[32];
; CHECK-DAG: st.param.f64 [param0+0], [[P0]];
; CHECK-DAG: st.param.f64 [param0], [[P0]];
; CHECK-DAG: st.param.b8 [param0+9], [[P2]];
; CHECK-DAG: st.param.b8 [param0+10], [[P2_shr_1]];
; CHECK-DAG: st.param.b8 [param0+11], [[P2_shr_2]];
Expand All @@ -358,7 +358,7 @@ define %s_i8f32p @test_s_i8f32p(%s_i8f32p %a) {
; CHECK-NEXT: (
; CHECK-NEXT: param0
; CHECK-NEXT: );
; CHECK-DAG: ld.param.f64 [[R0:%fd[0-9]+]], [retval0+0];
; CHECK-DAG: ld.param.f64 [[R0:%fd[0-9]+]], [retval0];
; CHECK-DAG: ld.param.b8 [[R2_0:%rs[0-9]+]], [retval0+9];
; CHECK-DAG: ld.param.b8 [[R2_1:%rs[0-9]+]], [retval0+10];
; CHECK-DAG: ld.param.b8 [[R2_2:%rs[0-9]+]], [retval0+11];
Expand All @@ -368,7 +368,7 @@ define %s_i8f32p @test_s_i8f32p(%s_i8f32p %a) {
; CHECK-DAG: ld.param.b8 [[R2_6:%rs[0-9]+]], [retval0+15];
; CHECK-DAG: ld.param.b8 [[R2_7:%rs[0-9]+]], [retval0+16];
; CHECK: } // callseq
; CHECK-DAG: st.param.f64 [func_retval0+0], [[R0]];
; CHECK-DAG: st.param.f64 [func_retval0], [[R0]];
; CHECK-DAG: st.param.b8 [func_retval0+9],
; CHECK-DAG: st.param.b8 [func_retval0+10],
; CHECK-DAG: st.param.b8 [func_retval0+11],
Expand Down
58 changes: 29 additions & 29 deletions llvm/test/CodeGen/NVPTX/unfold-masked-merge-vector-variablemask.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@ define <1 x i8> @out_v1i8(<1 x i8> %x, <1 x i8> %y, <1 x i8> %mask) nounwind {
; CHECK-NEXT: not.b16 %rs5, %rs2;
; CHECK-NEXT: and.b16 %rs6, %rs4, %rs5;
; CHECK-NEXT: or.b16 %rs7, %rs3, %rs6;
; CHECK-NEXT: st.param.b8 [func_retval0+0], %rs7;
; CHECK-NEXT: st.param.b8 [func_retval0], %rs7;
; CHECK-NEXT: ret;
%mx = and <1 x i8> %x, %mask
%notmask = xor <1 x i8> %mask, <i8 -1>
Expand All @@ -44,7 +44,7 @@ define <1 x i16> @out_v1i16(<1 x i16> %x, <1 x i16> %y, <1 x i16> %mask) nounwin
; CHECK-NEXT: not.b16 %rs5, %rs2;
; CHECK-NEXT: and.b16 %rs6, %rs4, %rs5;
; CHECK-NEXT: or.b16 %rs7, %rs3, %rs6;
; CHECK-NEXT: st.param.b16 [func_retval0+0], %rs7;
; CHECK-NEXT: st.param.b16 [func_retval0], %rs7;
; CHECK-NEXT: ret;
%mx = and <1 x i16> %x, %mask
%notmask = xor <1 x i16> %mask, <i16 -1>
Expand All @@ -70,7 +70,7 @@ define <4 x i8> @out_v4i8(<4 x i8> %x, <4 x i8> %y, <4 x i8> %mask) nounwind {
; CHECK-NEXT: xor.b32 %r7, %r1, -1;
; CHECK-NEXT: and.b32 %r8, %r3, %r7;
; CHECK-NEXT: or.b32 %r9, %r5, %r8;
; CHECK-NEXT: st.param.b32 [func_retval0+0], %r9;
; CHECK-NEXT: st.param.b32 [func_retval0], %r9;
; CHECK-NEXT: ret;
%mx = and <4 x i8> %x, %mask
%notmask = xor <4 x i8> %mask, <i8 -1, i8 -1, i8 -1, i8 -1>
Expand All @@ -92,7 +92,7 @@ define <4 x i8> @out_v4i8_undef(<4 x i8> %x, <4 x i8> %y, <4 x i8> %mask) nounwi
; CHECK-NEXT: xor.b32 %r7, %r1, -16711681;
; CHECK-NEXT: and.b32 %r8, %r3, %r7;
; CHECK-NEXT: or.b32 %r9, %r5, %r8;
; CHECK-NEXT: st.param.b32 [func_retval0+0], %r9;
; CHECK-NEXT: st.param.b32 [func_retval0], %r9;
; CHECK-NEXT: ret;
%mx = and <4 x i8> %x, %mask
%notmask = xor <4 x i8> %mask, <i8 -1, i8 -1, i8 undef, i8 -1>
Expand All @@ -114,7 +114,7 @@ define <2 x i16> @out_v2i16(<2 x i16> %x, <2 x i16> %y, <2 x i16> %mask) nounwin
; CHECK-NEXT: xor.b32 %r7, %r1, -1;
; CHECK-NEXT: and.b32 %r8, %r3, %r7;
; CHECK-NEXT: or.b32 %r9, %r5, %r8;
; CHECK-NEXT: st.param.b32 [func_retval0+0], %r9;
; CHECK-NEXT: st.param.b32 [func_retval0], %r9;
; CHECK-NEXT: ret;
%mx = and <2 x i16> %x, %mask
%notmask = xor <2 x i16> %mask, <i16 -1, i16 -1>
Expand All @@ -136,7 +136,7 @@ define <1 x i32> @out_v1i32(<1 x i32> %x, <1 x i32> %y, <1 x i32> %mask) nounwin
; CHECK-NEXT: not.b32 %r5, %r2;
; CHECK-NEXT: and.b32 %r6, %r4, %r5;
; CHECK-NEXT: or.b32 %r7, %r3, %r6;
; CHECK-NEXT: st.param.b32 [func_retval0+0], %r7;
; CHECK-NEXT: st.param.b32 [func_retval0], %r7;
; CHECK-NEXT: ret;
%mx = and <1 x i32> %x, %mask
%notmask = xor <1 x i32> %mask, <i32 -1>
Expand Down Expand Up @@ -166,7 +166,7 @@ define <8 x i8> @out_v8i8(<8 x i8> %x, <8 x i8> %y, <8 x i8> %mask) nounwind {
; CHECK-NEXT: and.b32 %r18, %r2, %r15;
; CHECK-NEXT: or.b32 %r19, %r13, %r18;
; CHECK-NEXT: or.b32 %r20, %r11, %r17;
; CHECK-NEXT: st.param.v2.b32 [func_retval0+0], {%r20, %r19};
; CHECK-NEXT: st.param.v2.b32 [func_retval0], {%r20, %r19};
; CHECK-NEXT: ret;
%mx = and <8 x i8> %x, %mask
%notmask = xor <8 x i8> %mask, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
Expand All @@ -192,7 +192,7 @@ define <4 x i16> @out_v4i16(<4 x i16> %x, <4 x i16> %y, <4 x i16> %mask) nounwin
; CHECK-NEXT: and.b32 %r18, %r2, %r15;
; CHECK-NEXT: or.b32 %r19, %r13, %r18;
; CHECK-NEXT: or.b32 %r20, %r11, %r17;
; CHECK-NEXT: st.param.v2.b32 [func_retval0+0], {%r20, %r19};
; CHECK-NEXT: st.param.v2.b32 [func_retval0], {%r20, %r19};
; CHECK-NEXT: ret;
%mx = and <4 x i16> %x, %mask
%notmask = xor <4 x i16> %mask, <i16 -1, i16 -1, i16 -1, i16 -1>
Expand All @@ -218,7 +218,7 @@ define <4 x i16> @out_v4i16_undef(<4 x i16> %x, <4 x i16> %y, <4 x i16> %mask) n
; CHECK-NEXT: and.b32 %r18, %r2, %r15;
; CHECK-NEXT: or.b32 %r19, %r13, %r18;
; CHECK-NEXT: or.b32 %r20, %r11, %r17;
; CHECK-NEXT: st.param.v2.b32 [func_retval0+0], {%r20, %r19};
; CHECK-NEXT: st.param.v2.b32 [func_retval0], {%r20, %r19};
; CHECK-NEXT: ret;
%mx = and <4 x i16> %x, %mask
%notmask = xor <4 x i16> %mask, <i16 -1, i16 -1, i16 undef, i16 -1>
Expand All @@ -244,7 +244,7 @@ define <2 x i32> @out_v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %mask) nounwin
; CHECK-NEXT: and.b32 %r12, %r8, %r9;
; CHECK-NEXT: or.b32 %r13, %r6, %r12;
; CHECK-NEXT: or.b32 %r14, %r5, %r11;
; CHECK-NEXT: st.param.v2.b32 [func_retval0+0], {%r14, %r13};
; CHECK-NEXT: st.param.v2.b32 [func_retval0], {%r14, %r13};
; CHECK-NEXT: ret;
%mx = and <2 x i32> %x, %mask
%notmask = xor <2 x i32> %mask, <i32 -1, i32 -1>
Expand All @@ -266,7 +266,7 @@ define <1 x i64> @out_v1i64(<1 x i64> %x, <1 x i64> %y, <1 x i64> %mask) nounwin
; CHECK-NEXT: not.b64 %rd5, %rd2;
; CHECK-NEXT: and.b64 %rd6, %rd4, %rd5;
; CHECK-NEXT: or.b64 %rd7, %rd3, %rd6;
; CHECK-NEXT: st.param.b64 [func_retval0+0], %rd7;
; CHECK-NEXT: st.param.b64 [func_retval0], %rd7;
; CHECK-NEXT: ret;
%mx = and <1 x i64> %x, %mask
%notmask = xor <1 x i64> %mask, <i64 -1>
Expand Down Expand Up @@ -304,7 +304,7 @@ define <16 x i8> @out_v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> %mask) nounwin
; CHECK-NEXT: or.b32 %r38, %r25, %r35;
; CHECK-NEXT: or.b32 %r39, %r23, %r34;
; CHECK-NEXT: or.b32 %r40, %r21, %r33;
; CHECK-NEXT: st.param.v4.b32 [func_retval0+0], {%r40, %r39, %r38, %r37};
; CHECK-NEXT: st.param.v4.b32 [func_retval0], {%r40, %r39, %r38, %r37};
; CHECK-NEXT: ret;
%mx = and <16 x i8> %x, %mask
%notmask = xor <16 x i8> %mask, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
Expand Down Expand Up @@ -338,7 +338,7 @@ define <8 x i16> @out_v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %mask) nounwin
; CHECK-NEXT: or.b32 %r38, %r25, %r35;
; CHECK-NEXT: or.b32 %r39, %r23, %r34;
; CHECK-NEXT: or.b32 %r40, %r21, %r33;
; CHECK-NEXT: st.param.v4.b32 [func_retval0+0], {%r40, %r39, %r38, %r37};
; CHECK-NEXT: st.param.v4.b32 [func_retval0], {%r40, %r39, %r38, %r37};
; CHECK-NEXT: ret;
%mx = and <8 x i16> %x, %mask
%notmask = xor <8 x i16> %mask, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
Expand Down Expand Up @@ -372,7 +372,7 @@ define <4 x i32> @out_v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mask) nounwin
; CHECK-NEXT: or.b32 %r26, %r11, %r23;
; CHECK-NEXT: or.b32 %r27, %r10, %r22;
; CHECK-NEXT: or.b32 %r28, %r9, %r21;
; CHECK-NEXT: st.param.v4.b32 [func_retval0+0], {%r28, %r27, %r26, %r25};
; CHECK-NEXT: st.param.v4.b32 [func_retval0], {%r28, %r27, %r26, %r25};
; CHECK-NEXT: ret;
%mx = and <4 x i32> %x, %mask
%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
Expand Down Expand Up @@ -403,7 +403,7 @@ define <4 x i32> @out_v4i32_undef(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mask) n
; CHECK-NEXT: or.b32 %r23, %r12, %r22;
; CHECK-NEXT: or.b32 %r24, %r11, %r21;
; CHECK-NEXT: or.b32 %r25, %r10, %r20;
; CHECK-NEXT: st.param.v4.b32 [func_retval0+0], {%r25, %r24, %r9, %r23};
; CHECK-NEXT: st.param.v4.b32 [func_retval0], {%r25, %r24, %r9, %r23};
; CHECK-NEXT: ret;
%mx = and <4 x i32> %x, %mask
%notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 undef, i32 -1>
Expand All @@ -429,7 +429,7 @@ define <2 x i64> @out_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %mask) nounwin
; CHECK-NEXT: and.b64 %rd12, %rd8, %rd9;
; CHECK-NEXT: or.b64 %rd13, %rd6, %rd12;
; CHECK-NEXT: or.b64 %rd14, %rd5, %rd11;
; CHECK-NEXT: st.param.v2.b64 [func_retval0+0], {%rd14, %rd13};
; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd14, %rd13};
; CHECK-NEXT: ret;
%mx = and <2 x i64> %x, %mask
%notmask = xor <2 x i64> %mask, <i64 -1, i64 -1>
Expand Down Expand Up @@ -458,7 +458,7 @@ define <1 x i8> @in_v1i8(<1 x i8> %x, <1 x i8> %y, <1 x i8> %mask) nounwind {
; CHECK-NEXT: ld.param.u8 %rs4, [in_v1i8_param_2];
; CHECK-NEXT: and.b16 %rs5, %rs3, %rs4;
; CHECK-NEXT: xor.b16 %rs6, %rs5, %rs2;
; CHECK-NEXT: st.param.b8 [func_retval0+0], %rs6;
; CHECK-NEXT: st.param.b8 [func_retval0], %rs6;
; CHECK-NEXT: ret;
%n0 = xor <1 x i8> %x, %y
%n1 = and <1 x i8> %n0, %mask
Expand All @@ -482,7 +482,7 @@ define <1 x i16> @in_v1i16(<1 x i16> %x, <1 x i16> %y, <1 x i16> %mask) nounwind
; CHECK-NEXT: ld.param.u16 %rs4, [in_v1i16_param_2];
; CHECK-NEXT: and.b16 %rs5, %rs3, %rs4;
; CHECK-NEXT: xor.b16 %rs6, %rs5, %rs2;
; CHECK-NEXT: st.param.b16 [func_retval0+0], %rs6;
; CHECK-NEXT: st.param.b16 [func_retval0], %rs6;
; CHECK-NEXT: ret;
%n0 = xor <1 x i16> %x, %y
%n1 = and <1 x i16> %n0, %mask
Expand All @@ -506,7 +506,7 @@ define <4 x i8> @in_v4i8(<4 x i8> %x, <4 x i8> %y, <4 x i8> %mask) nounwind {
; CHECK-NEXT: ld.param.u32 %r4, [in_v4i8_param_2];
; CHECK-NEXT: and.b32 %r5, %r3, %r4;
; CHECK-NEXT: xor.b32 %r6, %r5, %r2;
; CHECK-NEXT: st.param.b32 [func_retval0+0], %r6;
; CHECK-NEXT: st.param.b32 [func_retval0], %r6;
; CHECK-NEXT: ret;
%n0 = xor <4 x i8> %x, %y
%n1 = and <4 x i8> %n0, %mask
Expand All @@ -526,7 +526,7 @@ define <2 x i16> @in_v2i16(<2 x i16> %x, <2 x i16> %y, <2 x i16> %mask) nounwind
; CHECK-NEXT: ld.param.u32 %r4, [in_v2i16_param_2];
; CHECK-NEXT: and.b32 %r5, %r3, %r4;
; CHECK-NEXT: xor.b32 %r6, %r5, %r2;
; CHECK-NEXT: st.param.b32 [func_retval0+0], %r6;
; CHECK-NEXT: st.param.b32 [func_retval0], %r6;
; CHECK-NEXT: ret;
%n0 = xor <2 x i16> %x, %y
%n1 = and <2 x i16> %n0, %mask
Expand All @@ -546,7 +546,7 @@ define <1 x i32> @in_v1i32(<1 x i32> %x, <1 x i32> %y, <1 x i32> %mask) nounwind
; CHECK-NEXT: ld.param.u32 %r4, [in_v1i32_param_2];
; CHECK-NEXT: and.b32 %r5, %r3, %r4;
; CHECK-NEXT: xor.b32 %r6, %r5, %r2;
; CHECK-NEXT: st.param.b32 [func_retval0+0], %r6;
; CHECK-NEXT: st.param.b32 [func_retval0], %r6;
; CHECK-NEXT: ret;
%n0 = xor <1 x i32> %x, %y
%n1 = and <1 x i32> %n0, %mask
Expand All @@ -573,7 +573,7 @@ define <8 x i8> @in_v8i8(<8 x i8> %x, <8 x i8> %y, <8 x i8> %mask) nounwind {
; CHECK-NEXT: xor.b32 %r11, %r1, %r3;
; CHECK-NEXT: and.b32 %r12, %r11, %r5;
; CHECK-NEXT: xor.b32 %r13, %r12, %r3;
; CHECK-NEXT: st.param.v2.b32 [func_retval0+0], {%r13, %r9};
; CHECK-NEXT: st.param.v2.b32 [func_retval0], {%r13, %r9};
; CHECK-NEXT: ret;
%n0 = xor <8 x i8> %x, %y
%n1 = and <8 x i8> %n0, %mask
Expand All @@ -596,7 +596,7 @@ define <4 x i16> @in_v4i16(<4 x i16> %x, <4 x i16> %y, <4 x i16> %mask) nounwind
; CHECK-NEXT: xor.b32 %r11, %r1, %r3;
; CHECK-NEXT: and.b32 %r12, %r11, %r5;
; CHECK-NEXT: xor.b32 %r13, %r12, %r3;
; CHECK-NEXT: st.param.v2.b32 [func_retval0+0], {%r13, %r9};
; CHECK-NEXT: st.param.v2.b32 [func_retval0], {%r13, %r9};
; CHECK-NEXT: ret;
%n0 = xor <4 x i16> %x, %y
%n1 = and <4 x i16> %n0, %mask
Expand All @@ -619,7 +619,7 @@ define <2 x i32> @in_v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %mask) nounwind
; CHECK-NEXT: and.b32 %r10, %r5, %r8;
; CHECK-NEXT: xor.b32 %r11, %r10, %r4;
; CHECK-NEXT: xor.b32 %r12, %r9, %r3;
; CHECK-NEXT: st.param.v2.b32 [func_retval0+0], {%r12, %r11};
; CHECK-NEXT: st.param.v2.b32 [func_retval0], {%r12, %r11};
; CHECK-NEXT: ret;
%n0 = xor <2 x i32> %x, %y
%n1 = and <2 x i32> %n0, %mask
Expand All @@ -639,7 +639,7 @@ define <1 x i64> @in_v1i64(<1 x i64> %x, <1 x i64> %y, <1 x i64> %mask) nounwind
; CHECK-NEXT: ld.param.u64 %rd4, [in_v1i64_param_2];
; CHECK-NEXT: and.b64 %rd5, %rd3, %rd4;
; CHECK-NEXT: xor.b64 %rd6, %rd5, %rd2;
; CHECK-NEXT: st.param.b64 [func_retval0+0], %rd6;
; CHECK-NEXT: st.param.b64 [func_retval0], %rd6;
; CHECK-NEXT: ret;
%n0 = xor <1 x i64> %x, %y
%n1 = and <1 x i64> %n0, %mask
Expand Down Expand Up @@ -672,7 +672,7 @@ define <16 x i8> @in_v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> %mask) nounwind
; CHECK-NEXT: xor.b32 %r23, %r19, %r7;
; CHECK-NEXT: xor.b32 %r25, %r18, %r6;
; CHECK-NEXT: xor.b32 %r27, %r17, %r5;
; CHECK-NEXT: st.param.v4.b32 [func_retval0+0], {%r27, %r25, %r23, %r21};
; CHECK-NEXT: st.param.v4.b32 [func_retval0], {%r27, %r25, %r23, %r21};
; CHECK-NEXT: ret;
%n0 = xor <16 x i8> %x, %y
%n1 = and <16 x i8> %n0, %mask
Expand Down Expand Up @@ -701,7 +701,7 @@ define <8 x i16> @in_v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %mask) nounwind
; CHECK-NEXT: xor.b32 %r23, %r19, %r7;
; CHECK-NEXT: xor.b32 %r25, %r18, %r6;
; CHECK-NEXT: xor.b32 %r27, %r17, %r5;
; CHECK-NEXT: st.param.v4.b32 [func_retval0+0], {%r27, %r25, %r23, %r21};
; CHECK-NEXT: st.param.v4.b32 [func_retval0], {%r27, %r25, %r23, %r21};
; CHECK-NEXT: ret;
%n0 = xor <8 x i16> %x, %y
%n1 = and <8 x i16> %n0, %mask
Expand Down Expand Up @@ -730,7 +730,7 @@ define <4 x i32> @in_v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mask) nounwind
; CHECK-NEXT: xor.b32 %r22, %r19, %r7;
; CHECK-NEXT: xor.b32 %r23, %r18, %r6;
; CHECK-NEXT: xor.b32 %r24, %r17, %r5;
; CHECK-NEXT: st.param.v4.b32 [func_retval0+0], {%r24, %r23, %r22, %r21};
; CHECK-NEXT: st.param.v4.b32 [func_retval0], {%r24, %r23, %r22, %r21};
; CHECK-NEXT: ret;
%n0 = xor <4 x i32> %x, %y
%n1 = and <4 x i32> %n0, %mask
Expand All @@ -753,7 +753,7 @@ define <2 x i64> @in_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %mask) nounwind
; CHECK-NEXT: and.b64 %rd10, %rd5, %rd8;
; CHECK-NEXT: xor.b64 %rd11, %rd10, %rd4;
; CHECK-NEXT: xor.b64 %rd12, %rd9, %rd3;
; CHECK-NEXT: st.param.v2.b64 [func_retval0+0], {%rd12, %rd11};
; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd12, %rd11};
; CHECK-NEXT: ret;
%n0 = xor <2 x i64> %x, %y
%n1 = and <2 x i64> %n0, %mask
Expand Down
22 changes: 11 additions & 11 deletions llvm/test/CodeGen/NVPTX/vaargs.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -17,55 +17,55 @@ entry:
; Test va_start
; CHECK: .param .align 8 .b8 foo_vararg[]
; CHECK: mov.u[[BITS]] [[VA_PTR:%(r|rd)[0-9]+]], foo_vararg;
; CHECK-NEXT: st.u[[BITS]] [%SP+0], [[VA_PTR]];
; CHECK-NEXT: st.u[[BITS]] [%SP], [[VA_PTR]];

call void @llvm.va_start(ptr %al)

; Test va_copy()
; CHECK-NEXT: ld.u[[BITS]] [[VA_PTR:%(r|rd)[0-9]+]], [%SP+0];
; CHECK-NEXT: ld.u[[BITS]] [[VA_PTR:%(r|rd)[0-9]+]], [%SP];
; CHECK-NEXT: st.u[[BITS]] [%SP+{{[0-9]+}}], [[VA_PTR]];

call void @llvm.va_copy(ptr %al2, ptr %al)

; Test va_arg(ap, int32_t)
; CHECK-NEXT: ld.u[[BITS]] [[VA_PTR:%(r|rd)[0-9]+]], [%SP+0];
; CHECK-NEXT: ld.u[[BITS]] [[VA_PTR:%(r|rd)[0-9]+]], [%SP];
; CHECK-NEXT: add.s[[BITS]] [[VA_PTR_TMP:%(r|rd)[0-9]+]], [[VA_PTR]], 3;
; CHECK-NEXT: and.b[[BITS]] [[VA_PTR_ALIGN:%(r|rd)[0-9]+]], [[VA_PTR_TMP]], -4;
; CHECK-NEXT: add.s[[BITS]] [[VA_PTR_NEXT:%(r|rd)[0-9]+]], [[VA_PTR_ALIGN]], 4;
; CHECK-NEXT: st.u[[BITS]] [%SP+0], [[VA_PTR_NEXT]];
; CHECK-NEXT: st.u[[BITS]] [%SP], [[VA_PTR_NEXT]];
; CHECK-NEXT: ld.local.u32 %r{{[0-9]+}}, [[[VA_PTR_ALIGN]]];

%0 = va_arg ptr %al, i32

; Test va_arg(ap, int64_t)
; CHECK-NEXT: ld.u[[BITS]] [[VA_PTR:%(r|rd)[0-9]+]], [%SP+0];
; CHECK-NEXT: ld.u[[BITS]] [[VA_PTR:%(r|rd)[0-9]+]], [%SP];
; CHECK-NEXT: add.s[[BITS]] [[VA_PTR_TMP:%(r|rd)[0-9]+]], [[VA_PTR]], 7;
; CHECK-NEXT: and.b[[BITS]] [[VA_PTR_ALIGN:%(r|rd)[0-9]+]], [[VA_PTR_TMP]], -8;
; CHECK-NEXT: add.s[[BITS]] [[VA_PTR_NEXT:%(r|rd)[0-9]+]], [[VA_PTR_ALIGN]], 8;
; CHECK-NEXT: st.u[[BITS]] [%SP+0], [[VA_PTR_NEXT]];
; CHECK-NEXT: st.u[[BITS]] [%SP], [[VA_PTR_NEXT]];
; CHECK-NEXT: ld.local.u64 %rd{{[0-9]+}}, [[[VA_PTR_ALIGN]]];

%1 = va_arg ptr %al, i64

; Test va_arg(ap, double)
; CHECK-NEXT: ld.u[[BITS]] [[VA_PTR:%(r|rd)[0-9]+]], [%SP+0];
; CHECK-NEXT: ld.u[[BITS]] [[VA_PTR:%(r|rd)[0-9]+]], [%SP];
; CHECK-NEXT: add.s[[BITS]] [[VA_PTR_TMP:%(r|rd)[0-9]+]], [[VA_PTR]], 7;
; CHECK-NEXT: and.b[[BITS]] [[VA_PTR_ALIGN:%(r|rd)[0-9]+]], [[VA_PTR_TMP]], -8;
; CHECK-NEXT: add.s[[BITS]] [[VA_PTR_NEXT:%(r|rd)[0-9]+]], [[VA_PTR_ALIGN]], 8;
; CHECK-NEXT: st.u[[BITS]] [%SP+0], [[VA_PTR_NEXT]];
; CHECK-NEXT: st.u[[BITS]] [%SP], [[VA_PTR_NEXT]];
; CHECK-NEXT: ld.local.f64 %fd{{[0-9]+}}, [[[VA_PTR_ALIGN]]];

%2 = va_arg ptr %al, double

; Test va_arg(ap, ptr)
; CHECK-NEXT: ld.u[[BITS]] [[VA_PTR:%(r|rd)[0-9]+]], [%SP+0];
; CHECK-NEXT: ld.u[[BITS]] [[VA_PTR:%(r|rd)[0-9]+]], [%SP];
; CHECK32-NEXT: add.s32 [[VA_PTR_TMP:%r[0-9]+]], [[VA_PTR]], 3;
; CHECK64-NEXT: add.s64 [[VA_PTR_TMP:%rd[0-9]+]], [[VA_PTR]], 7;
; CHECK32-NEXT: and.b32 [[VA_PTR_ALIGN:%r[0-9]+]], [[VA_PTR_TMP]], -4;
; CHECK64-NEXT: and.b64 [[VA_PTR_ALIGN:%rd[0-9]+]], [[VA_PTR_TMP]], -8;
; CHECK32-NEXT: add.s32 [[VA_PTR_NEXT:%r[0-9]+]], [[VA_PTR_ALIGN]], 4;
; CHECK64-NEXT: add.s64 [[VA_PTR_NEXT:%rd[0-9]+]], [[VA_PTR_ALIGN]], 8;
; CHECK-NEXT: st.u[[BITS]] [%SP+0], [[VA_PTR_NEXT]];
; CHECK-NEXT: st.u[[BITS]] [%SP], [[VA_PTR_NEXT]];
; CHECK-NEXT: ld.local.u[[BITS]] %{{(r|rd)[0-9]+}}, [[[VA_PTR_ALIGN]]];

%3 = va_arg ptr %al, ptr
Expand All @@ -91,7 +91,7 @@ define i32 @test_foo(i32 %i, i64 %l, double %d, ptr %p) {
; Store arguments to an array
; CHECK32: .param .align 8 .b8 param1[24];
; CHECK64: .param .align 8 .b8 param1[28];
; CHECK-NEXT: st.param.b32 [param1+0], [[ARG_I32]];
; CHECK-NEXT: st.param.b32 [param1], [[ARG_I32]];
; CHECK-NEXT: st.param.b64 [param1+4], [[ARG_I64]];
; CHECK-NEXT: st.param.f64 [param1+12], [[ARG_DOUBLE]];
; CHECK-NEXT: st.param.b[[BITS]] [param1+20], [[ARG_VOID_PTR]];
Expand Down
48 changes: 24 additions & 24 deletions llvm/test/CodeGen/NVPTX/variadics-backend.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -42,7 +42,7 @@ define dso_local i32 @variadics1(i32 noundef %first, ...) {
; CHECK-PTX-NEXT: cvt.rn.f64.s32 %fd5, %r9;
; CHECK-PTX-NEXT: add.rn.f64 %fd6, %fd5, %fd4;
; CHECK-PTX-NEXT: cvt.rzi.s32.f64 %r10, %fd6;
; CHECK-PTX-NEXT: st.param.b32 [func_retval0+0], %r10;
; CHECK-PTX-NEXT: st.param.b32 [func_retval0], %r10;
; CHECK-PTX-NEXT: ret;
entry:
%vlist = alloca ptr, align 8
Expand Down Expand Up @@ -112,7 +112,7 @@ define dso_local i32 @foo() {
; CHECK-PTX-NEXT: mov.u64 %SPL, __local_depot1;
; CHECK-PTX-NEXT: cvta.local.u64 %SP, %SPL;
; CHECK-PTX-NEXT: mov.u64 %rd1, 4294967297;
; CHECK-PTX-NEXT: st.u64 [%SP+0], %rd1;
; CHECK-PTX-NEXT: st.u64 [%SP], %rd1;
; CHECK-PTX-NEXT: mov.b32 %r1, 1;
; CHECK-PTX-NEXT: st.u32 [%SP+8], %r1;
; CHECK-PTX-NEXT: mov.u64 %rd2, 1;
Expand All @@ -123,19 +123,19 @@ define dso_local i32 @foo() {
; CHECK-PTX-NEXT: add.u64 %rd4, %SP, 0;
; CHECK-PTX-NEXT: { // callseq 0, 0
; CHECK-PTX-NEXT: .param .b32 param0;
; CHECK-PTX-NEXT: st.param.b32 [param0+0], 1;
; CHECK-PTX-NEXT: st.param.b32 [param0], 1;
; CHECK-PTX-NEXT: .param .b64 param1;
; CHECK-PTX-NEXT: st.param.b64 [param1+0], %rd4;
; CHECK-PTX-NEXT: st.param.b64 [param1], %rd4;
; CHECK-PTX-NEXT: .param .b32 retval0;
; CHECK-PTX-NEXT: call.uni (retval0),
; CHECK-PTX-NEXT: variadics1,
; CHECK-PTX-NEXT: (
; CHECK-PTX-NEXT: param0,
; CHECK-PTX-NEXT: param1
; CHECK-PTX-NEXT: );
; CHECK-PTX-NEXT: ld.param.b32 %r2, [retval0+0];
; CHECK-PTX-NEXT: ld.param.b32 %r2, [retval0];
; CHECK-PTX-NEXT: } // callseq 0
; CHECK-PTX-NEXT: st.param.b32 [func_retval0+0], %r2;
; CHECK-PTX-NEXT: st.param.b32 [func_retval0], %r2;
; CHECK-PTX-NEXT: ret;
entry:
%conv = sext i8 1 to i32
Expand Down Expand Up @@ -174,14 +174,14 @@ define dso_local i32 @variadics2(i32 noundef %first, ...) {
; CHECK-PTX-NEXT: ld.u8 %rs3, [%rd7];
; CHECK-PTX-NEXT: shl.b16 %rs4, %rs3, 8;
; CHECK-PTX-NEXT: or.b16 %rs5, %rs4, %rs2;
; CHECK-PTX-NEXT: st.u16 [%SP+0], %rs5;
; CHECK-PTX-NEXT: st.u16 [%SP], %rs5;
; CHECK-PTX-NEXT: ld.u64 %rd8, [%rd3+8];
; CHECK-PTX-NEXT: add.s32 %r4, %r1, %r2;
; CHECK-PTX-NEXT: add.s32 %r5, %r4, %r3;
; CHECK-PTX-NEXT: cvt.u64.u32 %rd9, %r5;
; CHECK-PTX-NEXT: add.s64 %rd10, %rd9, %rd8;
; CHECK-PTX-NEXT: cvt.u32.u64 %r6, %rd10;
; CHECK-PTX-NEXT: st.param.b32 [func_retval0+0], %r6;
; CHECK-PTX-NEXT: st.param.b32 [func_retval0], %r6;
; CHECK-PTX-NEXT: ret;
entry:
%vlist = alloca ptr, align 8
Expand Down Expand Up @@ -237,7 +237,7 @@ define dso_local i32 @bar() {
; CHECK-PTX-NEXT: cvt.u16.u8 %rs6, %rs5;
; CHECK-PTX-NEXT: shl.b16 %rs7, %rs6, 8;
; CHECK-PTX-NEXT: or.b16 %rs8, %rs7, %rs4;
; CHECK-PTX-NEXT: st.u16 [%SP+0], %rs8;
; CHECK-PTX-NEXT: st.u16 [%SP], %rs8;
; CHECK-PTX-NEXT: mov.b32 %r1, 1;
; CHECK-PTX-NEXT: st.u32 [%SP+8], %r1;
; CHECK-PTX-NEXT: add.u64 %rd5, %SP, 8;
Expand All @@ -248,19 +248,19 @@ define dso_local i32 @bar() {
; CHECK-PTX-NEXT: st.u64 [%SP+16], %rd7;
; CHECK-PTX-NEXT: { // callseq 1, 0
; CHECK-PTX-NEXT: .param .b32 param0;
; CHECK-PTX-NEXT: st.param.b32 [param0+0], 1;
; CHECK-PTX-NEXT: st.param.b32 [param0], 1;
; CHECK-PTX-NEXT: .param .b64 param1;
; CHECK-PTX-NEXT: st.param.b64 [param1+0], %rd5;
; CHECK-PTX-NEXT: st.param.b64 [param1], %rd5;
; CHECK-PTX-NEXT: .param .b32 retval0;
; CHECK-PTX-NEXT: call.uni (retval0),
; CHECK-PTX-NEXT: variadics2,
; CHECK-PTX-NEXT: (
; CHECK-PTX-NEXT: param0,
; CHECK-PTX-NEXT: param1
; CHECK-PTX-NEXT: );
; CHECK-PTX-NEXT: ld.param.b32 %r2, [retval0+0];
; CHECK-PTX-NEXT: ld.param.b32 %r2, [retval0];
; CHECK-PTX-NEXT: } // callseq 1
; CHECK-PTX-NEXT: st.param.b32 [func_retval0+0], %r2;
; CHECK-PTX-NEXT: st.param.b32 [func_retval0], %r2;
; CHECK-PTX-NEXT: ret;
entry:
%s1.sroa.3 = alloca [3 x i8], align 1
Expand All @@ -286,7 +286,7 @@ define dso_local i32 @variadics3(i32 noundef %first, ...) {
; CHECK-PTX-NEXT: add.s32 %r5, %r1, %r2;
; CHECK-PTX-NEXT: add.s32 %r6, %r5, %r3;
; CHECK-PTX-NEXT: add.s32 %r7, %r6, %r4;
; CHECK-PTX-NEXT: st.param.b32 [func_retval0+0], %r7;
; CHECK-PTX-NEXT: st.param.b32 [func_retval0], %r7;
; CHECK-PTX-NEXT: ret;
entry:
%vlist = alloca ptr, align 8
Expand Down Expand Up @@ -321,23 +321,23 @@ define dso_local i32 @baz() {
; CHECK-PTX-NEXT: mov.u64 %SPL, __local_depot5;
; CHECK-PTX-NEXT: cvta.local.u64 %SP, %SPL;
; CHECK-PTX-NEXT: mov.b32 %r1, 1;
; CHECK-PTX-NEXT: st.v4.u32 [%SP+0], {%r1, %r1, %r1, %r1};
; CHECK-PTX-NEXT: st.v4.u32 [%SP], {%r1, %r1, %r1, %r1};
; CHECK-PTX-NEXT: add.u64 %rd1, %SP, 0;
; CHECK-PTX-NEXT: { // callseq 2, 0
; CHECK-PTX-NEXT: .param .b32 param0;
; CHECK-PTX-NEXT: st.param.b32 [param0+0], 1;
; CHECK-PTX-NEXT: st.param.b32 [param0], 1;
; CHECK-PTX-NEXT: .param .b64 param1;
; CHECK-PTX-NEXT: st.param.b64 [param1+0], %rd1;
; CHECK-PTX-NEXT: st.param.b64 [param1], %rd1;
; CHECK-PTX-NEXT: .param .b32 retval0;
; CHECK-PTX-NEXT: call.uni (retval0),
; CHECK-PTX-NEXT: variadics3,
; CHECK-PTX-NEXT: (
; CHECK-PTX-NEXT: param0,
; CHECK-PTX-NEXT: param1
; CHECK-PTX-NEXT: );
; CHECK-PTX-NEXT: ld.param.b32 %r2, [retval0+0];
; CHECK-PTX-NEXT: ld.param.b32 %r2, [retval0];
; CHECK-PTX-NEXT: } // callseq 2
; CHECK-PTX-NEXT: st.param.b32 [func_retval0+0], %r2;
; CHECK-PTX-NEXT: st.param.b32 [func_retval0], %r2;
; CHECK-PTX-NEXT: ret;
entry:
%call = call i32 (i32, ...) @variadics3(i32 noundef 1, <4 x i32> noundef <i32 1, i32 1, i32 1, i32 1>)
Expand All @@ -360,7 +360,7 @@ define dso_local i32 @variadics4(ptr noundef byval(%struct.S2) align 8 %first, .
; CHECK-PTX-NEXT: add.s64 %rd7, %rd5, %rd6;
; CHECK-PTX-NEXT: add.s64 %rd8, %rd7, %rd4;
; CHECK-PTX-NEXT: cvt.u32.u64 %r1, %rd8;
; CHECK-PTX-NEXT: st.param.b32 [func_retval0+0], %r1;
; CHECK-PTX-NEXT: st.param.b32 [func_retval0], %r1;
; CHECK-PTX-NEXT: ret;
entry:
%vlist = alloca ptr, align 8
Expand Down Expand Up @@ -395,7 +395,7 @@ define dso_local void @qux() {
; CHECK-PTX-NEXT: mov.u64 %SPL, __local_depot7;
; CHECK-PTX-NEXT: cvta.local.u64 %SP, %SPL;
; CHECK-PTX-NEXT: ld.global.nc.u64 %rd1, [__const_$_qux_$_s];
; CHECK-PTX-NEXT: st.u64 [%SP+0], %rd1;
; CHECK-PTX-NEXT: st.u64 [%SP], %rd1;
; CHECK-PTX-NEXT: mov.u64 %rd2, __const_$_qux_$_s;
; CHECK-PTX-NEXT: add.s64 %rd3, %rd2, 8;
; CHECK-PTX-NEXT: ld.global.nc.u64 %rd4, [%rd3];
Expand All @@ -405,18 +405,18 @@ define dso_local void @qux() {
; CHECK-PTX-NEXT: add.u64 %rd6, %SP, 16;
; CHECK-PTX-NEXT: { // callseq 3, 0
; CHECK-PTX-NEXT: .param .align 8 .b8 param0[16];
; CHECK-PTX-NEXT: st.param.b64 [param0+0], %rd1;
; CHECK-PTX-NEXT: st.param.b64 [param0], %rd1;
; CHECK-PTX-NEXT: st.param.b64 [param0+8], %rd4;
; CHECK-PTX-NEXT: .param .b64 param1;
; CHECK-PTX-NEXT: st.param.b64 [param1+0], %rd6;
; CHECK-PTX-NEXT: st.param.b64 [param1], %rd6;
; CHECK-PTX-NEXT: .param .b32 retval0;
; CHECK-PTX-NEXT: call.uni (retval0),
; CHECK-PTX-NEXT: variadics4,
; CHECK-PTX-NEXT: (
; CHECK-PTX-NEXT: param0,
; CHECK-PTX-NEXT: param1
; CHECK-PTX-NEXT: );
; CHECK-PTX-NEXT: ld.param.b32 %r1, [retval0+0];
; CHECK-PTX-NEXT: ld.param.b32 %r1, [retval0];
; CHECK-PTX-NEXT: } // callseq 3
; CHECK-PTX-NEXT: ret;
entry:
Expand Down
14 changes: 7 additions & 7 deletions llvm/test/CodeGen/NVPTX/vec-param-load.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@ define <16 x float> @test_v16f32(<16 x float> %a) {
; CHECK-DAG: ld.param.v4.f32 {[[V_8_11:(%f[0-9]+[, ]*){4}]]}, [test_v16f32_param_0+32];
; CHECK-DAG: ld.param.v4.f32 {[[V_4_7:(%f[0-9]+[, ]*){4}]]}, [test_v16f32_param_0+16];
; CHECK-DAG: ld.param.v4.f32 {[[V_0_3:(%f[0-9]+[, ]*){4}]]}, [test_v16f32_param_0];
; CHECK-DAG: st.param.v4.f32 [func_retval0+0], {[[V_0_3]]}
; CHECK-DAG: st.param.v4.f32 [func_retval0], {[[V_0_3]]}
; CHECK-DAG: st.param.v4.f32 [func_retval0+16], {[[V_4_7]]}
; CHECK-DAG: st.param.v4.f32 [func_retval0+32], {[[V_8_11]]}
; CHECK-DAG: st.param.v4.f32 [func_retval0+48], {[[V_12_15]]}
Expand All @@ -21,7 +21,7 @@ define <8 x float> @test_v8f32(<8 x float> %a) {
; CHECK-LABEL: test_v8f32(
; CHECK-DAG: ld.param.v4.f32 {[[V_4_7:(%f[0-9]+[, ]*){4}]]}, [test_v8f32_param_0+16];
; CHECK-DAG: ld.param.v4.f32 {[[V_0_3:(%f[0-9]+[, ]*){4}]]}, [test_v8f32_param_0];
; CHECK-DAG: st.param.v4.f32 [func_retval0+0], {[[V_0_3]]}
; CHECK-DAG: st.param.v4.f32 [func_retval0], {[[V_0_3]]}
; CHECK-DAG: st.param.v4.f32 [func_retval0+16], {[[V_4_7]]}
; CHECK: ret;
ret <8 x float> %a
Expand All @@ -30,15 +30,15 @@ define <8 x float> @test_v8f32(<8 x float> %a) {
define <4 x float> @test_v4f32(<4 x float> %a) {
; CHECK-LABEL: test_v4f32(
; CHECK-DAG: ld.param.v4.f32 {[[V_0_3:(%f[0-9]+[, ]*){4}]]}, [test_v4f32_param_0];
; CHECK-DAG: st.param.v4.f32 [func_retval0+0], {[[V_0_3]]}
; CHECK-DAG: st.param.v4.f32 [func_retval0], {[[V_0_3]]}
; CHECK: ret;
ret <4 x float> %a
}

define <2 x float> @test_v2f32(<2 x float> %a) {
; CHECK-LABEL: test_v2f32(
; CHECK-DAG: ld.param.v2.f32 {[[V_0_3:(%f[0-9]+[, ]*){2}]]}, [test_v2f32_param_0];
; CHECK-DAG: st.param.v2.f32 [func_retval0+0], {[[V_0_3]]}
; CHECK-DAG: st.param.v2.f32 [func_retval0], {[[V_0_3]]}
; CHECK: ret;
ret <2 x float> %a
}
Expand All @@ -48,7 +48,7 @@ define <3 x float> @test_v3f32(<3 x float> %a) {
; CHECK-LABEL: test_v3f32(
; CHECK-DAG: ld.param.f32 [[V_2:%f[0-9]+]], [test_v3f32_param_0+8];
; CHECK-DAG: ld.param.v2.f32 {[[V_0_1:(%f[0-9]+[, ]*){2}]]}, [test_v3f32_param_0];
; CHECK-DAG: st.param.v2.f32 [func_retval0+0], {[[V_0_1]]}
; CHECK-DAG: st.param.v2.f32 [func_retval0], {[[V_0_1]]}
; CHECK-DAG: st.param.f32 [func_retval0+8], [[V_2]]
; CHECK: ret;
ret <3 x float> %a
Expand All @@ -60,7 +60,7 @@ define <8 x i64> @test_v8i64(<8 x i64> %a) {
; CHECK-DAG: ld.param.v2.u64 {[[V_4_5:(%rd[0-9]+[, ]*){2}]]}, [test_v8i64_param_0+32];
; CHECK-DAG: ld.param.v2.u64 {[[V_2_3:(%rd[0-9]+[, ]*){2}]]}, [test_v8i64_param_0+16];
; CHECK-DAG: ld.param.v2.u64 {[[V_0_1:(%rd[0-9]+[, ]*){2}]]}, [test_v8i64_param_0];
; CHECK-DAG: st.param.v2.b64 [func_retval0+0], {[[V_0_1]]}
; CHECK-DAG: st.param.v2.b64 [func_retval0], {[[V_0_1]]}
; CHECK-DAG: st.param.v2.b64 [func_retval0+16], {[[V_2_3]]}
; CHECK-DAG: st.param.v2.b64 [func_retval0+32], {[[V_4_5]]}
; CHECK-DAG: st.param.v2.b64 [func_retval0+48], {[[V_6_7]]}
Expand All @@ -72,7 +72,7 @@ define <16 x i16> @test_v16i16(<16 x i16> %a) {
; CHECK-LABEL: test_v16i16(
; CHECK-DAG: ld.param.v4.u32 {[[V_8_15:(%r[0-9]+[, ]*){4}]]}, [test_v16i16_param_0+16];
; CHECK-DAG: ld.param.v4.u32 {[[V_0_7:(%r[0-9]+[, ]*){4}]]}, [test_v16i16_param_0];
; CHECK-DAG: st.param.v4.b32 [func_retval0+0], {[[V_0_7]]}
; CHECK-DAG: st.param.v4.b32 [func_retval0], {[[V_0_7]]}
; CHECK-DAG: st.param.v4.b32 [func_retval0+16], {[[V_8_15]]}
; CHECK: ret;
ret <16 x i16> %a
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/NVPTX/vector-args.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -29,7 +29,7 @@ define <4 x float> @baz(<4 x float> %a) {
; CHECK: .func (.param .align 16 .b8 func_retval0[16]) baz
; CHECK: .param .align 16 .b8 baz_param_0[16]
; CHECK: ld.param.v4.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}}
; CHECK: st.param.v4.f32 [func_retval0+0], {%f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}}
; CHECK: st.param.v4.f32 [func_retval0], {%f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}}
%t1 = fmul <4 x float> %a, %a
ret <4 x float> %t1
}
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/NVPTX/vector-call.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@ declare void @bar(<4 x i32>)
; CHECK-LABEL: .func foo(
; CHECK-DAG: ld.param.v4.u32 {[[E0:%r[0-9]+]], [[E1:%r[0-9]+]], [[E2:%r[0-9]+]], [[E3:%r[0-9]+]]}, [foo_param_0];
; CHECK: .param .align 16 .b8 param0[16];
; CHECK-DAG: st.param.v4.b32 [param0+0], {[[E0]], [[E1]], [[E2]], [[E3]]};
; CHECK-DAG: st.param.v4.b32 [param0], {[[E0]], [[E1]], [[E2]], [[E3]]};
; CHECK: call.uni
; CHECK: ret;
define void @foo(<4 x i32> %a) {
Expand All @@ -20,7 +20,7 @@ define void @foo(<4 x i32> %a) {
; CHECK-DAG: ld.param.v2.u32 {[[E0:%r[0-9]+]], [[E1:%r[0-9]+]]}, [foo3_param_0];
; CHECK-DAG: ld.param.u32 [[E2:%r[0-9]+]], [foo3_param_0+8];
; CHECK: .param .align 16 .b8 param0[16];
; CHECK-DAG: st.param.v2.b32 [param0+0], {[[E0]], [[E1]]};
; CHECK-DAG: st.param.v2.b32 [param0], {[[E0]], [[E1]]};
; CHECK-DAG: st.param.b32 [param0+8], [[E2]];
; CHECK: call.uni
; CHECK: ret;
Expand Down
76 changes: 38 additions & 38 deletions llvm/test/CodeGen/NVPTX/vector-returns.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@ define <3 x i64> @long3() {
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov.u64 %rd1, 0;
; CHECK-NEXT: st.param.v2.b64 [func_retval0+0], {%rd1, %rd1};
; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd1, %rd1};
; CHECK-NEXT: st.param.b64 [func_retval0+16], %rd1;
; CHECK-NEXT: ret;
ret <3 x i64> zeroinitializer
Expand All @@ -23,7 +23,7 @@ define <2 x i64> @long2() {
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov.u64 %rd1, 0;
; CHECK-NEXT: st.param.v2.b64 [func_retval0+0], {%rd1, %rd1};
; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd1, %rd1};
; CHECK-NEXT: ret;
ret <2 x i64> zeroinitializer
}
Expand All @@ -35,7 +35,7 @@ define <1 x i64> @long1() {
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov.u64 %rd1, 0;
; CHECK-NEXT: st.param.b64 [func_retval0+0], %rd1;
; CHECK-NEXT: st.param.b64 [func_retval0], %rd1;
; CHECK-NEXT: ret;
ret <1 x i64> zeroinitializer
}
Expand All @@ -47,7 +47,7 @@ define <5 x i32> @int5() {
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: st.param.v4.b32 [func_retval0+0], {%r1, %r1, %r1, %r1};
; CHECK-NEXT: st.param.v4.b32 [func_retval0], {%r1, %r1, %r1, %r1};
; CHECK-NEXT: st.param.b32 [func_retval0+16], %r1;
; CHECK-NEXT: ret;
ret <5 x i32> zeroinitializer
Expand All @@ -60,7 +60,7 @@ define <4 x i32> @int4() {
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: st.param.v4.b32 [func_retval0+0], {%r1, %r1, %r1, %r1};
; CHECK-NEXT: st.param.v4.b32 [func_retval0], {%r1, %r1, %r1, %r1};
; CHECK-NEXT: ret;
ret <4 x i32> zeroinitializer
}
Expand All @@ -72,7 +72,7 @@ define <3 x i32> @int3() {
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: st.param.v2.b32 [func_retval0+0], {%r1, %r1};
; CHECK-NEXT: st.param.v2.b32 [func_retval0], {%r1, %r1};
; CHECK-NEXT: st.param.b32 [func_retval0+8], %r1;
; CHECK-NEXT: ret;
ret <3 x i32> zeroinitializer
Expand All @@ -85,7 +85,7 @@ define <2 x i32> @int2() {
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: st.param.v2.b32 [func_retval0+0], {%r1, %r1};
; CHECK-NEXT: st.param.v2.b32 [func_retval0], {%r1, %r1};
; CHECK-NEXT: ret;
ret <2 x i32> zeroinitializer
}
Expand All @@ -97,7 +97,7 @@ define <1 x i32> @int1() {
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: st.param.b32 [func_retval0+0], %r1;
; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
ret <1 x i32> zeroinitializer
}
Expand All @@ -109,7 +109,7 @@ define <9 x i16> @short9() {
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov.u16 %rs1, 0;
; CHECK-NEXT: st.param.v4.b16 [func_retval0+0], {%rs1, %rs1, %rs1, %rs1};
; CHECK-NEXT: st.param.v4.b16 [func_retval0], {%rs1, %rs1, %rs1, %rs1};
; CHECK-NEXT: st.param.v4.b16 [func_retval0+8], {%rs1, %rs1, %rs1, %rs1};
; CHECK-NEXT: st.param.b16 [func_retval0+16], %rs1;
; CHECK-NEXT: ret;
Expand All @@ -123,7 +123,7 @@ define <8 x i16> @short8() {
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: st.param.v4.b32 [func_retval0+0], {%r1, %r1, %r1, %r1};
; CHECK-NEXT: st.param.v4.b32 [func_retval0], {%r1, %r1, %r1, %r1};
; CHECK-NEXT: ret;
ret <8 x i16> zeroinitializer
}
Expand All @@ -135,7 +135,7 @@ define <7 x i16> @short7() {
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov.u16 %rs1, 0;
; CHECK-NEXT: st.param.v4.b16 [func_retval0+0], {%rs1, %rs1, %rs1, %rs1};
; CHECK-NEXT: st.param.v4.b16 [func_retval0], {%rs1, %rs1, %rs1, %rs1};
; CHECK-NEXT: st.param.v2.b16 [func_retval0+8], {%rs1, %rs1};
; CHECK-NEXT: st.param.b16 [func_retval0+12], %rs1;
; CHECK-NEXT: ret;
Expand All @@ -149,7 +149,7 @@ define <5 x i16> @short5() {
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov.u16 %rs1, 0;
; CHECK-NEXT: st.param.v4.b16 [func_retval0+0], {%rs1, %rs1, %rs1, %rs1};
; CHECK-NEXT: st.param.v4.b16 [func_retval0], {%rs1, %rs1, %rs1, %rs1};
; CHECK-NEXT: st.param.b16 [func_retval0+8], %rs1;
; CHECK-NEXT: ret;
ret <5 x i16> zeroinitializer
Expand All @@ -162,7 +162,7 @@ define <4 x i16> @short4() {
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: st.param.v2.b32 [func_retval0+0], {%r1, %r1};
; CHECK-NEXT: st.param.v2.b32 [func_retval0], {%r1, %r1};
; CHECK-NEXT: ret;
ret <4 x i16> zeroinitializer
}
Expand All @@ -174,7 +174,7 @@ define <3 x i16> @short3() {
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov.u16 %rs1, 0;
; CHECK-NEXT: st.param.v2.b16 [func_retval0+0], {%rs1, %rs1};
; CHECK-NEXT: st.param.v2.b16 [func_retval0], {%rs1, %rs1};
; CHECK-NEXT: st.param.b16 [func_retval0+4], %rs1;
; CHECK-NEXT: ret;
ret <3 x i16> zeroinitializer
Expand All @@ -187,7 +187,7 @@ define <2 x i16> @short2() {
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: st.param.b32 [func_retval0+0], %r1;
; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
ret <2 x i16> zeroinitializer
}
Expand All @@ -199,7 +199,7 @@ define <1 x i16> @short1() {
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov.u16 %rs1, 0;
; CHECK-NEXT: st.param.b16 [func_retval0+0], %rs1;
; CHECK-NEXT: st.param.b16 [func_retval0], %rs1;
; CHECK-NEXT: ret;
ret <1 x i16> zeroinitializer
}
Expand All @@ -211,7 +211,7 @@ define <17 x i8> @byte17() {
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov.u16 %rs1, 0;
; CHECK-NEXT: st.param.v4.b8 [func_retval0+0], {%rs1, %rs1, %rs1, %rs1};
; CHECK-NEXT: st.param.v4.b8 [func_retval0], {%rs1, %rs1, %rs1, %rs1};
; CHECK-NEXT: st.param.v4.b8 [func_retval0+4], {%rs1, %rs1, %rs1, %rs1};
; CHECK-NEXT: st.param.v4.b8 [func_retval0+8], {%rs1, %rs1, %rs1, %rs1};
; CHECK-NEXT: st.param.v4.b8 [func_retval0+12], {%rs1, %rs1, %rs1, %rs1};
Expand All @@ -227,7 +227,7 @@ define <16 x i8> @byte16() {
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: st.param.v4.b32 [func_retval0+0], {%r1, %r1, %r1, %r1};
; CHECK-NEXT: st.param.v4.b32 [func_retval0], {%r1, %r1, %r1, %r1};
; CHECK-NEXT: ret;
ret <16 x i8> zeroinitializer
}
Expand All @@ -239,7 +239,7 @@ define <15 x i8> @byte15() {
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov.u16 %rs1, 0;
; CHECK-NEXT: st.param.v4.b8 [func_retval0+0], {%rs1, %rs1, %rs1, %rs1};
; CHECK-NEXT: st.param.v4.b8 [func_retval0], {%rs1, %rs1, %rs1, %rs1};
; CHECK-NEXT: st.param.v4.b8 [func_retval0+4], {%rs1, %rs1, %rs1, %rs1};
; CHECK-NEXT: st.param.v4.b8 [func_retval0+8], {%rs1, %rs1, %rs1, %rs1};
; CHECK-NEXT: st.param.v2.b8 [func_retval0+12], {%rs1, %rs1};
Expand All @@ -255,7 +255,7 @@ define <9 x i8> @byte9() {
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov.u16 %rs1, 0;
; CHECK-NEXT: st.param.v4.b8 [func_retval0+0], {%rs1, %rs1, %rs1, %rs1};
; CHECK-NEXT: st.param.v4.b8 [func_retval0], {%rs1, %rs1, %rs1, %rs1};
; CHECK-NEXT: st.param.v4.b8 [func_retval0+4], {%rs1, %rs1, %rs1, %rs1};
; CHECK-NEXT: st.param.b8 [func_retval0+8], %rs1;
; CHECK-NEXT: ret;
Expand All @@ -269,7 +269,7 @@ define <8 x i8> @byte8() {
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: st.param.v2.b32 [func_retval0+0], {%r1, %r1};
; CHECK-NEXT: st.param.v2.b32 [func_retval0], {%r1, %r1};
; CHECK-NEXT: ret;
ret <8 x i8> zeroinitializer
}
Expand All @@ -281,7 +281,7 @@ define <7 x i8> @byte7() {
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov.u16 %rs1, 0;
; CHECK-NEXT: st.param.v4.b8 [func_retval0+0], {%rs1, %rs1, %rs1, %rs1};
; CHECK-NEXT: st.param.v4.b8 [func_retval0], {%rs1, %rs1, %rs1, %rs1};
; CHECK-NEXT: st.param.v2.b8 [func_retval0+4], {%rs1, %rs1};
; CHECK-NEXT: st.param.b8 [func_retval0+6], %rs1;
; CHECK-NEXT: ret;
Expand All @@ -295,7 +295,7 @@ define <5 x i8> @byte5() {
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov.u16 %rs1, 0;
; CHECK-NEXT: st.param.v4.b8 [func_retval0+0], {%rs1, %rs1, %rs1, %rs1};
; CHECK-NEXT: st.param.v4.b8 [func_retval0], {%rs1, %rs1, %rs1, %rs1};
; CHECK-NEXT: st.param.b8 [func_retval0+4], %rs1;
; CHECK-NEXT: ret;
ret <5 x i8> zeroinitializer
Expand All @@ -308,7 +308,7 @@ define <4 x i8> @byte4() {
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: st.param.b32 [func_retval0+0], %r1;
; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
ret <4 x i8> zeroinitializer
}
Expand All @@ -320,7 +320,7 @@ define <3 x i8> @byte3() {
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: st.param.b32 [func_retval0+0], %r1;
; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
ret <3 x i8> zeroinitializer
}
Expand All @@ -332,7 +332,7 @@ define <2 x i8> @byte2() {
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: st.param.b32 [func_retval0+0], %r1;
; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
ret <2 x i8> zeroinitializer
}
Expand All @@ -344,7 +344,7 @@ define <1 x i8> @byte1() {
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov.u16 %rs1, 0;
; CHECK-NEXT: st.param.b8 [func_retval0+0], %rs1;
; CHECK-NEXT: st.param.b8 [func_retval0], %rs1;
; CHECK-NEXT: ret;
ret <1 x i8> zeroinitializer
}
Expand All @@ -356,7 +356,7 @@ define <17 x i1> @bit17() {
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov.u16 %rs1, 0;
; CHECK-NEXT: st.param.v4.b8 [func_retval0+0], {%rs1, %rs1, %rs1, %rs1};
; CHECK-NEXT: st.param.v4.b8 [func_retval0], {%rs1, %rs1, %rs1, %rs1};
; CHECK-NEXT: st.param.v4.b8 [func_retval0+4], {%rs1, %rs1, %rs1, %rs1};
; CHECK-NEXT: st.param.v4.b8 [func_retval0+8], {%rs1, %rs1, %rs1, %rs1};
; CHECK-NEXT: st.param.v4.b8 [func_retval0+12], {%rs1, %rs1, %rs1, %rs1};
Expand All @@ -372,7 +372,7 @@ define <16 x i1> @bit16() {
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov.u16 %rs1, 0;
; CHECK-NEXT: st.param.v2.b8 [func_retval0+0], {%rs1, %rs1};
; CHECK-NEXT: st.param.v2.b8 [func_retval0], {%rs1, %rs1};
; CHECK-NEXT: st.param.v2.b8 [func_retval0+2], {%rs1, %rs1};
; CHECK-NEXT: st.param.v2.b8 [func_retval0+4], {%rs1, %rs1};
; CHECK-NEXT: st.param.v2.b8 [func_retval0+6], {%rs1, %rs1};
Expand All @@ -391,7 +391,7 @@ define <15 x i1> @bit15() {
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov.u16 %rs1, 0;
; CHECK-NEXT: st.param.v2.b8 [func_retval0+0], {%rs1, %rs1};
; CHECK-NEXT: st.param.v2.b8 [func_retval0], {%rs1, %rs1};
; CHECK-NEXT: st.param.v2.b8 [func_retval0+2], {%rs1, %rs1};
; CHECK-NEXT: st.param.v2.b8 [func_retval0+4], {%rs1, %rs1};
; CHECK-NEXT: st.param.v2.b8 [func_retval0+6], {%rs1, %rs1};
Expand All @@ -410,7 +410,7 @@ define <9 x i1> @bit9() {
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov.u16 %rs1, 0;
; CHECK-NEXT: st.param.v2.b8 [func_retval0+0], {%rs1, %rs1};
; CHECK-NEXT: st.param.v2.b8 [func_retval0], {%rs1, %rs1};
; CHECK-NEXT: st.param.v2.b8 [func_retval0+2], {%rs1, %rs1};
; CHECK-NEXT: st.param.v2.b8 [func_retval0+4], {%rs1, %rs1};
; CHECK-NEXT: st.param.v2.b8 [func_retval0+6], {%rs1, %rs1};
Expand All @@ -426,7 +426,7 @@ define <8 x i1> @bit8() {
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov.u16 %rs1, 0;
; CHECK-NEXT: st.param.b8 [func_retval0+0], %rs1;
; CHECK-NEXT: st.param.b8 [func_retval0], %rs1;
; CHECK-NEXT: st.param.b8 [func_retval0+1], %rs1;
; CHECK-NEXT: st.param.b8 [func_retval0+2], %rs1;
; CHECK-NEXT: st.param.b8 [func_retval0+3], %rs1;
Expand All @@ -445,7 +445,7 @@ define <7 x i1> @bit7() {
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov.u16 %rs1, 0;
; CHECK-NEXT: st.param.b8 [func_retval0+0], %rs1;
; CHECK-NEXT: st.param.b8 [func_retval0], %rs1;
; CHECK-NEXT: st.param.b8 [func_retval0+1], %rs1;
; CHECK-NEXT: st.param.b8 [func_retval0+2], %rs1;
; CHECK-NEXT: st.param.b8 [func_retval0+3], %rs1;
Expand All @@ -463,7 +463,7 @@ define <5 x i1> @bit5() {
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov.u16 %rs1, 0;
; CHECK-NEXT: st.param.b8 [func_retval0+0], %rs1;
; CHECK-NEXT: st.param.b8 [func_retval0], %rs1;
; CHECK-NEXT: st.param.b8 [func_retval0+1], %rs1;
; CHECK-NEXT: st.param.b8 [func_retval0+2], %rs1;
; CHECK-NEXT: st.param.b8 [func_retval0+3], %rs1;
Expand All @@ -479,7 +479,7 @@ define <4 x i1> @bit4() {
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov.u16 %rs1, 0;
; CHECK-NEXT: st.param.b8 [func_retval0+0], %rs1;
; CHECK-NEXT: st.param.b8 [func_retval0], %rs1;
; CHECK-NEXT: st.param.b8 [func_retval0+1], %rs1;
; CHECK-NEXT: st.param.b8 [func_retval0+2], %rs1;
; CHECK-NEXT: st.param.b8 [func_retval0+3], %rs1;
Expand All @@ -494,7 +494,7 @@ define <3 x i1> @bit3() {
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov.u16 %rs1, 0;
; CHECK-NEXT: st.param.b8 [func_retval0+0], %rs1;
; CHECK-NEXT: st.param.b8 [func_retval0], %rs1;
; CHECK-NEXT: st.param.b8 [func_retval0+1], %rs1;
; CHECK-NEXT: st.param.b8 [func_retval0+2], %rs1;
; CHECK-NEXT: ret;
Expand All @@ -508,7 +508,7 @@ define <2 x i1> @bit2() {
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov.u16 %rs1, 0;
; CHECK-NEXT: st.param.b8 [func_retval0+0], %rs1;
; CHECK-NEXT: st.param.b8 [func_retval0], %rs1;
; CHECK-NEXT: st.param.b8 [func_retval0+1], %rs1;
; CHECK-NEXT: ret;
ret <2 x i1> zeroinitializer
Expand All @@ -521,7 +521,7 @@ define <1 x i1> @bit1() {
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov.u16 %rs1, 0;
; CHECK-NEXT: st.param.b8 [func_retval0+0], %rs1;
; CHECK-NEXT: st.param.b8 [func_retval0], %rs1;
; CHECK-NEXT: ret;
ret <1 x i1> zeroinitializer
}
2 changes: 1 addition & 1 deletion llvm/test/DebugInfo/NVPTX/dbg-declare-alloca.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@
; CHECK: .loc 1 5 3 // t.c:5:3
; CHECK: { // callseq 0, 0
; CHECK: .param .b64 param0;
; CHECK: st.param.b64 [param0+0], %rd1;
; CHECK: st.param.b64 [param0], %rd1;
; CHECK: call.uni
; CHECK: escape_foo,
; CHECK: (
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/Transforms/NaryReassociate/NVPTX/nary-slsr.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -22,7 +22,7 @@ define void @nary_reassociate_after_slsr(i32 %a, i32 %b, i32 %c) {
%abc = add i32 %ab, %c
call void @foo(i32 %abc)
; CHECK: call void @foo(i32 %abc)
; PTX: st.param.b32 [param0+0], [[abc:%r[0-9]+]];
; PTX: st.param.b32 [param0], [[abc:%r[0-9]+]];

%b2 = shl i32 %b, 1
%ab2 = add i32 %a, %b2
Expand All @@ -31,7 +31,7 @@ define void @nary_reassociate_after_slsr(i32 %a, i32 %b, i32 %c) {
; PTX: add.s32 [[ab2c:%r[0-9]+]], [[abc]], [[b]]
call void @foo(i32 %ab2c)
; CHECK-NEXT: call void @foo(i32 %ab2c)
; PTX: st.param.b32 [param0+0], [[ab2c]];
; PTX: st.param.b32 [param0], [[ab2c]];

%b3 = mul i32 %b, 3
%ab3 = add i32 %a, %b3
Expand All @@ -40,7 +40,7 @@ define void @nary_reassociate_after_slsr(i32 %a, i32 %b, i32 %c) {
; PTX: add.s32 [[ab3c:%r[0-9]+]], [[ab2c]], [[b]]
call void @foo(i32 %ab3c)
; CHECK-NEXT: call void @foo(i32 %ab3c)
; PTX: st.param.b32 [param0+0], [[ab3c]];
; PTX: st.param.b32 [param0], [[ab3c]];

ret void
}
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/nvptx-basic.ll.expected
View file
Original file line number Diff line number Diff line change
Expand Up @@ -23,18 +23,18 @@ define dso_local void @caller_St8x4(ptr nocapture noundef readonly byval(%struct
; CHECK-NEXT: ld.param.u64 %rd3, [caller_St8x4_param_0+8];
; CHECK-NEXT: st.u64 [%SP+8], %rd3;
; CHECK-NEXT: ld.param.u64 %rd4, [caller_St8x4_param_0];
; CHECK-NEXT: st.u64 [%SP+0], %rd4;
; CHECK-NEXT: st.u64 [%SP], %rd4;
; CHECK-NEXT: { // callseq 0, 0
; CHECK-NEXT: .param .align 16 .b8 param0[32];
; CHECK-NEXT: st.param.v2.b64 [param0+0], {%rd4, %rd3};
; CHECK-NEXT: st.param.v2.b64 [param0], {%rd4, %rd3};
; CHECK-NEXT: st.param.v2.b64 [param0+16], {%rd2, %rd1};
; CHECK-NEXT: .param .align 16 .b8 retval0[32];
; CHECK-NEXT: call.uni (retval0),
; CHECK-NEXT: callee_St8x4,
; CHECK-NEXT: (
; CHECK-NEXT: param0
; CHECK-NEXT: );
; CHECK-NEXT: ld.param.v2.b64 {%rd5, %rd6}, [retval0+0];
; CHECK-NEXT: ld.param.v2.b64 {%rd5, %rd6}, [retval0];
; CHECK-NEXT: ld.param.v2.b64 {%rd7, %rd8}, [retval0+16];
; CHECK-NEXT: } // callseq 0
; CHECK-NEXT: st.u64 [%r1], %rd5;
Expand Down Expand Up @@ -66,7 +66,7 @@ define internal fastcc [4 x i64] @callee_St8x4(ptr nocapture noundef readonly by
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.v2.u64 {%rd1, %rd2}, [callee_St8x4_param_0];
; CHECK-NEXT: ld.param.v2.u64 {%rd3, %rd4}, [callee_St8x4_param_0+16];
; CHECK-NEXT: st.param.v2.b64 [func_retval0+0], {%rd1, %rd2};
; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd1, %rd2};
; CHECK-NEXT: st.param.v2.b64 [func_retval0+16], {%rd3, %rd4};
; CHECK-NEXT: ret;
%1 = load i64, ptr %in, align 8
Expand Down