48 changes: 24 additions & 24 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmadd-constrained-sdnode.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@

declare <2 x half> @llvm.experimental.constrained.fma.v2f16(<2 x half>, <2 x half>, <2 x half>, metadata, metadata)

define <2 x half> @vfmadd_vv_v2f16(<2 x half> %va, <2 x half> %vb, <2 x half> %vc) {
define <2 x half> @vfmadd_vv_v2f16(<2 x half> %va, <2 x half> %vb, <2 x half> %vc) strictfp {
; CHECK-LABEL: vfmadd_vv_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
Expand All @@ -19,7 +19,7 @@ define <2 x half> @vfmadd_vv_v2f16(<2 x half> %va, <2 x half> %vb, <2 x half> %v
ret <2 x half> %vd
}

define <2 x half> @vfmadd_vf_v2f16(<2 x half> %va, <2 x half> %vb, half %c) {
define <2 x half> @vfmadd_vf_v2f16(<2 x half> %va, <2 x half> %vb, half %c) strictfp {
; CHECK-LABEL: vfmadd_vf_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
Expand All @@ -33,7 +33,7 @@ define <2 x half> @vfmadd_vf_v2f16(<2 x half> %va, <2 x half> %vb, half %c) {

declare <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half>, <4 x half>, <4 x half>, metadata, metadata)

define <4 x half> @vfmadd_vv_v4f16(<4 x half> %va, <4 x half> %vb, <4 x half> %vc) {
define <4 x half> @vfmadd_vv_v4f16(<4 x half> %va, <4 x half> %vb, <4 x half> %vc) strictfp {
; CHECK-LABEL: vfmadd_vv_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
Expand All @@ -43,7 +43,7 @@ define <4 x half> @vfmadd_vv_v4f16(<4 x half> %va, <4 x half> %vb, <4 x half> %v
ret <4 x half> %vd
}

define <4 x half> @vfmadd_vf_v4f16(<4 x half> %va, <4 x half> %vb, half %c) {
define <4 x half> @vfmadd_vf_v4f16(<4 x half> %va, <4 x half> %vb, half %c) strictfp {
; CHECK-LABEL: vfmadd_vf_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
Expand All @@ -57,7 +57,7 @@ define <4 x half> @vfmadd_vf_v4f16(<4 x half> %va, <4 x half> %vb, half %c) {

declare <8 x half> @llvm.experimental.constrained.fma.v8f16(<8 x half>, <8 x half>, <8 x half>, metadata, metadata)

define <8 x half> @vfmadd_vv_v8f16(<8 x half> %va, <8 x half> %vb, <8 x half> %vc) {
define <8 x half> @vfmadd_vv_v8f16(<8 x half> %va, <8 x half> %vb, <8 x half> %vc) strictfp {
; CHECK-LABEL: vfmadd_vv_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
Expand All @@ -67,7 +67,7 @@ define <8 x half> @vfmadd_vv_v8f16(<8 x half> %va, <8 x half> %vb, <8 x half> %v
ret <8 x half> %vd
}

define <8 x half> @vfmadd_vf_v8f16(<8 x half> %va, <8 x half> %vb, half %c) {
define <8 x half> @vfmadd_vf_v8f16(<8 x half> %va, <8 x half> %vb, half %c) strictfp {
; CHECK-LABEL: vfmadd_vf_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
Expand All @@ -81,7 +81,7 @@ define <8 x half> @vfmadd_vf_v8f16(<8 x half> %va, <8 x half> %vb, half %c) {

declare <16 x half> @llvm.experimental.constrained.fma.v16f16(<16 x half>, <16 x half>, <16 x half>, metadata, metadata)

define <16 x half> @vfmadd_vv_v16f16(<16 x half> %va, <16 x half> %vb, <16 x half> %vc) {
define <16 x half> @vfmadd_vv_v16f16(<16 x half> %va, <16 x half> %vb, <16 x half> %vc) strictfp {
; CHECK-LABEL: vfmadd_vv_v16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
Expand All @@ -91,7 +91,7 @@ define <16 x half> @vfmadd_vv_v16f16(<16 x half> %va, <16 x half> %vb, <16 x hal
ret <16 x half> %vd
}

define <16 x half> @vfmadd_vf_v16f16(<16 x half> %va, <16 x half> %vb, half %c) {
define <16 x half> @vfmadd_vf_v16f16(<16 x half> %va, <16 x half> %vb, half %c) strictfp {
; CHECK-LABEL: vfmadd_vf_v16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
Expand All @@ -105,7 +105,7 @@ define <16 x half> @vfmadd_vf_v16f16(<16 x half> %va, <16 x half> %vb, half %c)

declare <32 x half> @llvm.experimental.constrained.fma.v32f16(<32 x half>, <32 x half>, <32 x half>, metadata, metadata)

define <32 x half> @vfmadd_vv_v32f16(<32 x half> %va, <32 x half> %vb, <32 x half> %vc) {
define <32 x half> @vfmadd_vv_v32f16(<32 x half> %va, <32 x half> %vb, <32 x half> %vc) strictfp {
; CHECK-LABEL: vfmadd_vv_v32f16:
; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 32
Expand All @@ -116,7 +116,7 @@ define <32 x half> @vfmadd_vv_v32f16(<32 x half> %va, <32 x half> %vb, <32 x hal
ret <32 x half> %vd
}

define <32 x half> @vfmadd_vf_v32f16(<32 x half> %va, <32 x half> %vb, half %c) {
define <32 x half> @vfmadd_vf_v32f16(<32 x half> %va, <32 x half> %vb, half %c) strictfp {
; CHECK-LABEL: vfmadd_vf_v32f16:
; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 32
Expand All @@ -131,7 +131,7 @@ define <32 x half> @vfmadd_vf_v32f16(<32 x half> %va, <32 x half> %vb, half %c)

declare <2 x float> @llvm.experimental.constrained.fma.v2f32(<2 x float>, <2 x float>, <2 x float>, metadata, metadata)

define <2 x float> @vfmadd_vv_v2f32(<2 x float> %va, <2 x float> %vb, <2 x float> %vc) {
define <2 x float> @vfmadd_vv_v2f32(<2 x float> %va, <2 x float> %vb, <2 x float> %vc) strictfp {
; CHECK-LABEL: vfmadd_vv_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
Expand All @@ -141,7 +141,7 @@ define <2 x float> @vfmadd_vv_v2f32(<2 x float> %va, <2 x float> %vb, <2 x float
ret <2 x float> %vd
}

define <2 x float> @vfmadd_vf_v2f32(<2 x float> %va, <2 x float> %vb, float %c) {
define <2 x float> @vfmadd_vf_v2f32(<2 x float> %va, <2 x float> %vb, float %c) strictfp {
; CHECK-LABEL: vfmadd_vf_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
Expand All @@ -155,7 +155,7 @@ define <2 x float> @vfmadd_vf_v2f32(<2 x float> %va, <2 x float> %vb, float %c)

declare <4 x float> @llvm.experimental.constrained.fma.v4f32(<4 x float>, <4 x float>, <4 x float>, metadata, metadata)

define <4 x float> @vfmadd_vv_v4f32(<4 x float> %va, <4 x float> %vb, <4 x float> %vc) {
define <4 x float> @vfmadd_vv_v4f32(<4 x float> %va, <4 x float> %vb, <4 x float> %vc) strictfp {
; CHECK-LABEL: vfmadd_vv_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
Expand All @@ -165,7 +165,7 @@ define <4 x float> @vfmadd_vv_v4f32(<4 x float> %va, <4 x float> %vb, <4 x float
ret <4 x float> %vd
}

define <4 x float> @vfmadd_vf_v4f32(<4 x float> %va, <4 x float> %vb, float %c) {
define <4 x float> @vfmadd_vf_v4f32(<4 x float> %va, <4 x float> %vb, float %c) strictfp {
; CHECK-LABEL: vfmadd_vf_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
Expand All @@ -179,7 +179,7 @@ define <4 x float> @vfmadd_vf_v4f32(<4 x float> %va, <4 x float> %vb, float %c)

declare <8 x float> @llvm.experimental.constrained.fma.v8f32(<8 x float>, <8 x float>, <8 x float>, metadata, metadata)

define <8 x float> @vfmadd_vv_v8f32(<8 x float> %va, <8 x float> %vb, <8 x float> %vc) {
define <8 x float> @vfmadd_vv_v8f32(<8 x float> %va, <8 x float> %vb, <8 x float> %vc) strictfp {
; CHECK-LABEL: vfmadd_vv_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
Expand All @@ -189,7 +189,7 @@ define <8 x float> @vfmadd_vv_v8f32(<8 x float> %va, <8 x float> %vb, <8 x float
ret <8 x float> %vd
}

define <8 x float> @vfmadd_vf_v8f32(<8 x float> %va, <8 x float> %vb, float %c) {
define <8 x float> @vfmadd_vf_v8f32(<8 x float> %va, <8 x float> %vb, float %c) strictfp {
; CHECK-LABEL: vfmadd_vf_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
Expand All @@ -203,7 +203,7 @@ define <8 x float> @vfmadd_vf_v8f32(<8 x float> %va, <8 x float> %vb, float %c)

declare <16 x float> @llvm.experimental.constrained.fma.v16f32(<16 x float>, <16 x float>, <16 x float>, metadata, metadata)

define <16 x float> @vfmadd_vv_v16f32(<16 x float> %va, <16 x float> %vb, <16 x float> %vc) {
define <16 x float> @vfmadd_vv_v16f32(<16 x float> %va, <16 x float> %vb, <16 x float> %vc) strictfp {
; CHECK-LABEL: vfmadd_vv_v16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
Expand All @@ -213,7 +213,7 @@ define <16 x float> @vfmadd_vv_v16f32(<16 x float> %va, <16 x float> %vb, <16 x
ret <16 x float> %vd
}

define <16 x float> @vfmadd_vf_v16f32(<16 x float> %va, <16 x float> %vb, float %c) {
define <16 x float> @vfmadd_vf_v16f32(<16 x float> %va, <16 x float> %vb, float %c) strictfp {
; CHECK-LABEL: vfmadd_vf_v16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
Expand All @@ -227,7 +227,7 @@ define <16 x float> @vfmadd_vf_v16f32(<16 x float> %va, <16 x float> %vb, float

declare <2 x double> @llvm.experimental.constrained.fma.v2f64(<2 x double>, <2 x double>, <2 x double>, metadata, metadata)

define <2 x double> @vfmadd_vv_v2f64(<2 x double> %va, <2 x double> %vb, <2 x double> %vc) {
define <2 x double> @vfmadd_vv_v2f64(<2 x double> %va, <2 x double> %vb, <2 x double> %vc) strictfp {
; CHECK-LABEL: vfmadd_vv_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
Expand All @@ -237,7 +237,7 @@ define <2 x double> @vfmadd_vv_v2f64(<2 x double> %va, <2 x double> %vb, <2 x do
ret <2 x double> %vd
}

define <2 x double> @vfmadd_vf_v2f64(<2 x double> %va, <2 x double> %vb, double %c) {
define <2 x double> @vfmadd_vf_v2f64(<2 x double> %va, <2 x double> %vb, double %c) strictfp {
; CHECK-LABEL: vfmadd_vf_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
Expand All @@ -251,7 +251,7 @@ define <2 x double> @vfmadd_vf_v2f64(<2 x double> %va, <2 x double> %vb, double

declare <4 x double> @llvm.experimental.constrained.fma.v4f64(<4 x double>, <4 x double>, <4 x double>, metadata, metadata)

define <4 x double> @vfmadd_vv_v4f64(<4 x double> %va, <4 x double> %vb, <4 x double> %vc) {
define <4 x double> @vfmadd_vv_v4f64(<4 x double> %va, <4 x double> %vb, <4 x double> %vc) strictfp {
; CHECK-LABEL: vfmadd_vv_v4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
Expand All @@ -261,7 +261,7 @@ define <4 x double> @vfmadd_vv_v4f64(<4 x double> %va, <4 x double> %vb, <4 x do
ret <4 x double> %vd
}

define <4 x double> @vfmadd_vf_v4f64(<4 x double> %va, <4 x double> %vb, double %c) {
define <4 x double> @vfmadd_vf_v4f64(<4 x double> %va, <4 x double> %vb, double %c) strictfp {
; CHECK-LABEL: vfmadd_vf_v4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
Expand All @@ -275,7 +275,7 @@ define <4 x double> @vfmadd_vf_v4f64(<4 x double> %va, <4 x double> %vb, double

declare <8 x double> @llvm.experimental.constrained.fma.v8f64(<8 x double>, <8 x double>, <8 x double>, metadata, metadata)

define <8 x double> @vfmadd_vv_v8f64(<8 x double> %va, <8 x double> %vb, <8 x double> %vc) {
define <8 x double> @vfmadd_vv_v8f64(<8 x double> %va, <8 x double> %vb, <8 x double> %vc) strictfp {
; CHECK-LABEL: vfmadd_vv_v8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
Expand All @@ -285,7 +285,7 @@ define <8 x double> @vfmadd_vv_v8f64(<8 x double> %va, <8 x double> %vb, <8 x do
ret <8 x double> %vd
}

define <8 x double> @vfmadd_vf_v8f64(<8 x double> %va, <8 x double> %vb, double %c) {
define <8 x double> @vfmadd_vf_v8f64(<8 x double> %va, <8 x double> %vb, double %c) strictfp {
; CHECK-LABEL: vfmadd_vf_v8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
Expand Down
48 changes: 24 additions & 24 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmsub-constrained-sdnode.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@

declare <2 x half> @llvm.experimental.constrained.fma.v2f16(<2 x half>, <2 x half>, <2 x half>, metadata, metadata)

define <2 x half> @vfmsub_vv_v2f16(<2 x half> %va, <2 x half> %vb, <2 x half> %vc) {
define <2 x half> @vfmsub_vv_v2f16(<2 x half> %va, <2 x half> %vb, <2 x half> %vc) strictfp {
; CHECK-LABEL: vfmsub_vv_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
Expand All @@ -20,7 +20,7 @@ define <2 x half> @vfmsub_vv_v2f16(<2 x half> %va, <2 x half> %vb, <2 x half> %v
ret <2 x half> %vd
}

define <2 x half> @vfmsub_vf_v2f16(<2 x half> %va, <2 x half> %vb, half %c) {
define <2 x half> @vfmsub_vf_v2f16(<2 x half> %va, <2 x half> %vb, half %c) strictfp {
; CHECK-LABEL: vfmsub_vf_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
Expand All @@ -35,7 +35,7 @@ define <2 x half> @vfmsub_vf_v2f16(<2 x half> %va, <2 x half> %vb, half %c) {

declare <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half>, <4 x half>, <4 x half>, metadata, metadata)

define <4 x half> @vfmsub_vv_v4f16(<4 x half> %va, <4 x half> %vb, <4 x half> %vc) {
define <4 x half> @vfmsub_vv_v4f16(<4 x half> %va, <4 x half> %vb, <4 x half> %vc) strictfp {
; CHECK-LABEL: vfmsub_vv_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
Expand All @@ -46,7 +46,7 @@ define <4 x half> @vfmsub_vv_v4f16(<4 x half> %va, <4 x half> %vb, <4 x half> %v
ret <4 x half> %vd
}

define <4 x half> @vfmsub_vf_v4f16(<4 x half> %va, <4 x half> %vb, half %c) {
define <4 x half> @vfmsub_vf_v4f16(<4 x half> %va, <4 x half> %vb, half %c) strictfp {
; CHECK-LABEL: vfmsub_vf_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
Expand All @@ -61,7 +61,7 @@ define <4 x half> @vfmsub_vf_v4f16(<4 x half> %va, <4 x half> %vb, half %c) {

declare <8 x half> @llvm.experimental.constrained.fma.v8f16(<8 x half>, <8 x half>, <8 x half>, metadata, metadata)

define <8 x half> @vfmsub_vv_v8f16(<8 x half> %va, <8 x half> %vb, <8 x half> %vc) {
define <8 x half> @vfmsub_vv_v8f16(<8 x half> %va, <8 x half> %vb, <8 x half> %vc) strictfp {
; CHECK-LABEL: vfmsub_vv_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
Expand All @@ -72,7 +72,7 @@ define <8 x half> @vfmsub_vv_v8f16(<8 x half> %va, <8 x half> %vb, <8 x half> %v
ret <8 x half> %vd
}

define <8 x half> @vfmsub_vf_v8f16(<8 x half> %va, <8 x half> %vb, half %c) {
define <8 x half> @vfmsub_vf_v8f16(<8 x half> %va, <8 x half> %vb, half %c) strictfp {
; CHECK-LABEL: vfmsub_vf_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
Expand All @@ -87,7 +87,7 @@ define <8 x half> @vfmsub_vf_v8f16(<8 x half> %va, <8 x half> %vb, half %c) {

declare <16 x half> @llvm.experimental.constrained.fma.v16f16(<16 x half>, <16 x half>, <16 x half>, metadata, metadata)

define <16 x half> @vfmsub_vv_v16f16(<16 x half> %va, <16 x half> %vb, <16 x half> %vc) {
define <16 x half> @vfmsub_vv_v16f16(<16 x half> %va, <16 x half> %vb, <16 x half> %vc) strictfp {
; CHECK-LABEL: vfmsub_vv_v16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
Expand All @@ -98,7 +98,7 @@ define <16 x half> @vfmsub_vv_v16f16(<16 x half> %va, <16 x half> %vb, <16 x hal
ret <16 x half> %vd
}

define <16 x half> @vfmsub_vf_v16f16(<16 x half> %va, <16 x half> %vb, half %c) {
define <16 x half> @vfmsub_vf_v16f16(<16 x half> %va, <16 x half> %vb, half %c) strictfp {
; CHECK-LABEL: vfmsub_vf_v16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
Expand All @@ -113,7 +113,7 @@ define <16 x half> @vfmsub_vf_v16f16(<16 x half> %va, <16 x half> %vb, half %c)

declare <32 x half> @llvm.experimental.constrained.fma.v32f16(<32 x half>, <32 x half>, <32 x half>, metadata, metadata)

define <32 x half> @vfmsub_vv_v32f16(<32 x half> %va, <32 x half> %vb, <32 x half> %vc) {
define <32 x half> @vfmsub_vv_v32f16(<32 x half> %va, <32 x half> %vb, <32 x half> %vc) strictfp {
; CHECK-LABEL: vfmsub_vv_v32f16:
; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 32
Expand All @@ -125,7 +125,7 @@ define <32 x half> @vfmsub_vv_v32f16(<32 x half> %va, <32 x half> %vb, <32 x hal
ret <32 x half> %vd
}

define <32 x half> @vfmsub_vf_v32f16(<32 x half> %va, <32 x half> %vb, half %c) {
define <32 x half> @vfmsub_vf_v32f16(<32 x half> %va, <32 x half> %vb, half %c) strictfp {
; CHECK-LABEL: vfmsub_vf_v32f16:
; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 32
Expand All @@ -141,7 +141,7 @@ define <32 x half> @vfmsub_vf_v32f16(<32 x half> %va, <32 x half> %vb, half %c)

declare <2 x float> @llvm.experimental.constrained.fma.v2f32(<2 x float>, <2 x float>, <2 x float>, metadata, metadata)

define <2 x float> @vfmsub_vv_v2f32(<2 x float> %va, <2 x float> %vb, <2 x float> %vc) {
define <2 x float> @vfmsub_vv_v2f32(<2 x float> %va, <2 x float> %vb, <2 x float> %vc) strictfp {
; CHECK-LABEL: vfmsub_vv_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
Expand All @@ -152,7 +152,7 @@ define <2 x float> @vfmsub_vv_v2f32(<2 x float> %va, <2 x float> %vb, <2 x float
ret <2 x float> %vd
}

define <2 x float> @vfmsub_vf_v2f32(<2 x float> %va, <2 x float> %vb, float %c) {
define <2 x float> @vfmsub_vf_v2f32(<2 x float> %va, <2 x float> %vb, float %c) strictfp {
; CHECK-LABEL: vfmsub_vf_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
Expand All @@ -167,7 +167,7 @@ define <2 x float> @vfmsub_vf_v2f32(<2 x float> %va, <2 x float> %vb, float %c)

declare <4 x float> @llvm.experimental.constrained.fma.v4f32(<4 x float>, <4 x float>, <4 x float>, metadata, metadata)

define <4 x float> @vfmsub_vv_v4f32(<4 x float> %va, <4 x float> %vb, <4 x float> %vc) {
define <4 x float> @vfmsub_vv_v4f32(<4 x float> %va, <4 x float> %vb, <4 x float> %vc) strictfp {
; CHECK-LABEL: vfmsub_vv_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
Expand All @@ -178,7 +178,7 @@ define <4 x float> @vfmsub_vv_v4f32(<4 x float> %va, <4 x float> %vb, <4 x float
ret <4 x float> %vd
}

define <4 x float> @vfmsub_vf_v4f32(<4 x float> %va, <4 x float> %vb, float %c) {
define <4 x float> @vfmsub_vf_v4f32(<4 x float> %va, <4 x float> %vb, float %c) strictfp {
; CHECK-LABEL: vfmsub_vf_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
Expand All @@ -193,7 +193,7 @@ define <4 x float> @vfmsub_vf_v4f32(<4 x float> %va, <4 x float> %vb, float %c)

declare <8 x float> @llvm.experimental.constrained.fma.v8f32(<8 x float>, <8 x float>, <8 x float>, metadata, metadata)

define <8 x float> @vfmsub_vv_v8f32(<8 x float> %va, <8 x float> %vb, <8 x float> %vc) {
define <8 x float> @vfmsub_vv_v8f32(<8 x float> %va, <8 x float> %vb, <8 x float> %vc) strictfp {
; CHECK-LABEL: vfmsub_vv_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
Expand All @@ -204,7 +204,7 @@ define <8 x float> @vfmsub_vv_v8f32(<8 x float> %va, <8 x float> %vb, <8 x float
ret <8 x float> %vd
}

define <8 x float> @vfmsub_vf_v8f32(<8 x float> %va, <8 x float> %vb, float %c) {
define <8 x float> @vfmsub_vf_v8f32(<8 x float> %va, <8 x float> %vb, float %c) strictfp {
; CHECK-LABEL: vfmsub_vf_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
Expand All @@ -219,7 +219,7 @@ define <8 x float> @vfmsub_vf_v8f32(<8 x float> %va, <8 x float> %vb, float %c)

declare <16 x float> @llvm.experimental.constrained.fma.v16f32(<16 x float>, <16 x float>, <16 x float>, metadata, metadata)

define <16 x float> @vfmsub_vv_v16f32(<16 x float> %va, <16 x float> %vb, <16 x float> %vc) {
define <16 x float> @vfmsub_vv_v16f32(<16 x float> %va, <16 x float> %vb, <16 x float> %vc) strictfp {
; CHECK-LABEL: vfmsub_vv_v16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
Expand All @@ -230,7 +230,7 @@ define <16 x float> @vfmsub_vv_v16f32(<16 x float> %va, <16 x float> %vb, <16 x
ret <16 x float> %vd
}

define <16 x float> @vfmsub_vf_v16f32(<16 x float> %va, <16 x float> %vb, float %c) {
define <16 x float> @vfmsub_vf_v16f32(<16 x float> %va, <16 x float> %vb, float %c) strictfp {
; CHECK-LABEL: vfmsub_vf_v16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
Expand All @@ -245,7 +245,7 @@ define <16 x float> @vfmsub_vf_v16f32(<16 x float> %va, <16 x float> %vb, float

declare <2 x double> @llvm.experimental.constrained.fma.v2f64(<2 x double>, <2 x double>, <2 x double>, metadata, metadata)

define <2 x double> @vfmsub_vv_v2f64(<2 x double> %va, <2 x double> %vb, <2 x double> %vc) {
define <2 x double> @vfmsub_vv_v2f64(<2 x double> %va, <2 x double> %vb, <2 x double> %vc) strictfp {
; CHECK-LABEL: vfmsub_vv_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
Expand All @@ -256,7 +256,7 @@ define <2 x double> @vfmsub_vv_v2f64(<2 x double> %va, <2 x double> %vb, <2 x do
ret <2 x double> %vd
}

define <2 x double> @vfmsub_vf_v2f64(<2 x double> %va, <2 x double> %vb, double %c) {
define <2 x double> @vfmsub_vf_v2f64(<2 x double> %va, <2 x double> %vb, double %c) strictfp {
; CHECK-LABEL: vfmsub_vf_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
Expand All @@ -271,7 +271,7 @@ define <2 x double> @vfmsub_vf_v2f64(<2 x double> %va, <2 x double> %vb, double

declare <4 x double> @llvm.experimental.constrained.fma.v4f64(<4 x double>, <4 x double>, <4 x double>, metadata, metadata)

define <4 x double> @vfmsub_vv_v4f64(<4 x double> %va, <4 x double> %vb, <4 x double> %vc) {
define <4 x double> @vfmsub_vv_v4f64(<4 x double> %va, <4 x double> %vb, <4 x double> %vc) strictfp {
; CHECK-LABEL: vfmsub_vv_v4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
Expand All @@ -282,7 +282,7 @@ define <4 x double> @vfmsub_vv_v4f64(<4 x double> %va, <4 x double> %vb, <4 x do
ret <4 x double> %vd
}

define <4 x double> @vfmsub_vf_v4f64(<4 x double> %va, <4 x double> %vb, double %c) {
define <4 x double> @vfmsub_vf_v4f64(<4 x double> %va, <4 x double> %vb, double %c) strictfp {
; CHECK-LABEL: vfmsub_vf_v4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
Expand All @@ -297,7 +297,7 @@ define <4 x double> @vfmsub_vf_v4f64(<4 x double> %va, <4 x double> %vb, double

declare <8 x double> @llvm.experimental.constrained.fma.v8f64(<8 x double>, <8 x double>, <8 x double>, metadata, metadata)

define <8 x double> @vfmsub_vv_v8f64(<8 x double> %va, <8 x double> %vb, <8 x double> %vc) {
define <8 x double> @vfmsub_vv_v8f64(<8 x double> %va, <8 x double> %vb, <8 x double> %vc) strictfp {
; CHECK-LABEL: vfmsub_vv_v8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
Expand All @@ -308,7 +308,7 @@ define <8 x double> @vfmsub_vv_v8f64(<8 x double> %va, <8 x double> %vb, <8 x do
ret <8 x double> %vd
}

define <8 x double> @vfmsub_vf_v8f64(<8 x double> %va, <8 x double> %vb, double %c) {
define <8 x double> @vfmsub_vf_v8f64(<8 x double> %va, <8 x double> %vb, double %c) strictfp {
; CHECK-LABEL: vfmsub_vf_v8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
Expand Down
60 changes: 30 additions & 30 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-constrained-sdnode.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
; RUN: -verify-machineinstrs < %s | FileCheck %s

declare <1 x half> @llvm.experimental.constrained.fmul.v1f16(<1 x half>, <1 x half>, metadata, metadata)
define <1 x half> @vfmul_vv_v1f16(<1 x half> %va, <1 x half> %vb) {
define <1 x half> @vfmul_vv_v1f16(<1 x half> %va, <1 x half> %vb) strictfp {
; CHECK-LABEL: vfmul_vv_v1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
Expand All @@ -16,7 +16,7 @@ entry:
ret <1 x half> %vc
}

define <1 x half> @vfmul_vf_v1f16(<1 x half> %va, half %b) {
define <1 x half> @vfmul_vf_v1f16(<1 x half> %va, half %b) strictfp {
; CHECK-LABEL: vfmul_vf_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
Expand All @@ -29,7 +29,7 @@ define <1 x half> @vfmul_vf_v1f16(<1 x half> %va, half %b) {
}

declare <2 x half> @llvm.experimental.constrained.fmul.v2f16(<2 x half>, <2 x half>, metadata, metadata)
define <2 x half> @vfmul_vv_v2f16(<2 x half> %va, <2 x half> %vb) {
define <2 x half> @vfmul_vv_v2f16(<2 x half> %va, <2 x half> %vb) strictfp {
; CHECK-LABEL: vfmul_vv_v2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
Expand All @@ -40,7 +40,7 @@ entry:
ret <2 x half> %vc
}

define <2 x half> @vfmul_vf_v2f16(<2 x half> %va, half %b) {
define <2 x half> @vfmul_vf_v2f16(<2 x half> %va, half %b) strictfp {
; CHECK-LABEL: vfmul_vf_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
Expand All @@ -53,7 +53,7 @@ define <2 x half> @vfmul_vf_v2f16(<2 x half> %va, half %b) {
}

declare <4 x half> @llvm.experimental.constrained.fmul.v4f16(<4 x half>, <4 x half>, metadata, metadata)
define <4 x half> @vfmul_vv_v4f16(<4 x half> %va, <4 x half> %vb) {
define <4 x half> @vfmul_vv_v4f16(<4 x half> %va, <4 x half> %vb) strictfp {
; CHECK-LABEL: vfmul_vv_v4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
Expand All @@ -64,7 +64,7 @@ entry:
ret <4 x half> %vc
}

define <4 x half> @vfmul_vf_v4f16(<4 x half> %va, half %b) {
define <4 x half> @vfmul_vf_v4f16(<4 x half> %va, half %b) strictfp {
; CHECK-LABEL: vfmul_vf_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
Expand All @@ -77,7 +77,7 @@ define <4 x half> @vfmul_vf_v4f16(<4 x half> %va, half %b) {
}

declare <8 x half> @llvm.experimental.constrained.fmul.v8f16(<8 x half>, <8 x half>, metadata, metadata)
define <8 x half> @vfmul_vv_v8f16(<8 x half> %va, <8 x half> %vb) {
define <8 x half> @vfmul_vv_v8f16(<8 x half> %va, <8 x half> %vb) strictfp {
; CHECK-LABEL: vfmul_vv_v8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
Expand All @@ -88,7 +88,7 @@ entry:
ret <8 x half> %vc
}

define <8 x half> @vfmul_vf_v8f16(<8 x half> %va, half %b) {
define <8 x half> @vfmul_vf_v8f16(<8 x half> %va, half %b) strictfp {
; CHECK-LABEL: vfmul_vf_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
Expand All @@ -101,7 +101,7 @@ define <8 x half> @vfmul_vf_v8f16(<8 x half> %va, half %b) {
}

declare <16 x half> @llvm.experimental.constrained.fmul.v16f16(<16 x half>, <16 x half>, metadata, metadata)
define <16 x half> @vfmul_vv_v16f16(<16 x half> %va, <16 x half> %vb) {
define <16 x half> @vfmul_vv_v16f16(<16 x half> %va, <16 x half> %vb) strictfp {
; CHECK-LABEL: vfmul_vv_v16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
Expand All @@ -112,7 +112,7 @@ entry:
ret <16 x half> %vc
}

define <16 x half> @vfmul_vf_v16f16(<16 x half> %va, half %b) {
define <16 x half> @vfmul_vf_v16f16(<16 x half> %va, half %b) strictfp {
; CHECK-LABEL: vfmul_vf_v16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
Expand All @@ -125,7 +125,7 @@ define <16 x half> @vfmul_vf_v16f16(<16 x half> %va, half %b) {
}

declare <32 x half> @llvm.experimental.constrained.fmul.v32f16(<32 x half>, <32 x half>, metadata, metadata)
define <32 x half> @vfmul_vv_v32f16(<32 x half> %va, <32 x half> %vb) {
define <32 x half> @vfmul_vv_v32f16(<32 x half> %va, <32 x half> %vb) strictfp {
; CHECK-LABEL: vfmul_vv_v32f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li a0, 32
Expand All @@ -137,7 +137,7 @@ entry:
ret <32 x half> %vc
}

define <32 x half> @vfmul_vf_v32f16(<32 x half> %va, half %b) {
define <32 x half> @vfmul_vf_v32f16(<32 x half> %va, half %b) strictfp {
; CHECK-LABEL: vfmul_vf_v32f16:
; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 32
Expand All @@ -151,7 +151,7 @@ define <32 x half> @vfmul_vf_v32f16(<32 x half> %va, half %b) {
}

declare <1 x float> @llvm.experimental.constrained.fmul.v1f32(<1 x float>, <1 x float>, metadata, metadata)
define <1 x float> @vfmul_vv_v1f32(<1 x float> %va, <1 x float> %vb) {
define <1 x float> @vfmul_vv_v1f32(<1 x float> %va, <1 x float> %vb) strictfp {
; CHECK-LABEL: vfmul_vv_v1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
Expand All @@ -162,7 +162,7 @@ entry:
ret <1 x float> %vc
}

define <1 x float> @vfmul_vf_v1f32(<1 x float> %va, float %b) {
define <1 x float> @vfmul_vf_v1f32(<1 x float> %va, float %b) strictfp {
; CHECK-LABEL: vfmul_vf_v1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
Expand All @@ -175,7 +175,7 @@ define <1 x float> @vfmul_vf_v1f32(<1 x float> %va, float %b) {
}

declare <2 x float> @llvm.experimental.constrained.fmul.v2f32(<2 x float>, <2 x float>, metadata, metadata)
define <2 x float> @vfmul_vv_v2f32(<2 x float> %va, <2 x float> %vb) {
define <2 x float> @vfmul_vv_v2f32(<2 x float> %va, <2 x float> %vb) strictfp {
; CHECK-LABEL: vfmul_vv_v2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
Expand All @@ -186,7 +186,7 @@ entry:
ret <2 x float> %vc
}

define <2 x float> @vfmul_vf_v2f32(<2 x float> %va, float %b) {
define <2 x float> @vfmul_vf_v2f32(<2 x float> %va, float %b) strictfp {
; CHECK-LABEL: vfmul_vf_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
Expand All @@ -199,7 +199,7 @@ define <2 x float> @vfmul_vf_v2f32(<2 x float> %va, float %b) {
}

declare <4 x float> @llvm.experimental.constrained.fmul.v4f32(<4 x float>, <4 x float>, metadata, metadata)
define <4 x float> @vfmul_vv_v4f32(<4 x float> %va, <4 x float> %vb) {
define <4 x float> @vfmul_vv_v4f32(<4 x float> %va, <4 x float> %vb) strictfp {
; CHECK-LABEL: vfmul_vv_v4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
Expand All @@ -210,7 +210,7 @@ entry:
ret <4 x float> %vc
}

define <4 x float> @vfmul_vf_v4f32(<4 x float> %va, float %b) {
define <4 x float> @vfmul_vf_v4f32(<4 x float> %va, float %b) strictfp {
; CHECK-LABEL: vfmul_vf_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
Expand All @@ -223,7 +223,7 @@ define <4 x float> @vfmul_vf_v4f32(<4 x float> %va, float %b) {
}

declare <8 x float> @llvm.experimental.constrained.fmul.v8f32(<8 x float>, <8 x float>, metadata, metadata)
define <8 x float> @vfmul_vv_v8f32(<8 x float> %va, <8 x float> %vb) {
define <8 x float> @vfmul_vv_v8f32(<8 x float> %va, <8 x float> %vb) strictfp {
; CHECK-LABEL: vfmul_vv_v8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
Expand All @@ -234,7 +234,7 @@ entry:
ret <8 x float> %vc
}

define <8 x float> @vfmul_vf_v8f32(<8 x float> %va, float %b) {
define <8 x float> @vfmul_vf_v8f32(<8 x float> %va, float %b) strictfp {
; CHECK-LABEL: vfmul_vf_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
Expand All @@ -247,7 +247,7 @@ define <8 x float> @vfmul_vf_v8f32(<8 x float> %va, float %b) {
}

declare <16 x float> @llvm.experimental.constrained.fmul.v16f32(<16 x float>, <16 x float>, metadata, metadata)
define <16 x float> @vfmul_vv_v16f32(<16 x float> %va, <16 x float> %vb) {
define <16 x float> @vfmul_vv_v16f32(<16 x float> %va, <16 x float> %vb) strictfp {
; CHECK-LABEL: vfmul_vv_v16f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
Expand All @@ -258,7 +258,7 @@ entry:
ret <16 x float> %vc
}

define <16 x float> @vfmul_vf_v16f32(<16 x float> %va, float %b) {
define <16 x float> @vfmul_vf_v16f32(<16 x float> %va, float %b) strictfp {
; CHECK-LABEL: vfmul_vf_v16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
Expand All @@ -271,7 +271,7 @@ define <16 x float> @vfmul_vf_v16f32(<16 x float> %va, float %b) {
}

declare <1 x double> @llvm.experimental.constrained.fmul.v1f64(<1 x double>, <1 x double>, metadata, metadata)
define <1 x double> @vfmul_vv_v1f64(<1 x double> %va, <1 x double> %vb) {
define <1 x double> @vfmul_vv_v1f64(<1 x double> %va, <1 x double> %vb) strictfp {
; CHECK-LABEL: vfmul_vv_v1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
Expand All @@ -282,7 +282,7 @@ entry:
ret <1 x double> %vc
}

define <1 x double> @vfmul_vf_v1f64(<1 x double> %va, double %b) {
define <1 x double> @vfmul_vf_v1f64(<1 x double> %va, double %b) strictfp {
; CHECK-LABEL: vfmul_vf_v1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
Expand All @@ -295,7 +295,7 @@ define <1 x double> @vfmul_vf_v1f64(<1 x double> %va, double %b) {
}

declare <2 x double> @llvm.experimental.constrained.fmul.v2f64(<2 x double>, <2 x double>, metadata, metadata)
define <2 x double> @vfmul_vv_v2f64(<2 x double> %va, <2 x double> %vb) {
define <2 x double> @vfmul_vv_v2f64(<2 x double> %va, <2 x double> %vb) strictfp {
; CHECK-LABEL: vfmul_vv_v2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
Expand All @@ -306,7 +306,7 @@ entry:
ret <2 x double> %vc
}

define <2 x double> @vfmul_vf_v2f64(<2 x double> %va, double %b) {
define <2 x double> @vfmul_vf_v2f64(<2 x double> %va, double %b) strictfp {
; CHECK-LABEL: vfmul_vf_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
Expand All @@ -319,7 +319,7 @@ define <2 x double> @vfmul_vf_v2f64(<2 x double> %va, double %b) {
}

declare <4 x double> @llvm.experimental.constrained.fmul.v4f64(<4 x double>, <4 x double>, metadata, metadata)
define <4 x double> @vfmul_vv_v4f64(<4 x double> %va, <4 x double> %vb) {
define <4 x double> @vfmul_vv_v4f64(<4 x double> %va, <4 x double> %vb) strictfp {
; CHECK-LABEL: vfmul_vv_v4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
Expand All @@ -330,7 +330,7 @@ entry:
ret <4 x double> %vc
}

define <4 x double> @vfmul_vf_v4f64(<4 x double> %va, double %b) {
define <4 x double> @vfmul_vf_v4f64(<4 x double> %va, double %b) strictfp {
; CHECK-LABEL: vfmul_vf_v4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
Expand All @@ -343,7 +343,7 @@ define <4 x double> @vfmul_vf_v4f64(<4 x double> %va, double %b) {
}

declare <8 x double> @llvm.experimental.constrained.fmul.v8f64(<8 x double>, <8 x double>, metadata, metadata)
define <8 x double> @vfmul_vv_v8f64(<8 x double> %va, <8 x double> %vb) {
define <8 x double> @vfmul_vv_v8f64(<8 x double> %va, <8 x double> %vb) strictfp {
; CHECK-LABEL: vfmul_vv_v8f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
Expand All @@ -354,7 +354,7 @@ entry:
ret <8 x double> %vc
}

define <8 x double> @vfmul_vf_v8f64(<8 x double> %va, double %b) {
define <8 x double> @vfmul_vf_v8f64(<8 x double> %va, double %b) strictfp {
; CHECK-LABEL: vfmul_vf_v8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
Expand Down
48 changes: 24 additions & 24 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmadd-constrained-sdnode.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@

declare <2 x half> @llvm.experimental.constrained.fma.v2f16(<2 x half>, <2 x half>, <2 x half>, metadata, metadata)

define <2 x half> @vfnmsub_vv_v2f16(<2 x half> %va, <2 x half> %vb, <2 x half> %vc) {
define <2 x half> @vfnmsub_vv_v2f16(<2 x half> %va, <2 x half> %vb, <2 x half> %vc) strictfp {
; CHECK-LABEL: vfnmsub_vv_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
Expand All @@ -21,7 +21,7 @@ define <2 x half> @vfnmsub_vv_v2f16(<2 x half> %va, <2 x half> %vb, <2 x half> %
ret <2 x half> %vd
}

define <2 x half> @vfnmsub_vf_v2f16(<2 x half> %va, <2 x half> %vb, half %c) {
define <2 x half> @vfnmsub_vf_v2f16(<2 x half> %va, <2 x half> %vb, half %c) strictfp {
; CHECK-LABEL: vfnmsub_vf_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
Expand All @@ -37,7 +37,7 @@ define <2 x half> @vfnmsub_vf_v2f16(<2 x half> %va, <2 x half> %vb, half %c) {

declare <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half>, <4 x half>, <4 x half>, metadata, metadata)

define <4 x half> @vfnmsub_vv_v4f16(<4 x half> %va, <4 x half> %vb, <4 x half> %vc) {
define <4 x half> @vfnmsub_vv_v4f16(<4 x half> %va, <4 x half> %vb, <4 x half> %vc) strictfp {
; CHECK-LABEL: vfnmsub_vv_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
Expand All @@ -49,7 +49,7 @@ define <4 x half> @vfnmsub_vv_v4f16(<4 x half> %va, <4 x half> %vb, <4 x half> %
ret <4 x half> %vd
}

define <4 x half> @vfnmsub_vf_v4f16(<4 x half> %va, <4 x half> %vb, half %c) {
define <4 x half> @vfnmsub_vf_v4f16(<4 x half> %va, <4 x half> %vb, half %c) strictfp {
; CHECK-LABEL: vfnmsub_vf_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
Expand All @@ -65,7 +65,7 @@ define <4 x half> @vfnmsub_vf_v4f16(<4 x half> %va, <4 x half> %vb, half %c) {

declare <8 x half> @llvm.experimental.constrained.fma.v8f16(<8 x half>, <8 x half>, <8 x half>, metadata, metadata)

define <8 x half> @vfnmsub_vv_v8f16(<8 x half> %va, <8 x half> %vb, <8 x half> %vc) {
define <8 x half> @vfnmsub_vv_v8f16(<8 x half> %va, <8 x half> %vb, <8 x half> %vc) strictfp {
; CHECK-LABEL: vfnmsub_vv_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
Expand All @@ -77,7 +77,7 @@ define <8 x half> @vfnmsub_vv_v8f16(<8 x half> %va, <8 x half> %vb, <8 x half> %
ret <8 x half> %vd
}

define <8 x half> @vfnmsub_vf_v8f16(<8 x half> %va, <8 x half> %vb, half %c) {
define <8 x half> @vfnmsub_vf_v8f16(<8 x half> %va, <8 x half> %vb, half %c) strictfp {
; CHECK-LABEL: vfnmsub_vf_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
Expand All @@ -93,7 +93,7 @@ define <8 x half> @vfnmsub_vf_v8f16(<8 x half> %va, <8 x half> %vb, half %c) {

declare <16 x half> @llvm.experimental.constrained.fma.v16f16(<16 x half>, <16 x half>, <16 x half>, metadata, metadata)

define <16 x half> @vfnmsub_vv_v16f16(<16 x half> %va, <16 x half> %vb, <16 x half> %vc) {
define <16 x half> @vfnmsub_vv_v16f16(<16 x half> %va, <16 x half> %vb, <16 x half> %vc) strictfp {
; CHECK-LABEL: vfnmsub_vv_v16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
Expand All @@ -105,7 +105,7 @@ define <16 x half> @vfnmsub_vv_v16f16(<16 x half> %va, <16 x half> %vb, <16 x ha
ret <16 x half> %vd
}

define <16 x half> @vfnmsub_vf_v16f16(<16 x half> %va, <16 x half> %vb, half %c) {
define <16 x half> @vfnmsub_vf_v16f16(<16 x half> %va, <16 x half> %vb, half %c) strictfp {
; CHECK-LABEL: vfnmsub_vf_v16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
Expand All @@ -121,7 +121,7 @@ define <16 x half> @vfnmsub_vf_v16f16(<16 x half> %va, <16 x half> %vb, half %c)

declare <32 x half> @llvm.experimental.constrained.fma.v32f16(<32 x half>, <32 x half>, <32 x half>, metadata, metadata)

define <32 x half> @vfnmsub_vv_v32f16(<32 x half> %va, <32 x half> %vb, <32 x half> %vc) {
define <32 x half> @vfnmsub_vv_v32f16(<32 x half> %va, <32 x half> %vb, <32 x half> %vc) strictfp {
; CHECK-LABEL: vfnmsub_vv_v32f16:
; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 32
Expand All @@ -134,7 +134,7 @@ define <32 x half> @vfnmsub_vv_v32f16(<32 x half> %va, <32 x half> %vb, <32 x ha
ret <32 x half> %vd
}

define <32 x half> @vfnmsub_vf_v32f16(<32 x half> %va, <32 x half> %vb, half %c) {
define <32 x half> @vfnmsub_vf_v32f16(<32 x half> %va, <32 x half> %vb, half %c) strictfp {
; CHECK-LABEL: vfnmsub_vf_v32f16:
; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 32
Expand All @@ -151,7 +151,7 @@ define <32 x half> @vfnmsub_vf_v32f16(<32 x half> %va, <32 x half> %vb, half %c)

declare <2 x float> @llvm.experimental.constrained.fma.v2f32(<2 x float>, <2 x float>, <2 x float>, metadata, metadata)

define <2 x float> @vfnmsub_vv_v2f32(<2 x float> %va, <2 x float> %vb, <2 x float> %vc) {
define <2 x float> @vfnmsub_vv_v2f32(<2 x float> %va, <2 x float> %vb, <2 x float> %vc) strictfp {
; CHECK-LABEL: vfnmsub_vv_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
Expand All @@ -163,7 +163,7 @@ define <2 x float> @vfnmsub_vv_v2f32(<2 x float> %va, <2 x float> %vb, <2 x floa
ret <2 x float> %vd
}

define <2 x float> @vfnmsub_vf_v2f32(<2 x float> %va, <2 x float> %vb, float %c) {
define <2 x float> @vfnmsub_vf_v2f32(<2 x float> %va, <2 x float> %vb, float %c) strictfp {
; CHECK-LABEL: vfnmsub_vf_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
Expand All @@ -179,7 +179,7 @@ define <2 x float> @vfnmsub_vf_v2f32(<2 x float> %va, <2 x float> %vb, float %c)

declare <4 x float> @llvm.experimental.constrained.fma.v4f32(<4 x float>, <4 x float>, <4 x float>, metadata, metadata)

define <4 x float> @vfnmsub_vv_v4f32(<4 x float> %va, <4 x float> %vb, <4 x float> %vc) {
define <4 x float> @vfnmsub_vv_v4f32(<4 x float> %va, <4 x float> %vb, <4 x float> %vc) strictfp {
; CHECK-LABEL: vfnmsub_vv_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
Expand All @@ -191,7 +191,7 @@ define <4 x float> @vfnmsub_vv_v4f32(<4 x float> %va, <4 x float> %vb, <4 x floa
ret <4 x float> %vd
}

define <4 x float> @vfnmsub_vf_v4f32(<4 x float> %va, <4 x float> %vb, float %c) {
define <4 x float> @vfnmsub_vf_v4f32(<4 x float> %va, <4 x float> %vb, float %c) strictfp {
; CHECK-LABEL: vfnmsub_vf_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
Expand All @@ -207,7 +207,7 @@ define <4 x float> @vfnmsub_vf_v4f32(<4 x float> %va, <4 x float> %vb, float %c)

declare <8 x float> @llvm.experimental.constrained.fma.v8f32(<8 x float>, <8 x float>, <8 x float>, metadata, metadata)

define <8 x float> @vfnmsub_vv_v8f32(<8 x float> %va, <8 x float> %vb, <8 x float> %vc) {
define <8 x float> @vfnmsub_vv_v8f32(<8 x float> %va, <8 x float> %vb, <8 x float> %vc) strictfp {
; CHECK-LABEL: vfnmsub_vv_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
Expand All @@ -219,7 +219,7 @@ define <8 x float> @vfnmsub_vv_v8f32(<8 x float> %va, <8 x float> %vb, <8 x floa
ret <8 x float> %vd
}

define <8 x float> @vfnmsub_vf_v8f32(<8 x float> %va, <8 x float> %vb, float %c) {
define <8 x float> @vfnmsub_vf_v8f32(<8 x float> %va, <8 x float> %vb, float %c) strictfp {
; CHECK-LABEL: vfnmsub_vf_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
Expand All @@ -235,7 +235,7 @@ define <8 x float> @vfnmsub_vf_v8f32(<8 x float> %va, <8 x float> %vb, float %c)

declare <16 x float> @llvm.experimental.constrained.fma.v16f32(<16 x float>, <16 x float>, <16 x float>, metadata, metadata)

define <16 x float> @vfnmsub_vv_v16f32(<16 x float> %va, <16 x float> %vb, <16 x float> %vc) {
define <16 x float> @vfnmsub_vv_v16f32(<16 x float> %va, <16 x float> %vb, <16 x float> %vc) strictfp {
; CHECK-LABEL: vfnmsub_vv_v16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
Expand All @@ -247,7 +247,7 @@ define <16 x float> @vfnmsub_vv_v16f32(<16 x float> %va, <16 x float> %vb, <16 x
ret <16 x float> %vd
}

define <16 x float> @vfnmsub_vf_v16f32(<16 x float> %va, <16 x float> %vb, float %c) {
define <16 x float> @vfnmsub_vf_v16f32(<16 x float> %va, <16 x float> %vb, float %c) strictfp {
; CHECK-LABEL: vfnmsub_vf_v16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
Expand All @@ -263,7 +263,7 @@ define <16 x float> @vfnmsub_vf_v16f32(<16 x float> %va, <16 x float> %vb, float

declare <2 x double> @llvm.experimental.constrained.fma.v2f64(<2 x double>, <2 x double>, <2 x double>, metadata, metadata)

define <2 x double> @vfnmsub_vv_v2f64(<2 x double> %va, <2 x double> %vb, <2 x double> %vc) {
define <2 x double> @vfnmsub_vv_v2f64(<2 x double> %va, <2 x double> %vb, <2 x double> %vc) strictfp {
; CHECK-LABEL: vfnmsub_vv_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
Expand All @@ -275,7 +275,7 @@ define <2 x double> @vfnmsub_vv_v2f64(<2 x double> %va, <2 x double> %vb, <2 x d
ret <2 x double> %vd
}

define <2 x double> @vfnmsub_vf_v2f64(<2 x double> %va, <2 x double> %vb, double %c) {
define <2 x double> @vfnmsub_vf_v2f64(<2 x double> %va, <2 x double> %vb, double %c) strictfp {
; CHECK-LABEL: vfnmsub_vf_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
Expand All @@ -291,7 +291,7 @@ define <2 x double> @vfnmsub_vf_v2f64(<2 x double> %va, <2 x double> %vb, double

declare <4 x double> @llvm.experimental.constrained.fma.v4f64(<4 x double>, <4 x double>, <4 x double>, metadata, metadata)

define <4 x double> @vfnmsub_vv_v4f64(<4 x double> %va, <4 x double> %vb, <4 x double> %vc) {
define <4 x double> @vfnmsub_vv_v4f64(<4 x double> %va, <4 x double> %vb, <4 x double> %vc) strictfp {
; CHECK-LABEL: vfnmsub_vv_v4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
Expand All @@ -303,7 +303,7 @@ define <4 x double> @vfnmsub_vv_v4f64(<4 x double> %va, <4 x double> %vb, <4 x d
ret <4 x double> %vd
}

define <4 x double> @vfnmsub_vf_v4f64(<4 x double> %va, <4 x double> %vb, double %c) {
define <4 x double> @vfnmsub_vf_v4f64(<4 x double> %va, <4 x double> %vb, double %c) strictfp {
; CHECK-LABEL: vfnmsub_vf_v4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
Expand All @@ -319,7 +319,7 @@ define <4 x double> @vfnmsub_vf_v4f64(<4 x double> %va, <4 x double> %vb, double

declare <8 x double> @llvm.experimental.constrained.fma.v8f64(<8 x double>, <8 x double>, <8 x double>, metadata, metadata)

define <8 x double> @vfnmsub_vv_v8f64(<8 x double> %va, <8 x double> %vb, <8 x double> %vc) {
define <8 x double> @vfnmsub_vv_v8f64(<8 x double> %va, <8 x double> %vb, <8 x double> %vc) strictfp {
; CHECK-LABEL: vfnmsub_vv_v8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
Expand All @@ -331,7 +331,7 @@ define <8 x double> @vfnmsub_vv_v8f64(<8 x double> %va, <8 x double> %vb, <8 x d
ret <8 x double> %vd
}

define <8 x double> @vfnmsub_vf_v8f64(<8 x double> %va, <8 x double> %vb, double %c) {
define <8 x double> @vfnmsub_vf_v8f64(<8 x double> %va, <8 x double> %vb, double %c) strictfp {
; CHECK-LABEL: vfnmsub_vf_v8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
Expand Down
48 changes: 24 additions & 24 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmsub-constrained-sdnode.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@

declare <2 x half> @llvm.experimental.constrained.fma.v2f16(<2 x half>, <2 x half>, <2 x half>, metadata, metadata)

define <2 x half> @vfnmsub_vv_v2f16(<2 x half> %va, <2 x half> %vb, <2 x half> %vc) {
define <2 x half> @vfnmsub_vv_v2f16(<2 x half> %va, <2 x half> %vb, <2 x half> %vc) strictfp {
; CHECK-LABEL: vfnmsub_vv_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
Expand All @@ -20,7 +20,7 @@ define <2 x half> @vfnmsub_vv_v2f16(<2 x half> %va, <2 x half> %vb, <2 x half> %
ret <2 x half> %vd
}

define <2 x half> @vfnmsub_vf_v2f16(<2 x half> %va, <2 x half> %vb, half %c) {
define <2 x half> @vfnmsub_vf_v2f16(<2 x half> %va, <2 x half> %vb, half %c) strictfp {
; CHECK-LABEL: vfnmsub_vf_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
Expand All @@ -35,7 +35,7 @@ define <2 x half> @vfnmsub_vf_v2f16(<2 x half> %va, <2 x half> %vb, half %c) {

declare <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half>, <4 x half>, <4 x half>, metadata, metadata)

define <4 x half> @vfnmsub_vv_v4f16(<4 x half> %va, <4 x half> %vb, <4 x half> %vc) {
define <4 x half> @vfnmsub_vv_v4f16(<4 x half> %va, <4 x half> %vb, <4 x half> %vc) strictfp {
; CHECK-LABEL: vfnmsub_vv_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
Expand All @@ -46,7 +46,7 @@ define <4 x half> @vfnmsub_vv_v4f16(<4 x half> %va, <4 x half> %vb, <4 x half> %
ret <4 x half> %vd
}

define <4 x half> @vfnmsub_vf_v4f16(<4 x half> %va, <4 x half> %vb, half %c) {
define <4 x half> @vfnmsub_vf_v4f16(<4 x half> %va, <4 x half> %vb, half %c) strictfp {
; CHECK-LABEL: vfnmsub_vf_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
Expand All @@ -61,7 +61,7 @@ define <4 x half> @vfnmsub_vf_v4f16(<4 x half> %va, <4 x half> %vb, half %c) {

declare <8 x half> @llvm.experimental.constrained.fma.v8f16(<8 x half>, <8 x half>, <8 x half>, metadata, metadata)

define <8 x half> @vfnmsub_vv_v8f16(<8 x half> %va, <8 x half> %vb, <8 x half> %vc) {
define <8 x half> @vfnmsub_vv_v8f16(<8 x half> %va, <8 x half> %vb, <8 x half> %vc) strictfp {
; CHECK-LABEL: vfnmsub_vv_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
Expand All @@ -72,7 +72,7 @@ define <8 x half> @vfnmsub_vv_v8f16(<8 x half> %va, <8 x half> %vb, <8 x half> %
ret <8 x half> %vd
}

define <8 x half> @vfnmsub_vf_v8f16(<8 x half> %va, <8 x half> %vb, half %c) {
define <8 x half> @vfnmsub_vf_v8f16(<8 x half> %va, <8 x half> %vb, half %c) strictfp {
; CHECK-LABEL: vfnmsub_vf_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
Expand All @@ -87,7 +87,7 @@ define <8 x half> @vfnmsub_vf_v8f16(<8 x half> %va, <8 x half> %vb, half %c) {

declare <16 x half> @llvm.experimental.constrained.fma.v16f16(<16 x half>, <16 x half>, <16 x half>, metadata, metadata)

define <16 x half> @vfnmsub_vv_v16f16(<16 x half> %va, <16 x half> %vb, <16 x half> %vc) {
define <16 x half> @vfnmsub_vv_v16f16(<16 x half> %va, <16 x half> %vb, <16 x half> %vc) strictfp {
; CHECK-LABEL: vfnmsub_vv_v16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
Expand All @@ -98,7 +98,7 @@ define <16 x half> @vfnmsub_vv_v16f16(<16 x half> %va, <16 x half> %vb, <16 x ha
ret <16 x half> %vd
}

define <16 x half> @vfnmsub_vf_v16f16(<16 x half> %va, <16 x half> %vb, half %c) {
define <16 x half> @vfnmsub_vf_v16f16(<16 x half> %va, <16 x half> %vb, half %c) strictfp {
; CHECK-LABEL: vfnmsub_vf_v16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
Expand All @@ -113,7 +113,7 @@ define <16 x half> @vfnmsub_vf_v16f16(<16 x half> %va, <16 x half> %vb, half %c)

declare <32 x half> @llvm.experimental.constrained.fma.v32f16(<32 x half>, <32 x half>, <32 x half>, metadata, metadata)

define <32 x half> @vfnmsub_vv_v32f16(<32 x half> %va, <32 x half> %vb, <32 x half> %vc) {
define <32 x half> @vfnmsub_vv_v32f16(<32 x half> %va, <32 x half> %vb, <32 x half> %vc) strictfp {
; CHECK-LABEL: vfnmsub_vv_v32f16:
; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 32
Expand All @@ -125,7 +125,7 @@ define <32 x half> @vfnmsub_vv_v32f16(<32 x half> %va, <32 x half> %vb, <32 x ha
ret <32 x half> %vd
}

define <32 x half> @vfnmsub_vf_v32f16(<32 x half> %va, <32 x half> %vb, half %c) {
define <32 x half> @vfnmsub_vf_v32f16(<32 x half> %va, <32 x half> %vb, half %c) strictfp {
; CHECK-LABEL: vfnmsub_vf_v32f16:
; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 32
Expand All @@ -141,7 +141,7 @@ define <32 x half> @vfnmsub_vf_v32f16(<32 x half> %va, <32 x half> %vb, half %c)

declare <2 x float> @llvm.experimental.constrained.fma.v2f32(<2 x float>, <2 x float>, <2 x float>, metadata, metadata)

define <2 x float> @vfnmsub_vv_v2f32(<2 x float> %va, <2 x float> %vb, <2 x float> %vc) {
define <2 x float> @vfnmsub_vv_v2f32(<2 x float> %va, <2 x float> %vb, <2 x float> %vc) strictfp {
; CHECK-LABEL: vfnmsub_vv_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
Expand All @@ -152,7 +152,7 @@ define <2 x float> @vfnmsub_vv_v2f32(<2 x float> %va, <2 x float> %vb, <2 x floa
ret <2 x float> %vd
}

define <2 x float> @vfnmsub_vf_v2f32(<2 x float> %va, <2 x float> %vb, float %c) {
define <2 x float> @vfnmsub_vf_v2f32(<2 x float> %va, <2 x float> %vb, float %c) strictfp {
; CHECK-LABEL: vfnmsub_vf_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
Expand All @@ -167,7 +167,7 @@ define <2 x float> @vfnmsub_vf_v2f32(<2 x float> %va, <2 x float> %vb, float %c)

declare <4 x float> @llvm.experimental.constrained.fma.v4f32(<4 x float>, <4 x float>, <4 x float>, metadata, metadata)

define <4 x float> @vfnmsub_vv_v4f32(<4 x float> %va, <4 x float> %vb, <4 x float> %vc) {
define <4 x float> @vfnmsub_vv_v4f32(<4 x float> %va, <4 x float> %vb, <4 x float> %vc) strictfp {
; CHECK-LABEL: vfnmsub_vv_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
Expand All @@ -178,7 +178,7 @@ define <4 x float> @vfnmsub_vv_v4f32(<4 x float> %va, <4 x float> %vb, <4 x floa
ret <4 x float> %vd
}

define <4 x float> @vfnmsub_vf_v4f32(<4 x float> %va, <4 x float> %vb, float %c) {
define <4 x float> @vfnmsub_vf_v4f32(<4 x float> %va, <4 x float> %vb, float %c) strictfp {
; CHECK-LABEL: vfnmsub_vf_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
Expand All @@ -193,7 +193,7 @@ define <4 x float> @vfnmsub_vf_v4f32(<4 x float> %va, <4 x float> %vb, float %c)

declare <8 x float> @llvm.experimental.constrained.fma.v8f32(<8 x float>, <8 x float>, <8 x float>, metadata, metadata)

define <8 x float> @vfnmsub_vv_v8f32(<8 x float> %va, <8 x float> %vb, <8 x float> %vc) {
define <8 x float> @vfnmsub_vv_v8f32(<8 x float> %va, <8 x float> %vb, <8 x float> %vc) strictfp {
; CHECK-LABEL: vfnmsub_vv_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
Expand All @@ -204,7 +204,7 @@ define <8 x float> @vfnmsub_vv_v8f32(<8 x float> %va, <8 x float> %vb, <8 x floa
ret <8 x float> %vd
}

define <8 x float> @vfnmsub_vf_v8f32(<8 x float> %va, <8 x float> %vb, float %c) {
define <8 x float> @vfnmsub_vf_v8f32(<8 x float> %va, <8 x float> %vb, float %c) strictfp {
; CHECK-LABEL: vfnmsub_vf_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
Expand All @@ -219,7 +219,7 @@ define <8 x float> @vfnmsub_vf_v8f32(<8 x float> %va, <8 x float> %vb, float %c)

declare <16 x float> @llvm.experimental.constrained.fma.v16f32(<16 x float>, <16 x float>, <16 x float>, metadata, metadata)

define <16 x float> @vfnmsub_vv_v16f32(<16 x float> %va, <16 x float> %vb, <16 x float> %vc) {
define <16 x float> @vfnmsub_vv_v16f32(<16 x float> %va, <16 x float> %vb, <16 x float> %vc) strictfp {
; CHECK-LABEL: vfnmsub_vv_v16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
Expand All @@ -230,7 +230,7 @@ define <16 x float> @vfnmsub_vv_v16f32(<16 x float> %va, <16 x float> %vb, <16 x
ret <16 x float> %vd
}

define <16 x float> @vfnmsub_vf_v16f32(<16 x float> %va, <16 x float> %vb, float %c) {
define <16 x float> @vfnmsub_vf_v16f32(<16 x float> %va, <16 x float> %vb, float %c) strictfp {
; CHECK-LABEL: vfnmsub_vf_v16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
Expand All @@ -245,7 +245,7 @@ define <16 x float> @vfnmsub_vf_v16f32(<16 x float> %va, <16 x float> %vb, float

declare <2 x double> @llvm.experimental.constrained.fma.v2f64(<2 x double>, <2 x double>, <2 x double>, metadata, metadata)

define <2 x double> @vfnmsub_vv_v2f64(<2 x double> %va, <2 x double> %vb, <2 x double> %vc) {
define <2 x double> @vfnmsub_vv_v2f64(<2 x double> %va, <2 x double> %vb, <2 x double> %vc) strictfp {
; CHECK-LABEL: vfnmsub_vv_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
Expand All @@ -256,7 +256,7 @@ define <2 x double> @vfnmsub_vv_v2f64(<2 x double> %va, <2 x double> %vb, <2 x d
ret <2 x double> %vd
}

define <2 x double> @vfnmsub_vf_v2f64(<2 x double> %va, <2 x double> %vb, double %c) {
define <2 x double> @vfnmsub_vf_v2f64(<2 x double> %va, <2 x double> %vb, double %c) strictfp {
; CHECK-LABEL: vfnmsub_vf_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
Expand All @@ -271,7 +271,7 @@ define <2 x double> @vfnmsub_vf_v2f64(<2 x double> %va, <2 x double> %vb, double

declare <4 x double> @llvm.experimental.constrained.fma.v4f64(<4 x double>, <4 x double>, <4 x double>, metadata, metadata)

define <4 x double> @vfnmsub_vv_v4f64(<4 x double> %va, <4 x double> %vb, <4 x double> %vc) {
define <4 x double> @vfnmsub_vv_v4f64(<4 x double> %va, <4 x double> %vb, <4 x double> %vc) strictfp {
; CHECK-LABEL: vfnmsub_vv_v4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
Expand All @@ -282,7 +282,7 @@ define <4 x double> @vfnmsub_vv_v4f64(<4 x double> %va, <4 x double> %vb, <4 x d
ret <4 x double> %vd
}

define <4 x double> @vfnmsub_vf_v4f64(<4 x double> %va, <4 x double> %vb, double %c) {
define <4 x double> @vfnmsub_vf_v4f64(<4 x double> %va, <4 x double> %vb, double %c) strictfp {
; CHECK-LABEL: vfnmsub_vf_v4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
Expand All @@ -297,7 +297,7 @@ define <4 x double> @vfnmsub_vf_v4f64(<4 x double> %va, <4 x double> %vb, double

declare <8 x double> @llvm.experimental.constrained.fma.v8f64(<8 x double>, <8 x double>, <8 x double>, metadata, metadata)

define <8 x double> @vfnmsub_vv_v8f64(<8 x double> %va, <8 x double> %vb, <8 x double> %vc) {
define <8 x double> @vfnmsub_vv_v8f64(<8 x double> %va, <8 x double> %vb, <8 x double> %vc) strictfp {
; CHECK-LABEL: vfnmsub_vv_v8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
Expand All @@ -308,7 +308,7 @@ define <8 x double> @vfnmsub_vv_v8f64(<8 x double> %va, <8 x double> %vb, <8 x d
ret <8 x double> %vd
}

define <8 x double> @vfnmsub_vf_v8f64(<8 x double> %va, <8 x double> %vb, double %c) {
define <8 x double> @vfnmsub_vf_v8f64(<8 x double> %va, <8 x double> %vb, double %c) strictfp {
; CHECK-LABEL: vfnmsub_vf_v8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
Expand Down
18 changes: 9 additions & 9 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfpext-constrained-sdnode.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
; RUN: -verify-machineinstrs < %s | FileCheck %s

declare <2 x float> @llvm.experimental.constrained.fpext.v2f32.v2f16(<2 x half>, metadata)
define <2 x float> @vfpext_v2f16_v2f32(<2 x half> %va) {
define <2 x float> @vfpext_v2f16_v2f32(<2 x half> %va) strictfp {
; CHECK-LABEL: vfpext_v2f16_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
Expand All @@ -17,7 +17,7 @@ define <2 x float> @vfpext_v2f16_v2f32(<2 x half> %va) {
}

declare <2 x double> @llvm.experimental.constrained.fpext.v2f64.v2f16(<2 x half>, metadata)
define <2 x double> @vfpext_v2f16_v2f64(<2 x half> %va) {
define <2 x double> @vfpext_v2f16_v2f64(<2 x half> %va) strictfp {
; CHECK-LABEL: vfpext_v2f16_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
Expand All @@ -30,7 +30,7 @@ define <2 x double> @vfpext_v2f16_v2f64(<2 x half> %va) {
}

declare <4 x float> @llvm.experimental.constrained.fpext.v4f32.v4f16(<4 x half>, metadata)
define <4 x float> @vfpext_v4f16_v4f32(<4 x half> %va) {
define <4 x float> @vfpext_v4f16_v4f32(<4 x half> %va) strictfp {
; CHECK-LABEL: vfpext_v4f16_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
Expand All @@ -42,7 +42,7 @@ define <4 x float> @vfpext_v4f16_v4f32(<4 x half> %va) {
}

declare <4 x double> @llvm.experimental.constrained.fpext.v4f64.v4f16(<4 x half>, metadata)
define <4 x double> @vfpext_v4f16_v4f64(<4 x half> %va) {
define <4 x double> @vfpext_v4f16_v4f64(<4 x half> %va) strictfp {
; CHECK-LABEL: vfpext_v4f16_v4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
Expand All @@ -55,7 +55,7 @@ define <4 x double> @vfpext_v4f16_v4f64(<4 x half> %va) {
}

declare <8 x float> @llvm.experimental.constrained.fpext.v8f32.v8f16(<8 x half>, metadata)
define <8 x float> @vfpext_v8f16_v8f32(<8 x half> %va) {
define <8 x float> @vfpext_v8f16_v8f32(<8 x half> %va) strictfp {
; CHECK-LABEL: vfpext_v8f16_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
Expand All @@ -67,7 +67,7 @@ define <8 x float> @vfpext_v8f16_v8f32(<8 x half> %va) {
}

declare <8 x double> @llvm.experimental.constrained.fpext.v8f64.v8f16(<8 x half>, metadata)
define <8 x double> @vfpext_v8f16_v8f64(<8 x half> %va) {
define <8 x double> @vfpext_v8f16_v8f64(<8 x half> %va) strictfp {
; CHECK-LABEL: vfpext_v8f16_v8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
Expand All @@ -80,7 +80,7 @@ define <8 x double> @vfpext_v8f16_v8f64(<8 x half> %va) {
}

declare <2 x double> @llvm.experimental.constrained.fpext.v2f64.v2f32(<2 x float>, metadata)
define <2 x double> @vfpext_v2f32_v2f64(<2 x float> %va) {
define <2 x double> @vfpext_v2f32_v2f64(<2 x float> %va) strictfp {
; CHECK-LABEL: vfpext_v2f32_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
Expand All @@ -92,7 +92,7 @@ define <2 x double> @vfpext_v2f32_v2f64(<2 x float> %va) {
}

declare <4 x double> @llvm.experimental.constrained.fpext.v4f64.v4f32(<4 x float>, metadata)
define <4 x double> @vfpext_v4f32_v4f64(<4 x float> %va) {
define <4 x double> @vfpext_v4f32_v4f64(<4 x float> %va) strictfp {
; CHECK-LABEL: vfpext_v4f32_v4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
Expand All @@ -104,7 +104,7 @@ define <4 x double> @vfpext_v4f32_v4f64(<4 x float> %va) {
}

declare <8 x double> @llvm.experimental.constrained.fpext.v8f64.v8f32(<8 x float>, metadata)
define <8 x double> @vfpext_v8f32_v8f64(<8 x float> %va) {
define <8 x double> @vfpext_v8f32_v8f64(<8 x float> %va) strictfp {
; CHECK-LABEL: vfpext_v8f32_v8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
Expand Down
288 changes: 144 additions & 144 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptoi-constrained-sdnode.ll
View file

Large diffs are not rendered by default.

18 changes: 9 additions & 9 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptrunc-constrained-sdnode.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
; RUN: -verify-machineinstrs < %s | FileCheck %s

declare <2 x float> @llvm.experimental.constrained.fptrunc.v2f32.v2f64(<2 x double>, metadata, metadata)
define <2 x float> @vfptrunc_v2f64_v2f32(<2 x double> %va) {
define <2 x float> @vfptrunc_v2f64_v2f32(<2 x double> %va) strictfp {
; CHECK-LABEL: vfptrunc_v2f64_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
Expand All @@ -17,7 +17,7 @@ define <2 x float> @vfptrunc_v2f64_v2f32(<2 x double> %va) {
}

declare <2 x half> @llvm.experimental.constrained.fptrunc.v2f16.v2f64(<2 x double>, metadata, metadata)
define <2 x half> @vfptrunc_v2f64_v2f16(<2 x double> %va) {
define <2 x half> @vfptrunc_v2f64_v2f16(<2 x double> %va) strictfp {
; CHECK-LABEL: vfptrunc_v2f64_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
Expand All @@ -30,7 +30,7 @@ define <2 x half> @vfptrunc_v2f64_v2f16(<2 x double> %va) {
}

declare <2 x half> @llvm.experimental.constrained.fptrunc.v2f16.v2f32(<2 x float>, metadata, metadata)
define <2 x half> @vfptrunc_v2f32_v2f16(<2 x float> %va) {
define <2 x half> @vfptrunc_v2f32_v2f16(<2 x float> %va) strictfp {
; CHECK-LABEL: vfptrunc_v2f32_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
Expand All @@ -42,7 +42,7 @@ define <2 x half> @vfptrunc_v2f32_v2f16(<2 x float> %va) {
}

declare <4 x float> @llvm.experimental.constrained.fptrunc.v4f32.v4f64(<4 x double>, metadata, metadata)
define <4 x float> @vfptrunc_v4f64_v4f32(<4 x double> %va) {
define <4 x float> @vfptrunc_v4f64_v4f32(<4 x double> %va) strictfp {
; CHECK-LABEL: vfptrunc_v4f64_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
Expand All @@ -54,7 +54,7 @@ define <4 x float> @vfptrunc_v4f64_v4f32(<4 x double> %va) {
}

declare <4 x half> @llvm.experimental.constrained.fptrunc.v4f16.v4f64(<4 x double>, metadata, metadata)
define <4 x half> @vfptrunc_v4f64_v4f16(<4 x double> %va) {
define <4 x half> @vfptrunc_v4f64_v4f16(<4 x double> %va) strictfp {
; CHECK-LABEL: vfptrunc_v4f64_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
Expand All @@ -67,7 +67,7 @@ define <4 x half> @vfptrunc_v4f64_v4f16(<4 x double> %va) {
}

declare <4 x half> @llvm.experimental.constrained.fptrunc.v4f16.v4f32(<4 x float>, metadata, metadata)
define <4 x half> @vfptrunc_v4f32_v4f16(<4 x float> %va) {
define <4 x half> @vfptrunc_v4f32_v4f16(<4 x float> %va) strictfp {
; CHECK-LABEL: vfptrunc_v4f32_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
Expand All @@ -79,7 +79,7 @@ define <4 x half> @vfptrunc_v4f32_v4f16(<4 x float> %va) {
}

declare <8 x float> @llvm.experimental.constrained.fptrunc.v8f32.v8f64(<8 x double>, metadata, metadata)
define <8 x float> @vfptrunc_v8f64_v8f32(<8 x double> %va) {
define <8 x float> @vfptrunc_v8f64_v8f32(<8 x double> %va) strictfp {
; CHECK-LABEL: vfptrunc_v8f64_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
Expand All @@ -91,7 +91,7 @@ define <8 x float> @vfptrunc_v8f64_v8f32(<8 x double> %va) {
}

declare <8 x half> @llvm.experimental.constrained.fptrunc.v8f16.v8f64(<8 x double>, metadata, metadata)
define <8 x half> @vfptrunc_v8f64_v8f16(<8 x double> %va) {
define <8 x half> @vfptrunc_v8f64_v8f16(<8 x double> %va) strictfp {
; CHECK-LABEL: vfptrunc_v8f64_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
Expand All @@ -104,7 +104,7 @@ define <8 x half> @vfptrunc_v8f64_v8f16(<8 x double> %va) {
}

declare <8 x half> @llvm.experimental.constrained.fptrunc.v8f16.v8f32(<8 x float>, metadata, metadata)
define <8 x half> @vfptrunc_v8f32_v8f16(<8 x float> %va) {
define <8 x half> @vfptrunc_v8f32_v8f16(<8 x float> %va) strictfp {
; CHECK-LABEL: vfptrunc_v8f32_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
Expand Down
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-constrained-sdnode.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@

declare <2 x half> @llvm.experimental.constrained.sqrt.v2f16(<2 x half>, metadata, metadata)

define <2 x half> @vfsqrt_v2f16(<2 x half> %v) {
define <2 x half> @vfsqrt_v2f16(<2 x half> %v) strictfp {
; CHECK-LABEL: vfsqrt_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
Expand All @@ -18,7 +18,7 @@ define <2 x half> @vfsqrt_v2f16(<2 x half> %v) {

declare <4 x half> @llvm.experimental.constrained.sqrt.v4f16(<4 x half>, metadata, metadata)

define <4 x half> @vfsqrt_v4f16(<4 x half> %v) {
define <4 x half> @vfsqrt_v4f16(<4 x half> %v) strictfp {
; CHECK-LABEL: vfsqrt_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
Expand All @@ -30,7 +30,7 @@ define <4 x half> @vfsqrt_v4f16(<4 x half> %v) {

declare <8 x half> @llvm.experimental.constrained.sqrt.v8f16(<8 x half>, metadata, metadata)

define <8 x half> @vfsqrt_v8f16(<8 x half> %v) {
define <8 x half> @vfsqrt_v8f16(<8 x half> %v) strictfp {
; CHECK-LABEL: vfsqrt_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
Expand All @@ -42,7 +42,7 @@ define <8 x half> @vfsqrt_v8f16(<8 x half> %v) {

declare <16 x half> @llvm.experimental.constrained.sqrt.v16f16(<16 x half>, metadata, metadata)

define <16 x half> @vfsqrt_v16f16(<16 x half> %v) {
define <16 x half> @vfsqrt_v16f16(<16 x half> %v) strictfp {
; CHECK-LABEL: vfsqrt_v16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
Expand All @@ -54,7 +54,7 @@ define <16 x half> @vfsqrt_v16f16(<16 x half> %v) {

declare <32 x half> @llvm.experimental.constrained.sqrt.v32f16(<32 x half>, metadata, metadata)

define <32 x half> @vfsqrt_v32f16(<32 x half> %v) {
define <32 x half> @vfsqrt_v32f16(<32 x half> %v) strictfp {
; CHECK-LABEL: vfsqrt_v32f16:
; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 32
Expand All @@ -67,7 +67,7 @@ define <32 x half> @vfsqrt_v32f16(<32 x half> %v) {

declare <2 x float> @llvm.experimental.constrained.sqrt.v2f32(<2 x float>, metadata, metadata)

define <2 x float> @vfsqrt_v2f32(<2 x float> %v) {
define <2 x float> @vfsqrt_v2f32(<2 x float> %v) strictfp {
; CHECK-LABEL: vfsqrt_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
Expand All @@ -79,7 +79,7 @@ define <2 x float> @vfsqrt_v2f32(<2 x float> %v) {

declare <4 x float> @llvm.experimental.constrained.sqrt.v4f32(<4 x float>, metadata, metadata)

define <4 x float> @vfsqrt_v4f32(<4 x float> %v) {
define <4 x float> @vfsqrt_v4f32(<4 x float> %v) strictfp {
; CHECK-LABEL: vfsqrt_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
Expand All @@ -91,7 +91,7 @@ define <4 x float> @vfsqrt_v4f32(<4 x float> %v) {

declare <8 x float> @llvm.experimental.constrained.sqrt.v8f32(<8 x float>, metadata, metadata)

define <8 x float> @vfsqrt_v8f32(<8 x float> %v) {
define <8 x float> @vfsqrt_v8f32(<8 x float> %v) strictfp {
; CHECK-LABEL: vfsqrt_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
Expand All @@ -103,7 +103,7 @@ define <8 x float> @vfsqrt_v8f32(<8 x float> %v) {

declare <16 x float> @llvm.experimental.constrained.sqrt.v16f32(<16 x float>, metadata, metadata)

define <16 x float> @vfsqrt_v16f32(<16 x float> %v) {
define <16 x float> @vfsqrt_v16f32(<16 x float> %v) strictfp {
; CHECK-LABEL: vfsqrt_v16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
Expand All @@ -115,7 +115,7 @@ define <16 x float> @vfsqrt_v16f32(<16 x float> %v) {

declare <2 x double> @llvm.experimental.constrained.sqrt.v2f64(<2 x double>, metadata, metadata)

define <2 x double> @vfsqrt_v2f64(<2 x double> %v) {
define <2 x double> @vfsqrt_v2f64(<2 x double> %v) strictfp {
; CHECK-LABEL: vfsqrt_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
Expand All @@ -127,7 +127,7 @@ define <2 x double> @vfsqrt_v2f64(<2 x double> %v) {

declare <4 x double> @llvm.experimental.constrained.sqrt.v4f64(<4 x double>, metadata, metadata)

define <4 x double> @vfsqrt_v4f64(<4 x double> %v) {
define <4 x double> @vfsqrt_v4f64(<4 x double> %v) strictfp {
; CHECK-LABEL: vfsqrt_v4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
Expand All @@ -139,7 +139,7 @@ define <4 x double> @vfsqrt_v4f64(<4 x double> %v) {

declare <8 x double> @llvm.experimental.constrained.sqrt.v8f64(<8 x double>, metadata, metadata)

define <8 x double> @vfsqrt_v8f64(<8 x double> %v) {
define <8 x double> @vfsqrt_v8f64(<8 x double> %v) strictfp {
; CHECK-LABEL: vfsqrt_v8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
Expand Down
54 changes: 27 additions & 27 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-constrained-sdnode.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
; RUN: -verify-machineinstrs < %s | FileCheck %s

declare <2 x half> @llvm.experimental.constrained.fsub.v2f16(<2 x half>, <2 x half>, metadata, metadata)
define <2 x half> @vfsub_vv_v2f16(<2 x half> %va, <2 x half> %vb) {
define <2 x half> @vfsub_vv_v2f16(<2 x half> %va, <2 x half> %vb) strictfp {
; CHECK-LABEL: vfsub_vv_v2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
Expand All @@ -16,7 +16,7 @@ entry:
ret <2 x half> %vc
}

define <2 x half> @vfsub_vf_v2f16(<2 x half> %va, half %b) {
define <2 x half> @vfsub_vf_v2f16(<2 x half> %va, half %b) strictfp {
; CHECK-LABEL: vfsub_vf_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
Expand All @@ -29,7 +29,7 @@ define <2 x half> @vfsub_vf_v2f16(<2 x half> %va, half %b) {
}

declare <4 x half> @llvm.experimental.constrained.fsub.v4f16(<4 x half>, <4 x half>, metadata, metadata)
define <4 x half> @vfsub_vv_v4f16(<4 x half> %va, <4 x half> %vb) {
define <4 x half> @vfsub_vv_v4f16(<4 x half> %va, <4 x half> %vb) strictfp {
; CHECK-LABEL: vfsub_vv_v4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
Expand All @@ -40,7 +40,7 @@ entry:
ret <4 x half> %vc
}

define <4 x half> @vfsub_vf_v4f16(<4 x half> %va, half %b) {
define <4 x half> @vfsub_vf_v4f16(<4 x half> %va, half %b) strictfp {
; CHECK-LABEL: vfsub_vf_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
Expand All @@ -53,7 +53,7 @@ define <4 x half> @vfsub_vf_v4f16(<4 x half> %va, half %b) {
}

declare <8 x half> @llvm.experimental.constrained.fsub.v8f16(<8 x half>, <8 x half>, metadata, metadata)
define <8 x half> @vfsub_vv_v8f16(<8 x half> %va, <8 x half> %vb) {
define <8 x half> @vfsub_vv_v8f16(<8 x half> %va, <8 x half> %vb) strictfp {
; CHECK-LABEL: vfsub_vv_v8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
Expand All @@ -64,7 +64,7 @@ entry:
ret <8 x half> %vc
}

define <8 x half> @vfsub_vf_v8f16(<8 x half> %va, half %b) {
define <8 x half> @vfsub_vf_v8f16(<8 x half> %va, half %b) strictfp {
; CHECK-LABEL: vfsub_vf_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
Expand All @@ -76,7 +76,7 @@ define <8 x half> @vfsub_vf_v8f16(<8 x half> %va, half %b) {
ret <8 x half> %vc
}

define <8 x half> @vfsub_fv_v8f16(<8 x half> %va, half %b) {
define <8 x half> @vfsub_fv_v8f16(<8 x half> %va, half %b) strictfp {
; CHECK-LABEL: vfsub_fv_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
Expand All @@ -89,7 +89,7 @@ define <8 x half> @vfsub_fv_v8f16(<8 x half> %va, half %b) {
}

declare <16 x half> @llvm.experimental.constrained.fsub.v16f16(<16 x half>, <16 x half>, metadata, metadata)
define <16 x half> @vfsub_vv_v16f16(<16 x half> %va, <16 x half> %vb) {
define <16 x half> @vfsub_vv_v16f16(<16 x half> %va, <16 x half> %vb) strictfp {
; CHECK-LABEL: vfsub_vv_v16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
Expand All @@ -100,7 +100,7 @@ entry:
ret <16 x half> %vc
}

define <16 x half> @vfsub_vf_v16f16(<16 x half> %va, half %b) {
define <16 x half> @vfsub_vf_v16f16(<16 x half> %va, half %b) strictfp {
; CHECK-LABEL: vfsub_vf_v16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
Expand All @@ -113,7 +113,7 @@ define <16 x half> @vfsub_vf_v16f16(<16 x half> %va, half %b) {
}

declare <32 x half> @llvm.experimental.constrained.fsub.v32f16(<32 x half>, <32 x half>, metadata, metadata)
define <32 x half> @vfsub_vv_v32f16(<32 x half> %va, <32 x half> %vb) {
define <32 x half> @vfsub_vv_v32f16(<32 x half> %va, <32 x half> %vb) strictfp {
; CHECK-LABEL: vfsub_vv_v32f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li a0, 32
Expand All @@ -125,7 +125,7 @@ entry:
ret <32 x half> %vc
}

define <32 x half> @vfsub_vf_v32f16(<32 x half> %va, half %b) {
define <32 x half> @vfsub_vf_v32f16(<32 x half> %va, half %b) strictfp {
; CHECK-LABEL: vfsub_vf_v32f16:
; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 32
Expand All @@ -139,7 +139,7 @@ define <32 x half> @vfsub_vf_v32f16(<32 x half> %va, half %b) {
}

declare <2 x float> @llvm.experimental.constrained.fsub.v2f32(<2 x float>, <2 x float>, metadata, metadata)
define <2 x float> @vfsub_vv_v2f32(<2 x float> %va, <2 x float> %vb) {
define <2 x float> @vfsub_vv_v2f32(<2 x float> %va, <2 x float> %vb) strictfp {
; CHECK-LABEL: vfsub_vv_v2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
Expand All @@ -150,7 +150,7 @@ entry:
ret <2 x float> %vc
}

define <2 x float> @vfsub_vf_v2f32(<2 x float> %va, float %b) {
define <2 x float> @vfsub_vf_v2f32(<2 x float> %va, float %b) strictfp {
; CHECK-LABEL: vfsub_vf_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
Expand All @@ -163,7 +163,7 @@ define <2 x float> @vfsub_vf_v2f32(<2 x float> %va, float %b) {
}

declare <4 x float> @llvm.experimental.constrained.fsub.v4f32(<4 x float>, <4 x float>, metadata, metadata)
define <4 x float> @vfsub_vv_v4f32(<4 x float> %va, <4 x float> %vb) {
define <4 x float> @vfsub_vv_v4f32(<4 x float> %va, <4 x float> %vb) strictfp {
; CHECK-LABEL: vfsub_vv_v4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
Expand All @@ -174,7 +174,7 @@ entry:
ret <4 x float> %vc
}

define <4 x float> @vfsub_vf_v4f32(<4 x float> %va, float %b) {
define <4 x float> @vfsub_vf_v4f32(<4 x float> %va, float %b) strictfp {
; CHECK-LABEL: vfsub_vf_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
Expand All @@ -187,7 +187,7 @@ define <4 x float> @vfsub_vf_v4f32(<4 x float> %va, float %b) {
}

declare <8 x float> @llvm.experimental.constrained.fsub.v8f32(<8 x float>, <8 x float>, metadata, metadata)
define <8 x float> @vfsub_vv_v8f32(<8 x float> %va, <8 x float> %vb) {
define <8 x float> @vfsub_vv_v8f32(<8 x float> %va, <8 x float> %vb) strictfp {
; CHECK-LABEL: vfsub_vv_v8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
Expand All @@ -198,7 +198,7 @@ entry:
ret <8 x float> %vc
}

define <8 x float> @vfsub_vf_v8f32(<8 x float> %va, float %b) {
define <8 x float> @vfsub_vf_v8f32(<8 x float> %va, float %b) strictfp {
; CHECK-LABEL: vfsub_vf_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
Expand All @@ -210,7 +210,7 @@ define <8 x float> @vfsub_vf_v8f32(<8 x float> %va, float %b) {
ret <8 x float> %vc
}

define <8 x float> @vfsub_fv_v8f32(<8 x float> %va, float %b) {
define <8 x float> @vfsub_fv_v8f32(<8 x float> %va, float %b) strictfp {
; CHECK-LABEL: vfsub_fv_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
Expand All @@ -223,7 +223,7 @@ define <8 x float> @vfsub_fv_v8f32(<8 x float> %va, float %b) {
}

declare <16 x float> @llvm.experimental.constrained.fsub.v16f32(<16 x float>, <16 x float>, metadata, metadata)
define <16 x float> @vfsub_vv_v16f32(<16 x float> %va, <16 x float> %vb) {
define <16 x float> @vfsub_vv_v16f32(<16 x float> %va, <16 x float> %vb) strictfp {
; CHECK-LABEL: vfsub_vv_v16f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
Expand All @@ -234,7 +234,7 @@ entry:
ret <16 x float> %vc
}

define <16 x float> @vfsub_vf_v16f32(<16 x float> %va, float %b) {
define <16 x float> @vfsub_vf_v16f32(<16 x float> %va, float %b) strictfp {
; CHECK-LABEL: vfsub_vf_v16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
Expand All @@ -247,7 +247,7 @@ define <16 x float> @vfsub_vf_v16f32(<16 x float> %va, float %b) {
}

declare <2 x double> @llvm.experimental.constrained.fsub.v2f64(<2 x double>, <2 x double>, metadata, metadata)
define <2 x double> @vfsub_vv_v2f64(<2 x double> %va, <2 x double> %vb) {
define <2 x double> @vfsub_vv_v2f64(<2 x double> %va, <2 x double> %vb) strictfp {
; CHECK-LABEL: vfsub_vv_v2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
Expand All @@ -258,7 +258,7 @@ entry:
ret <2 x double> %vc
}

define <2 x double> @vfsub_vf_v2f64(<2 x double> %va, double %b) {
define <2 x double> @vfsub_vf_v2f64(<2 x double> %va, double %b) strictfp {
; CHECK-LABEL: vfsub_vf_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
Expand All @@ -271,7 +271,7 @@ define <2 x double> @vfsub_vf_v2f64(<2 x double> %va, double %b) {
}

declare <4 x double> @llvm.experimental.constrained.fsub.v4f64(<4 x double>, <4 x double>, metadata, metadata)
define <4 x double> @vfsub_vv_v4f64(<4 x double> %va, <4 x double> %vb) {
define <4 x double> @vfsub_vv_v4f64(<4 x double> %va, <4 x double> %vb) strictfp {
; CHECK-LABEL: vfsub_vv_v4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
Expand All @@ -282,7 +282,7 @@ entry:
ret <4 x double> %vc
}

define <4 x double> @vfsub_vf_v4f64(<4 x double> %va, double %b) {
define <4 x double> @vfsub_vf_v4f64(<4 x double> %va, double %b) strictfp {
; CHECK-LABEL: vfsub_vf_v4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
Expand All @@ -295,7 +295,7 @@ define <4 x double> @vfsub_vf_v4f64(<4 x double> %va, double %b) {
}

declare <8 x double> @llvm.experimental.constrained.fsub.v8f64(<8 x double>, <8 x double>, metadata, metadata)
define <8 x double> @vfsub_vv_v8f64(<8 x double> %va, <8 x double> %vb) {
define <8 x double> @vfsub_vv_v8f64(<8 x double> %va, <8 x double> %vb) strictfp {
; CHECK-LABEL: vfsub_vv_v8f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
Expand All @@ -306,7 +306,7 @@ entry:
ret <8 x double> %vc
}

define <8 x double> @vfsub_vf_v8f64(<8 x double> %va, double %b) {
define <8 x double> @vfsub_vf_v8f64(<8 x double> %va, double %b) strictfp {
; CHECK-LABEL: vfsub_vf_v8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
Expand All @@ -318,7 +318,7 @@ define <8 x double> @vfsub_vf_v8f64(<8 x double> %va, double %b) {
ret <8 x double> %vc
}

define <8 x double> @vfsub_fv_v8f64(<8 x double> %va, double %b) {
define <8 x double> @vfsub_fv_v8f64(<8 x double> %va, double %b) strictfp {
; CHECK-LABEL: vfsub_fv_v8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
Expand Down
288 changes: 144 additions & 144 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vitofp-constrained-sdnode.ll
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Large diffs are not rendered by default.

30 changes: 15 additions & 15 deletions llvm/test/CodeGen/RISCV/rvv/fnearbyint-constrained-sdnode.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@

declare <vscale x 1 x half> @llvm.experimental.constrained.nearbyint.nxv1f16(<vscale x 1 x half>, metadata, metadata)

define <vscale x 1 x half> @nearbyint_nxv1f16(<vscale x 1 x half> %v) {
define <vscale x 1 x half> @nearbyint_nxv1f16(<vscale x 1 x half> %v) strictfp {
; CHECK-LABEL: nearbyint_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
Expand All @@ -29,7 +29,7 @@ define <vscale x 1 x half> @nearbyint_nxv1f16(<vscale x 1 x half> %v) {

declare <vscale x 2 x half> @llvm.experimental.constrained.nearbyint.nxv2f16(<vscale x 2 x half>, metadata, metadata)

define <vscale x 2 x half> @nearbyint_nxv2f16(<vscale x 2 x half> %v) {
define <vscale x 2 x half> @nearbyint_nxv2f16(<vscale x 2 x half> %v) strictfp {
; CHECK-LABEL: nearbyint_nxv2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
Expand All @@ -52,7 +52,7 @@ define <vscale x 2 x half> @nearbyint_nxv2f16(<vscale x 2 x half> %v) {

declare <vscale x 4 x half> @llvm.experimental.constrained.nearbyint.nxv4f16(<vscale x 4 x half>, metadata, metadata)

define <vscale x 4 x half> @nearbyint_nxv4f16(<vscale x 4 x half> %v) {
define <vscale x 4 x half> @nearbyint_nxv4f16(<vscale x 4 x half> %v) strictfp {
; CHECK-LABEL: nearbyint_nxv4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
Expand All @@ -75,7 +75,7 @@ define <vscale x 4 x half> @nearbyint_nxv4f16(<vscale x 4 x half> %v) {

declare <vscale x 8 x half> @llvm.experimental.constrained.nearbyint.nxv8f16(<vscale x 8 x half>, metadata, metadata)

define <vscale x 8 x half> @nearbyint_nxv8f16(<vscale x 8 x half> %v) {
define <vscale x 8 x half> @nearbyint_nxv8f16(<vscale x 8 x half> %v) strictfp {
; CHECK-LABEL: nearbyint_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
Expand All @@ -98,7 +98,7 @@ define <vscale x 8 x half> @nearbyint_nxv8f16(<vscale x 8 x half> %v) {

declare <vscale x 16 x half> @llvm.experimental.constrained.nearbyint.nxv16f16(<vscale x 16 x half>, metadata, metadata)

define <vscale x 16 x half> @nearbyint_nxv16f16(<vscale x 16 x half> %v) {
define <vscale x 16 x half> @nearbyint_nxv16f16(<vscale x 16 x half> %v) strictfp {
; CHECK-LABEL: nearbyint_nxv16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
Expand All @@ -121,7 +121,7 @@ define <vscale x 16 x half> @nearbyint_nxv16f16(<vscale x 16 x half> %v) {

declare <vscale x 32 x half> @llvm.experimental.constrained.nearbyint.nxv32f16(<vscale x 32 x half>, metadata, metadata)

define <vscale x 32 x half> @nearbyint_nxv32f16(<vscale x 32 x half> %v) {
define <vscale x 32 x half> @nearbyint_nxv32f16(<vscale x 32 x half> %v) strictfp {
; CHECK-LABEL: nearbyint_nxv32f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
Expand All @@ -144,7 +144,7 @@ define <vscale x 32 x half> @nearbyint_nxv32f16(<vscale x 32 x half> %v) {

declare <vscale x 1 x float> @llvm.experimental.constrained.nearbyint.nxv1f32(<vscale x 1 x float>, metadata, metadata)

define <vscale x 1 x float> @nearbyint_nxv1f32(<vscale x 1 x float> %v) {
define <vscale x 1 x float> @nearbyint_nxv1f32(<vscale x 1 x float> %v) strictfp {
; CHECK-LABEL: nearbyint_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
Expand All @@ -167,7 +167,7 @@ define <vscale x 1 x float> @nearbyint_nxv1f32(<vscale x 1 x float> %v) {

declare <vscale x 2 x float> @llvm.experimental.constrained.nearbyint.nxv2f32(<vscale x 2 x float>, metadata, metadata)

define <vscale x 2 x float> @nearbyint_nxv2f32(<vscale x 2 x float> %v) {
define <vscale x 2 x float> @nearbyint_nxv2f32(<vscale x 2 x float> %v) strictfp {
; CHECK-LABEL: nearbyint_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
Expand All @@ -190,7 +190,7 @@ define <vscale x 2 x float> @nearbyint_nxv2f32(<vscale x 2 x float> %v) {

declare <vscale x 4 x float> @llvm.experimental.constrained.nearbyint.nxv4f32(<vscale x 4 x float>, metadata, metadata)

define <vscale x 4 x float> @nearbyint_nxv4f32(<vscale x 4 x float> %v) {
define <vscale x 4 x float> @nearbyint_nxv4f32(<vscale x 4 x float> %v) strictfp {
; CHECK-LABEL: nearbyint_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
Expand All @@ -213,7 +213,7 @@ define <vscale x 4 x float> @nearbyint_nxv4f32(<vscale x 4 x float> %v) {

declare <vscale x 8 x float> @llvm.experimental.constrained.nearbyint.nxv8f32(<vscale x 8 x float>, metadata, metadata)

define <vscale x 8 x float> @nearbyint_nxv8f32(<vscale x 8 x float> %v) {
define <vscale x 8 x float> @nearbyint_nxv8f32(<vscale x 8 x float> %v) strictfp {
; CHECK-LABEL: nearbyint_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
Expand All @@ -236,7 +236,7 @@ define <vscale x 8 x float> @nearbyint_nxv8f32(<vscale x 8 x float> %v) {

declare <vscale x 16 x float> @llvm.experimental.constrained.nearbyint.nxv16f32(<vscale x 16 x float>, metadata, metadata)

define <vscale x 16 x float> @nearbyint_nxv16f32(<vscale x 16 x float> %v) {
define <vscale x 16 x float> @nearbyint_nxv16f32(<vscale x 16 x float> %v) strictfp {
; CHECK-LABEL: nearbyint_nxv16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
Expand All @@ -259,7 +259,7 @@ define <vscale x 16 x float> @nearbyint_nxv16f32(<vscale x 16 x float> %v) {

declare <vscale x 1 x double> @llvm.experimental.constrained.nearbyint.nxv1f64(<vscale x 1 x double>, metadata, metadata)

define <vscale x 1 x double> @nearbyint_nxv1f64(<vscale x 1 x double> %v) {
define <vscale x 1 x double> @nearbyint_nxv1f64(<vscale x 1 x double> %v) strictfp {
; CHECK-LABEL: nearbyint_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
Expand All @@ -282,7 +282,7 @@ define <vscale x 1 x double> @nearbyint_nxv1f64(<vscale x 1 x double> %v) {

declare <vscale x 2 x double> @llvm.experimental.constrained.nearbyint.nxv2f64(<vscale x 2 x double>, metadata, metadata)

define <vscale x 2 x double> @nearbyint_nxv2f64(<vscale x 2 x double> %v) {
define <vscale x 2 x double> @nearbyint_nxv2f64(<vscale x 2 x double> %v) strictfp {
; CHECK-LABEL: nearbyint_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
Expand All @@ -305,7 +305,7 @@ define <vscale x 2 x double> @nearbyint_nxv2f64(<vscale x 2 x double> %v) {

declare <vscale x 4 x double> @llvm.experimental.constrained.nearbyint.nxv4f64(<vscale x 4 x double>, metadata, metadata)

define <vscale x 4 x double> @nearbyint_nxv4f64(<vscale x 4 x double> %v) {
define <vscale x 4 x double> @nearbyint_nxv4f64(<vscale x 4 x double> %v) strictfp {
; CHECK-LABEL: nearbyint_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
Expand All @@ -328,7 +328,7 @@ define <vscale x 4 x double> @nearbyint_nxv4f64(<vscale x 4 x double> %v) {

declare <vscale x 8 x double> @llvm.experimental.constrained.nearbyint.nxv8f64(<vscale x 8 x double>, metadata, metadata)

define <vscale x 8 x double> @nearbyint_nxv8f64(<vscale x 8 x double> %v) {
define <vscale x 8 x double> @nearbyint_nxv8f64(<vscale x 8 x double> %v) strictfp {
; CHECK-LABEL: nearbyint_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
Expand Down
30 changes: 15 additions & 15 deletions llvm/test/CodeGen/RISCV/rvv/fround-costrained-sdnode.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@

; This file tests the code generation for `llvm.experimental.constrained.round.*` on scalable vector type.

define <vscale x 1 x half> @round_nxv1f16(<vscale x 1 x half> %x) {
define <vscale x 1 x half> @round_nxv1f16(<vscale x 1 x half> %x) strictfp {
; CHECK-LABEL: round_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
Expand All @@ -28,7 +28,7 @@ define <vscale x 1 x half> @round_nxv1f16(<vscale x 1 x half> %x) {
}
declare <vscale x 1 x half> @llvm.experimental.constrained.round.nxv1f16(<vscale x 1 x half>, metadata)

define <vscale x 2 x half> @round_nxv2f16(<vscale x 2 x half> %x) {
define <vscale x 2 x half> @round_nxv2f16(<vscale x 2 x half> %x) strictfp {
; CHECK-LABEL: round_nxv2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
Expand All @@ -50,7 +50,7 @@ define <vscale x 2 x half> @round_nxv2f16(<vscale x 2 x half> %x) {
}
declare <vscale x 2 x half> @llvm.experimental.constrained.round.nxv2f16(<vscale x 2 x half>, metadata)

define <vscale x 4 x half> @round_nxv4f16(<vscale x 4 x half> %x) {
define <vscale x 4 x half> @round_nxv4f16(<vscale x 4 x half> %x) strictfp {
; CHECK-LABEL: round_nxv4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
Expand All @@ -72,7 +72,7 @@ define <vscale x 4 x half> @round_nxv4f16(<vscale x 4 x half> %x) {
}
declare <vscale x 4 x half> @llvm.experimental.constrained.round.nxv4f16(<vscale x 4 x half>, metadata)

define <vscale x 8 x half> @round_nxv8f16(<vscale x 8 x half> %x) {
define <vscale x 8 x half> @round_nxv8f16(<vscale x 8 x half> %x) strictfp {
; CHECK-LABEL: round_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
Expand All @@ -94,7 +94,7 @@ define <vscale x 8 x half> @round_nxv8f16(<vscale x 8 x half> %x) {
}
declare <vscale x 8 x half> @llvm.experimental.constrained.round.nxv8f16(<vscale x 8 x half>, metadata)

define <vscale x 16 x half> @round_nxv16f16(<vscale x 16 x half> %x) {
define <vscale x 16 x half> @round_nxv16f16(<vscale x 16 x half> %x) strictfp {
; CHECK-LABEL: round_nxv16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
Expand All @@ -116,7 +116,7 @@ define <vscale x 16 x half> @round_nxv16f16(<vscale x 16 x half> %x) {
}
declare <vscale x 16 x half> @llvm.experimental.constrained.round.nxv16f16(<vscale x 16 x half>, metadata)

define <vscale x 32 x half> @round_nxv32f16(<vscale x 32 x half> %x) {
define <vscale x 32 x half> @round_nxv32f16(<vscale x 32 x half> %x) strictfp {
; CHECK-LABEL: round_nxv32f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
Expand All @@ -138,7 +138,7 @@ define <vscale x 32 x half> @round_nxv32f16(<vscale x 32 x half> %x) {
}
declare <vscale x 32 x half> @llvm.experimental.constrained.round.nxv32f16(<vscale x 32 x half>, metadata)

define <vscale x 1 x float> @round_nxv1f32(<vscale x 1 x float> %x) {
define <vscale x 1 x float> @round_nxv1f32(<vscale x 1 x float> %x) strictfp {
; CHECK-LABEL: round_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
Expand All @@ -160,7 +160,7 @@ define <vscale x 1 x float> @round_nxv1f32(<vscale x 1 x float> %x) {
}
declare <vscale x 1 x float> @llvm.experimental.constrained.round.nxv1f32(<vscale x 1 x float>, metadata)

define <vscale x 2 x float> @round_nxv2f32(<vscale x 2 x float> %x) {
define <vscale x 2 x float> @round_nxv2f32(<vscale x 2 x float> %x) strictfp {
; CHECK-LABEL: round_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
Expand All @@ -182,7 +182,7 @@ define <vscale x 2 x float> @round_nxv2f32(<vscale x 2 x float> %x) {
}
declare <vscale x 2 x float> @llvm.experimental.constrained.round.nxv2f32(<vscale x 2 x float>, metadata)

define <vscale x 4 x float> @round_nxv4f32(<vscale x 4 x float> %x) {
define <vscale x 4 x float> @round_nxv4f32(<vscale x 4 x float> %x) strictfp {
; CHECK-LABEL: round_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
Expand All @@ -204,7 +204,7 @@ define <vscale x 4 x float> @round_nxv4f32(<vscale x 4 x float> %x) {
}
declare <vscale x 4 x float> @llvm.experimental.constrained.round.nxv4f32(<vscale x 4 x float>, metadata)

define <vscale x 8 x float> @round_nxv8f32(<vscale x 8 x float> %x) {
define <vscale x 8 x float> @round_nxv8f32(<vscale x 8 x float> %x) strictfp {
; CHECK-LABEL: round_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
Expand All @@ -226,7 +226,7 @@ define <vscale x 8 x float> @round_nxv8f32(<vscale x 8 x float> %x) {
}
declare <vscale x 8 x float> @llvm.experimental.constrained.round.nxv8f32(<vscale x 8 x float>, metadata)

define <vscale x 16 x float> @round_nxv16f32(<vscale x 16 x float> %x) {
define <vscale x 16 x float> @round_nxv16f32(<vscale x 16 x float> %x) strictfp {
; CHECK-LABEL: round_nxv16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
Expand All @@ -248,7 +248,7 @@ define <vscale x 16 x float> @round_nxv16f32(<vscale x 16 x float> %x) {
}
declare <vscale x 16 x float> @llvm.experimental.constrained.round.nxv16f32(<vscale x 16 x float>, metadata)

define <vscale x 1 x double> @round_nxv1f64(<vscale x 1 x double> %x) {
define <vscale x 1 x double> @round_nxv1f64(<vscale x 1 x double> %x) strictfp {
; CHECK-LABEL: round_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
Expand All @@ -270,7 +270,7 @@ define <vscale x 1 x double> @round_nxv1f64(<vscale x 1 x double> %x) {
}
declare <vscale x 1 x double> @llvm.experimental.constrained.round.nxv1f64(<vscale x 1 x double>, metadata)

define <vscale x 2 x double> @round_nxv2f64(<vscale x 2 x double> %x) {
define <vscale x 2 x double> @round_nxv2f64(<vscale x 2 x double> %x) strictfp {
; CHECK-LABEL: round_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
Expand All @@ -292,7 +292,7 @@ define <vscale x 2 x double> @round_nxv2f64(<vscale x 2 x double> %x) {
}
declare <vscale x 2 x double> @llvm.experimental.constrained.round.nxv2f64(<vscale x 2 x double>, metadata)

define <vscale x 4 x double> @round_nxv4f64(<vscale x 4 x double> %x) {
define <vscale x 4 x double> @round_nxv4f64(<vscale x 4 x double> %x) strictfp {
; CHECK-LABEL: round_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
Expand All @@ -314,7 +314,7 @@ define <vscale x 4 x double> @round_nxv4f64(<vscale x 4 x double> %x) {
}
declare <vscale x 4 x double> @llvm.experimental.constrained.round.nxv4f64(<vscale x 4 x double>, metadata)

define <vscale x 8 x double> @round_nxv8f64(<vscale x 8 x double> %x) {
define <vscale x 8 x double> @round_nxv8f64(<vscale x 8 x double> %x) strictfp {
; CHECK-LABEL: round_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
Expand Down
30 changes: 15 additions & 15 deletions llvm/test/CodeGen/RISCV/rvv/froundeven-constrained-sdnode.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@

; This file tests the code generation for `llvm.experimental.constrained.roundeven.*` on scalable vector type.

define <vscale x 1 x half> @roundeven_nxv1f16(<vscale x 1 x half> %x) {
define <vscale x 1 x half> @roundeven_nxv1f16(<vscale x 1 x half> %x) strictfp {
; CHECK-LABEL: roundeven_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
Expand All @@ -28,7 +28,7 @@ define <vscale x 1 x half> @roundeven_nxv1f16(<vscale x 1 x half> %x) {
}
declare <vscale x 1 x half> @llvm.experimental.constrained.roundeven.nxv1f16(<vscale x 1 x half>, metadata)

define <vscale x 2 x half> @roundeven_nxv2f16(<vscale x 2 x half> %x) {
define <vscale x 2 x half> @roundeven_nxv2f16(<vscale x 2 x half> %x) strictfp {
; CHECK-LABEL: roundeven_nxv2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
Expand All @@ -50,7 +50,7 @@ define <vscale x 2 x half> @roundeven_nxv2f16(<vscale x 2 x half> %x) {
}
declare <vscale x 2 x half> @llvm.experimental.constrained.roundeven.nxv2f16(<vscale x 2 x half>, metadata)

define <vscale x 4 x half> @roundeven_nxv4f16(<vscale x 4 x half> %x) {
define <vscale x 4 x half> @roundeven_nxv4f16(<vscale x 4 x half> %x) strictfp {
; CHECK-LABEL: roundeven_nxv4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
Expand All @@ -72,7 +72,7 @@ define <vscale x 4 x half> @roundeven_nxv4f16(<vscale x 4 x half> %x) {
}
declare <vscale x 4 x half> @llvm.experimental.constrained.roundeven.nxv4f16(<vscale x 4 x half>, metadata)

define <vscale x 8 x half> @roundeven_nxv8f16(<vscale x 8 x half> %x) {
define <vscale x 8 x half> @roundeven_nxv8f16(<vscale x 8 x half> %x) strictfp {
; CHECK-LABEL: roundeven_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
Expand All @@ -94,7 +94,7 @@ define <vscale x 8 x half> @roundeven_nxv8f16(<vscale x 8 x half> %x) {
}
declare <vscale x 8 x half> @llvm.experimental.constrained.roundeven.nxv8f16(<vscale x 8 x half>, metadata)

define <vscale x 16 x half> @roundeven_nxv16f16(<vscale x 16 x half> %x) {
define <vscale x 16 x half> @roundeven_nxv16f16(<vscale x 16 x half> %x) strictfp {
; CHECK-LABEL: roundeven_nxv16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
Expand All @@ -116,7 +116,7 @@ define <vscale x 16 x half> @roundeven_nxv16f16(<vscale x 16 x half> %x) {
}
declare <vscale x 16 x half> @llvm.experimental.constrained.roundeven.nxv16f16(<vscale x 16 x half>, metadata)

define <vscale x 32 x half> @roundeven_nxv32f16(<vscale x 32 x half> %x) {
define <vscale x 32 x half> @roundeven_nxv32f16(<vscale x 32 x half> %x) strictfp {
; CHECK-LABEL: roundeven_nxv32f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
Expand All @@ -138,7 +138,7 @@ define <vscale x 32 x half> @roundeven_nxv32f16(<vscale x 32 x half> %x) {
}
declare <vscale x 32 x half> @llvm.experimental.constrained.roundeven.nxv32f16(<vscale x 32 x half>, metadata)

define <vscale x 1 x float> @roundeven_nxv1f32(<vscale x 1 x float> %x) {
define <vscale x 1 x float> @roundeven_nxv1f32(<vscale x 1 x float> %x) strictfp {
; CHECK-LABEL: roundeven_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
Expand All @@ -160,7 +160,7 @@ define <vscale x 1 x float> @roundeven_nxv1f32(<vscale x 1 x float> %x) {
}
declare <vscale x 1 x float> @llvm.experimental.constrained.roundeven.nxv1f32(<vscale x 1 x float>, metadata)

define <vscale x 2 x float> @roundeven_nxv2f32(<vscale x 2 x float> %x) {
define <vscale x 2 x float> @roundeven_nxv2f32(<vscale x 2 x float> %x) strictfp {
; CHECK-LABEL: roundeven_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
Expand All @@ -182,7 +182,7 @@ define <vscale x 2 x float> @roundeven_nxv2f32(<vscale x 2 x float> %x) {
}
declare <vscale x 2 x float> @llvm.experimental.constrained.roundeven.nxv2f32(<vscale x 2 x float>, metadata)

define <vscale x 4 x float> @roundeven_nxv4f32(<vscale x 4 x float> %x) {
define <vscale x 4 x float> @roundeven_nxv4f32(<vscale x 4 x float> %x) strictfp {
; CHECK-LABEL: roundeven_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
Expand All @@ -204,7 +204,7 @@ define <vscale x 4 x float> @roundeven_nxv4f32(<vscale x 4 x float> %x) {
}
declare <vscale x 4 x float> @llvm.experimental.constrained.roundeven.nxv4f32(<vscale x 4 x float>, metadata)

define <vscale x 8 x float> @roundeven_nxv8f32(<vscale x 8 x float> %x) {
define <vscale x 8 x float> @roundeven_nxv8f32(<vscale x 8 x float> %x) strictfp {
; CHECK-LABEL: roundeven_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
Expand All @@ -226,7 +226,7 @@ define <vscale x 8 x float> @roundeven_nxv8f32(<vscale x 8 x float> %x) {
}
declare <vscale x 8 x float> @llvm.experimental.constrained.roundeven.nxv8f32(<vscale x 8 x float>, metadata)

define <vscale x 16 x float> @roundeven_nxv16f32(<vscale x 16 x float> %x) {
define <vscale x 16 x float> @roundeven_nxv16f32(<vscale x 16 x float> %x) strictfp {
; CHECK-LABEL: roundeven_nxv16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
Expand All @@ -248,7 +248,7 @@ define <vscale x 16 x float> @roundeven_nxv16f32(<vscale x 16 x float> %x) {
}
declare <vscale x 16 x float> @llvm.experimental.constrained.roundeven.nxv16f32(<vscale x 16 x float>, metadata)

define <vscale x 1 x double> @roundeven_nxv1f64(<vscale x 1 x double> %x) {
define <vscale x 1 x double> @roundeven_nxv1f64(<vscale x 1 x double> %x) strictfp {
; CHECK-LABEL: roundeven_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
Expand All @@ -270,7 +270,7 @@ define <vscale x 1 x double> @roundeven_nxv1f64(<vscale x 1 x double> %x) {
}
declare <vscale x 1 x double> @llvm.experimental.constrained.roundeven.nxv1f64(<vscale x 1 x double>, metadata)

define <vscale x 2 x double> @roundeven_nxv2f64(<vscale x 2 x double> %x) {
define <vscale x 2 x double> @roundeven_nxv2f64(<vscale x 2 x double> %x) strictfp {
; CHECK-LABEL: roundeven_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
Expand All @@ -292,7 +292,7 @@ define <vscale x 2 x double> @roundeven_nxv2f64(<vscale x 2 x double> %x) {
}
declare <vscale x 2 x double> @llvm.experimental.constrained.roundeven.nxv2f64(<vscale x 2 x double>, metadata)

define <vscale x 4 x double> @roundeven_nxv4f64(<vscale x 4 x double> %x) {
define <vscale x 4 x double> @roundeven_nxv4f64(<vscale x 4 x double> %x) strictfp {
; CHECK-LABEL: roundeven_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
Expand All @@ -314,7 +314,7 @@ define <vscale x 4 x double> @roundeven_nxv4f64(<vscale x 4 x double> %x) {
}
declare <vscale x 4 x double> @llvm.experimental.constrained.roundeven.nxv4f64(<vscale x 4 x double>, metadata)

define <vscale x 8 x double> @roundeven_nxv8f64(<vscale x 8 x double> %x) {
define <vscale x 8 x double> @roundeven_nxv8f64(<vscale x 8 x double> %x) strictfp {
; CHECK-LABEL: roundeven_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
Expand Down
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