122 changes: 49 additions & 73 deletions llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh -verify-machineinstrs \
; RUN: < %s | FileCheck %s
; RUN: -target-abi=lp64d < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16(
<vscale x 1 x half>,
<vscale x 1 x half>,
Expand Down Expand Up @@ -633,9 +633,8 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.f16(
define <vscale x 1 x i1> @intrinsic_vmfgt_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmfgt.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmfgt.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.f16(
Expand All @@ -657,10 +656,9 @@ define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vf_nxv1f16_f16(<vscale x 1 x i1>
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfgt.vf v10, v8, ft0, v0.t
; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
Expand All @@ -682,9 +680,8 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.f16(
define <vscale x 2 x i1> @intrinsic_vmfgt_vf_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmfgt.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmfgt.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.f16(
Expand All @@ -706,10 +703,9 @@ define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vf_nxv2f16_f16(<vscale x 2 x i1>
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfgt.vf v10, v8, ft0, v0.t
; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
Expand All @@ -731,9 +727,8 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.f16(
define <vscale x 4 x i1> @intrinsic_vmfgt_vf_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmfgt.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmfgt.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.f16(
Expand All @@ -755,10 +750,9 @@ define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vf_nxv4f16_f16(<vscale x 4 x i1>
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfgt.vf v10, v8, ft0, v0.t
; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret
entry:
Expand All @@ -780,9 +774,8 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.f16(
define <vscale x 8 x i1> @intrinsic_vmfgt_vf_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmfgt.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmfgt.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.f16(
Expand All @@ -804,10 +797,9 @@ define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vf_nxv8f16_f16(<vscale x 8 x i1>
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfgt.vf v11, v8, ft0, v0.t
; CHECK-NEXT: vmfgt.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
Expand All @@ -829,9 +821,8 @@ declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.f16(
define <vscale x 16 x i1> @intrinsic_vmfgt_vf_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmfgt.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmfgt.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.f16(
Expand All @@ -853,10 +844,9 @@ define <vscale x 16 x i1> @intrinsic_vmfgt_mask_vf_nxv16f16_f16(<vscale x 16 x i
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfgt.vf v13, v8, ft0, v0.t
; CHECK-NEXT: vmfgt.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
Expand All @@ -878,9 +868,8 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f32.f32(
define <vscale x 1 x i1> @intrinsic_vmfgt_vf_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmfgt.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmfgt.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f32.f32(
Expand All @@ -902,10 +891,9 @@ define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vf_nxv1f32_f32(<vscale x 1 x i1>
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfgt.vf v10, v8, ft0, v0.t
; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
Expand All @@ -927,9 +915,8 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f32.f32(
define <vscale x 2 x i1> @intrinsic_vmfgt_vf_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmfgt.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmfgt.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f32.f32(
Expand All @@ -951,10 +938,9 @@ define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vf_nxv2f32_f32(<vscale x 2 x i1>
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfgt.vf v10, v8, ft0, v0.t
; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret
entry:
Expand All @@ -976,9 +962,8 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f32.f32(
define <vscale x 4 x i1> @intrinsic_vmfgt_vf_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmfgt.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmfgt.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f32.f32(
Expand All @@ -1000,10 +985,9 @@ define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vf_nxv4f32_f32(<vscale x 4 x i1>
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfgt.vf v11, v8, ft0, v0.t
; CHECK-NEXT: vmfgt.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
Expand All @@ -1025,9 +1009,8 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f32.f32(
define <vscale x 8 x i1> @intrinsic_vmfgt_vf_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmfgt.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmfgt.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f32.f32(
Expand All @@ -1049,10 +1032,9 @@ define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vf_nxv8f32_f32(<vscale x 8 x i1>
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfgt.vf v13, v8, ft0, v0.t
; CHECK-NEXT: vmfgt.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
Expand All @@ -1074,9 +1056,8 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f64.f64(
define <vscale x 1 x i1> @intrinsic_vmfgt_vf_nxv1f64_f64(<vscale x 1 x double> %0, double %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vmfgt.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmfgt.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f64.f64(
Expand All @@ -1098,10 +1079,9 @@ define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vf_nxv1f64_f64(<vscale x 1 x i1>
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfgt.vf v10, v8, ft0, v0.t
; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret
entry:
Expand All @@ -1123,9 +1103,8 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f64.f64(
define <vscale x 2 x i1> @intrinsic_vmfgt_vf_nxv2f64_f64(<vscale x 2 x double> %0, double %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vmfgt.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmfgt.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f64.f64(
Expand All @@ -1147,10 +1126,9 @@ define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vf_nxv2f64_f64(<vscale x 2 x i1>
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfgt.vf v11, v8, ft0, v0.t
; CHECK-NEXT: vmfgt.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
Expand All @@ -1172,9 +1150,8 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f64.f64(
define <vscale x 4 x i1> @intrinsic_vmfgt_vf_nxv4f64_f64(<vscale x 4 x double> %0, double %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vmfgt.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmfgt.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f64.f64(
Expand All @@ -1196,10 +1173,9 @@ define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vf_nxv4f64_f64(<vscale x 4 x i1>
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfgt.vf v13, v8, ft0, v0.t
; CHECK-NEXT: vmfgt.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
Expand Down
146 changes: 49 additions & 97 deletions llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zfh -verify-machineinstrs \
; RUN: < %s | FileCheck %s
; RUN: -target-abi=ilp32d < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16(
<vscale x 1 x half>,
<vscale x 1 x half>,
Expand Down Expand Up @@ -633,9 +633,8 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.f16(
define <vscale x 1 x i1> @intrinsic_vmfle_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.f16(
Expand All @@ -657,10 +656,9 @@ define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f16_f16(<vscale x 1 x i1>
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfle.vf v10, v8, ft0, v0.t
; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
Expand All @@ -682,9 +680,8 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.f16(
define <vscale x 2 x i1> @intrinsic_vmfle_vf_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.f16(
Expand All @@ -706,10 +703,9 @@ define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f16_f16(<vscale x 2 x i1>
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfle.vf v10, v8, ft0, v0.t
; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
Expand All @@ -731,9 +727,8 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.f16(
define <vscale x 4 x i1> @intrinsic_vmfle_vf_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.f16(
Expand All @@ -755,10 +750,9 @@ define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f16_f16(<vscale x 4 x i1>
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfle.vf v10, v8, ft0, v0.t
; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret
entry:
Expand All @@ -780,9 +774,8 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.f16(
define <vscale x 8 x i1> @intrinsic_vmfle_vf_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.f16(
Expand All @@ -804,10 +797,9 @@ define <vscale x 8 x i1> @intrinsic_vmfle_mask_vf_nxv8f16_f16(<vscale x 8 x i1>
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfle.vf v11, v8, ft0, v0.t
; CHECK-NEXT: vmfle.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
Expand All @@ -829,9 +821,8 @@ declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.f16(
define <vscale x 16 x i1> @intrinsic_vmfle_vf_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.f16(
Expand All @@ -853,10 +844,9 @@ define <vscale x 16 x i1> @intrinsic_vmfle_mask_vf_nxv16f16_f16(<vscale x 16 x i
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfle.vf v13, v8, ft0, v0.t
; CHECK-NEXT: vmfle.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
Expand All @@ -878,9 +868,8 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32.f32(
define <vscale x 1 x i1> @intrinsic_vmfle_vf_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32.f32(
Expand All @@ -902,10 +891,9 @@ define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f32_f32(<vscale x 1 x i1>
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfle.vf v10, v8, ft0, v0.t
; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
Expand All @@ -927,9 +915,8 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f32.f32(
define <vscale x 2 x i1> @intrinsic_vmfle_vf_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f32.f32(
Expand All @@ -951,10 +938,9 @@ define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f32_f32(<vscale x 2 x i1>
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfle.vf v10, v8, ft0, v0.t
; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret
entry:
Expand All @@ -976,9 +962,8 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32.f32(
define <vscale x 4 x i1> @intrinsic_vmfle_vf_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32.f32(
Expand All @@ -1000,10 +985,9 @@ define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f32_f32(<vscale x 4 x i1>
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfle.vf v11, v8, ft0, v0.t
; CHECK-NEXT: vmfle.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
Expand All @@ -1025,9 +1009,8 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f32.f32(
define <vscale x 8 x i1> @intrinsic_vmfle_vf_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f32.f32(
Expand All @@ -1049,10 +1032,9 @@ define <vscale x 8 x i1> @intrinsic_vmfle_mask_vf_nxv8f32_f32(<vscale x 8 x i1>
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfle.vf v13, v8, ft0, v0.t
; CHECK-NEXT: vmfle.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
Expand All @@ -1074,13 +1056,8 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f64.f64(
define <vscale x 1 x i1> @intrinsic_vmfle_vf_nxv1f64_f64(<vscale x 1 x double> %0, double %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, ft0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f64.f64(
Expand All @@ -1101,16 +1078,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f64.f64(
define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp)
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfle.vf v10, v8, ft0, v0.t
; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f64.f64(
Expand All @@ -1131,13 +1103,8 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f64.f64(
define <vscale x 2 x i1> @intrinsic_vmfle_vf_nxv2f64_f64(<vscale x 2 x double> %0, double %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, ft0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f64.f64(
Expand All @@ -1158,16 +1125,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f64.f64(
define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp)
; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfle.vf v11, v8, ft0, v0.t
; CHECK-NEXT: vmfle.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f64.f64(
Expand All @@ -1188,13 +1150,8 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f64.f64(
define <vscale x 4 x i1> @intrinsic_vmfle_vf_nxv4f64_f64(<vscale x 4 x double> %0, double %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, ft0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f64.f64(
Expand All @@ -1215,16 +1172,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f64.f64(
define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp)
; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfle.vf v13, v8, ft0, v0.t
; CHECK-NEXT: vmfle.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f64.f64(
Expand Down
122 changes: 49 additions & 73 deletions llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh -verify-machineinstrs \
; RUN: < %s | FileCheck %s
; RUN: -target-abi=lp64d < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16(
<vscale x 1 x half>,
<vscale x 1 x half>,
Expand Down Expand Up @@ -633,9 +633,8 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.f16(
define <vscale x 1 x i1> @intrinsic_vmfle_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.f16(
Expand All @@ -657,10 +656,9 @@ define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f16_f16(<vscale x 1 x i1>
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfle.vf v10, v8, ft0, v0.t
; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
Expand All @@ -682,9 +680,8 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.f16(
define <vscale x 2 x i1> @intrinsic_vmfle_vf_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.f16(
Expand All @@ -706,10 +703,9 @@ define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f16_f16(<vscale x 2 x i1>
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfle.vf v10, v8, ft0, v0.t
; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
Expand All @@ -731,9 +727,8 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.f16(
define <vscale x 4 x i1> @intrinsic_vmfle_vf_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.f16(
Expand All @@ -755,10 +750,9 @@ define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f16_f16(<vscale x 4 x i1>
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfle.vf v10, v8, ft0, v0.t
; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret
entry:
Expand All @@ -780,9 +774,8 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.f16(
define <vscale x 8 x i1> @intrinsic_vmfle_vf_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.f16(
Expand All @@ -804,10 +797,9 @@ define <vscale x 8 x i1> @intrinsic_vmfle_mask_vf_nxv8f16_f16(<vscale x 8 x i1>
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfle.vf v11, v8, ft0, v0.t
; CHECK-NEXT: vmfle.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
Expand All @@ -829,9 +821,8 @@ declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.f16(
define <vscale x 16 x i1> @intrinsic_vmfle_vf_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.f16(
Expand All @@ -853,10 +844,9 @@ define <vscale x 16 x i1> @intrinsic_vmfle_mask_vf_nxv16f16_f16(<vscale x 16 x i
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfle.vf v13, v8, ft0, v0.t
; CHECK-NEXT: vmfle.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
Expand All @@ -878,9 +868,8 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32.f32(
define <vscale x 1 x i1> @intrinsic_vmfle_vf_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32.f32(
Expand All @@ -902,10 +891,9 @@ define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f32_f32(<vscale x 1 x i1>
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfle.vf v10, v8, ft0, v0.t
; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
Expand All @@ -927,9 +915,8 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f32.f32(
define <vscale x 2 x i1> @intrinsic_vmfle_vf_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f32.f32(
Expand All @@ -951,10 +938,9 @@ define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f32_f32(<vscale x 2 x i1>
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfle.vf v10, v8, ft0, v0.t
; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret
entry:
Expand All @@ -976,9 +962,8 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32.f32(
define <vscale x 4 x i1> @intrinsic_vmfle_vf_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32.f32(
Expand All @@ -1000,10 +985,9 @@ define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f32_f32(<vscale x 4 x i1>
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfle.vf v11, v8, ft0, v0.t
; CHECK-NEXT: vmfle.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
Expand All @@ -1025,9 +1009,8 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f32.f32(
define <vscale x 8 x i1> @intrinsic_vmfle_vf_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f32.f32(
Expand All @@ -1049,10 +1032,9 @@ define <vscale x 8 x i1> @intrinsic_vmfle_mask_vf_nxv8f32_f32(<vscale x 8 x i1>
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfle.vf v13, v8, ft0, v0.t
; CHECK-NEXT: vmfle.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
Expand All @@ -1074,9 +1056,8 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f64.f64(
define <vscale x 1 x i1> @intrinsic_vmfle_vf_nxv1f64_f64(<vscale x 1 x double> %0, double %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f64.f64(
Expand All @@ -1098,10 +1079,9 @@ define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f64_f64(<vscale x 1 x i1>
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfle.vf v10, v8, ft0, v0.t
; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret
entry:
Expand All @@ -1123,9 +1103,8 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f64.f64(
define <vscale x 2 x i1> @intrinsic_vmfle_vf_nxv2f64_f64(<vscale x 2 x double> %0, double %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f64.f64(
Expand All @@ -1147,10 +1126,9 @@ define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f64_f64(<vscale x 2 x i1>
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfle.vf v11, v8, ft0, v0.t
; CHECK-NEXT: vmfle.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
Expand All @@ -1172,9 +1150,8 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f64.f64(
define <vscale x 4 x i1> @intrinsic_vmfle_vf_nxv4f64_f64(<vscale x 4 x double> %0, double %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmfle.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f64.f64(
Expand All @@ -1196,10 +1173,9 @@ define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f64_f64(<vscale x 4 x i1>
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfle.vf v13, v8, ft0, v0.t
; CHECK-NEXT: vmfle.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
Expand Down
146 changes: 49 additions & 97 deletions llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zfh -verify-machineinstrs \
; RUN: < %s | FileCheck %s
; RUN: -target-abi=ilp32d < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16(
<vscale x 1 x half>,
<vscale x 1 x half>,
Expand Down Expand Up @@ -633,9 +633,8 @@ declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.f16(
define <vscale x 1 x i1> @intrinsic_vmflt_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.f16(
Expand All @@ -657,10 +656,9 @@ define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f16_f16(<vscale x 1 x i1>
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmflt.vf v10, v8, ft0, v0.t
; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
Expand All @@ -682,9 +680,8 @@ declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.f16(
define <vscale x 2 x i1> @intrinsic_vmflt_vf_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.f16(
Expand All @@ -706,10 +703,9 @@ define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f16_f16(<vscale x 2 x i1>
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmflt.vf v10, v8, ft0, v0.t
; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
Expand All @@ -731,9 +727,8 @@ declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.f16(
define <vscale x 4 x i1> @intrinsic_vmflt_vf_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.f16(
Expand All @@ -755,10 +750,9 @@ define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f16_f16(<vscale x 4 x i1>
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmflt.vf v10, v8, ft0, v0.t
; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret
entry:
Expand All @@ -780,9 +774,8 @@ declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.f16(
define <vscale x 8 x i1> @intrinsic_vmflt_vf_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.f16(
Expand All @@ -804,10 +797,9 @@ define <vscale x 8 x i1> @intrinsic_vmflt_mask_vf_nxv8f16_f16(<vscale x 8 x i1>
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmflt.vf v11, v8, ft0, v0.t
; CHECK-NEXT: vmflt.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
Expand All @@ -829,9 +821,8 @@ declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.f16(
define <vscale x 16 x i1> @intrinsic_vmflt_vf_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.f16(
Expand All @@ -853,10 +844,9 @@ define <vscale x 16 x i1> @intrinsic_vmflt_mask_vf_nxv16f16_f16(<vscale x 16 x i
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmflt.vf v13, v8, ft0, v0.t
; CHECK-NEXT: vmflt.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
Expand All @@ -878,9 +868,8 @@ declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f32.f32(
define <vscale x 1 x i1> @intrinsic_vmflt_vf_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f32.f32(
Expand All @@ -902,10 +891,9 @@ define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f32_f32(<vscale x 1 x i1>
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmflt.vf v10, v8, ft0, v0.t
; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
Expand All @@ -927,9 +915,8 @@ declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f32.f32(
define <vscale x 2 x i1> @intrinsic_vmflt_vf_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f32.f32(
Expand All @@ -951,10 +938,9 @@ define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f32_f32(<vscale x 2 x i1>
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmflt.vf v10, v8, ft0, v0.t
; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret
entry:
Expand All @@ -976,9 +962,8 @@ declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f32.f32(
define <vscale x 4 x i1> @intrinsic_vmflt_vf_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f32.f32(
Expand All @@ -1000,10 +985,9 @@ define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f32_f32(<vscale x 4 x i1>
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmflt.vf v11, v8, ft0, v0.t
; CHECK-NEXT: vmflt.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
Expand All @@ -1025,9 +1009,8 @@ declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f32.f32(
define <vscale x 8 x i1> @intrinsic_vmflt_vf_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f32.f32(
Expand All @@ -1049,10 +1032,9 @@ define <vscale x 8 x i1> @intrinsic_vmflt_mask_vf_nxv8f32_f32(<vscale x 8 x i1>
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmflt.vf v13, v8, ft0, v0.t
; CHECK-NEXT: vmflt.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
Expand All @@ -1074,13 +1056,8 @@ declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f64.f64(
define <vscale x 1 x i1> @intrinsic_vmflt_vf_nxv1f64_f64(<vscale x 1 x double> %0, double %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, ft0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f64.f64(
Expand All @@ -1101,16 +1078,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f64.f64(
define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp)
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmflt.vf v10, v8, ft0, v0.t
; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f64.f64(
Expand All @@ -1131,13 +1103,8 @@ declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f64.f64(
define <vscale x 2 x i1> @intrinsic_vmflt_vf_nxv2f64_f64(<vscale x 2 x double> %0, double %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, ft0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f64.f64(
Expand All @@ -1158,16 +1125,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f64.f64(
define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp)
; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmflt.vf v11, v8, ft0, v0.t
; CHECK-NEXT: vmflt.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f64.f64(
Expand All @@ -1188,13 +1150,8 @@ declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f64.f64(
define <vscale x 4 x i1> @intrinsic_vmflt_vf_nxv4f64_f64(<vscale x 4 x double> %0, double %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, ft0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f64.f64(
Expand All @@ -1215,16 +1172,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f64.f64(
define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp)
; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmflt.vf v13, v8, ft0, v0.t
; CHECK-NEXT: vmflt.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f64.f64(
Expand Down
122 changes: 49 additions & 73 deletions llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh -verify-machineinstrs \
; RUN: < %s | FileCheck %s
; RUN: -target-abi=lp64d < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16(
<vscale x 1 x half>,
<vscale x 1 x half>,
Expand Down Expand Up @@ -633,9 +633,8 @@ declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.f16(
define <vscale x 1 x i1> @intrinsic_vmflt_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.f16(
Expand All @@ -657,10 +656,9 @@ define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f16_f16(<vscale x 1 x i1>
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmflt.vf v10, v8, ft0, v0.t
; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
Expand All @@ -682,9 +680,8 @@ declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.f16(
define <vscale x 2 x i1> @intrinsic_vmflt_vf_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.f16(
Expand All @@ -706,10 +703,9 @@ define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f16_f16(<vscale x 2 x i1>
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmflt.vf v10, v8, ft0, v0.t
; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
Expand All @@ -731,9 +727,8 @@ declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.f16(
define <vscale x 4 x i1> @intrinsic_vmflt_vf_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.f16(
Expand All @@ -755,10 +750,9 @@ define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f16_f16(<vscale x 4 x i1>
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmflt.vf v10, v8, ft0, v0.t
; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret
entry:
Expand All @@ -780,9 +774,8 @@ declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.f16(
define <vscale x 8 x i1> @intrinsic_vmflt_vf_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.f16(
Expand All @@ -804,10 +797,9 @@ define <vscale x 8 x i1> @intrinsic_vmflt_mask_vf_nxv8f16_f16(<vscale x 8 x i1>
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmflt.vf v11, v8, ft0, v0.t
; CHECK-NEXT: vmflt.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
Expand All @@ -829,9 +821,8 @@ declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.f16(
define <vscale x 16 x i1> @intrinsic_vmflt_vf_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.f16(
Expand All @@ -853,10 +844,9 @@ define <vscale x 16 x i1> @intrinsic_vmflt_mask_vf_nxv16f16_f16(<vscale x 16 x i
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmflt.vf v13, v8, ft0, v0.t
; CHECK-NEXT: vmflt.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
Expand All @@ -878,9 +868,8 @@ declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f32.f32(
define <vscale x 1 x i1> @intrinsic_vmflt_vf_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f32.f32(
Expand All @@ -902,10 +891,9 @@ define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f32_f32(<vscale x 1 x i1>
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmflt.vf v10, v8, ft0, v0.t
; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
Expand All @@ -927,9 +915,8 @@ declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f32.f32(
define <vscale x 2 x i1> @intrinsic_vmflt_vf_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f32.f32(
Expand All @@ -951,10 +938,9 @@ define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f32_f32(<vscale x 2 x i1>
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmflt.vf v10, v8, ft0, v0.t
; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret
entry:
Expand All @@ -976,9 +962,8 @@ declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f32.f32(
define <vscale x 4 x i1> @intrinsic_vmflt_vf_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f32.f32(
Expand All @@ -1000,10 +985,9 @@ define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f32_f32(<vscale x 4 x i1>
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmflt.vf v11, v8, ft0, v0.t
; CHECK-NEXT: vmflt.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
Expand All @@ -1025,9 +1009,8 @@ declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f32.f32(
define <vscale x 8 x i1> @intrinsic_vmflt_vf_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f32.f32(
Expand All @@ -1049,10 +1032,9 @@ define <vscale x 8 x i1> @intrinsic_vmflt_mask_vf_nxv8f32_f32(<vscale x 8 x i1>
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmflt.vf v13, v8, ft0, v0.t
; CHECK-NEXT: vmflt.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
Expand All @@ -1074,9 +1056,8 @@ declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f64.f64(
define <vscale x 1 x i1> @intrinsic_vmflt_vf_nxv1f64_f64(<vscale x 1 x double> %0, double %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f64.f64(
Expand All @@ -1098,10 +1079,9 @@ define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f64_f64(<vscale x 1 x i1>
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmflt.vf v10, v8, ft0, v0.t
; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret
entry:
Expand All @@ -1123,9 +1103,8 @@ declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f64.f64(
define <vscale x 2 x i1> @intrinsic_vmflt_vf_nxv2f64_f64(<vscale x 2 x double> %0, double %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f64.f64(
Expand All @@ -1147,10 +1126,9 @@ define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f64_f64(<vscale x 2 x i1>
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmflt.vf v11, v8, ft0, v0.t
; CHECK-NEXT: vmflt.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
Expand All @@ -1172,9 +1150,8 @@ declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f64.f64(
define <vscale x 4 x i1> @intrinsic_vmflt_vf_nxv4f64_f64(<vscale x 4 x double> %0, double %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f64.f64(
Expand All @@ -1196,10 +1173,9 @@ define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f64_f64(<vscale x 4 x i1>
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmflt.vf v13, v8, ft0, v0.t
; CHECK-NEXT: vmflt.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
Expand Down
146 changes: 49 additions & 97 deletions llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zfh -verify-machineinstrs \
; RUN: < %s | FileCheck %s
; RUN: -target-abi=ilp32d < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16(
<vscale x 1 x half>,
<vscale x 1 x half>,
Expand Down Expand Up @@ -633,9 +633,8 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.f16(
define <vscale x 1 x i1> @intrinsic_vmfne_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.f16(
Expand All @@ -657,10 +656,9 @@ define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f16_f16(<vscale x 1 x i1>
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfne.vf v10, v8, ft0, v0.t
; CHECK-NEXT: vmfne.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
Expand All @@ -682,9 +680,8 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.f16(
define <vscale x 2 x i1> @intrinsic_vmfne_vf_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.f16(
Expand All @@ -706,10 +703,9 @@ define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f16_f16(<vscale x 2 x i1>
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfne.vf v10, v8, ft0, v0.t
; CHECK-NEXT: vmfne.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
Expand All @@ -731,9 +727,8 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.f16(
define <vscale x 4 x i1> @intrinsic_vmfne_vf_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.f16(
Expand All @@ -755,10 +750,9 @@ define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f16_f16(<vscale x 4 x i1>
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfne.vf v10, v8, ft0, v0.t
; CHECK-NEXT: vmfne.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret
entry:
Expand All @@ -780,9 +774,8 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.f16(
define <vscale x 8 x i1> @intrinsic_vmfne_vf_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.f16(
Expand All @@ -804,10 +797,9 @@ define <vscale x 8 x i1> @intrinsic_vmfne_mask_vf_nxv8f16_f16(<vscale x 8 x i1>
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfne.vf v11, v8, ft0, v0.t
; CHECK-NEXT: vmfne.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
Expand All @@ -829,9 +821,8 @@ declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.f16(
define <vscale x 16 x i1> @intrinsic_vmfne_vf_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.f16(
Expand All @@ -853,10 +844,9 @@ define <vscale x 16 x i1> @intrinsic_vmfne_mask_vf_nxv16f16_f16(<vscale x 16 x i
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfne.vf v13, v8, ft0, v0.t
; CHECK-NEXT: vmfne.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
Expand All @@ -878,9 +868,8 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f32.f32(
define <vscale x 1 x i1> @intrinsic_vmfne_vf_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f32.f32(
Expand All @@ -902,10 +891,9 @@ define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f32_f32(<vscale x 1 x i1>
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfne.vf v10, v8, ft0, v0.t
; CHECK-NEXT: vmfne.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
Expand All @@ -927,9 +915,8 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f32.f32(
define <vscale x 2 x i1> @intrinsic_vmfne_vf_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f32.f32(
Expand All @@ -951,10 +938,9 @@ define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f32_f32(<vscale x 2 x i1>
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfne.vf v10, v8, ft0, v0.t
; CHECK-NEXT: vmfne.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret
entry:
Expand All @@ -976,9 +962,8 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f32.f32(
define <vscale x 4 x i1> @intrinsic_vmfne_vf_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f32.f32(
Expand All @@ -1000,10 +985,9 @@ define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f32_f32(<vscale x 4 x i1>
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfne.vf v11, v8, ft0, v0.t
; CHECK-NEXT: vmfne.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
Expand All @@ -1025,9 +1009,8 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f32.f32(
define <vscale x 8 x i1> @intrinsic_vmfne_vf_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f32.f32(
Expand All @@ -1049,10 +1032,9 @@ define <vscale x 8 x i1> @intrinsic_vmfne_mask_vf_nxv8f32_f32(<vscale x 8 x i1>
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfne.vf v13, v8, ft0, v0.t
; CHECK-NEXT: vmfne.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
Expand All @@ -1074,13 +1056,8 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f64.f64(
define <vscale x 1 x i1> @intrinsic_vmfne_vf_nxv1f64_f64(<vscale x 1 x double> %0, double %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, ft0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f64.f64(
Expand All @@ -1101,16 +1078,11 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f64.f64(
define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp)
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfne.vf v10, v8, ft0, v0.t
; CHECK-NEXT: vmfne.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f64.f64(
Expand All @@ -1131,13 +1103,8 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f64.f64(
define <vscale x 2 x i1> @intrinsic_vmfne_vf_nxv2f64_f64(<vscale x 2 x double> %0, double %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, ft0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f64.f64(
Expand All @@ -1158,16 +1125,11 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f64.f64(
define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp)
; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfne.vf v11, v8, ft0, v0.t
; CHECK-NEXT: vmfne.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f64.f64(
Expand All @@ -1188,13 +1150,8 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f64.f64(
define <vscale x 4 x i1> @intrinsic_vmfne_vf_nxv4f64_f64(<vscale x 4 x double> %0, double %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, ft0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f64.f64(
Expand All @@ -1215,16 +1172,11 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f64.f64(
define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp)
; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfne.vf v13, v8, ft0, v0.t
; CHECK-NEXT: vmfne.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f64.f64(
Expand Down
122 changes: 49 additions & 73 deletions llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh -verify-machineinstrs \
; RUN: < %s | FileCheck %s
; RUN: -target-abi=lp64d < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16(
<vscale x 1 x half>,
<vscale x 1 x half>,
Expand Down Expand Up @@ -633,9 +633,8 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.f16(
define <vscale x 1 x i1> @intrinsic_vmfne_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.f16(
Expand All @@ -657,10 +656,9 @@ define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f16_f16(<vscale x 1 x i1>
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfne.vf v10, v8, ft0, v0.t
; CHECK-NEXT: vmfne.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
Expand All @@ -682,9 +680,8 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.f16(
define <vscale x 2 x i1> @intrinsic_vmfne_vf_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.f16(
Expand All @@ -706,10 +703,9 @@ define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f16_f16(<vscale x 2 x i1>
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfne.vf v10, v8, ft0, v0.t
; CHECK-NEXT: vmfne.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
Expand All @@ -731,9 +727,8 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.f16(
define <vscale x 4 x i1> @intrinsic_vmfne_vf_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.f16(
Expand All @@ -755,10 +750,9 @@ define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f16_f16(<vscale x 4 x i1>
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfne.vf v10, v8, ft0, v0.t
; CHECK-NEXT: vmfne.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret
entry:
Expand All @@ -780,9 +774,8 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.f16(
define <vscale x 8 x i1> @intrinsic_vmfne_vf_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.f16(
Expand All @@ -804,10 +797,9 @@ define <vscale x 8 x i1> @intrinsic_vmfne_mask_vf_nxv8f16_f16(<vscale x 8 x i1>
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfne.vf v11, v8, ft0, v0.t
; CHECK-NEXT: vmfne.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
Expand All @@ -829,9 +821,8 @@ declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.f16(
define <vscale x 16 x i1> @intrinsic_vmfne_vf_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.f16(
Expand All @@ -853,10 +844,9 @@ define <vscale x 16 x i1> @intrinsic_vmfne_mask_vf_nxv16f16_f16(<vscale x 16 x i
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfne.vf v13, v8, ft0, v0.t
; CHECK-NEXT: vmfne.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
Expand All @@ -878,9 +868,8 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f32.f32(
define <vscale x 1 x i1> @intrinsic_vmfne_vf_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f32.f32(
Expand All @@ -902,10 +891,9 @@ define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f32_f32(<vscale x 1 x i1>
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfne.vf v10, v8, ft0, v0.t
; CHECK-NEXT: vmfne.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
Expand All @@ -927,9 +915,8 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f32.f32(
define <vscale x 2 x i1> @intrinsic_vmfne_vf_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f32.f32(
Expand All @@ -951,10 +938,9 @@ define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f32_f32(<vscale x 2 x i1>
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfne.vf v10, v8, ft0, v0.t
; CHECK-NEXT: vmfne.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret
entry:
Expand All @@ -976,9 +962,8 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f32.f32(
define <vscale x 4 x i1> @intrinsic_vmfne_vf_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f32.f32(
Expand All @@ -1000,10 +985,9 @@ define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f32_f32(<vscale x 4 x i1>
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfne.vf v11, v8, ft0, v0.t
; CHECK-NEXT: vmfne.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
Expand All @@ -1025,9 +1009,8 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f32.f32(
define <vscale x 8 x i1> @intrinsic_vmfne_vf_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f32.f32(
Expand All @@ -1049,10 +1032,9 @@ define <vscale x 8 x i1> @intrinsic_vmfne_mask_vf_nxv8f32_f32(<vscale x 8 x i1>
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfne.vf v13, v8, ft0, v0.t
; CHECK-NEXT: vmfne.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
Expand All @@ -1074,9 +1056,8 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f64.f64(
define <vscale x 1 x i1> @intrinsic_vmfne_vf_nxv1f64_f64(<vscale x 1 x double> %0, double %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f64.f64(
Expand All @@ -1098,10 +1079,9 @@ define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f64_f64(<vscale x 1 x i1>
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfne.vf v10, v8, ft0, v0.t
; CHECK-NEXT: vmfne.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret
entry:
Expand All @@ -1123,9 +1103,8 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f64.f64(
define <vscale x 2 x i1> @intrinsic_vmfne_vf_nxv2f64_f64(<vscale x 2 x double> %0, double %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f64.f64(
Expand All @@ -1147,10 +1126,9 @@ define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f64_f64(<vscale x 2 x i1>
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfne.vf v11, v8, ft0, v0.t
; CHECK-NEXT: vmfne.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret
entry:
Expand All @@ -1172,9 +1150,8 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f64.f64(
define <vscale x 4 x i1> @intrinsic_vmfne_vf_nxv4f64_f64(<vscale x 4 x double> %0, double %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, ft0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmfne.vf v0, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f64.f64(
Expand All @@ -1196,10 +1173,9 @@ define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f64_f64(<vscale x 4 x i1>
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfne.vf v13, v8, ft0, v0.t
; CHECK-NEXT: vmfne.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret
entry:
Expand Down
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