28 changes: 28 additions & 0 deletions llvm/test/MC/X86/apx/evex-format-att.s
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Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,12 @@
# CHECK: encoding: [0x62,0xec,0xec,0x10,0x01,0x41,0x7b]
addq %r16, 123(%r17), %r18

## MRMDestMemCC

# CHECK: cfcmovbq %r16, 123(%r17,%r18,4)
# CHECK: encoding: [0x62,0xec,0xf8,0x0c,0x42,0x44,0x91,0x7b]
cfcmovbq %r16, 123(%r17,%r18,4)

## MRMSrcMem

# CHECK: vbroadcasti32x4 (%r16,%r17), %zmm0
Expand All @@ -20,6 +26,16 @@
# CHECK: encoding: [0x62,0xec,0xec,0x10,0x2b,0x48,0x7b]
subq 123(%r16), %r17, %r18

## MRMSrcMemCC

# CHECK: cfcmovbq 123(%r16,%r17,4), %r18
# CHECK: encoding: [0x62,0xec,0xf8,0x08,0x42,0x54,0x88,0x7b]
cfcmovbq 123(%r16,%r17,4), %r18

# CHECK: cfcmovbq 123(%r16,%r17,4), %r18, %r19
# CHECK: encoding: [0x62,0xec,0xe0,0x14,0x42,0x54,0x88,0x7b]
cfcmovbq 123(%r16,%r17,4), %r18, %r19

## MRM0m

# CHECK: vprorq $0, (%r16,%r17), %zmm0
Expand Down Expand Up @@ -122,12 +138,24 @@
# CHECK: encoding: [0x62,0xec,0xfc,0x0c,0x01,0xc1]
{nf} addq %r16, %r17

## MRMDestRegCC

# CHECK: cfcmovbq %r16, %r17
# CHECK: encoding: [0x62,0xec,0xfc,0x0c,0x42,0xc1]
cfcmovbq %r16, %r17

## MRMSrcReg

# CHECK: mulxq %r16, %r17, %r18
# CHECK: encoding: [0x62,0xea,0xf7,0x00,0xf6,0xd0]
mulxq %r16, %r17, %r18

## MRMSrcRegCC

# CHECK: cfcmovbq %r16, %r17, %r18
# CHECK: encoding: [0x62,0xec,0xec,0x14,0x42,0xc8]
cfcmovbq %r16, %r17, %r18

## MRMSrcReg4VOp3

# CHECK: bzhiq %r19, %r23, %r27
Expand Down
28 changes: 28 additions & 0 deletions llvm/test/MC/X86/apx/evex-format-intel.s
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Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,12 @@
# CHECK: encoding: [0x62,0xec,0xec,0x10,0x01,0x41,0x7b]
add r18, qword ptr [r17 + 123], r16

## MRMDestMemCC

# CHECK: cfcmovb qword ptr [r17 + 4*r18 + 123], r16
# CHECK: encoding: [0x62,0xec,0xf8,0x0c,0x42,0x44,0x91,0x7b]
cfcmovb qword ptr [r17 + 4*r18 + 123], r16

## MRMSrcMem

# CHECK: vbroadcasti32x4 zmm0, xmmword ptr [r16 + r17]
Expand All @@ -20,6 +26,16 @@
# CHECK: encoding: [0x62,0xec,0xec,0x10,0x2b,0x48,0x7b]
sub r18, r17, qword ptr [r16 + 123]

## MRMSrcMemCC

# CHECK: cfcmovb r18, qword ptr [r16 + 4*r17 + 123]
# CHECK: encoding: [0x62,0xec,0xf8,0x08,0x42,0x54,0x88,0x7b]
cfcmovb r18, qword ptr [r16 + 4*r17 + 123]

# CHECK: cfcmovb r19, r18, qword ptr [r16 + 4*r17 + 123]
# CHECK: encoding: [0x62,0xec,0xe0,0x14,0x42,0x54,0x88,0x7b]
cfcmovb r19, r18, qword ptr [r16 + 4*r17 + 123]

## MRM0m

# CHECK: vprorq zmm0, zmmword ptr [r16 + r17], 0
Expand Down Expand Up @@ -122,12 +138,24 @@
# CHECK: encoding: [0x62,0xec,0xfc,0x0c,0x01,0xc1]
{nf} add r17, r16

## MRMDestRegCC

# CHECK: cfcmovb r17, r16
# CHECK: encoding: [0x62,0xec,0xfc,0x0c,0x42,0xc1]
cfcmovb r17, r16

## MRMSrcReg

# CHECK: mulx r18, r17, r16
# CHECK: encoding: [0x62,0xea,0xf7,0x00,0xf6,0xd0]
mulx r18, r17, r16

## MRMSrcRegCC

# CHECK: cfcmovb r18, r17, r16
# CHECK: encoding: [0x62,0xec,0xec,0x14,0x42,0xc8]
cfcmovb r18, r17, r16

## MRMSrcReg4VOp3

# CHECK: bzhi r27, r23, r19
Expand Down
3 changes: 3 additions & 0 deletions llvm/test/TableGen/x86-fold-tables.inc
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Original file line number Diff line number Diff line change
Expand Up @@ -1937,8 +1937,11 @@ static const X86FoldTableEntry Table2[] = {
{X86::BLENDVPDrr0, X86::BLENDVPDrm0, TB_ALIGN_16},
{X86::BLENDVPSrr0, X86::BLENDVPSrm0, TB_ALIGN_16},
{X86::CMOV16rr, X86::CMOV16rm, 0},
{X86::CMOV16rr_ND, X86::CMOV16rm_ND, 0},
{X86::CMOV32rr, X86::CMOV32rm, 0},
{X86::CMOV32rr_ND, X86::CMOV32rm_ND, 0},
{X86::CMOV64rr, X86::CMOV64rm, 0},
{X86::CMOV64rr_ND, X86::CMOV64rm_ND, 0},
{X86::CMPPDrri, X86::CMPPDrmi, TB_ALIGN_16},
{X86::CMPPSrri, X86::CMPPSrmi, TB_ALIGN_16},
{X86::CMPSDrri, X86::CMPSDrmi, 0},
Expand Down
7 changes: 7 additions & 0 deletions llvm/utils/TableGen/X86ManualFoldTables.def
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Original file line number Diff line number Diff line change
Expand Up @@ -227,6 +227,13 @@ NOFOLD(MMX_MOVQ64rr_REV)
NOFOLD(INSERTPSrr)
NOFOLD(VINSERTPSZrr)
NOFOLD(VINSERTPSrr)
// Memory faults are suppressed for CFCMOV with memory operand.
NOFOLD(CFCMOV16rr_REV)
NOFOLD(CFCMOV32rr_REV)
NOFOLD(CFCMOV64rr_REV)
NOFOLD(CFCMOV16rr_ND)
NOFOLD(CFCMOV32rr_ND)
NOFOLD(CFCMOV64rr_ND)
#undef NOFOLD

#ifndef ENTRY
Expand Down
25 changes: 23 additions & 2 deletions llvm/utils/TableGen/X86RecognizableInstr.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -540,6 +540,13 @@ void RecognizableInstr::emitInstructionSpecifier() {
HANDLE_OPERAND(relocation)
HANDLE_OPERAND(opcodeModifier)
break;
case X86Local::MRMDestRegCC:
assert(numPhysicalOperands == 3 &&
"Unexpected number of operands for MRMDestRegCC");
HANDLE_OPERAND(rmRegister)
HANDLE_OPERAND(roRegister)
HANDLE_OPERAND(opcodeModifier)
break;
case X86Local::MRMDestReg:
// Operand 1 is a register operand in the R/M field.
// - In AVX512 there may be a mask operand here -
Expand All @@ -566,6 +573,13 @@ void RecognizableInstr::emitInstructionSpecifier() {
HANDLE_OPTIONAL(immediate)
HANDLE_OPTIONAL(immediate)
break;
case X86Local::MRMDestMemCC:
assert(numPhysicalOperands == 3 &&
"Unexpected number of operands for MRMDestMemCC");
HANDLE_OPERAND(memory)
HANDLE_OPERAND(roRegister)
HANDLE_OPERAND(opcodeModifier)
break;
case X86Local::MRMDestMem4VOp3CC:
// Operand 1 is a register operand in the Reg/Opcode field.
// Operand 2 is a register operand in the R/M field.
Expand Down Expand Up @@ -650,8 +664,10 @@ void RecognizableInstr::emitInstructionSpecifier() {
HANDLE_OPTIONAL(immediate)
break;
case X86Local::MRMSrcRegCC:
assert(numPhysicalOperands == 3 &&
assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
"Unexpected number of operands for MRMSrcRegCC");
if (IsND)
HANDLE_OPERAND(vvvvRegister)
HANDLE_OPERAND(roRegister)
HANDLE_OPERAND(rmRegister)
HANDLE_OPERAND(opcodeModifier)
Expand Down Expand Up @@ -700,8 +716,10 @@ void RecognizableInstr::emitInstructionSpecifier() {
HANDLE_OPTIONAL(immediate)
break;
case X86Local::MRMSrcMemCC:
assert(numPhysicalOperands == 3 &&
assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
"Unexpected number of operands for MRMSrcMemCC");
if (IsND)
HANDLE_OPERAND(vvvvRegister)
HANDLE_OPERAND(roRegister)
HANDLE_OPERAND(memory)
HANDLE_OPERAND(opcodeModifier)
Expand Down Expand Up @@ -871,6 +889,7 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
filter = std::make_unique<DumbFilter>();
break;
case X86Local::MRMDestReg:
case X86Local::MRMDestRegCC:
case X86Local::MRMSrcReg:
case X86Local::MRMSrcReg4VOp3:
case X86Local::MRMSrcRegOp4:
Expand All @@ -880,6 +899,7 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
filter = std::make_unique<ModFilter>(true);
break;
case X86Local::MRMDestMem:
case X86Local::MRMDestMemCC:
case X86Local::MRMDestMem4VOp3CC:
case X86Local::MRMDestMemFSIB:
case X86Local::MRMSrcMem:
Expand Down Expand Up @@ -950,6 +970,7 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
if (Form == X86Local::AddRegFrm || Form == X86Local::MRMSrcRegCC ||
Form == X86Local::MRMSrcMemCC || Form == X86Local::MRMXrCC ||
Form == X86Local::MRMXmCC || Form == X86Local::AddCCFrm ||
Form == X86Local::MRMDestRegCC || Form == X86Local::MRMDestMemCC ||
Form == X86Local::MRMDestMem4VOp3CC) {
uint8_t Count = Form == X86Local::AddRegFrm ? 8 : 16;
assert(((opcodeToSet % Count) == 0) && "ADDREG_FRM opcode not aligned");
Expand Down
2 changes: 2 additions & 0 deletions llvm/utils/TableGen/X86RecognizableInstr.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -106,6 +106,8 @@ enum {
RawFrmImm16 = 8,
AddCCFrm = 9,
PrefixByte = 10,
MRMDestRegCC = 18,
MRMDestMemCC = 19,
MRMDestMem4VOp3CC = 20,
MRMr0 = 21,
MRMSrcMemFSIB = 22,
Expand Down