41 changes: 17 additions & 24 deletions llvm/utils/TableGen/InfoByHwMode.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -40,8 +40,7 @@ enum : unsigned {
};

template <typename InfoT>
void union_modes(const InfoByHwMode<InfoT> &A,
const InfoByHwMode<InfoT> &B,
void union_modes(const InfoByHwMode<InfoT> &A, const InfoByHwMode<InfoT> &B,
SmallVectorImpl<unsigned> &Modes) {
auto AI = A.begin();
auto BI = B.begin();
Expand Down Expand Up @@ -85,9 +84,8 @@ void union_modes(const InfoByHwMode<InfoT> &A,
Modes.push_back(DefaultMode);
}

template <typename InfoT>
struct InfoByHwMode {
typedef std::map<unsigned,InfoT> MapType;
template <typename InfoT> struct InfoByHwMode {
typedef std::map<unsigned, InfoT> MapType;
typedef typename MapType::value_type PairType;
typedef typename MapType::iterator iterator;
typedef typename MapType::const_iterator const_iterator;
Expand All @@ -98,11 +96,11 @@ struct InfoByHwMode {
LLVM_ATTRIBUTE_ALWAYS_INLINE
iterator begin() { return Map.begin(); }
LLVM_ATTRIBUTE_ALWAYS_INLINE
iterator end() { return Map.end(); }
iterator end() { return Map.end(); }
LLVM_ATTRIBUTE_ALWAYS_INLINE
const_iterator begin() const { return Map.begin(); }
LLVM_ATTRIBUTE_ALWAYS_INLINE
const_iterator end() const { return Map.end(); }
const_iterator end() const { return Map.end(); }
LLVM_ATTRIBUTE_ALWAYS_INLINE
bool empty() const { return Map.empty(); }

Expand Down Expand Up @@ -156,15 +154,13 @@ struct InfoByHwMode {
struct ValueTypeByHwMode : public InfoByHwMode<MVT> {
ValueTypeByHwMode(Record *R, const CodeGenHwModes &CGH);
ValueTypeByHwMode(Record *R, MVT T);
ValueTypeByHwMode(MVT T) { Map.insert({DefaultMode,T}); }
ValueTypeByHwMode(MVT T) { Map.insert({DefaultMode, T}); }
ValueTypeByHwMode() = default;

bool operator== (const ValueTypeByHwMode &T) const;
bool operator< (const ValueTypeByHwMode &T) const;
bool operator==(const ValueTypeByHwMode &T) const;
bool operator<(const ValueTypeByHwMode &T) const;

bool isValid() const {
return !Map.empty();
}
bool isValid() const { return !Map.empty(); }
MVT getType(unsigned Mode) const { return get(Mode); }
MVT &getOrCreateTypeForMode(unsigned Mode, MVT Type);

Expand All @@ -178,8 +174,7 @@ struct ValueTypeByHwMode : public InfoByHwMode<MVT> {
}
};

ValueTypeByHwMode getValueTypeByHwMode(Record *Rec,
const CodeGenHwModes &CGH);
ValueTypeByHwMode getValueTypeByHwMode(Record *Rec, const CodeGenHwModes &CGH);

struct RegSizeInfo {
unsigned RegSize;
Expand All @@ -188,14 +183,12 @@ struct RegSizeInfo {

RegSizeInfo(Record *R, const CodeGenHwModes &CGH);
RegSizeInfo() = default;
bool operator< (const RegSizeInfo &I) const;
bool operator== (const RegSizeInfo &I) const {
bool operator<(const RegSizeInfo &I) const;
bool operator==(const RegSizeInfo &I) const {
return std::tie(RegSize, SpillSize, SpillAlignment) ==
std::tie(I.RegSize, I.SpillSize, I.SpillAlignment);
}
bool operator!= (const RegSizeInfo &I) const {
return !(*this == I);
}
bool operator!=(const RegSizeInfo &I) const { return !(*this == I); }

bool isSubClassOf(const RegSizeInfo &I) const;
void writeToStream(raw_ostream &OS) const;
Expand All @@ -204,9 +197,9 @@ struct RegSizeInfo {
struct RegSizeInfoByHwMode : public InfoByHwMode<RegSizeInfo> {
RegSizeInfoByHwMode(Record *R, const CodeGenHwModes &CGH);
RegSizeInfoByHwMode() = default;
bool operator< (const RegSizeInfoByHwMode &VI) const;
bool operator== (const RegSizeInfoByHwMode &VI) const;
bool operator!= (const RegSizeInfoByHwMode &VI) const {
bool operator<(const RegSizeInfoByHwMode &VI) const;
bool operator==(const RegSizeInfoByHwMode &VI) const;
bool operator!=(const RegSizeInfoByHwMode &VI) const {
return !(*this == VI);
}

Expand All @@ -224,7 +217,7 @@ raw_ostream &operator<<(raw_ostream &OS, const ValueTypeByHwMode &T);
raw_ostream &operator<<(raw_ostream &OS, const RegSizeInfo &T);
raw_ostream &operator<<(raw_ostream &OS, const RegSizeInfoByHwMode &T);

struct EncodingInfoByHwMode : public InfoByHwMode<Record*> {
struct EncodingInfoByHwMode : public InfoByHwMode<Record *> {
EncodingInfoByHwMode(Record *R, const CodeGenHwModes &CGH);
EncodingInfoByHwMode() = default;
};
Expand Down
26 changes: 18 additions & 8 deletions llvm/utils/TableGen/InstrDocsEmitter.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -44,11 +44,18 @@ static std::string escapeForRST(StringRef Str) {
for (char C : Str) {
switch (C) {
// We want special characters to be shown as their C escape codes.
case '\n': Result += "\\n"; break;
case '\t': Result += "\\t"; break;
case '\n':
Result += "\\n";
break;
case '\t':
Result += "\\t";
break;
// Underscore at the end of a line has a special meaning in rst.
case '_': Result += "\\_"; break;
default: Result += C;
case '_':
Result += "\\_";
break;
default:
Result += C;
}
}
return Result;
Expand Down Expand Up @@ -96,7 +103,10 @@ static void EmitInstrDocs(RecordKeeper &RK, raw_ostream &OS) {
std::vector<const char *> FlagStrings;
#define xstr(s) str(s)
#define str(s) #s
#define FLAG(f) if (II->f) { FlagStrings.push_back(str(f)); }
#define FLAG(f) \
if (II->f) { \
FlagStrings.push_back(str(f)); \
}
FLAG(isReturn)
FLAG(isEHScopeReturn)
FLAG(isBranch)
Expand All @@ -111,9 +121,9 @@ static void EmitInstrDocs(RecordKeeper &RK, raw_ostream &OS) {
FLAG(isTrap)
FLAG(canFoldAsLoad)
FLAG(mayLoad)
//FLAG(mayLoad_Unset) // Deliberately omitted.
// FLAG(mayLoad_Unset) // Deliberately omitted.
FLAG(mayStore)
//FLAG(mayStore_Unset) // Deliberately omitted.
// FLAG(mayStore_Unset) // Deliberately omitted.
FLAG(isPredicable)
FLAG(isConvertibleToThreeAddress)
FLAG(isCommutable)
Expand All @@ -125,7 +135,7 @@ static void EmitInstrDocs(RecordKeeper &RK, raw_ostream &OS) {
FLAG(hasCtrlDep)
FLAG(isNotDuplicable)
FLAG(hasSideEffects)
//FLAG(hasSideEffects_Unset) // Deliberately omitted.
// FLAG(hasSideEffects_Unset) // Deliberately omitted.
FLAG(isAsCheapAsAMove)
FLAG(hasExtraSrcRegAllocReq)
FLAG(hasExtraDefRegAllocReq)
Expand Down
178 changes: 108 additions & 70 deletions llvm/utils/TableGen/InstrInfoEmitter.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -53,8 +53,8 @@ class InstrInfoEmitter {
const CodeGenSchedModels &SchedModels;

public:
InstrInfoEmitter(RecordKeeper &R):
Records(R), CDP(R), SchedModels(CDP.getTargetInfo().getSchedModels()) {}
InstrInfoEmitter(RecordKeeper &R)
: Records(R), CDP(R), SchedModels(CDP.getTargetInfo().getSchedModels()) {}

// run - Output the instruction set description.
void run(raw_ostream &OS);
Expand All @@ -69,8 +69,8 @@ class InstrInfoEmitter {
/// The keys of this map are maps which have OpName enum values as their keys
/// and instruction operand indices as their values. The values of this map
/// are lists of instruction names.
typedef std::map<std::map<unsigned, unsigned>,
std::vector<std::string>> OpNameMapTy;
typedef std::map<std::map<unsigned, unsigned>, std::vector<std::string>>
OpNameMapTy;
typedef std::map<std::string, unsigned>::iterator StrUintMapIter;

/// Generate member functions in the target-specific GenInstrInfo class.
Expand All @@ -94,13 +94,14 @@ class InstrInfoEmitter {
void emitOperandTypeMappings(
raw_ostream &OS, const CodeGenTarget &Target,
ArrayRef<const CodeGenInstruction *> NumberedInstructions);
void initOperandMapData(
ArrayRef<const CodeGenInstruction *> NumberedInstructions,
StringRef Namespace,
std::map<std::string, unsigned> &Operands,
OpNameMapTy &OperandMap);
void emitOperandNameMappings(raw_ostream &OS, const CodeGenTarget &Target,
ArrayRef<const CodeGenInstruction*> NumberedInstructions);
void
initOperandMapData(ArrayRef<const CodeGenInstruction *> NumberedInstructions,
StringRef Namespace,
std::map<std::string, unsigned> &Operands,
OpNameMapTy &OperandMap);
void emitOperandNameMappings(
raw_ostream &OS, const CodeGenTarget &Target,
ArrayRef<const CodeGenInstruction *> NumberedInstructions);

void emitLogicalOperandSizeMappings(
raw_ostream &OS, StringRef Namespace,
Expand Down Expand Up @@ -193,8 +194,7 @@ InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
// Fill in constraint info.
Res += ", ";

const CGIOperandList::ConstraintInfo &Constraint =
Op.Constraints[j];
const CGIOperandList::ConstraintInfo &Constraint = Op.Constraints[j];
if (Constraint.isNone())
Res += "0";
else if (Constraint.isEarlyClobber())
Expand Down Expand Up @@ -246,10 +246,9 @@ void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS,
/// each instructions. This is used to generate the OperandMap table as
/// well as the getNamedOperandIdx() function.
void InstrInfoEmitter::initOperandMapData(
ArrayRef<const CodeGenInstruction *> NumberedInstructions,
StringRef Namespace,
std::map<std::string, unsigned> &Operands,
OpNameMapTy &OperandMap) {
ArrayRef<const CodeGenInstruction *> NumberedInstructions,
StringRef Namespace, std::map<std::string, unsigned> &Operands,
OpNameMapTy &OperandMap) {
unsigned NumOperands = 0;
for (const CodeGenInstruction *Inst : NumberedInstructions) {
if (!Inst->TheDef->getValueAsBit("UseNamedOperandTable"))
Expand All @@ -259,13 +258,13 @@ void InstrInfoEmitter::initOperandMapData(
StrUintMapIter I = Operands.find(Info.Name);

if (I == Operands.end()) {
I = Operands.insert(Operands.begin(),
std::pair<std::string, unsigned>(Info.Name, NumOperands++));
I = Operands.insert(Operands.begin(), std::pair<std::string, unsigned>(
Info.Name, NumOperands++));
}
OpList[I->second] = Info.MIOperandNo;
}
OperandMap[OpList].push_back(Namespace.str() + "::" +
Inst->TheDef->getName().str());
OperandMap[OpList].push_back(Namespace.str() +
"::" + Inst->TheDef->getName().str());
}
}

Expand All @@ -280,9 +279,9 @@ void InstrInfoEmitter::initOperandMapData(
/// - A function called getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
/// for looking up the operand index for an instruction, given a value from
/// OpName enum
void InstrInfoEmitter::emitOperandNameMappings(raw_ostream &OS,
const CodeGenTarget &Target,
ArrayRef<const CodeGenInstruction*> NumberedInstructions) {
void InstrInfoEmitter::emitOperandNameMappings(
raw_ostream &OS, const CodeGenTarget &Target,
ArrayRef<const CodeGenInstruction *> NumberedInstructions) {
StringRef Namespace = Target.getInstNamespace();
std::string OpNameNS = "OpName";
// Map of operand names to their enumeration value. This will be used to
Expand Down Expand Up @@ -380,7 +379,8 @@ void InstrInfoEmitter::emitOperandTypeMappings(
}
}

OS << " OPERAND_TYPE_LIST_END" << "\n};\n";
OS << " OPERAND_TYPE_LIST_END"
<< "\n};\n";
OS << "} // end namespace OpTypes\n";
OS << "} // end namespace " << Namespace << "\n";
OS << "} // end namespace llvm\n";
Expand Down Expand Up @@ -685,7 +685,7 @@ void InstrInfoEmitter::emitMCIIHelperMethods(raw_ostream &OS,

for (const Record *Rec : TIIPredicates) {
OS << "bool " << Rec->getValueAsString("FunctionName")
<< "(const MCInst &MI);\n";
<< "(const MCInst &MI);\n";
}

OS << "void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset "
Expand Down Expand Up @@ -939,7 +939,7 @@ void InstrInfoEmitter::run(raw_ostream &OS) {

// Collect all of the instruction's implicit uses and defs.
Records.startTimer("Collect uses/defs");
std::map<std::vector<Record*>, unsigned> EmittedLists;
std::map<std::vector<Record *>, unsigned> EmittedLists;
std::vector<std::vector<Record *>> ImplicitLists;
unsigned ImplicitListSize = 0;
for (const CodeGenInstruction *II : Target.getInstructionsByEnumValue()) {
Expand Down Expand Up @@ -1017,7 +1017,7 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
InstrNames.emitStringLiteralDef(OS, Twine("extern const char ") + TargetName +
"InstrNameData[]");

OS << "extern const unsigned " << TargetName <<"InstrNameIndices[] = {";
OS << "extern const unsigned " << TargetName << "InstrNameIndices[] = {";
Num = 0;
for (const CodeGenInstruction *Inst : NumberedInstructions) {
// Newline every eight entries.
Expand Down Expand Up @@ -1104,7 +1104,6 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
"unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);\n"
<< " ~" << ClassName << "() override = default;\n";


OS << "\n};\n} // end namespace llvm\n";

OS << "#endif // GET_INSTRINFO_HEADER\n\n";
Expand Down Expand Up @@ -1180,8 +1179,8 @@ void InstrInfoEmitter::emitRecord(
int MinOperands = 0;
if (!Inst.Operands.empty())
// Each logical operand can be multiple MI operands.
MinOperands = Inst.Operands.back().MIOperandNo +
Inst.Operands.back().MINumOperands;
MinOperands =
Inst.Operands.back().MIOperandNo + Inst.Operands.back().MINumOperands;

OS << " { ";
OS << Num << ",\t" << MinOperands << ",\t" << Inst.Operands.NumDefs << ",\t"
Expand All @@ -1202,49 +1201,88 @@ void InstrInfoEmitter::emitRecord(
OS << OperandInfoMap.find(OperandInfo)->second << ",\t0";

// Emit all of the target independent flags...
if (Inst.isPreISelOpcode) OS << "|(1ULL<<MCID::PreISelOpcode)";
if (Inst.isPseudo) OS << "|(1ULL<<MCID::Pseudo)";
if (Inst.isMeta) OS << "|(1ULL<<MCID::Meta)";
if (Inst.isReturn) OS << "|(1ULL<<MCID::Return)";
if (Inst.isEHScopeReturn) OS << "|(1ULL<<MCID::EHScopeReturn)";
if (Inst.isBranch) OS << "|(1ULL<<MCID::Branch)";
if (Inst.isIndirectBranch) OS << "|(1ULL<<MCID::IndirectBranch)";
if (Inst.isCompare) OS << "|(1ULL<<MCID::Compare)";
if (Inst.isMoveImm) OS << "|(1ULL<<MCID::MoveImm)";
if (Inst.isMoveReg) OS << "|(1ULL<<MCID::MoveReg)";
if (Inst.isBitcast) OS << "|(1ULL<<MCID::Bitcast)";
if (Inst.isAdd) OS << "|(1ULL<<MCID::Add)";
if (Inst.isTrap) OS << "|(1ULL<<MCID::Trap)";
if (Inst.isSelect) OS << "|(1ULL<<MCID::Select)";
if (Inst.isBarrier) OS << "|(1ULL<<MCID::Barrier)";
if (Inst.hasDelaySlot) OS << "|(1ULL<<MCID::DelaySlot)";
if (Inst.isCall) OS << "|(1ULL<<MCID::Call)";
if (Inst.canFoldAsLoad) OS << "|(1ULL<<MCID::FoldableAsLoad)";
if (Inst.mayLoad) OS << "|(1ULL<<MCID::MayLoad)";
if (Inst.mayStore) OS << "|(1ULL<<MCID::MayStore)";
if (Inst.mayRaiseFPException) OS << "|(1ULL<<MCID::MayRaiseFPException)";
if (Inst.isPredicable) OS << "|(1ULL<<MCID::Predicable)";
if (Inst.isConvertibleToThreeAddress) OS << "|(1ULL<<MCID::ConvertibleTo3Addr)";
if (Inst.isCommutable) OS << "|(1ULL<<MCID::Commutable)";
if (Inst.isTerminator) OS << "|(1ULL<<MCID::Terminator)";
if (Inst.isReMaterializable) OS << "|(1ULL<<MCID::Rematerializable)";
if (Inst.isNotDuplicable) OS << "|(1ULL<<MCID::NotDuplicable)";
if (Inst.Operands.hasOptionalDef) OS << "|(1ULL<<MCID::HasOptionalDef)";
if (Inst.usesCustomInserter) OS << "|(1ULL<<MCID::UsesCustomInserter)";
if (Inst.hasPostISelHook) OS << "|(1ULL<<MCID::HasPostISelHook)";
if (Inst.Operands.isVariadic)OS << "|(1ULL<<MCID::Variadic)";
if (Inst.hasSideEffects) OS << "|(1ULL<<MCID::UnmodeledSideEffects)";
if (Inst.isAsCheapAsAMove) OS << "|(1ULL<<MCID::CheapAsAMove)";
if (Inst.isPreISelOpcode)
OS << "|(1ULL<<MCID::PreISelOpcode)";
if (Inst.isPseudo)
OS << "|(1ULL<<MCID::Pseudo)";
if (Inst.isMeta)
OS << "|(1ULL<<MCID::Meta)";
if (Inst.isReturn)
OS << "|(1ULL<<MCID::Return)";
if (Inst.isEHScopeReturn)
OS << "|(1ULL<<MCID::EHScopeReturn)";
if (Inst.isBranch)
OS << "|(1ULL<<MCID::Branch)";
if (Inst.isIndirectBranch)
OS << "|(1ULL<<MCID::IndirectBranch)";
if (Inst.isCompare)
OS << "|(1ULL<<MCID::Compare)";
if (Inst.isMoveImm)
OS << "|(1ULL<<MCID::MoveImm)";
if (Inst.isMoveReg)
OS << "|(1ULL<<MCID::MoveReg)";
if (Inst.isBitcast)
OS << "|(1ULL<<MCID::Bitcast)";
if (Inst.isAdd)
OS << "|(1ULL<<MCID::Add)";
if (Inst.isTrap)
OS << "|(1ULL<<MCID::Trap)";
if (Inst.isSelect)
OS << "|(1ULL<<MCID::Select)";
if (Inst.isBarrier)
OS << "|(1ULL<<MCID::Barrier)";
if (Inst.hasDelaySlot)
OS << "|(1ULL<<MCID::DelaySlot)";
if (Inst.isCall)
OS << "|(1ULL<<MCID::Call)";
if (Inst.canFoldAsLoad)
OS << "|(1ULL<<MCID::FoldableAsLoad)";
if (Inst.mayLoad)
OS << "|(1ULL<<MCID::MayLoad)";
if (Inst.mayStore)
OS << "|(1ULL<<MCID::MayStore)";
if (Inst.mayRaiseFPException)
OS << "|(1ULL<<MCID::MayRaiseFPException)";
if (Inst.isPredicable)
OS << "|(1ULL<<MCID::Predicable)";
if (Inst.isConvertibleToThreeAddress)
OS << "|(1ULL<<MCID::ConvertibleTo3Addr)";
if (Inst.isCommutable)
OS << "|(1ULL<<MCID::Commutable)";
if (Inst.isTerminator)
OS << "|(1ULL<<MCID::Terminator)";
if (Inst.isReMaterializable)
OS << "|(1ULL<<MCID::Rematerializable)";
if (Inst.isNotDuplicable)
OS << "|(1ULL<<MCID::NotDuplicable)";
if (Inst.Operands.hasOptionalDef)
OS << "|(1ULL<<MCID::HasOptionalDef)";
if (Inst.usesCustomInserter)
OS << "|(1ULL<<MCID::UsesCustomInserter)";
if (Inst.hasPostISelHook)
OS << "|(1ULL<<MCID::HasPostISelHook)";
if (Inst.Operands.isVariadic)
OS << "|(1ULL<<MCID::Variadic)";
if (Inst.hasSideEffects)
OS << "|(1ULL<<MCID::UnmodeledSideEffects)";
if (Inst.isAsCheapAsAMove)
OS << "|(1ULL<<MCID::CheapAsAMove)";
if (!Target.getAllowRegisterRenaming() || Inst.hasExtraSrcRegAllocReq)
OS << "|(1ULL<<MCID::ExtraSrcRegAllocReq)";
if (!Target.getAllowRegisterRenaming() || Inst.hasExtraDefRegAllocReq)
OS << "|(1ULL<<MCID::ExtraDefRegAllocReq)";
if (Inst.isRegSequence) OS << "|(1ULL<<MCID::RegSequence)";
if (Inst.isExtractSubreg) OS << "|(1ULL<<MCID::ExtractSubreg)";
if (Inst.isInsertSubreg) OS << "|(1ULL<<MCID::InsertSubreg)";
if (Inst.isConvergent) OS << "|(1ULL<<MCID::Convergent)";
if (Inst.variadicOpsAreDefs) OS << "|(1ULL<<MCID::VariadicOpsAreDefs)";
if (Inst.isAuthenticated) OS << "|(1ULL<<MCID::Authenticated)";
if (Inst.isRegSequence)
OS << "|(1ULL<<MCID::RegSequence)";
if (Inst.isExtractSubreg)
OS << "|(1ULL<<MCID::ExtractSubreg)";
if (Inst.isInsertSubreg)
OS << "|(1ULL<<MCID::InsertSubreg)";
if (Inst.isConvergent)
OS << "|(1ULL<<MCID::Convergent)";
if (Inst.variadicOpsAreDefs)
OS << "|(1ULL<<MCID::VariadicOpsAreDefs)";
if (Inst.isAuthenticated)
OS << "|(1ULL<<MCID::Authenticated)";

// Emit all of the target-specific flags...
BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags");
Expand Down
42 changes: 21 additions & 21 deletions llvm/utils/TableGen/IntrinsicEmitter.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -60,8 +60,8 @@ class IntrinsicEmitter {
raw_ostream &OS);
void EmitGenerator(const CodeGenIntrinsicTable &Ints, raw_ostream &OS);
void EmitAttributes(const CodeGenIntrinsicTable &Ints, raw_ostream &OS);
void EmitIntrinsicToBuiltinMap(const CodeGenIntrinsicTable &Ints, bool IsClang,
raw_ostream &OS);
void EmitIntrinsicToBuiltinMap(const CodeGenIntrinsicTable &Ints,
bool IsClang, raw_ostream &OS);
};
} // End anonymous namespace

Expand Down Expand Up @@ -204,7 +204,7 @@ void IntrinsicEmitter::EmitIITInfo(raw_ostream &OS) {
}

void IntrinsicEmitter::EmitTargetInfo(const CodeGenIntrinsicTable &Ints,
raw_ostream &OS) {
raw_ostream &OS) {
OS << "// Target mapping\n";
OS << "#ifdef GET_INTRINSIC_TARGET_DATA\n";
OS << "struct IntrinsicTargetInfo {\n"
Expand Down Expand Up @@ -238,10 +238,10 @@ void IntrinsicEmitter::EmitIntrinsicToOverloadTable(
OS << " 0";
for (unsigned i = 0, e = Ints.size(); i != e; ++i) {
// Add one to the index so we emit a null bit for the invalid #0 intrinsic.
if ((i+1)%8 == 0)
if ((i + 1) % 8 == 0)
OS << ",\n 0";
if (Ints[i].isOverloaded)
OS << " | (1<<" << (i+1)%8 << ')';
OS << " | (1<<" << (i + 1) % 8 << ')';
}
OS << "\n};\n\n";
// OTable contains a true bit at the position if the intrinsic is overloaded.
Expand Down Expand Up @@ -271,7 +271,7 @@ void IntrinsicEmitter::EmitGenerator(const CodeGenIntrinsicTable &Ints,
// capture it in this vector, otherwise store a ~0U.
std::vector<unsigned> FixedEncodings;

SequenceToOffsetTable<std::vector<unsigned char> > LongEncodingTable;
SequenceToOffsetTable<std::vector<unsigned char>> LongEncodingTable;

std::vector<unsigned char> TypeSig;

Expand All @@ -292,7 +292,7 @@ void IntrinsicEmitter::EmitGenerator(const CodeGenIntrinsicTable &Ints,
Failed = true;
break;
}
Result = (Result << 4) | TypeSig[e-i-1];
Result = (Result << 4) | TypeSig[e - i - 1];
}

// If this could be encoded into a 31-bit word, return it.
Expand Down Expand Up @@ -330,7 +330,6 @@ void IntrinsicEmitter::EmitGenerator(const CodeGenIntrinsicTable &Ints,
TypeSig.clear();
ComputeFixedEncoding(Ints[i], TypeSig);


// Otherwise, emit the offset into the long encoding table. We emit it this
// way so that it is easier to read the offset in the .def file.
OS << "(1U<<31) | " << LongEncodingTable.get(TypeSig) << ", ";
Expand All @@ -344,7 +343,7 @@ void IntrinsicEmitter::EmitGenerator(const CodeGenIntrinsicTable &Ints,
LongEncodingTable.emit(OS, printIITEntry);
OS << " 255\n};\n\n";

OS << "#endif\n\n"; // End of GET_INTRINSIC_GENERATOR_GLOBAL
OS << "#endif\n\n"; // End of GET_INTRINSIC_GENERATOR_GLOBAL
}

namespace {
Expand Down Expand Up @@ -393,7 +392,8 @@ std::optional<bool> compareFnAttributes(const CodeGenIntrinsic *L,
// Try to order by readonly/readnone attribute.
uint32_t LK = L->ME.toIntValue();
uint32_t RK = R->ME.toIntValue();
if (LK != RK) return (LK > RK);
if (LK != RK)
return (LK > RK);

return std::nullopt;
}
Expand Down Expand Up @@ -438,8 +438,7 @@ void IntrinsicEmitter::EmitAttributes(const CodeGenIntrinsicTable &Ints,
if (!UniqArgAttributes.try_emplace(Attrs, ID).second)
continue;

assert(is_sorted(Attrs) &&
"Argument attributes are not sorted");
assert(is_sorted(Attrs) && "Argument attributes are not sorted");

OS << " case " << ID << ":\n";
OS << " return AttributeSet::get(C, {\n";
Expand Down Expand Up @@ -473,8 +472,8 @@ void IntrinsicEmitter::EmitAttributes(const CodeGenIntrinsicTable &Ints,
OS << " Attribute::get(C, Attribute::ImmArg),\n";
break;
case CodeGenIntrinsic::Alignment:
OS << " Attribute::get(C, Attribute::Alignment, "
<< Attr.Value << "),\n";
OS << " Attribute::get(C, Attribute::Alignment, " << Attr.Value
<< "),\n";
break;
case CodeGenIntrinsic::Dereferenceable:
OS << " Attribute::get(C, Attribute::Dereferenceable, "
Expand All @@ -489,7 +488,7 @@ void IntrinsicEmitter::EmitAttributes(const CodeGenIntrinsicTable &Ints,
OS << "}\n\n";

// Compute unique function attribute sets.
std::map<const CodeGenIntrinsic*, unsigned, FnAttributeComparator>
std::map<const CodeGenIntrinsic *, unsigned, FnAttributeComparator>
UniqFnAttributes;
OS << "static AttributeSet getIntrinsicFnAttributeSet("
<< "LLVMContext &C, unsigned ID) {\n"
Expand Down Expand Up @@ -542,17 +541,18 @@ void IntrinsicEmitter::EmitAttributes(const CodeGenIntrinsicTable &Ints,
OS << "AttributeList Intrinsic::getAttributes(LLVMContext &C, ID id) {\n";

// Compute the maximum number of attribute arguments and the map
typedef std::map<const CodeGenIntrinsic*, unsigned,
AttributeComparator> UniqAttrMapTy;
typedef std::map<const CodeGenIntrinsic *, unsigned, AttributeComparator>
UniqAttrMapTy;
UniqAttrMapTy UniqAttributes;
unsigned maxArgAttrs = 0;
unsigned AttrNum = 0;
for (unsigned i = 0, e = Ints.size(); i != e; ++i) {
const CodeGenIntrinsic &intrinsic = Ints[i];
maxArgAttrs =
std::max(maxArgAttrs, unsigned(intrinsic.ArgumentAttributes.size()));
std::max(maxArgAttrs, unsigned(intrinsic.ArgumentAttributes.size()));
unsigned &N = UniqAttributes[&intrinsic];
if (N) continue;
if (N)
continue;
N = ++AttrNum;
assert(N < 65536 && "Too many unique attributes for table!");
}
Expand All @@ -564,8 +564,8 @@ void IntrinsicEmitter::EmitAttributes(const CodeGenIntrinsicTable &Ints,
for (unsigned i = 0, e = Ints.size(); i != e; ++i) {
const CodeGenIntrinsic &intrinsic = Ints[i];

OS << " " << UniqAttributes[&intrinsic] << ", // "
<< intrinsic.Name << "\n";
OS << " " << UniqAttributes[&intrinsic] << ", // " << intrinsic.Name
<< "\n";
}
OS << " };\n\n";

Expand Down
9 changes: 4 additions & 5 deletions llvm/utils/TableGen/OptParserEmitter.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -196,9 +196,9 @@ static MarshallingInfo createMarshallingInfo(const Record &R) {
/// working with those options when given an input command line.
static void EmitOptParser(RecordKeeper &Records, raw_ostream &OS) {
// Get the option groups and options.
const std::vector<Record*> &Groups =
Records.getAllDerivedDefinitions("OptionGroup");
std::vector<Record*> Opts = Records.getAllDerivedDefinitions("Option");
const std::vector<Record *> &Groups =
Records.getAllDerivedDefinitions("OptionGroup");
std::vector<Record *> Opts = Records.getAllDerivedDefinitions("Option");

emitSourceFileHeader("Option Parsing Definitions", OS);

Expand Down Expand Up @@ -423,8 +423,7 @@ static void EmitOptParser(RecordKeeper &Records, raw_ostream &OS) {
write_cstring(OS, R.getValueAsString("Values"));
else if (!isa<UnsetInit>(R.getValueInit("ValuesCode"))) {
OS << getOptionName(R) << "_Values";
}
else
} else
OS << "nullptr";
};

Expand Down
4 changes: 2 additions & 2 deletions llvm/utils/TableGen/PredicateExpander.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -101,7 +101,6 @@ void PredicateExpander::expandCheckRegOperand(raw_ostream &OS, int OpIndex,
OS << Reg->getName();
}


void PredicateExpander::expandCheckRegOperandSimple(raw_ostream &OS,
int OpIndex,
StringRef FunctionMapper) {
Expand Down Expand Up @@ -487,7 +486,8 @@ void STIPredicateExpander::expandPrologue(raw_ostream &OS,
OS << "unsigned ProcessorID = getSchedModel().getProcessorID();\n";
}

void STIPredicateExpander::expandOpcodeGroup(raw_ostream &OS, const OpcodeGroup &Group,
void STIPredicateExpander::expandOpcodeGroup(raw_ostream &OS,
const OpcodeGroup &Group,
bool ShouldUpdateOpcodeMask) {
const OpcodeInfo &OI = Group.getOpcodeInfo();
for (const PredicateInfo &PI : OI.getPredicates()) {
Expand Down
94 changes: 48 additions & 46 deletions llvm/utils/TableGen/PseudoLoweringEmitter.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -27,19 +27,19 @@ class PseudoLoweringEmitter {
enum MapKind { Operand, Imm, Reg };
MapKind Kind;
union {
unsigned Operand; // Operand number mapped to.
uint64_t Imm; // Integer immedate value.
Record *Reg; // Physical register.
unsigned Operand; // Operand number mapped to.
uint64_t Imm; // Integer immedate value.
Record *Reg; // Physical register.
} Data;
};
struct PseudoExpansion {
CodeGenInstruction Source; // The source pseudo instruction definition.
CodeGenInstruction Dest; // The destination instruction to lower to.
CodeGenInstruction Source; // The source pseudo instruction definition.
CodeGenInstruction Dest; // The destination instruction to lower to.
IndexedMap<OpData> OperandMap;

PseudoExpansion(CodeGenInstruction &s, CodeGenInstruction &d,
IndexedMap<OpData> &m) :
Source(s), Dest(d), OperandMap(m) {}
IndexedMap<OpData> &m)
: Source(s), Dest(d), OperandMap(m) {}
};

RecordKeeper &Records;
Expand All @@ -57,6 +57,7 @@ class PseudoLoweringEmitter {
unsigned BaseIdx);
void evaluateExpansion(Record *Pseudo);
void emitLoweringEmitter(raw_ostream &o);

public:
PseudoLoweringEmitter(RecordKeeper &R) : Records(R), Target(R) {}

Expand All @@ -69,9 +70,9 @@ class PseudoLoweringEmitter {
// The pseudo expansion really should take a list of dags, not just
// a single dag, so we can do fancier things.

unsigned PseudoLoweringEmitter::
addDagOperandMapping(Record *Rec, DagInit *Dag, CodeGenInstruction &Insn,
IndexedMap<OpData> &OperandMap, unsigned BaseIdx) {
unsigned PseudoLoweringEmitter::addDagOperandMapping(
Record *Rec, DagInit *Dag, CodeGenInstruction &Insn,
IndexedMap<OpData> &OperandMap, unsigned BaseIdx) {
unsigned OpsAdded = 0;
for (unsigned i = 0, e = Dag->getNumArgs(); i != e; ++i) {
if (DefInit *DI = dyn_cast<DefInit>(Dag->getArg(i))) {
Expand All @@ -92,9 +93,9 @@ addDagOperandMapping(Record *Rec, DagInit *Dag, CodeGenInstruction &Insn,
// FIXME: Are the message operand types backward?
if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec) {
PrintError(Rec, "In pseudo instruction '" + Rec->getName() +
"', operand type '" + DI->getDef()->getName() +
"' does not match expansion operand type '" +
Insn.Operands[BaseIdx + i].Rec->getName() + "'");
"', operand type '" + DI->getDef()->getName() +
"' does not match expansion operand type '" +
Insn.Operands[BaseIdx + i].Rec->getName() + "'");
PrintFatalNote(DI->getDef(),
"Value was assigned at the following location:");
}
Expand All @@ -118,7 +119,7 @@ addDagOperandMapping(Record *Rec, DagInit *Dag, CodeGenInstruction &Insn,
// Just add the operands recursively. This is almost certainly
// a constant value for a complex operand (> 1 MI operand).
unsigned NewOps =
addDagOperandMapping(Rec, SubDag, Insn, OperandMap, BaseIdx + i);
addDagOperandMapping(Rec, SubDag, Insn, OperandMap, BaseIdx + i);
OpsAdded += NewOps;
// Since we added more than one, we also need to adjust the base.
BaseIdx += NewOps - 1;
Expand All @@ -140,15 +141,15 @@ void PseudoLoweringEmitter::evaluateExpansion(Record *Rec) {
DefInit *OpDef = dyn_cast<DefInit>(Dag->getOperator());
if (!OpDef) {
PrintError(Rec, "In pseudo instruction '" + Rec->getName() +
"', result operator is not a record");
"', result operator is not a record");
PrintFatalNote(Rec->getValue("ResultInst"),
"Result was assigned at the following location:");
}
Record *Operator = OpDef->getDef();
if (!Operator->isSubClassOf("Instruction")) {
PrintError(Rec, "In pseudo instruction '" + Rec->getName() +
"', result operator '" + Operator->getName() +
"' is not an instruction");
"', result operator '" + Operator->getName() +
"' is not an instruction");
PrintFatalNote(Rec->getValue("ResultInst"),
"Result was assigned at the following location:");
}
Expand All @@ -157,16 +158,16 @@ void PseudoLoweringEmitter::evaluateExpansion(Record *Rec) {

if (Insn.isCodeGenOnly || Insn.isPseudo) {
PrintError(Rec, "In pseudo instruction '" + Rec->getName() +
"', result operator '" + Operator->getName() +
"' cannot be a pseudo instruction");
"', result operator '" + Operator->getName() +
"' cannot be a pseudo instruction");
PrintFatalNote(Rec->getValue("ResultInst"),
"Result was assigned at the following location:");
}

if (Insn.Operands.size() != Dag->getNumArgs()) {
PrintError(Rec, "In pseudo instruction '" + Rec->getName() +
"', result operator '" + Operator->getName() +
"' has the wrong number of operands");
"', result operator '" + Operator->getName() +
"' has the wrong number of operands");
PrintFatalNote(Rec->getValue("ResultInst"),
"Result was assigned at the following location:");
}
Expand Down Expand Up @@ -201,19 +202,19 @@ void PseudoLoweringEmitter::evaluateExpansion(Record *Rec) {
if (OperandMap[Insn.Operands[i].MIOperandNo].Kind != OpData::Operand)
continue;
StringMap<unsigned>::iterator SourceOp =
SourceOperands.find(Dag->getArgNameStr(i));
SourceOperands.find(Dag->getArgNameStr(i));
if (SourceOp == SourceOperands.end()) {
PrintError(Rec, "In pseudo instruction '" + Rec->getName() +
"', output operand '" + Dag->getArgNameStr(i) +
"' has no matching source operand");
"', output operand '" + Dag->getArgNameStr(i) +
"' has no matching source operand");
PrintFatalNote(Rec->getValue("ResultInst"),
"Value was assigned at the following location:");
}
// Map the source operand to the destination operand index for each
// MachineInstr operand.
for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I)
OperandMap[Insn.Operands[i].MIOperandNo + I].Data.Operand =
SourceOp->getValue();
SourceOp->getValue();

LLVM_DEBUG(dbgs() << " " << SourceOp->getValue() << " ==> " << i
<< "\n");
Expand All @@ -226,7 +227,8 @@ void PseudoLoweringEmitter::emitLoweringEmitter(raw_ostream &o) {
// Emit file header.
emitSourceFileHeader("Pseudo-instruction MC lowering Source Fragment", o);

o << "bool " << Target.getName() + "AsmPrinter" << "::\n"
o << "bool " << Target.getName() + "AsmPrinter"
<< "::\n"
<< "emitPseudoExpansionLowering(MCStreamer &OutStreamer,\n"
<< " const MachineInstr *MI) {\n";

Expand All @@ -236,12 +238,12 @@ void PseudoLoweringEmitter::emitLoweringEmitter(raw_ostream &o) {
for (auto &Expansion : Expansions) {
CodeGenInstruction &Source = Expansion.Source;
CodeGenInstruction &Dest = Expansion.Dest;
o << " case " << Source.Namespace << "::"
<< Source.TheDef->getName() << ": {\n"
o << " case " << Source.Namespace << "::" << Source.TheDef->getName()
<< ": {\n"
<< " MCInst TmpInst;\n"
<< " MCOperand MCOp;\n"
<< " TmpInst.setOpcode(" << Dest.Namespace << "::"
<< Dest.TheDef->getName() << ");\n";
<< " TmpInst.setOpcode(" << Dest.Namespace
<< "::" << Dest.TheDef->getName() << ");\n";

// Copy the operands from the source instruction.
// FIXME: Instruction operands with defaults values (predicates and cc_out
Expand All @@ -252,29 +254,29 @@ void PseudoLoweringEmitter::emitLoweringEmitter(raw_ostream &o) {
o << " // Operand: " << DestOperand.Name << "\n";
for (unsigned i = 0, e = DestOperand.MINumOperands; i != e; ++i) {
switch (Expansion.OperandMap[MIOpNo + i].Kind) {
case OpData::Operand:
case OpData::Operand:
o << " lowerOperand(MI->getOperand("
<< Source.Operands[Expansion.OperandMap[MIOpNo].Data
.Operand].MIOperandNo + i
<< Source.Operands[Expansion.OperandMap[MIOpNo].Data.Operand]
.MIOperandNo +
i
<< "), MCOp);\n"
<< " TmpInst.addOperand(MCOp);\n";
break;
case OpData::Imm:
case OpData::Imm:
o << " TmpInst.addOperand(MCOperand::createImm("
<< Expansion.OperandMap[MIOpNo + i].Data.Imm << "));\n";
break;
case OpData::Reg: {
Record *Reg = Expansion.OperandMap[MIOpNo + i].Data.Reg;
o << " TmpInst.addOperand(MCOperand::createReg(";
// "zero_reg" is special.
if (Reg->getName() == "zero_reg")
o << "0";
else
o << Reg->getValueAsString("Namespace") << "::"
<< Reg->getName();
o << "));\n";
break;
}
case OpData::Reg: {
Record *Reg = Expansion.OperandMap[MIOpNo + i].Data.Reg;
o << " TmpInst.addOperand(MCOperand::createReg(";
// "zero_reg" is special.
if (Reg->getName() == "zero_reg")
o << "0";
else
o << Reg->getValueAsString("Namespace") << "::" << Reg->getName();
o << "));\n";
break;
}
}
}
MIOpNo += DestOperand.MINumOperands;
Expand Down
10 changes: 6 additions & 4 deletions llvm/utils/TableGen/RegisterBankEmitter.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -46,7 +46,9 @@ class RegisterBank {
/// Get the human-readable name for the bank.
StringRef getName() const { return TheDef.getValueAsString("Name"); }
/// Get the name of the enumerator in the ID enumeration.
std::string getEnumeratorName() const { return (TheDef.getName() + "ID").str(); }
std::string getEnumeratorName() const {
return (TheDef.getName() + "ID").str();
}

/// Get the name of the array holding the register class coverage data;
std::string getCoverageArrayName() const {
Expand Down Expand Up @@ -212,8 +214,7 @@ static void visitRegisterBankClasses(
}

void RegisterBankEmitter::emitBaseClassImplementation(
raw_ostream &OS, StringRef TargetName,
std::vector<RegisterBank> &Banks) {
raw_ostream &OS, StringRef TargetName, std::vector<RegisterBank> &Banks) {
const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank();
const CodeGenHwModes &CGH = Target.getHwModes();

Expand All @@ -229,7 +230,8 @@ void RegisterBankEmitter::emitBaseClassImplementation(
OS << "const uint32_t " << Bank.getCoverageArrayName() << "[] = {\n";
unsigned LowestIdxInWord = 0;
for (const auto &RCs : RCsGroupedByWord) {
OS << " // " << LowestIdxInWord << "-" << (LowestIdxInWord + 31) << "\n";
OS << " // " << LowestIdxInWord << "-" << (LowestIdxInWord + 31)
<< "\n";
for (const auto &RC : RCs) {
OS << " (1u << (" << RC->getQualifiedIdName() << " - "
<< LowestIdxInWord << ")) |\n";
Expand Down
226 changes: 111 additions & 115 deletions llvm/utils/TableGen/RegisterInfoEmitter.cpp
View file

Large diffs are not rendered by default.

2 changes: 1 addition & 1 deletion llvm/utils/TableGen/SDNodeProperties.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -34,6 +34,6 @@ enum SDNP {

unsigned parseSDPatternOperatorProperties(Record *R);

}
} // namespace llvm

#endif
42 changes: 22 additions & 20 deletions llvm/utils/TableGen/SearchableTableEmitter.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -134,7 +134,7 @@ class SearchableTableEmitter {
Twine("Entry for field '") + Field.Name + "' is null");
return std::string(Entry->first);
}
PrintFatalError(Loc, Twine("invalid field type for field '") + Field.Name +
PrintFatalError(Loc, Twine("invalid field type for field '") + Field.Name +
"'; expected: bit, bits, string, or code");
}

Expand Down Expand Up @@ -173,7 +173,7 @@ class SearchableTableEmitter {
return "uint32_t";
if (NumBits <= 64)
return "uint64_t";
PrintFatalError(Index.Loc, Twine("In table '") + Table.Name +
PrintFatalError(Index.Loc, Twine("In table '") + Table.Name +
"' lookup method '" + Index.Name +
"', key field '" + Field.Name +
"' of type bits is too large");
Expand Down Expand Up @@ -425,7 +425,7 @@ void SearchableTableEmitter::emitLookupFunction(const GenericTable &Table,

OS << " struct KeyType {\n";
for (const auto &Field : Index.Fields) {
OS << " " << searchableFieldType(Table, Index, Field, TypeInTempStruct)
OS << " " << searchableFieldType(Table, Index, Field, TypeInTempStruct)
<< " " << Field.Name << ";\n";
}
OS << " };\n";
Expand All @@ -436,7 +436,7 @@ void SearchableTableEmitter::emitLookupFunction(const GenericTable &Table,
if (isa<StringRecTy>(Field.RecType)) {
OS << ".upper()";
if (IsPrimary)
PrintFatalError(Index.Loc,
PrintFatalError(Index.Loc,
Twine("In table '") + Table.Name +
"', use a secondary lookup method for "
"case-insensitive comparison of field '" +
Expand Down Expand Up @@ -580,7 +580,7 @@ std::unique_ptr<SearchIndex> SearchableTableEmitter::parseSearchIndex(
Twine("In table '") + Table.Name +
"', 'PrimaryKey' or 'Key' refers to nonexistent field '" +
FieldName + "'");

Index->Fields.push_back(*Field);
}

Expand Down Expand Up @@ -643,11 +643,11 @@ void SearchableTableEmitter::collectTableEntries(
} else {
RecTy *Ty = resolveTypes(Field.RecType, TI->getType());
if (!Ty)
PrintFatalError(EntryRec->getValue(Field.Name),
PrintFatalError(EntryRec->getValue(Field.Name),
Twine("Field '") + Field.Name + "' of table '" +
Table.Name + "' entry has incompatible type: " +
TI->getType()->getAsString() + " vs. " +
Field.RecType->getAsString());
Table.Name + "' entry has incompatible type: " +
TI->getType()->getAsString() + " vs. " +
Field.RecType->getAsString());
Field.RecType = Ty;
}
}
Expand Down Expand Up @@ -702,7 +702,7 @@ void SearchableTableEmitter::run(raw_ostream &OS) {
StringRef FilterClass = EnumRec->getValueAsString("FilterClass");
Enum->Class = Records.getClass(FilterClass);
if (!Enum->Class)
PrintFatalError(EnumRec->getValue("FilterClass"),
PrintFatalError(EnumRec->getValue("FilterClass"),
Twine("Enum FilterClass '") + FilterClass +
"' does not exist");

Expand All @@ -723,11 +723,13 @@ void SearchableTableEmitter::run(raw_ostream &OS) {
for (const auto &FieldName : Fields) {
Table->Fields.emplace_back(FieldName); // Construct a GenericField.

if (auto TypeOfRecordVal = TableRec->getValue(("TypeOf_" + FieldName).str())) {
if (!parseFieldType(Table->Fields.back(), TypeOfRecordVal->getValue())) {
PrintError(TypeOfRecordVal,
Twine("Table '") + Table->Name +
"' has invalid 'TypeOf_" + FieldName +
if (auto TypeOfRecordVal =
TableRec->getValue(("TypeOf_" + FieldName).str())) {
if (!parseFieldType(Table->Fields.back(),
TypeOfRecordVal->getValue())) {
PrintError(TypeOfRecordVal,
Twine("Table '") + Table->Name + "' has invalid 'TypeOf_" +
FieldName +
"': " + TypeOfRecordVal->getValue()->getAsString());
PrintFatalNote("The 'TypeOf_xxx' field must be a string naming a "
"GenericEnum record, or \"code\"");
Expand All @@ -737,9 +739,9 @@ void SearchableTableEmitter::run(raw_ostream &OS) {

StringRef FilterClass = TableRec->getValueAsString("FilterClass");
if (!Records.getClass(FilterClass))
PrintFatalError(TableRec->getValue("FilterClass"),
Twine("Table FilterClass '") +
FilterClass + "' does not exist");
PrintFatalError(TableRec->getValue("FilterClass"),
Twine("Table FilterClass '") + FilterClass +
"' does not exist");

RecordVal *FilterClassFieldVal = TableRec->getValue("FilterClassField");
std::vector<Record *> Definitions =
Expand Down Expand Up @@ -779,14 +781,14 @@ void SearchableTableEmitter::run(raw_ostream &OS) {
Record *TableRec = IndexRec->getValueAsDef("Table");
auto It = TableMap.find(TableRec);
if (It == TableMap.end())
PrintFatalError(IndexRec->getValue("Table"),
PrintFatalError(IndexRec->getValue("Table"),
Twine("SearchIndex '") + IndexRec->getName() +
"' refers to nonexistent table '" +
TableRec->getName());

GenericTable &Table = *It->second;
Table.Indices.push_back(
parseSearchIndex(Table, IndexRec->getValue("Key"), IndexRec->getName(),
parseSearchIndex(Table, IndexRec->getValue("Key"), IndexRec->getName(),
IndexRec->getValueAsListOfStrings("Key"),
IndexRec->getValueAsBit("EarlyOut")));
}
Expand Down
12 changes: 6 additions & 6 deletions llvm/utils/TableGen/SequenceToOffsetTable.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -44,7 +44,7 @@ static inline void printChar(raw_ostream &OS, char C) {
///
/// @tparam SeqT The sequence container. (vector or string).
/// @tparam Less A stable comparator for SeqT elements.
template<typename SeqT, typename Less = std::less<typename SeqT::value_type> >
template <typename SeqT, typename Less = std::less<typename SeqT::value_type>>
class SequenceToOffsetTable {
typedef typename SeqT::value_type ElemT;

Expand All @@ -53,8 +53,8 @@ class SequenceToOffsetTable {
struct SeqLess {
Less L;
bool operator()(const SeqT &A, const SeqT &B) const {
return std::lexicographical_compare(A.rbegin(), A.rend(),
B.rbegin(), B.rend(), L);
return std::lexicographical_compare(A.rbegin(), A.rend(), B.rbegin(),
B.rend(), L);
}
};

Expand Down Expand Up @@ -153,15 +153,15 @@ class SequenceToOffsetTable {

/// emit - Print out the table as the body of an array initializer.
/// Use the Print function to print elements.
void emit(raw_ostream &OS,
void (*Print)(raw_ostream&, ElemT),
void emit(raw_ostream &OS, void (*Print)(raw_ostream &, ElemT),
const char *Term = "0") const {
assert((empty() || Entries) && "Call layout() before emit()");
for (typename SeqMap::const_iterator I = Seqs.begin(), E = Seqs.end();
I != E; ++I) {
OS << " /* " << I->second << " */ ";
for (typename SeqT::const_iterator SI = I->first.begin(),
SE = I->first.end(); SI != SE; ++SI) {
SE = I->first.end();
SI != SE; ++SI) {
Print(OS, *SI);
OS << ", ";
}
Expand Down
379 changes: 189 additions & 190 deletions llvm/utils/TableGen/SubtargetEmitter.cpp
View file

Large diffs are not rendered by default.

2 changes: 1 addition & 1 deletion llvm/utils/TableGen/SubtargetFeatureInfo.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -81,7 +81,7 @@ void SubtargetFeatureInfo::emitNameTable(
uint64_t IndexUB = 0;
for (const auto &SF : SubtargetFeatures)
if (IndexUB <= SF.second.Index)
IndexUB = SF.second.Index+1;
IndexUB = SF.second.Index + 1;

std::vector<std::string> Names;
if (IndexUB > 0)
Expand Down
3 changes: 2 additions & 1 deletion llvm/utils/TableGen/SubtargetFeatureInfo.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,8 @@

namespace llvm {
struct SubtargetFeatureInfo;
using SubtargetFeatureInfoMap = std::map<Record *, SubtargetFeatureInfo, LessRecordByID>;
using SubtargetFeatureInfoMap =
std::map<Record *, SubtargetFeatureInfo, LessRecordByID>;

/// Helper class for storing information on a subtarget feature which
/// participates in instruction matching.
Expand Down
2 changes: 0 additions & 2 deletions llvm/utils/TableGen/TableGenBackends.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -46,7 +46,6 @@
// backends, this means that the EmitFoo function is the only thing not in
// the anonymous namespace.


// FIXME: Reorganize TableGen so that build dependencies can be more
// accurately expressed. Currently, touching any of the emitters (or
// anything that they transitively depend on) causes everything dependent
Expand All @@ -57,7 +56,6 @@
// TableGen binary with as few dependencies as possible on the rest of
// LLVM.


namespace llvm {

class raw_ostream;
Expand Down
4 changes: 3 additions & 1 deletion llvm/utils/TableGen/Types.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,9 @@

using namespace llvm;

const char *llvm::getMinimalTypeForRange(uint64_t Range, unsigned MaxSize LLVM_ATTRIBUTE_UNUSED) {
const char *
llvm::getMinimalTypeForRange(uint64_t Range,
unsigned MaxSize LLVM_ATTRIBUTE_UNUSED) {
// TODO: The original callers only used 32 and 64 so these are the only
// values permitted. Rather than widen the supported values we should
// allow 64 for the callers that currently use 32 and remove the
Expand Down
2 changes: 1 addition & 1 deletion llvm/utils/TableGen/Types.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,6 +16,6 @@ namespace llvm {
/// MaxSize indicates the largest size of integer to consider (in bits) and only
/// supports values of at least 32.
const char *getMinimalTypeForRange(uint64_t Range, unsigned MaxSize = 64);
}
} // namespace llvm

#endif
6 changes: 4 additions & 2 deletions llvm/utils/TableGen/WebAssemblyDisassemblerEmitter.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -63,7 +63,8 @@ void emitWebAssemblyDisassemblerTables(
// should be the canonical one. This determines which variant gets
// printed in a disassembly. We want e.g. "call" not "i32.call", and
// "end" when we don't know if its "end_loop" or "end_block" etc.
bool IsCanonicalExisting = CGIP.second->TheDef->getValueAsBit("IsCanonical");
bool IsCanonicalExisting =
CGIP.second->TheDef->getValueAsBit("IsCanonical");
// We already have one marked explicitly as canonical, so keep it.
if (IsCanonicalExisting)
continue;
Expand Down Expand Up @@ -126,7 +127,8 @@ void emitWebAssemblyDisassemblerTables(
++J) {
size_t K = 0;
for (; K < CurOperandList.size(); ++K) {
if (OperandTable[J + K] != CurOperandList[K]) break;
if (OperandTable[J + K] != CurOperandList[K])
break;
}
if (K == CurOperandList.size()) {
OperandStart = J;
Expand Down
11 changes: 6 additions & 5 deletions llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -83,7 +83,8 @@ void X86CompressEVEXTablesEmitter::printTable(const std::vector<Entry> &Table,
void X86CompressEVEXTablesEmitter::printCheckPredicate(
const PredicateInstMap &PredicateInsts, raw_ostream &OS) {

OS << "static bool checkPredicate(unsigned Opc, const X86Subtarget *Subtarget) {\n"
OS << "static bool checkPredicate(unsigned Opc, const X86Subtarget "
"*Subtarget) {\n"
<< " switch (Opc) {\n"
<< " default: return true;\n";
for (const auto &[Key, Val] : PredicateInsts) {
Expand Down Expand Up @@ -207,9 +208,9 @@ void X86CompressEVEXTablesEmitter::run(raw_ostream &OS) {
NewInst = &TempInst;
}
} else {
// For each pre-compression instruction look for a match in the appropriate
// vector (instructions with the same opcode) using function object
// IsMatch.
// For each pre-compression instruction look for a match in the
// appropriate vector (instructions with the same opcode) using function
// object IsMatch.
auto Match = llvm::find_if(CompressedInsts[Opcode], IsMatch(Inst));
if (Match != CompressedInsts[Opcode].end())
NewInst = *Match;
Expand All @@ -225,7 +226,7 @@ void X86CompressEVEXTablesEmitter::run(raw_ostream &OS) {
return Name == "HasAVXNECONVERT" || Name == "HasAVXVNNI" ||
Name == "HasAVXIFMA";
});
if(It!= Predicates.end())
if (It != Predicates.end())
PredicateInsts[*It].push_back(NewInst);
}

Expand Down
4 changes: 1 addition & 3 deletions llvm/utils/TableGen/X86DisassemblerShared.h
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Original file line number Diff line number Diff line change
Expand Up @@ -49,9 +49,7 @@ struct OpcodeDecision {
struct ContextDecision {
OpcodeDecision opcodeDecisions[llvm::X86Disassembler::IC_max];

ContextDecision() {
memset(opcodeDecisions, 0, sizeof(opcodeDecisions));
}
ContextDecision() { memset(opcodeDecisions, 0, sizeof(opcodeDecisions)); }
};

#endif
21 changes: 13 additions & 8 deletions llvm/utils/TableGen/X86DisassemblerTables.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -41,8 +41,9 @@ static inline const char *stringForContext(InstructionContext insnContext) {
break;
#define ENUM_ENTRY_K_B(n, r, d) \
ENUM_ENTRY(n, r, d) \
ENUM_ENTRY(n##_K_B, r, d) ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) \
ENUM_ENTRY(n##_B, r, d) ENUM_ENTRY(n##_KZ_B, r, d)
ENUM_ENTRY(n##_K_B, r, d) \
ENUM_ENTRY(n##_KZ, r, d) \
ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d) ENUM_ENTRY(n##_KZ_B, r, d)
INSTRUCTION_CONTEXTS
#undef ENUM_ENTRY
#undef ENUM_ENTRY_K_B
Expand Down Expand Up @@ -595,8 +596,8 @@ static inline bool outranks(InstructionContext upper,
#define ENUM_ENTRY_K_B(n, r, d) \
ENUM_ENTRY(n, r, d) \
ENUM_ENTRY(n##_K_B, r, d) \
ENUM_ENTRY(n##_KZ_B, r, d) ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) \
ENUM_ENTRY(n##_B, r, d)
ENUM_ENTRY(n##_KZ_B, r, d) \
ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)
static int ranks[IC_max] = {INSTRUCTION_CONTEXTS};
#undef ENUM_ENTRY
#undef ENUM_ENTRY_K_B
Expand Down Expand Up @@ -822,7 +823,8 @@ void DisassemblerTables::emitContextDecision(raw_ostream &o1, raw_ostream &o2,
}

i2--;
o2.indent(i2) << "}};" << "\n";
o2.indent(i2) << "}};"
<< "\n";
}

void DisassemblerTables::emitInstructionInfo(raw_ostream &o,
Expand Down Expand Up @@ -859,7 +861,8 @@ void DisassemblerTables::emitInstructionInfo(raw_ostream &o,
}
o << " },\n";
}
o << "};" << "\n\n";
o << "};"
<< "\n\n";

o.indent(i * 2) << "static const struct InstructionSpecifier ";
o << INSTRUCTIONS_STR "[" << InstructionSpecifiers.size() << "] = {\n";
Expand All @@ -885,7 +888,8 @@ void DisassemblerTables::emitInstructionInfo(raw_ostream &o,
}

i--;
o.indent(i * 2) << "};" << "\n";
o.indent(i * 2) << "};"
<< "\n";
}

void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
Expand Down Expand Up @@ -1004,7 +1008,8 @@ void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
}

i--;
o.indent(i * 2) << "};" << "\n";
o.indent(i * 2) << "};"
<< "\n";
}

void DisassemblerTables::emitContextDecisions(raw_ostream &o1, raw_ostream &o2,
Expand Down
52 changes: 22 additions & 30 deletions llvm/utils/TableGen/X86DisassemblerTables.h
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Original file line number Diff line number Diff line change
Expand Up @@ -91,8 +91,8 @@ class DisassemblerTables {
/// @param ModRMTableNum - next table number for adding to ModRMTable.
/// @param decision - The ModR/M decision to emit. This decision has 256
/// entries - emitModRMDecision decides how to compact it.
void emitModRMDecision(raw_ostream &o1, raw_ostream &o2,
unsigned &i1, unsigned &i2, unsigned &ModRMTableNum,
void emitModRMDecision(raw_ostream &o1, raw_ostream &o2, unsigned &i1,
unsigned &i2, unsigned &ModRMTableNum,
ModRMDecision &decision) const;

/// emitOpcodeDecision - Emits an OpcodeDecision and all its subsidiary ModR/M
Expand All @@ -119,8 +119,8 @@ class DisassemblerTables {
/// @param ModRMTableNum - next table number for adding to ModRMTable.
/// @param decision - The OpcodeDecision to emit along with its subsidiary
/// structures.
void emitOpcodeDecision(raw_ostream &o1, raw_ostream &o2,
unsigned &i1, unsigned &i2, unsigned &ModRMTableNum,
void emitOpcodeDecision(raw_ostream &o1, raw_ostream &o2, unsigned &i1,
unsigned &i2, unsigned &ModRMTableNum,
OpcodeDecision &decision) const;

/// emitContextDecision - Emits a ContextDecision and all its subsidiary
Expand Down Expand Up @@ -153,9 +153,9 @@ class DisassemblerTables {
/// @param decision - The ContextDecision to emit along with its subsidiary
/// structures.
/// @param name - The name for the ContextDecision.
void emitContextDecision(raw_ostream &o1, raw_ostream &o2,
unsigned &i1, unsigned &i2, unsigned &ModRMTableNum,
ContextDecision &decision, const char* name) const;
void emitContextDecision(raw_ostream &o1, raw_ostream &o2, unsigned &i1,
unsigned &i2, unsigned &ModRMTableNum,
ContextDecision &decision, const char *name) const;

/// emitInstructionInfo - Prints the instruction specifier table, which has
/// one entry for each instruction, and contains name and operand
Expand Down Expand Up @@ -200,7 +200,8 @@ class DisassemblerTables {
/// IC is the context corresponding to the mask 0x00, and there are 256
/// possible masks.
///
/// @param o - The output stream to which the context table should be written.
/// @param o - The output stream to which the context table should be
/// written.
/// @param i - The indent level for use with the stream.
void emitContextTable(raw_ostream &o, uint32_t &i) const;

Expand All @@ -213,9 +214,8 @@ class DisassemblerTables {
/// @param i1 - The indent level to use with stream o1.
/// @param i2 - The indent level to use with stream o2.
/// @param ModRMTableNum - next table number for adding to ModRMTable.
void emitContextDecisions(raw_ostream &o1, raw_ostream &o2,
unsigned &i1, unsigned &i2,
unsigned &ModRMTableNum) const;
void emitContextDecisions(raw_ostream &o1, raw_ostream &o2, unsigned &i1,
unsigned &i2, unsigned &ModRMTableNum) const;

/// setTableFields - Uses a ModRMFilter to set the appropriate entries in a
/// ModRMDecision to refer to a particular instruction ID.
Expand All @@ -224,10 +224,9 @@ class DisassemblerTables {
/// @param filter - The filter to use in deciding which entries to populate.
/// @param uid - The unique ID to set matching entries to.
/// @param opcode - The opcode of the instruction, for error reporting.
void setTableFields(ModRMDecision &decision,
const ModRMFilter &filter,
InstrUID uid,
uint8_t opcode);
void setTableFields(ModRMDecision &decision, const ModRMFilter &filter,
InstrUID uid, uint8_t opcode);

public:
/// Constructor - Allocates space for the class decisions and clears them.
DisassemblerTables();
Expand All @@ -247,31 +246,26 @@ class DisassemblerTables {
/// @param insnContext - The context to use (IC, IC_64BIT, etc.)
/// @param opcode - The last byte of the opcode (not counting any escape
/// or extended opcodes).
/// @param filter - The ModRMFilter that decides which ModR/M byte values
/// @param filter - The ModRMFilter that decides which ModR/M byte
/// values
/// correspond to the desired instruction.
/// @param uid - The unique ID of the instruction.
/// @param is32bit - Instructon is only 32-bit
/// @param noPrefix - Instruction record has no prefix.
/// @param ignoresVEX_L - Instruction ignores VEX.L
/// @param ignoresVEX_W - Instruction ignores VEX.W
/// @param AddrSize - Instructions address size 16/32/64. 0 is unspecified
void setTableFields(OpcodeType type,
InstructionContext insnContext,
uint8_t opcode,
const ModRMFilter &filter,
InstrUID uid,
bool is32bit,
bool noPrefix,
bool ignoresVEX_L,
bool ignoresVEX_W,
unsigned AddrSize);
void setTableFields(OpcodeType type, InstructionContext insnContext,
uint8_t opcode, const ModRMFilter &filter, InstrUID uid,
bool is32bit, bool noPrefix, bool ignoresVEX_L,
bool ignoresVEX_W, unsigned AddrSize);

/// specForUID - Returns the instruction specifier for a given unique
/// instruction ID. Used when resolving collisions.
///
/// @param uid - The unique ID of the instruction.
/// @return - A reference to the instruction specifier.
InstructionSpecifier& specForUID(InstrUID uid) {
InstructionSpecifier &specForUID(InstrUID uid) {
if (uid >= InstructionSpecifiers.size())
InstructionSpecifiers.resize(uid + 1);

Expand All @@ -282,9 +276,7 @@ class DisassemblerTables {
// from any instructions added to the tables.
// @return - true if there were; false otherwise.

bool hasConflicts() {
return HasConflicts;
}
bool hasConflicts() { return HasConflicts; }
};

} // namespace X86Disassembler
Expand Down
12 changes: 6 additions & 6 deletions llvm/utils/TableGen/X86ModRMFilters.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -10,14 +10,14 @@

using namespace llvm::X86Disassembler;

void ModRMFilter::anchor() { }
void ModRMFilter::anchor() {}

void DumbFilter::anchor() { }
void DumbFilter::anchor() {}

void ModFilter::anchor() { }
void ModFilter::anchor() {}

void ExtendedFilter::anchor() { }
void ExtendedFilter::anchor() {}

void ExtendedRMFilter::anchor() { }
void ExtendedRMFilter::anchor() {}

void ExactFilter::anchor() { }
void ExactFilter::anchor() {}
29 changes: 14 additions & 15 deletions llvm/utils/TableGen/X86ModRMFilters.h
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Original file line number Diff line number Diff line change
Expand Up @@ -27,9 +27,10 @@ namespace X86Disassembler {
/// ModR/M bytes.
class ModRMFilter {
virtual void anchor();

public:
/// Destructor - Override as necessary.
virtual ~ModRMFilter() { }
virtual ~ModRMFilter() {}

/// isDumb - Indicates whether this filter returns the same value for
/// any value of the ModR/M byte.
Expand All @@ -50,14 +51,11 @@ class ModRMFilter {
/// for operands.
class DumbFilter : public ModRMFilter {
void anchor() override;

public:
bool isDumb() const override {
return true;
}
bool isDumb() const override { return true; }

bool accepts(uint8_t modRM) const override {
return true;
}
bool accepts(uint8_t modRM) const override { return true; }
};

/// ModFilter - Filters based on the mod bits [bits 7-6] of the ModR/M byte.
Expand All @@ -66,6 +64,7 @@ class DumbFilter : public ModRMFilter {
class ModFilter : public ModRMFilter {
void anchor() override;
bool R;

public:
/// Constructor
///
Expand All @@ -86,6 +85,7 @@ class ExtendedFilter : public ModRMFilter {
void anchor() override;
bool R;
uint8_t NNN;

public:
/// Constructor
///
Expand All @@ -95,9 +95,9 @@ class ExtendedFilter : public ModRMFilter {
ExtendedFilter(bool r, uint8_t nnn) : R(r), NNN(nnn) {}

bool accepts(uint8_t modRM) const override {
return (((R && ((modRM & 0xc0) == 0xc0)) ||
(!R && ((modRM & 0xc0) != 0xc0))) &&
(((modRM & 0x38) >> 3) == NNN));
return (
((R && ((modRM & 0xc0) == 0xc0)) || (!R && ((modRM & 0xc0) != 0xc0))) &&
(((modRM & 0x38) >> 3) == NNN));
}
};

Expand All @@ -107,6 +107,7 @@ class ExtendedRMFilter : public ModRMFilter {
void anchor() override;
bool R;
uint8_t NNN;

public:
/// Constructor
///
Expand All @@ -116,24 +117,22 @@ class ExtendedRMFilter : public ModRMFilter {
ExtendedRMFilter(bool r, uint8_t nnn) : R(r), NNN(nnn) {}

bool accepts(uint8_t modRM) const override {
return ((R && ((modRM & 0xc0) == 0xc0)) &&
((modRM & 0x7) == NNN));
return ((R && ((modRM & 0xc0) == 0xc0)) && ((modRM & 0x7) == NNN));
}
};
/// ExactFilter - The occasional extended opcode (such as VMCALL or MONITOR)
/// requires the ModR/M byte to have a specific value.
class ExactFilter : public ModRMFilter {
void anchor() override;
uint8_t ModRM;

public:
/// Constructor
///
/// \param modRM The required value of the full ModR/M byte.
ExactFilter(uint8_t modRM) : ModRM(modRM) {}

bool accepts(uint8_t modRM) const override {
return (ModRM == modRM);
}
bool accepts(uint8_t modRM) const override { return (ModRM == modRM); }
};

} // namespace X86Disassembler
Expand Down
2 changes: 1 addition & 1 deletion llvm/utils/TableGen/X86RecognizableInstr.cpp
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Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
//===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
//===- X86RecognizableInstr.cpp - Disassembler instruction spec -*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
Expand Down
2 changes: 1 addition & 1 deletion llvm/utils/TableGen/X86RecognizableInstr.h
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Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
//===- X86RecognizableInstr.h - Disassembler instruction spec ----*- C++ -*-===//
//===- X86RecognizableInstr.h - Disassembler instruction spec ---*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
Expand Down