36 changes: 18 additions & 18 deletions llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rem-rv64.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -19,7 +19,7 @@ body: |
; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
; CHECK-I-NEXT: $x10 = COPY [[ASHR]](s64)
; CHECK-I-NEXT: $x11 = COPY [[ASHR1]](s64)
; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64)
Expand Down Expand Up @@ -68,7 +68,7 @@ body: |
; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
; CHECK-I-NEXT: $x10 = COPY [[ASHR]](s64)
; CHECK-I-NEXT: $x11 = COPY [[ASHR1]](s64)
; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64)
Expand Down Expand Up @@ -117,7 +117,7 @@ body: |
; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
; CHECK-I-NEXT: $x10 = COPY [[ASHR]](s64)
; CHECK-I-NEXT: $x11 = COPY [[ASHR1]](s64)
; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64)
Expand Down Expand Up @@ -162,7 +162,7 @@ body: |
; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
; CHECK-I-NEXT: $x10 = COPY [[SEXT_INREG]](s64)
; CHECK-I-NEXT: $x11 = COPY [[SEXT_INREG1]](s64)
; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64)
Expand Down Expand Up @@ -197,7 +197,7 @@ body: |
; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
; CHECK-I-NEXT: $x10 = COPY [[COPY]](s64)
; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s64)
; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__moddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64)
Expand Down Expand Up @@ -236,7 +236,7 @@ body: |
; CHECK-I-NEXT: $x11 = COPY [[ASHR]](s64)
; CHECK-I-NEXT: $x12 = COPY %ylo(s64)
; CHECK-I-NEXT: $x13 = COPY [[ASHR1]](s64)
; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__modti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__modti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
Expand All @@ -260,7 +260,7 @@ body: |
; CHECK-M-NEXT: $x11 = COPY [[ASHR]](s64)
; CHECK-M-NEXT: $x12 = COPY %ylo(s64)
; CHECK-M-NEXT: $x13 = COPY [[ASHR1]](s64)
; CHECK-M-NEXT: PseudoCALL target-flags(riscv-plt) &__modti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__modti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-M-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
Expand Down Expand Up @@ -297,7 +297,7 @@ body: |
; CHECK-I-NEXT: $x11 = COPY %hi1(s64)
; CHECK-I-NEXT: $x12 = COPY %lo2(s64)
; CHECK-I-NEXT: $x13 = COPY %hi2(s64)
; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__modti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__modti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
Expand All @@ -315,7 +315,7 @@ body: |
; CHECK-M-NEXT: $x11 = COPY %hi1(s64)
; CHECK-M-NEXT: $x12 = COPY %lo2(s64)
; CHECK-M-NEXT: $x13 = COPY %hi2(s64)
; CHECK-M-NEXT: PseudoCALL target-flags(riscv-plt) &__modti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__modti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-M-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
Expand Down Expand Up @@ -349,7 +349,7 @@ body: |
; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
; CHECK-I-NEXT: $x10 = COPY [[AND]](s64)
; CHECK-I-NEXT: $x11 = COPY [[AND1]](s64)
; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64)
Expand Down Expand Up @@ -392,7 +392,7 @@ body: |
; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
; CHECK-I-NEXT: $x10 = COPY [[AND]](s64)
; CHECK-I-NEXT: $x11 = COPY [[AND1]](s64)
; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64)
Expand Down Expand Up @@ -435,7 +435,7 @@ body: |
; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
; CHECK-I-NEXT: $x10 = COPY [[AND]](s64)
; CHECK-I-NEXT: $x11 = COPY [[AND1]](s64)
; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64)
Expand Down Expand Up @@ -478,7 +478,7 @@ body: |
; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
; CHECK-I-NEXT: $x10 = COPY [[AND]](s64)
; CHECK-I-NEXT: $x11 = COPY [[AND1]](s64)
; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64)
Expand Down Expand Up @@ -513,7 +513,7 @@ body: |
; CHECK-I-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
; CHECK-I-NEXT: $x10 = COPY [[COPY]](s64)
; CHECK-I-NEXT: $x11 = COPY [[COPY1]](s64)
; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umoddi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
; CHECK-I-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: $x10 = COPY [[COPY2]](s64)
Expand Down Expand Up @@ -554,7 +554,7 @@ body: |
; CHECK-I-NEXT: $x11 = COPY [[AND1]](s64)
; CHECK-I-NEXT: $x12 = COPY [[AND2]](s64)
; CHECK-I-NEXT: $x13 = COPY [[AND3]](s64)
; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__umodti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umodti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
Expand All @@ -580,7 +580,7 @@ body: |
; CHECK-M-NEXT: $x11 = COPY [[AND1]](s64)
; CHECK-M-NEXT: $x12 = COPY [[AND2]](s64)
; CHECK-M-NEXT: $x13 = COPY [[AND3]](s64)
; CHECK-M-NEXT: PseudoCALL target-flags(riscv-plt) &__umodti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__umodti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-M-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
Expand Down Expand Up @@ -617,7 +617,7 @@ body: |
; CHECK-I-NEXT: $x11 = COPY %hi1(s64)
; CHECK-I-NEXT: $x12 = COPY %lo2(s64)
; CHECK-I-NEXT: $x13 = COPY %hi2(s64)
; CHECK-I-NEXT: PseudoCALL target-flags(riscv-plt) &__umodti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-I-NEXT: PseudoCALL target-flags(riscv-call) &__umodti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-I-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
; CHECK-I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
Expand All @@ -635,7 +635,7 @@ body: |
; CHECK-M-NEXT: $x11 = COPY %hi1(s64)
; CHECK-M-NEXT: $x12 = COPY %lo2(s64)
; CHECK-M-NEXT: $x13 = COPY %hi2(s64)
; CHECK-M-NEXT: PseudoCALL target-flags(riscv-plt) &__umodti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-M-NEXT: PseudoCALL target-flags(riscv-call) &__umodti3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
; CHECK-M-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
; CHECK-M-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-M-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/float-select-verify.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -67,11 +67,11 @@ define dso_local void @buz(i1 %pred, float %a, float %b) {
; CHECK-NEXT: [[FMV_X_W:%[0-9]+]]:gpr = FMV_X_W killed [[PHI1]]
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2
; CHECK-NEXT: $x10 = COPY [[FMV_X_W]]
; CHECK-NEXT: PseudoCALL target-flags(riscv-plt) @bar, csr_ilp32_lp64, implicit-def dead $x1, implicit $x10, implicit-def $x2
; CHECK-NEXT: PseudoCALL target-flags(riscv-call) @bar, csr_ilp32_lp64, implicit-def dead $x1, implicit $x10, implicit-def $x2
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2
; CHECK-NEXT: $x10 = COPY [[FCVT_L_S]]
; CHECK-NEXT: PseudoCALL target-flags(riscv-plt) @foo, csr_ilp32_lp64, implicit-def dead $x1, implicit $x10, implicit-def $x2
; CHECK-NEXT: PseudoCALL target-flags(riscv-call) @foo, csr_ilp32_lp64, implicit-def dead $x1, implicit $x10, implicit-def $x2
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2
; CHECK-NEXT: PseudoRET
entry:
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/live-sp.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -79,15 +79,15 @@ body: |
; CHECK-NEXT: SW renamable $x1, $x2, 4 :: (store (s32) into %ir.a)
; CHECK-NEXT: renamable $x11 = ADDIW killed renamable $x1, 0
; CHECK-NEXT: $x10 = COPY $x0
; CHECK-NEXT: PseudoCALL target-flags(riscv-plt) @vararg, csr_ilp32_lp64, implicit-def dead $x1, implicit killed $x10, implicit $x11, implicit-def $x2
; CHECK-NEXT: PseudoCALL target-flags(riscv-call) @vararg, csr_ilp32_lp64, implicit-def dead $x1, implicit killed $x10, implicit $x11, implicit-def $x2
; CHECK-NEXT: $x1 = LD $x2, 8 :: (load (s64) from %stack.1)
; CHECK-NEXT: $x2 = frame-destroy ADDI $x2, 16
; CHECK-NEXT: PseudoRET
SW renamable $x1, %stack.0.a, 0 :: (store (s32) into %ir.a)
renamable $x11 = ADDIW killed renamable $x1, 0
ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2
$x10 = COPY $x0
PseudoCALL target-flags(riscv-plt) @vararg, csr_ilp32_lp64, implicit-def dead $x1, implicit killed $x10, implicit $x11, implicit-def $x2
PseudoCALL target-flags(riscv-call) @vararg, csr_ilp32_lp64, implicit-def dead $x1, implicit killed $x10, implicit $x11, implicit-def $x2
ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2
PseudoRET
Expand Down
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/RISCV/make-compressible.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -550,18 +550,18 @@ body: |
; RV32-NEXT: renamable $f10_f = FLW $x10, 0 :: (load (s32) from %ir.g)
; RV32-NEXT: renamable $f11_f = FLW $x10, 4 :: (load (s32) from %ir.arrayidx1)
; RV32-NEXT: renamable $f12_f = FLW killed $x10, 8 :: (load (s32) from %ir.arrayidx2)
; RV32-NEXT: PseudoTAIL target-flags(riscv-plt) @load_common_ptr_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f
; RV32-NEXT: PseudoTAIL target-flags(riscv-call) @load_common_ptr_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f
; RV64-LABEL: name: load_common_ptr_float
; RV64: liveins: $x16
; RV64-NEXT: {{ $}}
; RV64-NEXT: renamable $f10_f = FLW renamable $x16, 0 :: (load (s32) from %ir.g)
; RV64-NEXT: renamable $f11_f = FLW renamable $x16, 4 :: (load (s32) from %ir.arrayidx1)
; RV64-NEXT: renamable $f12_f = FLW killed renamable $x16, 8 :: (load (s32) from %ir.arrayidx2)
; RV64-NEXT: PseudoTAIL target-flags(riscv-plt) @load_common_ptr_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f
; RV64-NEXT: PseudoTAIL target-flags(riscv-call) @load_common_ptr_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f
renamable $f10_f = FLW renamable $x16, 0 :: (load (s32) from %ir.g)
renamable $f11_f = FLW renamable $x16, 4 :: (load (s32) from %ir.arrayidx1)
renamable $f12_f = FLW killed renamable $x16, 8 :: (load (s32) from %ir.arrayidx2)
PseudoTAIL target-flags(riscv-plt) @load_common_ptr_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f
PseudoTAIL target-flags(riscv-call) @load_common_ptr_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f
...
---
Expand All @@ -578,19 +578,19 @@ body: |
; RV32-NEXT: renamable $f10_d = FLD $x10, 0 :: (load (s64) from %ir.g)
; RV32-NEXT: renamable $f11_d = FLD $x10, 8 :: (load (s64) from %ir.arrayidx1)
; RV32-NEXT: renamable $f12_d = FLD killed $x10, 16 :: (load (s64) from %ir.arrayidx2)
; RV32-NEXT: PseudoTAIL target-flags(riscv-plt) @load_common_ptr_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d
; RV32-NEXT: PseudoTAIL target-flags(riscv-call) @load_common_ptr_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d
; RV64-LABEL: name: load_common_ptr_double
; RV64: liveins: $x16
; RV64-NEXT: {{ $}}
; RV64-NEXT: $x10 = ADDI $x16, 0
; RV64-NEXT: renamable $f10_d = FLD $x10, 0 :: (load (s64) from %ir.g)
; RV64-NEXT: renamable $f11_d = FLD $x10, 8 :: (load (s64) from %ir.arrayidx1)
; RV64-NEXT: renamable $f12_d = FLD killed $x10, 16 :: (load (s64) from %ir.arrayidx2)
; RV64-NEXT: PseudoTAIL target-flags(riscv-plt) @load_common_ptr_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d
; RV64-NEXT: PseudoTAIL target-flags(riscv-call) @load_common_ptr_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d
renamable $f10_d = FLD renamable $x16, 0 :: (load (s64) from %ir.g)
renamable $f11_d = FLD renamable $x16, 8 :: (load (s64) from %ir.arrayidx1)
renamable $f12_d = FLD killed renamable $x16, 16 :: (load (s64) from %ir.arrayidx2)
PseudoTAIL target-flags(riscv-plt) @load_common_ptr_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d
PseudoTAIL target-flags(riscv-call) @load_common_ptr_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d
...
---
Expand Down Expand Up @@ -746,18 +746,18 @@ body: |
; RV32-NEXT: renamable $f10_f = FLW $x11, 16 :: (load (s32) from %ir.arrayidx)
; RV32-NEXT: renamable $f11_f = FLW $x11, 20 :: (load (s32) from %ir.arrayidx1)
; RV32-NEXT: renamable $f12_f = FLW killed $x11, 24 :: (load (s32) from %ir.arrayidx2)
; RV32-NEXT: PseudoTAIL target-flags(riscv-plt) @load_large_offset_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f
; RV32-NEXT: PseudoTAIL target-flags(riscv-call) @load_large_offset_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f
; RV64-LABEL: name: load_large_offset_float
; RV64: liveins: $x10
; RV64-NEXT: {{ $}}
; RV64-NEXT: renamable $f10_f = FLW renamable $x10, 400 :: (load (s32) from %ir.arrayidx)
; RV64-NEXT: renamable $f11_f = FLW renamable $x10, 404 :: (load (s32) from %ir.arrayidx1)
; RV64-NEXT: renamable $f12_f = FLW killed renamable $x10, 408 :: (load (s32) from %ir.arrayidx2)
; RV64-NEXT: PseudoTAIL target-flags(riscv-plt) @load_large_offset_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f
; RV64-NEXT: PseudoTAIL target-flags(riscv-call) @load_large_offset_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f
renamable $f10_f = FLW renamable $x10, 400 :: (load (s32) from %ir.arrayidx)
renamable $f11_f = FLW renamable $x10, 404 :: (load (s32) from %ir.arrayidx1)
renamable $f12_f = FLW killed renamable $x10, 408 :: (load (s32) from %ir.arrayidx2)
PseudoTAIL target-flags(riscv-plt) @load_large_offset_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f
PseudoTAIL target-flags(riscv-call) @load_large_offset_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f
...
---
Expand All @@ -774,19 +774,19 @@ body: |
; RV32-NEXT: renamable $f10_d = FLD $x11, 32 :: (load (s64) from %ir.arrayidx)
; RV32-NEXT: renamable $f11_d = FLD $x11, 40 :: (load (s64) from %ir.arrayidx1)
; RV32-NEXT: renamable $f12_d = FLD killed $x11, 48 :: (load (s64) from %ir.arrayidx2)
; RV32-NEXT: PseudoTAIL target-flags(riscv-plt) @load_large_offset_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d
; RV32-NEXT: PseudoTAIL target-flags(riscv-call) @load_large_offset_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d
; RV64-LABEL: name: load_large_offset_double
; RV64: liveins: $x10
; RV64-NEXT: {{ $}}
; RV64-NEXT: $x11 = ADDI $x10, 768
; RV64-NEXT: renamable $f10_d = FLD $x11, 32 :: (load (s64) from %ir.arrayidx)
; RV64-NEXT: renamable $f11_d = FLD $x11, 40 :: (load (s64) from %ir.arrayidx1)
; RV64-NEXT: renamable $f12_d = FLD killed $x11, 48 :: (load (s64) from %ir.arrayidx2)
; RV64-NEXT: PseudoTAIL target-flags(riscv-plt) @load_large_offset_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d
; RV64-NEXT: PseudoTAIL target-flags(riscv-call) @load_large_offset_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d
renamable $f10_d = FLD renamable $x10, 800 :: (load (s64) from %ir.arrayidx)
renamable $f11_d = FLD renamable $x10, 808 :: (load (s64) from %ir.arrayidx1)
renamable $f12_d = FLD killed renamable $x10, 816 :: (load (s64) from %ir.arrayidx2)
PseudoTAIL target-flags(riscv-plt) @load_large_offset_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d
PseudoTAIL target-flags(riscv-call) @load_large_offset_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d
...
---
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/mir-target-flags.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -35,7 +35,7 @@ define i32 @caller(i32 %a) nounwind {
; RV32-SMALL: target-flags(riscv-tprel-hi) @t_le
; RV32-SMALL-NEXT: target-flags(riscv-tprel-add) @t_le
; RV32-SMALL-NEXT: target-flags(riscv-tprel-lo) @t_le
; RV32-SMALL: target-flags(riscv-plt) @callee
; RV32-SMALL: target-flags(riscv-call) @callee
;
; RV32-MED-LABEL: name: caller
; RV32-MED: target-flags(riscv-got-hi) @g_e
Expand All @@ -44,16 +44,16 @@ define i32 @caller(i32 %a) nounwind {
; RV32-MED-NEXT: target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi1>
; RV32-MED: target-flags(riscv-tls-gd-hi) @t_un
; RV32-MED-NEXT: target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi2>
; RV32-MED: target-flags(riscv-plt) &__tls_get_addr
; RV32-MED: target-flags(riscv-call) &__tls_get_addr
; RV32-MED: target-flags(riscv-tls-gd-hi) @t_ld
; RV32-MED-NEXT: target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi3>
; RV32-MED: target-flags(riscv-plt) &__tls_get_addr
; RV32-MED: target-flags(riscv-call) &__tls_get_addr
; RV32-MED: target-flags(riscv-tls-got-hi) @t_ie
; RV32-MED-NEXT: target-flags(riscv-pcrel-lo) <mcsymbol .Lpcrel_hi4>
; RV32-MED: target-flags(riscv-tprel-hi) @t_le
; RV32-MED-NEXT: target-flags(riscv-tprel-add) @t_le
; RV32-MED-NEXT: target-flags(riscv-tprel-lo) @t_le
; RV32-MED: target-flags(riscv-plt) @callee
; RV32-MED: target-flags(riscv-call) @callee
;
%b = load i32, ptr @g_e
%c = load i32, ptr @g_i
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -76,7 +76,7 @@ body: |
; we have to allocate a virtual register to compute it.
; A later run of the the register scavenger won't find an available register
; either so it will have to spill one to the emergency spill slot.
PseudoCALL target-flags(riscv-plt) @foo, csr_ilp32_lp64, implicit-def $x1, implicit-def $x2, implicit $x1, implicit $x5, implicit $x6, implicit $x7, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $x28, implicit $x29, implicit $x30, implicit $x31
PseudoCALL target-flags(riscv-call) @foo, csr_ilp32_lp64, implicit-def $x1, implicit-def $x2, implicit $x1, implicit $x5, implicit $x6, implicit $x7, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $x28, implicit $x29, implicit $x30, implicit $x31
PseudoRET
...
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/rvv/addi-rvv-stack-object.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -53,7 +53,7 @@ body: |
bb.0 (%ir-block.0):
ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2
$x10 = ADDI %stack.0.local0, 0
PseudoCALL target-flags(riscv-plt) @extern, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit-def $x2
PseudoCALL target-flags(riscv-call) @extern, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit-def $x2
ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2
PseudoRET
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -55,6 +55,6 @@ body: |
; we have to allocate a virtual register to compute it.
; A later run of the the register scavenger won't find an available register
; either so it will have to spill one to the emergency spill slot.
PseudoCALL target-flags(riscv-plt) @fixedlen_vector_spillslot, csr_ilp32_lp64, implicit-def $x1, implicit-def $x2, implicit $x1, implicit $x5, implicit $x6, implicit $x7, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $x28, implicit $x29, implicit $x30, implicit $x31
PseudoCALL target-flags(riscv-call) @fixedlen_vector_spillslot, csr_ilp32_lp64, implicit-def $x1, implicit-def $x2, implicit $x1, implicit $x5, implicit $x6, implicit $x7, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $x28, implicit $x29, implicit $x30, implicit $x31
PseudoRET
...
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -87,6 +87,6 @@ body: |
; A later run of the the register scavenger won't find available registers
; either so it will have to spill two to the emergency spill slots
; required for this RVV computation.
PseudoCALL target-flags(riscv-plt) @spillslot, csr_ilp32_lp64, implicit-def $x1, implicit-def $x2, implicit $x1, implicit $x5, implicit $x6, implicit $x7, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $x28, implicit $x29, implicit $x30, implicit $x31
PseudoCALL target-flags(riscv-call) @spillslot, csr_ilp32_lp64, implicit-def $x1, implicit-def $x2, implicit $x1, implicit $x5, implicit $x6, implicit $x7, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $x28, implicit $x29, implicit $x30, implicit $x31
PseudoRET
...
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -188,7 +188,7 @@ body: |
$x10 = ADDI %stack.0.a, 0
$x11 = ADDI %stack.1.b, 0
$x12 = ADDI %stack.2.c, 0
PseudoCALL target-flags(riscv-plt) @extern, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit-def $x2
PseudoCALL target-flags(riscv-call) @extern, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit-def $x2
ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2
PseudoRET
Expand Down Expand Up @@ -233,7 +233,7 @@ body: |
$x10 = ADDI %stack.0.a, 0
$x11 = ADDI %stack.1.b, 0
$x12 = ADDI %stack.2.c, 0
PseudoCALL target-flags(riscv-plt) @extern, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit-def $x2
PseudoCALL target-flags(riscv-call) @extern, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit-def $x2
ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2
PseudoRET
Expand Down Expand Up @@ -278,7 +278,7 @@ body: |
$x10 = ADDI %stack.0.a, 0
$x11 = ADDI %stack.1.b, 0
$x12 = ADDI %stack.2.c, 0
PseudoCALL target-flags(riscv-plt) @extern, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit-def $x2
PseudoCALL target-flags(riscv-call) @extern, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit-def $x2
ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2
PseudoRET
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -189,7 +189,7 @@ body: |
; CHECK-NEXT: renamable $v8 = VL1RE8_V killed $x10 :: (load unknown-size from %stack.1, align 8)
; CHECK-NEXT: PseudoVSE8_V_MF8 killed renamable $v8, renamable $x8, 2, 3 /* e8 */, implicit $vl, implicit $vtype :: (store (s16) into %ir.0, align 1)
; CHECK-NEXT: $x10 = COPY renamable $x9
; CHECK-NEXT: PseudoCALL target-flags(riscv-plt) @fprintf, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit-def $x2, implicit-def dead $x10
; CHECK-NEXT: PseudoCALL target-flags(riscv-call) @fprintf, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit-def $x2, implicit-def dead $x10
; CHECK-NEXT: PseudoBR %bb.1
bb.0.entry:
successors: %bb.1(0x80000000)
Expand Down Expand Up @@ -219,7 +219,7 @@ body: |
PseudoVSE8_V_MF8 killed renamable $v8, renamable $x8, 2, 3, implicit $vl, implicit $vtype :: (store (s16) into %ir.0, align 1)
ADJCALLSTACKDOWN 0, 0, implicit-def dead $x2, implicit $x2
$x10 = COPY renamable $x9
PseudoCALL target-flags(riscv-plt) @fprintf, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit-def $x2, implicit-def dead $x10
PseudoCALL target-flags(riscv-call) @fprintf, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit-def $x2, implicit-def dead $x10
ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2
PseudoBR %bb.1
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/vector-abi.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,7 @@ define void @caller() {
; RV32: SW killed [[ADDI3]], %stack.0, 0 :: (store (s32) into %stack.0)
; RV32: [[ADDI4:%[0-9]+]]:gpr = ADDI %stack.0, 0
; RV32: $x10 = COPY [[ADDI4]]
; RV32: PseudoCALL target-flags(riscv-plt) @callee, csr_ilp32_lp64, implicit-def dead $x1, implicit $x10, implicit-def $x2
; RV32: PseudoCALL target-flags(riscv-call) @callee, csr_ilp32_lp64, implicit-def dead $x1, implicit $x10, implicit-def $x2
; RV32: ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2
; RV32: PseudoRET
; RV64-LABEL: name: caller
Expand All @@ -41,7 +41,7 @@ define void @caller() {
; RV64: SD killed [[ADDI3]], %stack.0, 0 :: (store (s64) into %stack.0)
; RV64: [[ADDI4:%[0-9]+]]:gpr = ADDI %stack.0, 0
; RV64: $x10 = COPY [[ADDI4]]
; RV64: PseudoCALL target-flags(riscv-plt) @callee, csr_ilp32_lp64, implicit-def dead $x1, implicit $x10, implicit-def $x2
; RV64: PseudoCALL target-flags(riscv-call) @callee, csr_ilp32_lp64, implicit-def dead $x1, implicit $x10, implicit-def $x2
; RV64: ADJCALLSTACKUP 0, 0, implicit-def dead $x2, implicit $x2
; RV64: PseudoRET
call void @callee(<4 x i8> <i8 4, i8 5, i8 6, i8 7>)
Expand Down