228 changes: 117 additions & 111 deletions llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -107,15 +107,12 @@ define i8 @test_cttz_i8(i8 %a) nounwind {
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: addi a0, zero, 8
; RV32I-NEXT: andi a2, a1, 255
; RV32I-NEXT: beqz a2, .LBB3_2
; RV32I-NEXT: j .LBB3_1
; RV32I-NEXT: .LBB3_1: # %cond.false
; RV32I-NEXT: addi a0, a1, -1
; RV32I-NEXT: not a1, a1
; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: andi a1, a0, 255
; RV32I-NEXT: beqz a1, .LBB3_1
; RV32I-NEXT: # %bb.2: # %cond.false
; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: not a0, a0
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lui a1, 349525
; RV32I-NEXT: addi a1, a1, 1365
; RV32I-NEXT: srli a2, a0, 1
Expand All @@ -138,7 +135,10 @@ define i8 @test_cttz_i8(i8 %a) nounwind {
; RV32I-NEXT: addi a2, a2, %lo(__mulsi3)
; RV32I-NEXT: jalr a2
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: .LBB3_2: # %cond.end
; RV32I-NEXT: j .LBB3_3
; RV32I-NEXT: .LBB3_1:
; RV32I-NEXT: addi a0, zero, 8
; RV32I-NEXT: .LBB3_3: # %cond.end
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
Expand All @@ -154,17 +154,14 @@ define i16 @test_cttz_i16(i16 %a) nounwind {
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: addi a0, zero, 16
; RV32I-NEXT: lui a2, 16
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: and a2, a1, a2
; RV32I-NEXT: beqz a2, .LBB4_2
; RV32I-NEXT: j .LBB4_1
; RV32I-NEXT: .LBB4_1: # %cond.false
; RV32I-NEXT: addi a0, a1, -1
; RV32I-NEXT: not a1, a1
; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: and a1, a0, a1
; RV32I-NEXT: beqz a1, .LBB4_1
; RV32I-NEXT: # %bb.2: # %cond.false
; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: not a0, a0
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lui a1, 349525
; RV32I-NEXT: addi a1, a1, 1365
; RV32I-NEXT: srli a2, a0, 1
Expand All @@ -187,7 +184,10 @@ define i16 @test_cttz_i16(i16 %a) nounwind {
; RV32I-NEXT: addi a2, a2, %lo(__mulsi3)
; RV32I-NEXT: jalr a2
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: .LBB4_2: # %cond.end
; RV32I-NEXT: j .LBB4_3
; RV32I-NEXT: .LBB4_1:
; RV32I-NEXT: addi a0, zero, 16
; RV32I-NEXT: .LBB4_3: # %cond.end
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
Expand All @@ -203,14 +203,11 @@ define i32 @test_cttz_i32(i32 %a) nounwind {
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: addi a0, zero, 32
; RV32I-NEXT: beqz a1, .LBB5_2
; RV32I-NEXT: j .LBB5_1
; RV32I-NEXT: .LBB5_1: # %cond.false
; RV32I-NEXT: addi a0, a1, -1
; RV32I-NEXT: not a1, a1
; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: beqz a0, .LBB5_1
; RV32I-NEXT: # %bb.2: # %cond.false
; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: not a0, a0
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lui a1, 349525
; RV32I-NEXT: addi a1, a1, 1365
; RV32I-NEXT: srli a2, a0, 1
Expand All @@ -233,7 +230,10 @@ define i32 @test_cttz_i32(i32 %a) nounwind {
; RV32I-NEXT: addi a2, a2, %lo(__mulsi3)
; RV32I-NEXT: jalr a2
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: .LBB5_2: # %cond.end
; RV32I-NEXT: j .LBB5_3
; RV32I-NEXT: .LBB5_1:
; RV32I-NEXT: addi a0, zero, 32
; RV32I-NEXT: .LBB5_3: # %cond.end
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
Expand All @@ -249,13 +249,10 @@ define i32 @test_ctlz_i32(i32 %a) nounwind {
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: addi a0, zero, 32
; RV32I-NEXT: beqz a1, .LBB6_2
; RV32I-NEXT: j .LBB6_1
; RV32I-NEXT: .LBB6_1: # %cond.false
; RV32I-NEXT: srli a0, a1, 1
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: beqz a0, .LBB6_1
; RV32I-NEXT: # %bb.2: # %cond.false
; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: srli a1, a0, 2
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: srli a1, a0, 4
Expand Down Expand Up @@ -287,7 +284,10 @@ define i32 @test_ctlz_i32(i32 %a) nounwind {
; RV32I-NEXT: addi a2, a2, %lo(__mulsi3)
; RV32I-NEXT: jalr a2
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: .LBB6_2: # %cond.end
; RV32I-NEXT: j .LBB6_3
; RV32I-NEXT: .LBB6_1:
; RV32I-NEXT: addi a0, zero, 32
; RV32I-NEXT: .LBB6_3: # %cond.end
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
Expand All @@ -309,58 +309,61 @@ define i64 @test_cttz_i64(i64 %a) nounwind {
; RV32I-NEXT: sw s5, 20(sp)
; RV32I-NEXT: sw s6, 16(sp)
; RV32I-NEXT: sw s7, 12(sp)
; RV32I-NEXT: sw s8, 8(sp)
; RV32I-NEXT: addi s0, sp, 48
; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: addi a0, s2, -1
; RV32I-NEXT: not a1, s2
; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: addi a0, s3, -1
; RV32I-NEXT: not a1, s3
; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: lui a1, 349525
; RV32I-NEXT: addi s4, a1, 1365
; RV32I-NEXT: addi s5, a1, 1365
; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: and a1, a1, s4
; RV32I-NEXT: and a1, a1, s5
; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi s5, a1, 819
; RV32I-NEXT: and a1, a0, s5
; RV32I-NEXT: addi s6, a1, 819
; RV32I-NEXT: and a1, a0, s6
; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, s5
; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi s3, a1, 257
; RV32I-NEXT: addi s4, a1, 257
; RV32I-NEXT: lui a1, %hi(__mulsi3)
; RV32I-NEXT: addi s6, a1, %lo(__mulsi3)
; RV32I-NEXT: addi s7, a1, %lo(__mulsi3)
; RV32I-NEXT: lui a1, 61681
; RV32I-NEXT: addi s7, a1, -241
; RV32I-NEXT: and a0, a0, s7
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: jalr s6
; RV32I-NEXT: addi a1, s1, -1
; RV32I-NEXT: not a2, s1
; RV32I-NEXT: and a1, a2, a1
; RV32I-NEXT: srli a2, a1, 1
; RV32I-NEXT: and a2, a2, s4
; RV32I-NEXT: sub a1, a1, a2
; RV32I-NEXT: and a2, a1, s5
; RV32I-NEXT: srli a1, a1, 2
; RV32I-NEXT: addi s8, a1, -241
; RV32I-NEXT: and a0, a0, s8
; RV32I-NEXT: mv a1, s4
; RV32I-NEXT: jalr s7
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: addi a0, s2, -1
; RV32I-NEXT: not a1, s2
; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: and a1, a1, s5
; RV32I-NEXT: add a1, a2, a1
; RV32I-NEXT: srli a2, a1, 4
; RV32I-NEXT: add a1, a1, a2
; RV32I-NEXT: and a1, a1, s7
; RV32I-NEXT: srli s1, a0, 24
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: jalr s6
; RV32I-NEXT: bnez s2, .LBB7_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: and a1, a0, s6
; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: and a0, a0, s8
; RV32I-NEXT: mv a1, s4
; RV32I-NEXT: jalr s7
; RV32I-NEXT: bnez s3, .LBB7_1
; RV32I-NEXT: # %bb.2:
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: addi s1, a0, 32
; RV32I-NEXT: .LBB7_2:
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: addi a0, a0, 32
; RV32I-NEXT: j .LBB7_3
; RV32I-NEXT: .LBB7_1:
; RV32I-NEXT: srli a0, s1, 24
; RV32I-NEXT: .LBB7_3:
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: lw s8, 8(sp)
; RV32I-NEXT: lw s7, 12(sp)
; RV32I-NEXT: lw s6, 16(sp)
; RV32I-NEXT: lw s5, 20(sp)
Expand Down Expand Up @@ -509,58 +512,61 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
; RV32I-NEXT: sw s5, 20(sp)
; RV32I-NEXT: sw s6, 16(sp)
; RV32I-NEXT: sw s7, 12(sp)
; RV32I-NEXT: sw s8, 8(sp)
; RV32I-NEXT: addi s0, sp, 48
; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: addi a0, s2, -1
; RV32I-NEXT: not a1, s2
; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: addi a0, s3, -1
; RV32I-NEXT: not a1, s3
; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: lui a1, 349525
; RV32I-NEXT: addi s4, a1, 1365
; RV32I-NEXT: addi s5, a1, 1365
; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: and a1, a1, s4
; RV32I-NEXT: and a1, a1, s5
; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi s5, a1, 819
; RV32I-NEXT: and a1, a0, s5
; RV32I-NEXT: addi s6, a1, 819
; RV32I-NEXT: and a1, a0, s6
; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, s5
; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi s3, a1, 257
; RV32I-NEXT: addi s4, a1, 257
; RV32I-NEXT: lui a1, %hi(__mulsi3)
; RV32I-NEXT: addi s6, a1, %lo(__mulsi3)
; RV32I-NEXT: addi s7, a1, %lo(__mulsi3)
; RV32I-NEXT: lui a1, 61681
; RV32I-NEXT: addi s7, a1, -241
; RV32I-NEXT: and a0, a0, s7
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: jalr s6
; RV32I-NEXT: addi a1, s1, -1
; RV32I-NEXT: not a2, s1
; RV32I-NEXT: and a1, a2, a1
; RV32I-NEXT: srli a2, a1, 1
; RV32I-NEXT: and a2, a2, s4
; RV32I-NEXT: sub a1, a1, a2
; RV32I-NEXT: and a2, a1, s5
; RV32I-NEXT: srli a1, a1, 2
; RV32I-NEXT: addi s8, a1, -241
; RV32I-NEXT: and a0, a0, s8
; RV32I-NEXT: mv a1, s4
; RV32I-NEXT: jalr s7
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: addi a0, s2, -1
; RV32I-NEXT: not a1, s2
; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: and a1, a1, s5
; RV32I-NEXT: add a1, a2, a1
; RV32I-NEXT: srli a2, a1, 4
; RV32I-NEXT: add a1, a1, a2
; RV32I-NEXT: and a1, a1, s7
; RV32I-NEXT: srli s1, a0, 24
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: jalr s6
; RV32I-NEXT: bnez s2, .LBB11_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: and a1, a0, s6
; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: and a0, a0, s8
; RV32I-NEXT: mv a1, s4
; RV32I-NEXT: jalr s7
; RV32I-NEXT: bnez s3, .LBB11_1
; RV32I-NEXT: # %bb.2:
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: addi s1, a0, 32
; RV32I-NEXT: .LBB11_2:
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: addi a0, a0, 32
; RV32I-NEXT: j .LBB11_3
; RV32I-NEXT: .LBB11_1:
; RV32I-NEXT: srli a0, s1, 24
; RV32I-NEXT: .LBB11_3:
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: lw s8, 8(sp)
; RV32I-NEXT: lw s7, 12(sp)
; RV32I-NEXT: lw s6, 16(sp)
; RV32I-NEXT: lw s5, 20(sp)
Expand Down
45 changes: 20 additions & 25 deletions llvm/test/CodeGen/RISCV/jumptable.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10,42 +10,37 @@ define void @jt(i32 %in, i32* %out) {
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: blt a2, a0, .LBB0_3
; RV32I-NEXT: j .LBB0_1
; RV32I-NEXT: .LBB0_1: # %entry
; RV32I-NEXT: blt a2, a0, .LBB0_4
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: addi a3, zero, 1
; RV32I-NEXT: beq a0, a3, .LBB0_5
; RV32I-NEXT: j .LBB0_2
; RV32I-NEXT: .LBB0_2: # %entry
; RV32I-NEXT: beq a0, a2, .LBB0_6
; RV32I-NEXT: j .LBB0_9
; RV32I-NEXT: .LBB0_6: # %bb2
; RV32I-NEXT: beq a0, a3, .LBB0_8
; RV32I-NEXT: # %bb.2: # %entry
; RV32I-NEXT: bne a0, a2, .LBB0_10
; RV32I-NEXT: # %bb.3: # %bb2
; RV32I-NEXT: addi a0, zero, 3
; RV32I-NEXT: sw a0, 0(a1)
; RV32I-NEXT: j .LBB0_9
; RV32I-NEXT: .LBB0_3: # %entry
; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: beq a0, a3, .LBB0_7
; RV32I-NEXT: j .LBB0_4
; RV32I-NEXT: j .LBB0_10
; RV32I-NEXT: .LBB0_4: # %entry
; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: beq a0, a3, .LBB0_9
; RV32I-NEXT: # %bb.5: # %entry
; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: beq a0, a2, .LBB0_8
; RV32I-NEXT: j .LBB0_9
; RV32I-NEXT: .LBB0_8: # %bb4
; RV32I-NEXT: bne a0, a2, .LBB0_10
; RV32I-NEXT: # %bb.6: # %bb4
; RV32I-NEXT: addi a0, zero, 1
; RV32I-NEXT: sw a0, 0(a1)
; RV32I-NEXT: .LBB0_9: # %exit
; RV32I-NEXT: j .LBB0_10
; RV32I-NEXT: .LBB0_8: # %bb1
; RV32I-NEXT: addi a0, zero, 4
; RV32I-NEXT: sw a0, 0(a1)
; RV32I-NEXT: j .LBB0_10
; RV32I-NEXT: .LBB0_9: # %bb3
; RV32I-NEXT: sw a2, 0(a1)
; RV32I-NEXT: .LBB0_10: # %exit
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB0_5: # %bb1
; RV32I-NEXT: addi a0, zero, 4
; RV32I-NEXT: sw a0, 0(a1)
; RV32I-NEXT: j .LBB0_9
; RV32I-NEXT: .LBB0_7: # %bb3
; RV32I-NEXT: sw a2, 0(a1)
; RV32I-NEXT: j .LBB0_9
entry:
switch i32 %in, label %exit [
i32 1, label %bb1
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/select-cc.ll
View file
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: llc -mtriple=riscv32 -disable-block-placement -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s

define i32 @foo(i32 %a, i32 *%b) {
Expand Down