62 changes: 45 additions & 17 deletions llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -3958,28 +3958,56 @@ def : InstAlias<"pfalse\t$Pd", (PFALSE PNRasPPR8:$Pd), 0>;
// SVE2.1 non-widening BFloat16 to BFloat16 instructions
//===----------------------------------------------------------------------===//

let Predicates = [HasSVE2p1_or_HasSME2p1, HasB16B16] in {
def BFADD_ZZZ : sve_fp_3op_u_zd<0b00, 0b000, "bfadd", ZPR16>;
def BFSUB_ZZZ : sve_fp_3op_u_zd<0b00, 0b001, "bfsub", ZPR16>;
def BFMUL_ZZZ : sve_fp_3op_u_zd<0b00, 0b010, "bfmul", ZPR16>;
let Predicates = [HasSVE2p1, HasB16B16, UseExperimentalZeroingPseudos] in {
defm BFADD_ZPZZ : sve2p1_bf_2op_p_zds_zeroing<int_aarch64_sve_fadd>;
defm BFSUB_ZPZZ : sve2p1_bf_2op_p_zds_zeroing<int_aarch64_sve_fsub>;
defm BFMUL_ZPZZ : sve2p1_bf_2op_p_zds_zeroing<int_aarch64_sve_fmul>;
defm BFMAXNM_ZPZZ : sve2p1_bf_2op_p_zds_zeroing<int_aarch64_sve_fmaxnm>;
defm BFMINNM_ZPZZ : sve2p1_bf_2op_p_zds_zeroing<int_aarch64_sve_fminnm>;
defm BFMIN_ZPZZ : sve2p1_bf_2op_p_zds_zeroing<int_aarch64_sve_fmin>;
defm BFMAX_ZPZZ : sve2p1_bf_2op_p_zds_zeroing<int_aarch64_sve_fmax>;
} //HasSVE2p1_or_HasSME2p1, HasB16B16, UseExperimentalZeroingPseudos

def BFMLA_ZPmZZ : sve_fp_3op_p_zds_a<0b00, 0b00, "bfmla", ZPR16>;
def BFMLS_ZPmZZ : sve_fp_3op_p_zds_a<0b00, 0b01, "bfmls", ZPR16>;
let Predicates = [HasSVE2p1, HasB16B16] in {

def BFADD_ZPZmZ : sve_fp_2op_p_zds<0b00, 0b0000, "bfadd", ZPR16>;
def BFSUB_ZPZmZ : sve_fp_2op_p_zds<0b00, 0b0001, "bfsub", ZPR16>;
def BFMUL_ZPZmZ : sve_fp_2op_p_zds<0b00, 0b0010, "bfmul", ZPR16>;
def BFMAXNM_ZPZmZ : sve_fp_2op_p_zds<0b00, 0b0100, "bfmaxnm", ZPR16>;
def BFMINNM_ZPZmZ : sve_fp_2op_p_zds<0b00, 0b0101, "bfminnm", ZPR16>;
def BFMAX_ZPZmZ : sve_fp_2op_p_zds<0b00, 0b0110, "bfmax", ZPR16>;
def BFMIN_ZPZmZ : sve_fp_2op_p_zds<0b00, 0b0111, "bfmin", ZPR16>;
defm BFMLA_ZPmZZ : sve_fp_3op_p_zds_a_bf<0b00, "bfmla", "BFMLA_ZPZZZ", AArch64fmla_m1>;
defm BFMLS_ZPmZZ : sve_fp_3op_p_zds_a_bf<0b01, "bfmls", "BFMLS_ZPZZZ", AArch64fmls_m1>;

defm BFMLA_ZZZI : sve2p1_fp_bfma_by_indexed_elem<"bfmla", 0b10>;
defm BFMLS_ZZZI : sve2p1_fp_bfma_by_indexed_elem<"bfmls", 0b11>;
defm BFMLA_ZPZZZ : sve_fp_3op_pred_bf<AArch64fmla_p>;
defm BFMLS_ZPZZZ : sve_fp_3op_pred_bf<AArch64fmls_p>;

defm BFMUL_ZZZI : sve2p1_fp_bfmul_by_indexed_elem<"bfmul">;
defm BFMLA_ZZZI : sve2p1_fp_bfma_by_indexed_elem<"bfmla", 0b10, int_aarch64_sve_fmla_lane>;
defm BFMLS_ZZZI : sve2p1_fp_bfma_by_indexed_elem<"bfmls", 0b11, int_aarch64_sve_fmls_lane>;

def BFCLAMP_ZZZ : sve2p1_fclamp<"bfclamp", 0b00, ZPR16>;
defm BFADD_ZPmZZ : sve2p1_bf_2op_p_zds<0b0000, "bfadd", "BFADD_ZPZZ", AArch64fadd_m1, DestructiveBinaryComm>;
defm BFSUB_ZPmZZ : sve2p1_bf_2op_p_zds<0b0001, "bfsub", "BFSUB_ZPZZ", AArch64fsub_m1, DestructiveBinaryComm>;
defm BFMUL_ZPmZZ : sve2p1_bf_2op_p_zds<0b0010, "bfmul", "BFMUL_ZPZZ", AArch64fmul_m1, DestructiveBinaryComm>;

defm BFADD_ZZZ : sve2p1_bf_3op_u_zd<0b000, "bfadd", fadd, AArch64fadd_p>;
defm BFSUB_ZZZ : sve2p1_bf_3op_u_zd<0b001, "bfsub", fsub, AArch64fsub_p>;
defm BFMUL_ZZZ : sve2p1_bf_3op_u_zd<0b010, "bfmul", fmul, AArch64fmul_p>;

defm BFADD_ZPZZ : sve2p1_bf_bin_pred_zds<AArch64fadd_p>;
defm BFSUB_ZPZZ : sve2p1_bf_bin_pred_zds<AArch64fsub_p>;
defm BFMUL_ZPZZ : sve2p1_bf_bin_pred_zds<AArch64fmul_p>;


defm BFMAX_ZPmZZ : sve2p1_bf_2op_p_zds<0b0110, "bfmax", "BFMAX_ZPZZ", int_aarch64_sve_fmax, DestructiveBinaryComm>;
defm BFMIN_ZPmZZ : sve2p1_bf_2op_p_zds<0b0111, "bfmin", "BFMIN_ZPZZ", int_aarch64_sve_fmin, DestructiveBinaryComm>;

defm BFMAX_ZPZZ : sve2p1_bf_bin_pred_zds<AArch64fmax_p>;
defm BFMIN_ZPZZ : sve2p1_bf_bin_pred_zds<AArch64fmin_p>;


defm BFMAXNM_ZPmZZ : sve2p1_bf_2op_p_zds<0b0100, "bfmaxnm", "BFMAXNM_ZPZZ", int_aarch64_sve_fmaxnm, DestructiveBinaryComm>;
defm BFMINNM_ZPmZZ : sve2p1_bf_2op_p_zds<0b0101, "bfminnm", "BFMINNM_ZPZZ", int_aarch64_sve_fminnm, DestructiveBinaryComm>;

defm BFMAXNM_ZPZZ : sve2p1_bf_bin_pred_zds<AArch64fmaxnm_p>;
defm BFMINNM_ZPZZ : sve2p1_bf_bin_pred_zds<AArch64fminnm_p>;

defm BFMUL_ZZZI : sve2p1_fp_bfmul_by_indexed_elem<"bfmul", int_aarch64_sve_fmul_lane>;

defm BFCLAMP_ZZZ : sve2p1_bfclamp<"bfclamp", int_aarch64_sve_fclamp>;
} // End HasSVE2p1_or_HasSME2p1, HasB16B16


Expand Down
58 changes: 56 additions & 2 deletions llvm/lib/Target/AArch64/SVEInstrFormats.td
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Original file line number Diff line number Diff line change
Expand Up @@ -2118,6 +2118,29 @@ class sve_fp_2op_p_zds<bits<2> sz, bits<4> opc, string asm,
let mayRaiseFPException = 1;
}

multiclass sve2p1_bf_2op_p_zds<bits<4> opc, string asm, string Ps,
SDPatternOperator op, DestructiveInstTypeEnum flags,
string revname="", bit isReverseInstr=0> {
let DestructiveInstType = flags in {
def NAME : sve_fp_2op_p_zds<0b00, opc, asm, ZPR16>,
SVEPseudo2Instr<Ps, 1>, SVEInstr2Rev<NAME , revname , isReverseInstr>;
}

def : SVE_3_Op_Pat<nxv8bf16, op, nxv8i1, nxv8bf16, nxv8bf16, !cast<Instruction>(NAME)>;
}

multiclass sve2p1_bf_bin_pred_zds<SDPatternOperator op> {
def _UNDEF : PredTwoOpPseudo<NAME, ZPR16, FalseLanesUndef>;

def : SVE_3_Op_Pat<nxv8bf16, op, nxv8i1, nxv8bf16, nxv8bf16, !cast<Pseudo>(NAME # _UNDEF)>;
}

multiclass sve2p1_bf_2op_p_zds_zeroing<SDPatternOperator op> {
def _ZERO : PredTwoOpPseudo<NAME, ZPR16, FalseLanesZero>;

def : SVE_3_Op_Pat_SelZero<nxv8bf16, op, nxv8i1, nxv8bf16, nxv8bf16, !cast<Pseudo>(NAME # _ZERO)>;
}

multiclass sve_fp_2op_p_zds<bits<4> opc, string asm, string Ps,
SDPatternOperator op, DestructiveInstTypeEnum flags,
string revname="", bit isReverseInstr=0> {
Expand Down Expand Up @@ -2266,6 +2289,14 @@ multiclass sve_fp_3op_u_zd<bits<3> opc, string asm, SDPatternOperator op,
def : SVE_2_Op_Pred_All_Active<nxv2f64, predicated_op, nxv2i1, nxv2f64, nxv2f64, !cast<Instruction>(NAME # _D)>;
}

multiclass sve2p1_bf_3op_u_zd<bits<3> opc1, string asm, SDPatternOperator op,
SDPatternOperator predicated_op = null_frag> {
def NAME : sve_fp_3op_u_zd<0b00, opc1, asm, ZPR16>;
def : SVE_2_Op_Pat<nxv8bf16, op, nxv8bf16, nxv8bf16, !cast<Instruction>(NAME)>;

def : SVE_2_Op_Pred_All_Active<nxv8bf16, predicated_op, nxv8i1, nxv8bf16, nxv8bf16, !cast<Instruction>(NAME)>;
}

multiclass sve_fp_3op_u_zd_ftsmul<bits<3> opc, string asm, SDPatternOperator op> {
def _H : sve_fp_3op_u_zd<0b01, opc, asm, ZPR16>;
def _S : sve_fp_3op_u_zd<0b10, opc, asm, ZPR32>;
Expand Down Expand Up @@ -2324,6 +2355,14 @@ multiclass sve_fp_3op_p_zds_a<bits<2> opc, string asm, string Ps,
def : SVE_4_Op_Pat<nxv2f64, op, nxv2i1, nxv2f64, nxv2f64, nxv2f64, !cast<Instruction>(NAME # _D)>;
}

multiclass sve_fp_3op_p_zds_a_bf<bits<2> opc, string asm, string Ps,
SDPatternOperator op> {
def NAME : sve_fp_3op_p_zds_a<0b00, opc, asm, ZPR16>,
SVEPseudo2Instr<Ps, 1>, SVEInstr2Rev<NAME, "", 0>;

def : SVE_4_Op_Pat<nxv8bf16, op, nxv8i1, nxv8bf16, nxv8bf16, nxv8bf16, !cast<Instruction>(NAME)>;
}

class sve_fp_3op_p_zds_b<bits<2> sz, bits<2> opc, string asm,
ZPRRegOp zprty>
: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm, zprty:$Za),
Expand Down Expand Up @@ -2391,7 +2430,7 @@ class sve_fp_fma_by_indexed_elem<bits<2> sz, bits<2> opc, string asm,
let mayRaiseFPException = 1;
}

multiclass sve2p1_fp_bfma_by_indexed_elem<string asm, bits<2> opc> {
multiclass sve2p1_fp_bfma_by_indexed_elem<string asm, bits<2> opc, SDPatternOperator op> {
def NAME : sve_fp_fma_by_indexed_elem<{0, ?}, opc, asm, ZPR16, ZPR3b16,
VectorIndexH32b> {
bits<3> Zm;
Expand All @@ -2400,6 +2439,8 @@ multiclass sve2p1_fp_bfma_by_indexed_elem<string asm, bits<2> opc> {
let Inst{20-19} = iop{1-0};
let Inst{18-16} = Zm;
}
def : Pat<(nxv8bf16 (op nxv8bf16:$op1, nxv8bf16:$op2, nxv8bf16:$op3, (i32 VectorIndexH32b_timm:$idx))),
(!cast<Instruction>(NAME) $op1, $op2, $op3, VectorIndexH32b_timm:$idx)>;
}

multiclass sve_fp_fma_by_indexed_elem<bits<2> opc, string asm,
Expand Down Expand Up @@ -2456,14 +2497,16 @@ class sve_fp_fmul_by_indexed_elem<bits<2> sz, bit o2, string asm, ZPRRegOp zprty
let mayRaiseFPException = 1;
}

multiclass sve2p1_fp_bfmul_by_indexed_elem<string asm> {
multiclass sve2p1_fp_bfmul_by_indexed_elem<string asm, SDPatternOperator ir_intrinsic> {
def NAME : sve_fp_fmul_by_indexed_elem<{0, ?}, 0b1, asm, ZPR16, ZPR3b16, VectorIndexH32b> {
bits<3> Zm;
bits<3> iop;
let Inst{22} = iop{2};
let Inst{20-19} = iop{1-0};
let Inst{18-16} = Zm;
}
def : Pat <(nxv8bf16 (ir_intrinsic nxv8bf16:$Op1, nxv8bf16:$Op2, (i32 VectorIndexH32b_timm:$idx))),
(!cast<Instruction>(NAME) $Op1, $Op2, VectorIndexH32b_timm:$idx)>;
}

multiclass sve_fp_fmul_by_indexed_elem<string asm, SDPatternOperator op> {
Expand Down Expand Up @@ -9100,6 +9143,12 @@ multiclass sve_fp_3op_pred_hfd<SDPatternOperator op> {
def : SVE_4_Op_Pat<nxv2f64, op, nxv2i1, nxv2f64, nxv2f64, nxv2f64, !cast<Instruction>(NAME # _D_UNDEF)>;
}

multiclass sve_fp_3op_pred_bf<SDPatternOperator op> {
def _UNDEF : PredThreeOpPseudo<NAME, ZPR16, FalseLanesUndef>;

def : SVE_4_Op_Pat<nxv8bf16, op, nxv8i1, nxv8bf16, nxv8bf16, nxv8bf16, !cast<Instruction>(NAME # _UNDEF)>;
}

// Predicated pseudo integer two operand instructions.
multiclass sve_int_bin_pred_bhsd<SDPatternOperator op> {
def _B_UNDEF : PredTwoOpPseudo<NAME # _B, ZPR8, FalseLanesUndef>;
Expand Down Expand Up @@ -9185,6 +9234,11 @@ multiclass sve2p1_fclamp<string asm, SDPatternOperator op> {
def : SVE_3_Op_Pat<nxv2f64, op, nxv2f64, nxv2f64, nxv2f64, !cast<Instruction>(NAME # _D)>;
}

multiclass sve2p1_bfclamp<string asm, SDPatternOperator op> {
def NAME : sve2p1_fclamp<asm, 0b00, ZPR16>;
def : SVE_3_Op_Pat<nxv8bf16, op, nxv8bf16, nxv8bf16, nxv8bf16, !cast<Instruction>(NAME)>;
}

// SVE two-way dot product
class sve2p1_two_way_dot_vv<string mnemonic, bit u>
: I<(outs ZPR32:$Zda), (ins ZPR32:$_Zda, ZPR16:$Zn, ZPR16:$Zm),
Expand Down
62 changes: 62 additions & 0 deletions llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfadd.ll
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Original file line number Diff line number Diff line change
@@ -0,0 +1,62 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p1 -mattr=+b16b16 -mattr=+use-experimental-zeroing-pseudos -verify-machineinstrs < %s \
; RUN: | FileCheck %s

define <vscale x 8 x bfloat> @bfadd_pred(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b){
; CHECK-LABEL: bfadd_pred:
; CHECK: // %bb.0:
; CHECK-NEXT: bfadd z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT: ret
%res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.nxv8bf16(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b)
ret <vscale x 8 x bfloat> %res
}

define <vscale x 8 x bfloat> @bfadd_zeroing(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) {
; CHECK-LABEL: bfadd_zeroing:
; CHECK: // %bb.0:
; CHECK-NEXT: movprfx z0.h, p0/z, z0.h
; CHECK-NEXT: bfadd z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT: ret
%a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> zeroinitializer
%out = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.nxv8bf16(<vscale x 8 x i1> %pg,
<vscale x 8 x bfloat> %a_z,
<vscale x 8 x bfloat> %b)
ret <vscale x 8 x bfloat> %out
}

define <vscale x 8 x bfloat> @bfadd_u(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b){
; CHECK-LABEL: bfadd_u:
; CHECK: // %bb.0:
; CHECK-NEXT: bfadd z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT: ret
%res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.u.nxv8bf16(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b)
ret <vscale x 8 x bfloat> %res
}

define <vscale x 8 x bfloat> @bfadd_u_ptrue(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b){
; CHECK-LABEL: bfadd_u_ptrue:
; CHECK: // %bb.0:
; CHECK-NEXT: bfadd z0.h, z0.h, z1.h
; CHECK-NEXT: ret
%elt = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
%res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.u.nxv8bf16(<vscale x 8 x i1> %elt, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b)
ret <vscale x 8 x bfloat> %res
}

define <vscale x 8 x bfloat> @bfadd_u_zeroing(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) {
; CHECK-LABEL: bfadd_u_zeroing:
; CHECK: // %bb.0:
; CHECK-NEXT: mov z2.h, #0 // =0x0
; CHECK-NEXT: sel z0.h, p0, z0.h, z2.h
; CHECK-NEXT: bfadd z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT: ret
%a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> zeroinitializer
%out = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.u.nxv8bf16(<vscale x 8 x i1> %pg,
<vscale x 8 x bfloat> %a_z,
<vscale x 8 x bfloat> %b)
ret <vscale x 8 x bfloat> %out
}

declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>)
declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fadd.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>)
declare <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 immarg)
13 changes: 13 additions & 0 deletions llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfclamp.ll
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@@ -0,0 +1,13 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p1 -mattr=+b16b16 -verify-machineinstrs < %s | FileCheck %s

define <vscale x 8 x bfloat> @bfclamp(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c){
; CHECK-LABEL: bfclamp:
; CHECK: // %bb.0:
; CHECK-NEXT: bfclamp z0.h, z1.h, z2.h
; CHECK-NEXT: ret
%res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fclamp.nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c)
ret <vscale x 8 x bfloat> %res
}

declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fclamp.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>)
74 changes: 74 additions & 0 deletions llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfmax.ll
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@@ -0,0 +1,74 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p1 -mattr=+b16b16 -mattr=+use-experimental-zeroing-pseudos -verify-machineinstrs < %s \
; RUN: | FileCheck %s

define <vscale x 8 x bfloat> @bfmax_pred(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b){
; CHECK-LABEL: bfmax_pred:
; CHECK: // %bb.0:
; CHECK-NEXT: bfmax z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT: ret
%res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.nxv8bf16(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b)
ret <vscale x 8 x bfloat> %res
}

define <vscale x 8 x bfloat> @bfmax(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b){
; CHECK-LABEL: bfmax:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: bfmax z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT: ret
%elt = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
%res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.nxv8bf16(<vscale x 8 x i1> %elt, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b)
ret <vscale x 8 x bfloat> %res
}

define <vscale x 8 x bfloat> @bfmax_zeroing(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) {
; CHECK-LABEL: bfmax_zeroing:
; CHECK: // %bb.0:
; CHECK-NEXT: movprfx z0.h, p0/z, z0.h
; CHECK-NEXT: bfmax z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT: ret
%a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> zeroinitializer
%out = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.nxv8bf16(<vscale x 8 x i1> %pg,
<vscale x 8 x bfloat> %a_z,
<vscale x 8 x bfloat> %b)
ret <vscale x 8 x bfloat> %out
}

define <vscale x 8 x bfloat> @bfmax_u_pred(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b){
; CHECK-LABEL: bfmax_u_pred:
; CHECK: // %bb.0:
; CHECK-NEXT: bfmax z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT: ret
%res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.u.nxv8bf16(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b)
ret <vscale x 8 x bfloat> %res
}

define <vscale x 8 x bfloat> @bfmax_u(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b){
; CHECK-LABEL: bfmax_u:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: bfmax z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT: ret
%elt = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
%res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.u.nxv8bf16(<vscale x 8 x i1> %elt, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b)
ret <vscale x 8 x bfloat> %res
}

define <vscale x 8 x bfloat> @bfmax_u_zeroing(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) {
; CHECK-LABEL: bfmax_u_zeroing:
; CHECK: // %bb.0:
; CHECK-NEXT: mov z2.h, #0 // =0x0
; CHECK-NEXT: sel z0.h, p0, z0.h, z2.h
; CHECK-NEXT: bfmax z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT: ret
%a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> zeroinitializer
%out = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.u.nxv8bf16(<vscale x 8 x i1> %pg,
<vscale x 8 x bfloat> %a_z,
<vscale x 8 x bfloat> %b)
ret <vscale x 8 x bfloat> %out
}

declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>)
declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmax.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>)
declare <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 immarg)
74 changes: 74 additions & 0 deletions llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfmaxnm.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p1 -mattr=+b16b16 -mattr=+use-experimental-zeroing-pseudos -verify-machineinstrs < %s \
; RUN: | FileCheck %s

define <vscale x 8 x bfloat> @bfmaxnm_pred(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b){
; CHECK-LABEL: bfmaxnm_pred:
; CHECK: // %bb.0:
; CHECK-NEXT: bfmaxnm z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT: ret
%res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.nxv8bf16(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b)
ret <vscale x 8 x bfloat> %res
}

define <vscale x 8 x bfloat> @bfmaxnm(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b){
; CHECK-LABEL: bfmaxnm:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: bfmaxnm z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT: ret
%elt = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
%res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.nxv8bf16(<vscale x 8 x i1> %elt, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b)
ret <vscale x 8 x bfloat> %res
}

define <vscale x 8 x bfloat> @bfmaxnm_zeroing(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) {
; CHECK-LABEL: bfmaxnm_zeroing:
; CHECK: // %bb.0:
; CHECK-NEXT: movprfx z0.h, p0/z, z0.h
; CHECK-NEXT: bfmaxnm z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT: ret
%a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> zeroinitializer
%out = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.nxv8bf16(<vscale x 8 x i1> %pg,
<vscale x 8 x bfloat> %a_z,
<vscale x 8 x bfloat> %b)
ret <vscale x 8 x bfloat> %out
}

define <vscale x 8 x bfloat> @bfmaxnm_u_pred(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b){
; CHECK-LABEL: bfmaxnm_u_pred:
; CHECK: // %bb.0:
; CHECK-NEXT: bfmaxnm z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT: ret
%res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.u.nxv8bf16(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b)
ret <vscale x 8 x bfloat> %res
}

define <vscale x 8 x bfloat> @bfmaxnm_u(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b){
; CHECK-LABEL: bfmaxnm_u:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: bfmaxnm z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT: ret
%elt = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
%res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.u.nxv8bf16(<vscale x 8 x i1> %elt, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b)
ret <vscale x 8 x bfloat> %res
}

define <vscale x 8 x bfloat> @bfmaxnm_u_zeroing(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) {
; CHECK-LABEL: bfmaxnm_u_zeroing:
; CHECK: // %bb.0:
; CHECK-NEXT: mov z2.h, #0 // =0x0
; CHECK-NEXT: sel z0.h, p0, z0.h, z2.h
; CHECK-NEXT: bfmaxnm z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT: ret
%a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> zeroinitializer
%out = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.u.nxv8bf16(<vscale x 8 x i1> %pg,
<vscale x 8 x bfloat> %a_z,
<vscale x 8 x bfloat> %b)
ret <vscale x 8 x bfloat> %out
}

declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>)
declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmaxnm.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>)
declare <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 immarg)
74 changes: 74 additions & 0 deletions llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfmin.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p1 -mattr=+b16b16 -mattr=+use-experimental-zeroing-pseudos -verify-machineinstrs < %s \
; RUN: | FileCheck %s

define <vscale x 8 x bfloat> @bfmin_pred(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b){
; CHECK-LABEL: bfmin_pred:
; CHECK: // %bb.0:
; CHECK-NEXT: bfmin z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT: ret
%res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.nxv8bf16(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b)
ret <vscale x 8 x bfloat> %res
}

define <vscale x 8 x bfloat> @bfmin(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b){
; CHECK-LABEL: bfmin:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: bfmin z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT: ret
%elt = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
%res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.nxv8bf16(<vscale x 8 x i1> %elt, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b)
ret <vscale x 8 x bfloat> %res
}

define <vscale x 8 x bfloat> @bfmin_zeroing(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) {
; CHECK-LABEL: bfmin_zeroing:
; CHECK: // %bb.0:
; CHECK-NEXT: movprfx z0.h, p0/z, z0.h
; CHECK-NEXT: bfmin z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT: ret
%a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> zeroinitializer
%out = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.nxv8bf16(<vscale x 8 x i1> %pg,
<vscale x 8 x bfloat> %a_z,
<vscale x 8 x bfloat> %b)
ret <vscale x 8 x bfloat> %out
}

define <vscale x 8 x bfloat> @bfmin_u_pred(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b){
; CHECK-LABEL: bfmin_u_pred:
; CHECK: // %bb.0:
; CHECK-NEXT: bfmin z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT: ret
%res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.u.nxv8bf16(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b)
ret <vscale x 8 x bfloat> %res
}

define <vscale x 8 x bfloat> @bfmin_u(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b){
; CHECK-LABEL: bfmin_u:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: bfmin z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT: ret
%elt = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
%res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.u.nxv8bf16(<vscale x 8 x i1> %elt, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b)
ret <vscale x 8 x bfloat> %res
}

define <vscale x 8 x bfloat> @bfmin_u_zeroing(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) {
; CHECK-LABEL: bfmin_u_zeroing:
; CHECK: // %bb.0:
; CHECK-NEXT: mov z2.h, #0 // =0x0
; CHECK-NEXT: sel z0.h, p0, z0.h, z2.h
; CHECK-NEXT: bfmin z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT: ret
%a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> zeroinitializer
%out = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.u.nxv8bf16(<vscale x 8 x i1> %pg,
<vscale x 8 x bfloat> %a_z,
<vscale x 8 x bfloat> %b)
ret <vscale x 8 x bfloat> %out
}

declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>)
declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmin.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>)
declare <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 immarg)
74 changes: 74 additions & 0 deletions llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfminnm.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p1 -mattr=+b16b16 -mattr=+use-experimental-zeroing-pseudos -verify-machineinstrs < %s \
; RUN: | FileCheck %s

define <vscale x 8 x bfloat> @bfminnm_pred(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b){
; CHECK-LABEL: bfminnm_pred:
; CHECK: // %bb.0:
; CHECK-NEXT: bfminnm z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT: ret
%res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.nxv8bf16(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b)
ret <vscale x 8 x bfloat> %res
}

define <vscale x 8 x bfloat> @bfminnm(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b){
; CHECK-LABEL: bfminnm:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: bfminnm z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT: ret
%elt = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
%res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.nxv8bf16(<vscale x 8 x i1> %elt, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b)
ret <vscale x 8 x bfloat> %res
}

define <vscale x 8 x bfloat> @bfminnm_zeroing(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) {
; CHECK-LABEL: bfminnm_zeroing:
; CHECK: // %bb.0:
; CHECK-NEXT: movprfx z0.h, p0/z, z0.h
; CHECK-NEXT: bfminnm z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT: ret
%a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> zeroinitializer
%out = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.nxv8bf16(<vscale x 8 x i1> %pg,
<vscale x 8 x bfloat> %a_z,
<vscale x 8 x bfloat> %b)
ret <vscale x 8 x bfloat> %out
}

define <vscale x 8 x bfloat> @bfminnm_u_pred(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b){
; CHECK-LABEL: bfminnm_u_pred:
; CHECK: // %bb.0:
; CHECK-NEXT: bfminnm z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT: ret
%res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.u.nxv8bf16(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b)
ret <vscale x 8 x bfloat> %res
}

define <vscale x 8 x bfloat> @bfminnm_u(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b){
; CHECK-LABEL: bfminnm_u:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: bfminnm z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT: ret
%elt = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
%res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.u.nxv8bf16(<vscale x 8 x i1> %elt, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b)
ret <vscale x 8 x bfloat> %res
}

define <vscale x 8 x bfloat> @bfminnm_u_zeroing(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) {
; CHECK-LABEL: bfminnm_u_zeroing:
; CHECK: // %bb.0:
; CHECK-NEXT: mov z2.h, #0 // =0x0
; CHECK-NEXT: sel z0.h, p0, z0.h, z2.h
; CHECK-NEXT: bfminnm z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT: ret
%a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> zeroinitializer
%out = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.u.nxv8bf16(<vscale x 8 x i1> %pg,
<vscale x 8 x bfloat> %a_z,
<vscale x 8 x bfloat> %b)
ret <vscale x 8 x bfloat> %out
}

declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>)
declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>)
declare <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 immarg)
35 changes: 35 additions & 0 deletions llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfmla.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p1 -mattr=+b16b16 -verify-machineinstrs < %s | FileCheck %s

define <vscale x 8 x bfloat> @bfmla_m(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c){
; CHECK-LABEL: bfmla_m:
; CHECK: // %bb.0:
; CHECK-NEXT: bfmla z0.h, p0/m, z1.h, z2.h
; CHECK-NEXT: ret
%res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.nxv8bf16(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c)
ret <vscale x 8 x bfloat> %res
}

define <vscale x 8 x bfloat> @bfmla_x(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c){
; CHECK-LABEL: bfmla_x:
; CHECK: // %bb.0:
; CHECK-NEXT: bfmla z0.h, p0/m, z1.h, z2.h
; CHECK-NEXT: ret
%res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.u.nxv8bf16(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c)
ret <vscale x 8 x bfloat> %res
}

define <vscale x 8 x bfloat> @bfmla_z(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c){
; CHECK-LABEL: bfmla_z:
; CHECK: // %bb.0:
; CHECK-NEXT: mov z3.h, #0 // =0x0
; CHECK-NEXT: sel z0.h, p0, z0.h, z3.h
; CHECK-NEXT: bfmla z0.h, p0/m, z1.h, z2.h
; CHECK-NEXT: ret
%a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> zeroinitializer
%res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.nxv8bf16(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a_z, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c)
ret <vscale x 8 x bfloat> %res
}

declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>)
declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>)
31 changes: 31 additions & 0 deletions llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfmla_lane.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p1 -mattr=+b16b16 -verify-machineinstrs < %s | FileCheck %s

define <vscale x 8 x bfloat> @bfmla_lane_idx1(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c){
; CHECK-LABEL: bfmla_lane_idx1:
; CHECK: // %bb.0:
; CHECK-NEXT: bfmla z0.h, z1.h, z2.h[1]
; CHECK-NEXT: ret
%res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.lane.nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c, i32 1)
ret <vscale x 8 x bfloat> %res
}

define <vscale x 8 x bfloat> @bfmla_lane_idx3(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c){
; CHECK-LABEL: bfmla_lane_idx3:
; CHECK: // %bb.0:
; CHECK-NEXT: bfmla z0.h, z1.h, z2.h[3]
; CHECK-NEXT: ret
%res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.lane.nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c, i32 3)
ret <vscale x 8 x bfloat> %res
}

define <vscale x 8 x bfloat> @bfmla_lane_idx7(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c){
; CHECK-LABEL: bfmla_lane_idx7:
; CHECK: // %bb.0:
; CHECK-NEXT: bfmla z0.h, z1.h, z2.h[7]
; CHECK-NEXT: ret
%res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.lane.nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c, i32 7)
ret <vscale x 8 x bfloat> %res
}

declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmla.lane.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32)
49 changes: 21 additions & 28 deletions llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfmls.ll
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@@ -1,43 +1,36 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2p1 -mattr=+b16b16 -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p1 -mattr=+b16b16 -verify-machineinstrs < %s | FileCheck %s

define <vscale x 4 x float> @bfmlslb_f32(<vscale x 4 x float> %zda, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) {
; CHECK-LABEL: bfmlslb_f32:
define <vscale x 8 x bfloat> @bfmls_m(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c){
; CHECK-LABEL: bfmls_m:
; CHECK: // %bb.0:
; CHECK-NEXT: bfmlslb z0.s, z1.h, z2.h
; CHECK-NEXT: bfmls z0.h, p0/m, z1.h, z2.h
; CHECK-NEXT: ret
%out = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlslb(<vscale x 4 x float> %zda, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm)
ret <vscale x 4 x float> %out
%res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.nxv8bf16(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c)
ret <vscale x 8 x bfloat> %res
}

define <vscale x 4 x float> @bfmlslt_f32(<vscale x 4 x float> %zda, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) {
; CHECK-LABEL: bfmlslt_f32:
define <vscale x 8 x bfloat> @bfmls_x(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c){
; CHECK-LABEL: bfmls_x:
; CHECK: // %bb.0:
; CHECK-NEXT: bfmlslt z0.s, z1.h, z2.h
; CHECK-NEXT: bfmls z0.h, p0/m, z1.h, z2.h
; CHECK-NEXT: ret
%out = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlslt(<vscale x 4 x float> %zda, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm)
ret <vscale x 4 x float> %out
%res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.u.nxv8bf16(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c)
ret <vscale x 8 x bfloat> %res
}

define <vscale x 4 x float> @bfmlslb_lane_f32(<vscale x 4 x float> %zda, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) {
; CHECK-LABEL: bfmlslb_lane_f32:
; CHECK: // %bb.0:
; CHECK-NEXT: bfmlslb z0.s, z1.h, z2.h[7]
; CHECK-NEXT: ret
%out = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlslb.lane(<vscale x 4 x float> %zda, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm, i32 7)
ret <vscale x 4 x float> %out
}

define <vscale x 4 x float> @bfmlslt_lane_f32(<vscale x 4 x float> %zda, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) {
; CHECK-LABEL: bfmlslt_lane_f32:
define <vscale x 8 x bfloat> @bfmls_z(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c){
; CHECK-LABEL: bfmls_z:
; CHECK: // %bb.0:
; CHECK-NEXT: bfmlslt z0.s, z1.h, z2.h[7]
; CHECK-NEXT: mov z3.h, #0 // =0x0
; CHECK-NEXT: sel z0.h, p0, z0.h, z3.h
; CHECK-NEXT: bfmls z0.h, p0/m, z1.h, z2.h
; CHECK-NEXT: ret
%out = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlslt.lane(<vscale x 4 x float> %zda, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm, i32 7)
ret <vscale x 4 x float> %out
%a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> zeroinitializer
%res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.nxv8bf16(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a_z, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c)
ret <vscale x 8 x bfloat> %res
}

declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlslb(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>)
declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlslt(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>)
declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlslb.lane(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32)
declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlslt.lane(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32)
declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>)
declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>)
31 changes: 31 additions & 0 deletions llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfmls_lane.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p1 -mattr=+b16b16 -verify-machineinstrs < %s | FileCheck %s

define <vscale x 8 x bfloat> @bfmls_lane_idx1(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c){
; CHECK-LABEL: bfmls_lane_idx1:
; CHECK: // %bb.0:
; CHECK-NEXT: bfmls z0.h, z1.h, z2.h[1]
; CHECK-NEXT: ret
%res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.lane.nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c, i32 1)
ret <vscale x 8 x bfloat> %res
}

define <vscale x 8 x bfloat> @bfmls_lane_idx3(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c){
; CHECK-LABEL: bfmls_lane_idx3:
; CHECK: // %bb.0:
; CHECK-NEXT: bfmls z0.h, z1.h, z2.h[3]
; CHECK-NEXT: ret
%res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.lane.nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c, i32 3)
ret <vscale x 8 x bfloat> %res
}

define <vscale x 8 x bfloat> @bfmls_lane_idx7(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c){
; CHECK-LABEL: bfmls_lane_idx7:
; CHECK: // %bb.0:
; CHECK-NEXT: bfmls z0.h, z1.h, z2.h[7]
; CHECK-NEXT: ret
%res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.lane.nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c, i32 7)
ret <vscale x 8 x bfloat> %res
}

declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmls.lane.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32)
43 changes: 43 additions & 0 deletions llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfmlsl.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p1 -mattr=+b16b16 -verify-machineinstrs < %s | FileCheck %s

define <vscale x 4 x float> @bfmlslb_f32(<vscale x 4 x float> %zda, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) {
; CHECK-LABEL: bfmlslb_f32:
; CHECK: // %bb.0:
; CHECK-NEXT: bfmlslb z0.s, z1.h, z2.h
; CHECK-NEXT: ret
%out = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlslb(<vscale x 4 x float> %zda, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm)
ret <vscale x 4 x float> %out
}

define <vscale x 4 x float> @bfmlslt_f32(<vscale x 4 x float> %zda, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) {
; CHECK-LABEL: bfmlslt_f32:
; CHECK: // %bb.0:
; CHECK-NEXT: bfmlslt z0.s, z1.h, z2.h
; CHECK-NEXT: ret
%out = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlslt(<vscale x 4 x float> %zda, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm)
ret <vscale x 4 x float> %out
}

define <vscale x 4 x float> @bfmlslb_lane_f32(<vscale x 4 x float> %zda, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) {
; CHECK-LABEL: bfmlslb_lane_f32:
; CHECK: // %bb.0:
; CHECK-NEXT: bfmlslb z0.s, z1.h, z2.h[7]
; CHECK-NEXT: ret
%out = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlslb.lane(<vscale x 4 x float> %zda, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm, i32 7)
ret <vscale x 4 x float> %out
}

define <vscale x 4 x float> @bfmlslt_lane_f32(<vscale x 4 x float> %zda, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) {
; CHECK-LABEL: bfmlslt_lane_f32:
; CHECK: // %bb.0:
; CHECK-NEXT: bfmlslt z0.s, z1.h, z2.h[7]
; CHECK-NEXT: ret
%out = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlslt.lane(<vscale x 4 x float> %zda, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm, i32 7)
ret <vscale x 4 x float> %out
}

declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlslb(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>)
declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlslt(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>)
declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlslb.lane(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32)
declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlslt.lane(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32)
62 changes: 62 additions & 0 deletions llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfmul.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p1 -mattr=+b16b16 -mattr=+use-experimental-zeroing-pseudos -verify-machineinstrs < %s \
; RUN: | FileCheck %s

define <vscale x 8 x bfloat> @bfmul_pred(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b){
; CHECK-LABEL: bfmul_pred:
; CHECK: // %bb.0:
; CHECK-NEXT: bfmul z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT: ret
%res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.nxv8bf16(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b)
ret <vscale x 8 x bfloat> %res
}

define <vscale x 8 x bfloat> @bfmul_zeroing(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) {
; CHECK-LABEL: bfmul_zeroing:
; CHECK: // %bb.0:
; CHECK-NEXT: movprfx z0.h, p0/z, z0.h
; CHECK-NEXT: bfmul z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT: ret
%a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> zeroinitializer
%out = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.nxv8bf16(<vscale x 8 x i1> %pg,
<vscale x 8 x bfloat> %a_z,
<vscale x 8 x bfloat> %b)
ret <vscale x 8 x bfloat> %out
}

define <vscale x 8 x bfloat> @bfmul_u_pred(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b){
; CHECK-LABEL: bfmul_u_pred:
; CHECK: // %bb.0:
; CHECK-NEXT: bfmul z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT: ret
%res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.u.nxv8bf16(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b)
ret <vscale x 8 x bfloat> %res
}

define <vscale x 8 x bfloat> @bfmul_u(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b){
; CHECK-LABEL: bfmul_u:
; CHECK: // %bb.0:
; CHECK-NEXT: bfmul z0.h, z0.h, z1.h
; CHECK-NEXT: ret
%elt = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
%res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.u.nxv8bf16(<vscale x 8 x i1> %elt, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b)
ret <vscale x 8 x bfloat> %res
}

define <vscale x 8 x bfloat> @bfmul_u_zeroing(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) {
; CHECK-LABEL: bfmul_u_zeroing:
; CHECK: // %bb.0:
; CHECK-NEXT: mov z2.h, #0 // =0x0
; CHECK-NEXT: sel z0.h, p0, z0.h, z2.h
; CHECK-NEXT: bfmul z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT: ret
%a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> zeroinitializer
%out = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.u.nxv8bf16(<vscale x 8 x i1> %pg,
<vscale x 8 x bfloat> %a_z,
<vscale x 8 x bfloat> %b)
ret <vscale x 8 x bfloat> %out
}

declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>)
declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>)
declare <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 immarg)
37 changes: 37 additions & 0 deletions llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfmul_lane.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p1 -mattr=+b16b16 -verify-machineinstrs < %s | FileCheck %s

define <vscale x 8 x bfloat> @bfmul_lane_idx1(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) {
; CHECK-LABEL: bfmul_lane_idx1:
; CHECK: // %bb.0:
; CHECK-NEXT: bfmul z0.h, z0.h, z1.h[1]
; CHECK-NEXT: ret
%out = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.lane.nxv8bf16(<vscale x 8 x bfloat> %a,
<vscale x 8 x bfloat> %b,
i32 1)
ret <vscale x 8 x bfloat> %out
}

define <vscale x 8 x bfloat> @bfmul_lane_idx3(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) {
; CHECK-LABEL: bfmul_lane_idx3:
; CHECK: // %bb.0:
; CHECK-NEXT: bfmul z0.h, z0.h, z1.h[3]
; CHECK-NEXT: ret
%out = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.lane.nxv8bf16(<vscale x 8 x bfloat> %a,
<vscale x 8 x bfloat> %b,
i32 3)
ret <vscale x 8 x bfloat> %out
}

define <vscale x 8 x bfloat> @bfmul_lane_idx7(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) {
; CHECK-LABEL: bfmul_lane_idx7:
; CHECK: // %bb.0:
; CHECK-NEXT: bfmul z0.h, z0.h, z1.h[7]
; CHECK-NEXT: ret
%out = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.lane.nxv8bf16(<vscale x 8 x bfloat> %a,
<vscale x 8 x bfloat> %b,
i32 7)
ret <vscale x 8 x bfloat> %out
}

declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.lane.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32)
62 changes: 62 additions & 0 deletions llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfsub.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p1 -mattr=+b16b16 -mattr=+use-experimental-zeroing-pseudos -verify-machineinstrs < %s \
; RUN: | FileCheck %s

define <vscale x 8 x bfloat> @bfsub_pred(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b){
; CHECK-LABEL: bfsub_pred:
; CHECK: // %bb.0:
; CHECK-NEXT: bfsub z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT: ret
%res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.nxv8bf16(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b)
ret <vscale x 8 x bfloat> %res
}

define <vscale x 8 x bfloat> @bfsub_zeroing(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) {
; CHECK-LABEL: bfsub_zeroing:
; CHECK: // %bb.0:
; CHECK-NEXT: movprfx z0.h, p0/z, z0.h
; CHECK-NEXT: bfsub z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT: ret
%a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> zeroinitializer
%out = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.nxv8bf16(<vscale x 8 x i1> %pg,
<vscale x 8 x bfloat> %a_z,
<vscale x 8 x bfloat> %b)
ret <vscale x 8 x bfloat> %out
}

define <vscale x 8 x bfloat> @bfsub_u_pred(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b){
; CHECK-LABEL: bfsub_u_pred:
; CHECK: // %bb.0:
; CHECK-NEXT: bfsub z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT: ret
%res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.u.nxv8bf16(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b)
ret <vscale x 8 x bfloat> %res
}

define <vscale x 8 x bfloat> @bfsub_u(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b){
; CHECK-LABEL: bfsub_u:
; CHECK: // %bb.0:
; CHECK-NEXT: bfsub z0.h, z0.h, z1.h
; CHECK-NEXT: ret
%elt = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
%res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.u.nxv8bf16(<vscale x 8 x i1> %elt, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b)
ret <vscale x 8 x bfloat> %res
}

define <vscale x 8 x bfloat> @bfsub_u_zeroing(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) {
; CHECK-LABEL: bfsub_u_zeroing:
; CHECK: // %bb.0:
; CHECK-NEXT: mov z2.h, #0 // =0x0
; CHECK-NEXT: sel z0.h, p0, z0.h, z2.h
; CHECK-NEXT: bfsub z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT: ret
%a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> zeroinitializer
%out = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.u.nxv8bf16(<vscale x 8 x i1> %pg,
<vscale x 8 x bfloat> %a_z,
<vscale x 8 x bfloat> %b)
ret <vscale x 8 x bfloat> %out
}

declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>)
declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fsub.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>)
declare <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 immarg)
20 changes: 10 additions & 10 deletions llvm/test/MC/AArch64/SVE2p1/bfadd.s
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Expand Up @@ -16,61 +16,61 @@ bfadd z23.h, p3/m, z23.h, z13.h // 01100101-00000000-10001101-10110111
// CHECK-INST: movprfx z23.h, p3/m, z31.h
// CHECK-INST: bfadd z23.h, p3/m, z23.h, z13.h
// CHECK-ENCODING: [0xb7,0x8d,0x00,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65008db7 <unknown>

movprfx z23, z31
bfadd z23.h, p3/m, z23.h, z13.h // 01100101-00000000-10001101-10110111
// CHECK-INST: movprfx z23, z31
// CHECK-INST: bfadd z23.h, p3/m, z23.h, z13.h
// CHECK-ENCODING: [0xb7,0x8d,0x00,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65008db7 <unknown>

bfadd z0.h, p0/m, z0.h, z0.h // 01100101-00000000-10000000-00000000
// CHECK-INST: bfadd z0.h, p0/m, z0.h, z0.h
// CHECK-ENCODING: [0x00,0x80,0x00,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65008000 <unknown>

bfadd z21.h, p5/m, z21.h, z10.h // 01100101-00000000-10010101-01010101
// CHECK-INST: bfadd z21.h, p5/m, z21.h, z10.h
// CHECK-ENCODING: [0x55,0x95,0x00,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65009555 <unknown>

bfadd z23.h, p3/m, z23.h, z13.h // 01100101-00000000-10001101-10110111
// CHECK-INST: bfadd z23.h, p3/m, z23.h, z13.h
// CHECK-ENCODING: [0xb7,0x8d,0x00,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65008db7 <unknown>

bfadd z31.h, p7/m, z31.h, z31.h // 01100101-00000000-10011111-11111111
// CHECK-INST: bfadd z31.h, p7/m, z31.h, z31.h
// CHECK-ENCODING: [0xff,0x9f,0x00,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65009fff <unknown>

bfadd z0.h, z0.h, z0.h // 01100101-00000000-00000000-00000000
// CHECK-INST: bfadd z0.h, z0.h, z0.h
// CHECK-ENCODING: [0x00,0x00,0x00,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65000000 <unknown>

bfadd z21.h, z10.h, z21.h // 01100101-00010101-00000001-01010101
// CHECK-INST: bfadd z21.h, z10.h, z21.h
// CHECK-ENCODING: [0x55,0x01,0x15,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65150155 <unknown>

bfadd z23.h, z13.h, z8.h // 01100101-00001000-00000001-10110111
// CHECK-INST: bfadd z23.h, z13.h, z8.h
// CHECK-ENCODING: [0xb7,0x01,0x08,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 650801b7 <unknown>

bfadd z31.h, z31.h, z31.h // 01100101-00011111-00000011-11111111
// CHECK-INST: bfadd z31.h, z31.h, z31.h
// CHECK-ENCODING: [0xff,0x03,0x1f,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 651f03ff <unknown>
10 changes: 5 additions & 5 deletions llvm/test/MC/AArch64/SVE2p1/bfclamp.s
View file
Original file line number Diff line number Diff line change
Expand Up @@ -17,30 +17,30 @@ bfclamp z23.h, z13.h, z8.h // 01100100-00101000-00100101-10110111
// CHECK-INST: movprfx z23, z31
// CHECK-INST: bfclamp z23.h, z13.h, z8.h
// CHECK-ENCODING: [0xb7,0x25,0x28,0x64]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 642825b7 <unknown>

bfclamp z0.h, z0.h, z0.h // 01100100-00100000-00100100-00000000
// CHECK-INST: bfclamp z0.h, z0.h, z0.h
// CHECK-ENCODING: [0x00,0x24,0x20,0x64]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 64202400 <unknown>

bfclamp z21.h, z10.h, z21.h // 01100100-00110101-00100101-01010101
// CHECK-INST: bfclamp z21.h, z10.h, z21.h
// CHECK-ENCODING: [0x55,0x25,0x35,0x64]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 64352555 <unknown>

bfclamp z23.h, z13.h, z8.h // 01100100-00101000-00100101-10110111
// CHECK-INST: bfclamp z23.h, z13.h, z8.h
// CHECK-ENCODING: [0xb7,0x25,0x28,0x64]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 642825b7 <unknown>

bfclamp z31.h, z31.h, z31.h // 01100100-00111111-00100111-11111111
// CHECK-INST: bfclamp z31.h, z31.h, z31.h
// CHECK-ENCODING: [0xff,0x27,0x3f,0x64]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 643f27ff <unknown>

12 changes: 6 additions & 6 deletions llvm/test/MC/AArch64/SVE2p1/bfmax.s
View file
Original file line number Diff line number Diff line change
Expand Up @@ -17,37 +17,37 @@ bfmax z23.h, p3/m, z23.h, z13.h // 01100101-00000110-10001101-10110111
// CHECK-INST: movprfx z23.h, p3/m, z31.h
// CHECK-INST: bfmax z23.h, p3/m, z23.h, z13.h
// CHECK-ENCODING: [0xb7,0x8d,0x06,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65068db7 <unknown>

movprfx z23, z31
bfmax z23.h, p3/m, z23.h, z13.h // 01100101-00000110-10001101-10110111
// CHECK-INST: movprfx z23, z31
// CHECK-INST: bfmax z23.h, p3/m, z23.h, z13.h
// CHECK-ENCODING: [0xb7,0x8d,0x06,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65068db7 <unknown>

bfmax z0.h, p0/m, z0.h, z0.h // 01100101-00000110-10000000-00000000
// CHECK-INST: bfmax z0.h, p0/m, z0.h, z0.h
// CHECK-ENCODING: [0x00,0x80,0x06,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65068000 <unknown>

bfmax z21.h, p5/m, z21.h, z10.h // 01100101-00000110-10010101-01010101
// CHECK-INST: bfmax z21.h, p5/m, z21.h, z10.h
// CHECK-ENCODING: [0x55,0x95,0x06,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65069555 <unknown>

bfmax z23.h, p3/m, z23.h, z13.h // 01100101-00000110-10001101-10110111
// CHECK-INST: bfmax z23.h, p3/m, z23.h, z13.h
// CHECK-ENCODING: [0xb7,0x8d,0x06,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65068db7 <unknown>

bfmax z31.h, p7/m, z31.h, z31.h // 01100101-00000110-10011111-11111111
// CHECK-INST: bfmax z31.h, p7/m, z31.h, z31.h
// CHECK-ENCODING: [0xff,0x9f,0x06,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65069fff <unknown>
12 changes: 6 additions & 6 deletions llvm/test/MC/AArch64/SVE2p1/bfmaxnm.s
View file
Original file line number Diff line number Diff line change
Expand Up @@ -17,38 +17,38 @@ bfmaxnm z23.h, p3/m, z23.h, z13.h // 01100101-00000100-10001101-10110111
// CHECK-INST: movprfx z23.h, p3/m, z31.h
// CHECK-INST: bfmaxnm z23.h, p3/m, z23.h, z13.h
// CHECK-ENCODING: [0xb7,0x8d,0x04,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65048db7 <unknown>

movprfx z23, z31
bfmaxnm z23.h, p3/m, z23.h, z13.h // 01100101-00000100-10001101-10110111
// CHECK-INST: movprfx z23, z31
// CHECK-INST: bfmaxnm z23.h, p3/m, z23.h, z13.h
// CHECK-ENCODING: [0xb7,0x8d,0x04,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65048db7 <unknown>

bfmaxnm z0.h, p0/m, z0.h, z0.h // 01100101-00000100-10000000-00000000
// CHECK-INST: bfmaxnm z0.h, p0/m, z0.h, z0.h
// CHECK-ENCODING: [0x00,0x80,0x04,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65048000 <unknown>

bfmaxnm z21.h, p5/m, z21.h, z10.h // 01100101-00000100-10010101-01010101
// CHECK-INST: bfmaxnm z21.h, p5/m, z21.h, z10.h
// CHECK-ENCODING: [0x55,0x95,0x04,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65049555 <unknown>

bfmaxnm z23.h, p3/m, z23.h, z13.h // 01100101-00000100-10001101-10110111
// CHECK-INST: bfmaxnm z23.h, p3/m, z23.h, z13.h
// CHECK-ENCODING: [0xb7,0x8d,0x04,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65048db7 <unknown>

bfmaxnm z31.h, p7/m, z31.h, z31.h // 01100101-00000100-10011111-11111111
// CHECK-INST: bfmaxnm z31.h, p7/m, z31.h, z31.h
// CHECK-ENCODING: [0xff,0x9f,0x04,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65049fff <unknown>

12 changes: 6 additions & 6 deletions llvm/test/MC/AArch64/SVE2p1/bfmin.s
View file
Original file line number Diff line number Diff line change
Expand Up @@ -17,38 +17,38 @@ bfmin z23.h, p3/m, z23.h, z13.h // 01100101-00000111-10001101-10110111
// CHECK-INST: movprfx z23.h, p3/m, z31.h
// CHECK-INST: bfmin z23.h, p3/m, z23.h, z13.h
// CHECK-ENCODING: [0xb7,0x8d,0x07,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65078db7 <unknown>

movprfx z23, z31
bfmin z23.h, p3/m, z23.h, z13.h // 01100101-00000111-10001101-10110111
// CHECK-INST: movprfx z23, z31
// CHECK-INST: bfmin z23.h, p3/m, z23.h, z13.h
// CHECK-ENCODING: [0xb7,0x8d,0x07,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65078db7 <unknown>

bfmin z0.h, p0/m, z0.h, z0.h // 01100101-00000111-10000000-00000000
// CHECK-INST: bfmin z0.h, p0/m, z0.h, z0.h
// CHECK-ENCODING: [0x00,0x80,0x07,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65078000 <unknown>

bfmin z21.h, p5/m, z21.h, z10.h // 01100101-00000111-10010101-01010101
// CHECK-INST: bfmin z21.h, p5/m, z21.h, z10.h
// CHECK-ENCODING: [0x55,0x95,0x07,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65079555 <unknown>

bfmin z23.h, p3/m, z23.h, z13.h // 01100101-00000111-10001101-10110111
// CHECK-INST: bfmin z23.h, p3/m, z23.h, z13.h
// CHECK-ENCODING: [0xb7,0x8d,0x07,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65078db7 <unknown>

bfmin z31.h, p7/m, z31.h, z31.h // 01100101-00000111-10011111-11111111
// CHECK-INST: bfmin z31.h, p7/m, z31.h, z31.h
// CHECK-ENCODING: [0xff,0x9f,0x07,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65079fff <unknown>

12 changes: 6 additions & 6 deletions llvm/test/MC/AArch64/SVE2p1/bfminnm.s
View file
Original file line number Diff line number Diff line change
Expand Up @@ -17,38 +17,38 @@ bfminnm z23.h, p3/m, z23.h, z13.h // 01100101-00000101-10001101-10110111
// CHECK-INST: movprfx z23.h, p3/m, z31.h
// CHECK-INST: bfminnm z23.h, p3/m, z23.h, z13.h
// CHECK-ENCODING: [0xb7,0x8d,0x05,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65058db7 <unknown>

movprfx z23, z31
bfminnm z23.h, p3/m, z23.h, z13.h // 01100101-00000101-10001101-10110111
// CHECK-INST: movprfx z23, z31
// CHECK-INST: bfminnm z23.h, p3/m, z23.h, z13.h
// CHECK-ENCODING: [0xb7,0x8d,0x05,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65058db7 <unknown>

bfminnm z0.h, p0/m, z0.h, z0.h // 01100101-00000101-10000000-00000000
// CHECK-INST: bfminnm z0.h, p0/m, z0.h, z0.h
// CHECK-ENCODING: [0x00,0x80,0x05,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65058000 <unknown>

bfminnm z21.h, p5/m, z21.h, z10.h // 01100101-00000101-10010101-01010101
// CHECK-INST: bfminnm z21.h, p5/m, z21.h, z10.h
// CHECK-ENCODING: [0x55,0x95,0x05,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65059555 <unknown>

bfminnm z23.h, p3/m, z23.h, z13.h // 01100101-00000101-10001101-10110111
// CHECK-INST: bfminnm z23.h, p3/m, z23.h, z13.h
// CHECK-ENCODING: [0xb7,0x8d,0x05,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65058db7 <unknown>

bfminnm z31.h, p7/m, z31.h, z31.h // 01100101-00000101-10011111-11111111
// CHECK-INST: bfminnm z31.h, p7/m, z31.h, z31.h
// CHECK-ENCODING: [0xff,0x9f,0x05,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65059fff <unknown>

22 changes: 11 additions & 11 deletions llvm/test/MC/AArch64/SVE2p1/bfmla.s
View file
Original file line number Diff line number Diff line change
Expand Up @@ -17,31 +17,31 @@ bfmla z23.h, z13.h, z0.h[5] // 01100100-01101000-00001001-10110111
// CHECK-INST: movprfx z23, z31
// CHECK-INST: bfmla z23.h, z13.h, z0.h[5]
// CHECK-ENCODING: [0xb7,0x09,0x68,0x64]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 646809b7 <unknown>

bfmla z0.h, z0.h, z0.h[0] // 01100100-00100000-00001000-00000000
// CHECK-INST: bfmla z0.h, z0.h, z0.h[0]
// CHECK-ENCODING: [0x00,0x08,0x20,0x64]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 64200800 <unknown>

bfmla z21.h, z10.h, z5.h[6] // 01100100-01110101-00001001-01010101
// CHECK-INST: bfmla z21.h, z10.h, z5.h[6]
// CHECK-ENCODING: [0x55,0x09,0x75,0x64]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 64750955 <unknown>

bfmla z23.h, z13.h, z0.h[5] // 01100100-01101000-00001001-10110111
// CHECK-INST: bfmla z23.h, z13.h, z0.h[5]
// CHECK-ENCODING: [0xb7,0x09,0x68,0x64]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 646809b7 <unknown>

bfmla z31.h, z31.h, z7.h[7] // 01100100-01111111-00001011-11111111
// CHECK-INST: bfmla z31.h, z31.h, z7.h[7]
// CHECK-ENCODING: [0xff,0x0b,0x7f,0x64]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 647f0bff <unknown>


Expand All @@ -50,38 +50,38 @@ bfmla z23.h, p3/m, z13.h, z8.h // 01100101-00101000-00001101-10110111
// CHECK-INST: movprfx z23.h, p3/m, z31.h
// CHECK-INST: bfmla z23.h, p3/m, z13.h, z8.h
// CHECK-ENCODING: [0xb7,0x0d,0x28,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65280db7 <unknown>

movprfx z23, z31
bfmla z23.h, p3/m, z13.h, z8.h // 01100101-00101000-00001101-10110111
// CHECK-INST: movprfx z23, z31
// CHECK-INST: bfmla z23.h, p3/m, z13.h, z8.h
// CHECK-ENCODING: [0xb7,0x0d,0x28,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65280db7 <unknown>

bfmla z0.h, p0/m, z0.h, z0.h // 01100101-00100000-00000000-00000000
// CHECK-INST: bfmla z0.h, p0/m, z0.h, z0.h
// CHECK-ENCODING: [0x00,0x00,0x20,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65200000 <unknown>

bfmla z21.h, p5/m, z10.h, z21.h // 01100101-00110101-00010101-01010101
// CHECK-INST: bfmla z21.h, p5/m, z10.h, z21.h
// CHECK-ENCODING: [0x55,0x15,0x35,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65351555 <unknown>

bfmla z23.h, p3/m, z13.h, z8.h // 01100101-00101000-00001101-10110111
// CHECK-INST: bfmla z23.h, p3/m, z13.h, z8.h
// CHECK-ENCODING: [0xb7,0x0d,0x28,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65280db7 <unknown>

bfmla z31.h, p7/m, z31.h, z31.h // 01100101-00111111-00011111-11111111
// CHECK-INST: bfmla z31.h, p7/m, z31.h, z31.h
// CHECK-ENCODING: [0xff,0x1f,0x3f,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 653f1fff <unknown>

22 changes: 11 additions & 11 deletions llvm/test/MC/AArch64/SVE2p1/bfmls.s
View file
Original file line number Diff line number Diff line change
Expand Up @@ -17,31 +17,31 @@ bfmls z23.h, z13.h, z0.h[5] // 01100100-01101000-00001101-10110111
// CHECK-INST: movprfx z23, z31
// CHECK-INST: bfmls z23.h, z13.h, z0.h[5]
// CHECK-ENCODING: [0xb7,0x0d,0x68,0x64]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 64680db7 <unknown>

bfmls z0.h, z0.h, z0.h[0] // 01100100-00100000-00001100-00000000
// CHECK-INST: bfmls z0.h, z0.h, z0.h[0]
// CHECK-ENCODING: [0x00,0x0c,0x20,0x64]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 64200c00 <unknown>

bfmls z21.h, z10.h, z5.h[6] // 01100100-01110101-00001101-01010101
// CHECK-INST: bfmls z21.h, z10.h, z5.h[6]
// CHECK-ENCODING: [0x55,0x0d,0x75,0x64]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 64750d55 <unknown>

bfmls z23.h, z13.h, z0.h[5] // 01100100-01101000-00001101-10110111
// CHECK-INST: bfmls z23.h, z13.h, z0.h[5]
// CHECK-ENCODING: [0xb7,0x0d,0x68,0x64]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 64680db7 <unknown>

bfmls z31.h, z31.h, z7.h[7] // 01100100-01111111-00001111-11111111
// CHECK-INST: bfmls z31.h, z31.h, z7.h[7]
// CHECK-ENCODING: [0xff,0x0f,0x7f,0x64]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 647f0fff <unknown>


Expand All @@ -50,38 +50,38 @@ bfmls z23.h, p3/m, z13.h, z8.h // 01100101-00101000-00101101-10110111
// CHECK-INST: movprfx z23.h, p3/m, z31.h
// CHECK-INST: bfmls z23.h, p3/m, z13.h, z8.h
// CHECK-ENCODING: [0xb7,0x2d,0x28,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65282db7 <unknown>

movprfx z23, z31
bfmls z23.h, p3/m, z13.h, z8.h // 01100101-00101000-00101101-10110111
// CHECK-INST: movprfx z23, z31
// CHECK-INST: bfmls z23.h, p3/m, z13.h, z8.h
// CHECK-ENCODING: [0xb7,0x2d,0x28,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65282db7 <unknown>

bfmls z0.h, p0/m, z0.h, z0.h // 01100101-00100000-00100000-00000000
// CHECK-INST: bfmls z0.h, p0/m, z0.h, z0.h
// CHECK-ENCODING: [0x00,0x20,0x20,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65202000 <unknown>

bfmls z21.h, p5/m, z10.h, z21.h // 01100101-00110101-00110101-01010101
// CHECK-INST: bfmls z21.h, p5/m, z10.h, z21.h
// CHECK-ENCODING: [0x55,0x35,0x35,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65353555 <unknown>

bfmls z23.h, p3/m, z13.h, z8.h // 01100101-00101000-00101101-10110111
// CHECK-INST: bfmls z23.h, p3/m, z13.h, z8.h
// CHECK-ENCODING: [0xb7,0x2d,0x28,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65282db7 <unknown>

bfmls z31.h, p7/m, z31.h, z31.h // 01100101-00111111-00111111-11111111
// CHECK-INST: bfmls z31.h, p7/m, z31.h, z31.h
// CHECK-ENCODING: [0xff,0x3f,0x3f,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 653f3fff <unknown>

28 changes: 14 additions & 14 deletions llvm/test/MC/AArch64/SVE2p1/bfmul.s
View file
Original file line number Diff line number Diff line change
Expand Up @@ -14,88 +14,88 @@
bfmul z0.h, z0.h, z0.h[0] // 01100100-00100000-00101000-00000000
// CHECK-INST: bfmul z0.h, z0.h, z0.h[0]
// CHECK-ENCODING: [0x00,0x28,0x20,0x64]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 64202800 <unknown>

bfmul z21.h, z10.h, z5.h[6] // 01100100-01110101-00101001-01010101
// CHECK-INST: bfmul z21.h, z10.h, z5.h[6]
// CHECK-ENCODING: [0x55,0x29,0x75,0x64]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 64752955 <unknown>

bfmul z23.h, z13.h, z0.h[5] // 01100100-01101000-00101001-10110111
// CHECK-INST: bfmul z23.h, z13.h, z0.h[5]
// CHECK-ENCODING: [0xb7,0x29,0x68,0x64]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 646829b7 <unknown>

bfmul z31.h, z31.h, z7.h[7] // 01100100-01111111-00101011-11111111
// CHECK-INST: bfmul z31.h, z31.h, z7.h[7]
// CHECK-ENCODING: [0xff,0x2b,0x7f,0x64]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 647f2bff <unknown>

movprfx z23.h, p3/m, z31.h
bfmul z23.h, p3/m, z23.h, z13.h // 01100101-00000010-10001101-10110111
// CHECK-INST: movprfx z23.h, p3/m, z31.h
// CHECK-INST: bfmul z23.h, p3/m, z23.h, z13.h
// CHECK-ENCODING: [0xb7,0x8d,0x02,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65028db7 <unknown>

movprfx z23, z31
bfmul z23.h, p3/m, z23.h, z13.h // 01100101-00000010-10001101-10110111
// CHECK-INST: movprfx z23, z31
// CHECK-INST: bfmul z23.h, p3/m, z23.h, z13.h
// CHECK-ENCODING: [0xb7,0x8d,0x02,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65028db7 <unknown>

bfmul z0.h, p0/m, z0.h, z0.h // 01100101-00000010-10000000-00000000
// CHECK-INST: bfmul z0.h, p0/m, z0.h, z0.h
// CHECK-ENCODING: [0x00,0x80,0x02,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65028000 <unknown>

bfmul z21.h, p5/m, z21.h, z10.h // 01100101-00000010-10010101-01010101
// CHECK-INST: bfmul z21.h, p5/m, z21.h, z10.h
// CHECK-ENCODING: [0x55,0x95,0x02,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65029555 <unknown>

bfmul z23.h, p3/m, z23.h, z13.h // 01100101-00000010-10001101-10110111
// CHECK-INST: bfmul z23.h, p3/m, z23.h, z13.h
// CHECK-ENCODING: [0xb7,0x8d,0x02,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65028db7 <unknown>

bfmul z31.h, p7/m, z31.h, z31.h // 01100101-00000010-10011111-11111111
// CHECK-INST: bfmul z31.h, p7/m, z31.h, z31.h
// CHECK-ENCODING: [0xff,0x9f,0x02,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65029fff <unknown>

bfmul z0.h, z0.h, z0.h // 01100101-00000000-00001000-00000000
// CHECK-INST: bfmul z0.h, z0.h, z0.h
// CHECK-ENCODING: [0x00,0x08,0x00,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65000800 <unknown>

bfmul z21.h, z10.h, z21.h // 01100101-00010101-00001001-01010101
// CHECK-INST: bfmul z21.h, z10.h, z21.h
// CHECK-ENCODING: [0x55,0x09,0x15,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65150955 <unknown>

bfmul z23.h, z13.h, z8.h // 01100101-00001000-00001001-10110111
// CHECK-INST: bfmul z23.h, z13.h, z8.h
// CHECK-ENCODING: [0xb7,0x09,0x08,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 650809b7 <unknown>

bfmul z31.h, z31.h, z31.h // 01100101-00011111-00001011-11111111
// CHECK-INST: bfmul z31.h, z31.h, z31.h
// CHECK-ENCODING: [0xff,0x0b,0x1f,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 651f0bff <unknown>

20 changes: 10 additions & 10 deletions llvm/test/MC/AArch64/SVE2p1/bfsub.s
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,61 +16,61 @@ bfsub z23.h, p3/m, z23.h, z13.h // 01100101-00000001-10001101-10110111
// CHECK-INST: movprfx z23.h, p3/m, z31.h
// CHECK-INST: bfsub z23.h, p3/m, z23.h, z13.h
// CHECK-ENCODING: [0xb7,0x8d,0x01,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65018db7 <unknown>

movprfx z23, z31
bfsub z23.h, p3/m, z23.h, z13.h // 01100101-00000001-10001101-10110111
// CHECK-INST: movprfx z23, z31
// CHECK-INST: bfsub z23.h, p3/m, z23.h, z13.h
// CHECK-ENCODING: [0xb7,0x8d,0x01,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65018db7 <unknown>

bfsub z0.h, p0/m, z0.h, z0.h // 01100101-00000001-10000000-00000000
// CHECK-INST: bfsub z0.h, p0/m, z0.h, z0.h
// CHECK-ENCODING: [0x00,0x80,0x01,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65018000 <unknown>

bfsub z21.h, p5/m, z21.h, z10.h // 01100101-00000001-10010101-01010101
// CHECK-INST: bfsub z21.h, p5/m, z21.h, z10.h
// CHECK-ENCODING: [0x55,0x95,0x01,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65019555 <unknown>

bfsub z23.h, p3/m, z23.h, z13.h // 01100101-00000001-10001101-10110111
// CHECK-INST: bfsub z23.h, p3/m, z23.h, z13.h
// CHECK-ENCODING: [0xb7,0x8d,0x01,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65018db7 <unknown>

bfsub z31.h, p7/m, z31.h, z31.h // 01100101-00000001-10011111-11111111
// CHECK-INST: bfsub z31.h, p7/m, z31.h, z31.h
// CHECK-ENCODING: [0xff,0x9f,0x01,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65019fff <unknown>

bfsub z0.h, z0.h, z0.h // 01100101-00000000-00000100-00000000
// CHECK-INST: bfsub z0.h, z0.h, z0.h
// CHECK-ENCODING: [0x00,0x04,0x00,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65000400 <unknown>

bfsub z21.h, z10.h, z21.h // 01100101-00010101-00000101-01010101
// CHECK-INST: bfsub z21.h, z10.h, z21.h
// CHECK-ENCODING: [0x55,0x05,0x15,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 65150555 <unknown>

bfsub z23.h, z13.h, z8.h // 01100101-00001000-00000101-10110111
// CHECK-INST: bfsub z23.h, z13.h, z8.h
// CHECK-ENCODING: [0xb7,0x05,0x08,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 650805b7 <unknown>

bfsub z31.h, z31.h, z31.h // 01100101-00011111-00000111-11111111
// CHECK-INST: bfsub z31.h, z31.h, z31.h
// CHECK-ENCODING: [0xff,0x07,0x1f,0x65]
// CHECK-ERROR: instruction requires: b16b16 sme2p1 or sve2p1
// CHECK-ERROR: instruction requires: b16b16 sve2p1
// CHECK-UNKNOWN: 651f07ff <unknown>