22 changes: 11 additions & 11 deletions llvm/lib/Target/Mips/MipsExpandPseudo.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -347,58 +347,58 @@ bool MipsExpandPseudo::expandAtomicBinOpSubword(
switch (I->getOpcode()) {
case Mips::ATOMIC_LOAD_NAND_I8_POSTRA:
SEOp = Mips::SEB;
LLVM_FALLTHROUGH;
[[fallthrough]];
case Mips::ATOMIC_LOAD_NAND_I16_POSTRA:
IsNand = true;
break;
case Mips::ATOMIC_SWAP_I8_POSTRA:
SEOp = Mips::SEB;
LLVM_FALLTHROUGH;
[[fallthrough]];
case Mips::ATOMIC_SWAP_I16_POSTRA:
IsSwap = true;
break;
case Mips::ATOMIC_LOAD_ADD_I8_POSTRA:
SEOp = Mips::SEB;
LLVM_FALLTHROUGH;
[[fallthrough]];
case Mips::ATOMIC_LOAD_ADD_I16_POSTRA:
Opcode = Mips::ADDu;
break;
case Mips::ATOMIC_LOAD_SUB_I8_POSTRA:
SEOp = Mips::SEB;
LLVM_FALLTHROUGH;
[[fallthrough]];
case Mips::ATOMIC_LOAD_SUB_I16_POSTRA:
Opcode = Mips::SUBu;
break;
case Mips::ATOMIC_LOAD_AND_I8_POSTRA:
SEOp = Mips::SEB;
LLVM_FALLTHROUGH;
[[fallthrough]];
case Mips::ATOMIC_LOAD_AND_I16_POSTRA:
Opcode = Mips::AND;
break;
case Mips::ATOMIC_LOAD_OR_I8_POSTRA:
SEOp = Mips::SEB;
LLVM_FALLTHROUGH;
[[fallthrough]];
case Mips::ATOMIC_LOAD_OR_I16_POSTRA:
Opcode = Mips::OR;
break;
case Mips::ATOMIC_LOAD_XOR_I8_POSTRA:
SEOp = Mips::SEB;
LLVM_FALLTHROUGH;
[[fallthrough]];
case Mips::ATOMIC_LOAD_XOR_I16_POSTRA:
Opcode = Mips::XOR;
break;
case Mips::ATOMIC_LOAD_UMIN_I8_POSTRA:
case Mips::ATOMIC_LOAD_UMIN_I16_POSTRA:
IsUnsigned = true;
LLVM_FALLTHROUGH;
[[fallthrough]];
case Mips::ATOMIC_LOAD_MIN_I8_POSTRA:
case Mips::ATOMIC_LOAD_MIN_I16_POSTRA:
IsMin = true;
break;
case Mips::ATOMIC_LOAD_UMAX_I8_POSTRA:
case Mips::ATOMIC_LOAD_UMAX_I16_POSTRA:
IsUnsigned = true;
LLVM_FALLTHROUGH;
[[fallthrough]];
case Mips::ATOMIC_LOAD_MAX_I8_POSTRA:
case Mips::ATOMIC_LOAD_MAX_I16_POSTRA:
IsMax = true;
Expand Down Expand Up @@ -694,15 +694,15 @@ bool MipsExpandPseudo::expandAtomicBinOp(MachineBasicBlock &BB,
case Mips::ATOMIC_LOAD_UMIN_I32_POSTRA:
case Mips::ATOMIC_LOAD_UMIN_I64_POSTRA:
IsUnsigned = true;
LLVM_FALLTHROUGH;
[[fallthrough]];
case Mips::ATOMIC_LOAD_MIN_I32_POSTRA:
case Mips::ATOMIC_LOAD_MIN_I64_POSTRA:
IsMin = true;
break;
case Mips::ATOMIC_LOAD_UMAX_I32_POSTRA:
case Mips::ATOMIC_LOAD_UMAX_I64_POSTRA:
IsUnsigned = true;
LLVM_FALLTHROUGH;
[[fallthrough]];
case Mips::ATOMIC_LOAD_MAX_I32_POSTRA:
case Mips::ATOMIC_LOAD_MAX_I64_POSTRA:
IsMax = true;
Expand Down
12 changes: 6 additions & 6 deletions llvm/lib/Target/Mips/MipsISelLowering.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3323,19 +3323,19 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
break;
case CCValAssign::SExtUpper:
UseUpperBits = true;
LLVM_FALLTHROUGH;
[[fallthrough]];
case CCValAssign::SExt:
Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg);
break;
case CCValAssign::ZExtUpper:
UseUpperBits = true;
LLVM_FALLTHROUGH;
[[fallthrough]];
case CCValAssign::ZExt:
Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg);
break;
case CCValAssign::AExtUpper:
UseUpperBits = true;
LLVM_FALLTHROUGH;
[[fallthrough]];
case CCValAssign::AExt:
Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg);
break;
Expand Down Expand Up @@ -3854,19 +3854,19 @@ MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
break;
case CCValAssign::AExtUpper:
UseUpperBits = true;
LLVM_FALLTHROUGH;
[[fallthrough]];
case CCValAssign::AExt:
Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val);
break;
case CCValAssign::ZExtUpper:
UseUpperBits = true;
LLVM_FALLTHROUGH;
[[fallthrough]];
case CCValAssign::ZExt:
Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val);
break;
case CCValAssign::SExtUpper:
UseUpperBits = true;
LLVM_FALLTHROUGH;
[[fallthrough]];
case CCValAssign::SExt:
Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val);
break;
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -172,7 +172,7 @@ void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
MI.addOperand(MachineOperand::CreateReg(Mips::SP, false, true));
break;
}
LLVM_FALLTHROUGH;
[[fallthrough]];
case Mips::BuildPairF64:
case Mips::ExtractElementF64:
if (Subtarget->isABI_FPXX() && !Subtarget->hasMTHC1())
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2017,7 +2017,7 @@ NVPTXAsmPrinter::lowerConstantForGV(const Constant *CV, bool ProcessingGeneric)
// expression properly. This is important for differences between
// blockaddress labels. Since the two labels are in the same function, it
// is reasonable to treat their delta as a 32-bit value.
LLVM_FALLTHROUGH;
[[fallthrough]];
case Instruction::BitCast:
return lowerConstantForGV(CE->getOperand(0), ProcessingGeneric);

Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1439,7 +1439,7 @@ bool PPCAsmParser::ParseOperand(OperandVector &Operands) {
if (!ParseExpression(EVal))
break;
// Fall-through
LLVM_FALLTHROUGH;
[[fallthrough]];
default:
return Error(S, "unknown operand");
}
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/PowerPC/PPCFastISel.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -912,7 +912,7 @@ bool PPCFastISel::PPCEmitCmp(const Value *SrcValue1, const Value *SrcValue2,
case MVT::i8:
case MVT::i16:
NeedsExt = true;
LLVM_FALLTHROUGH;
[[fallthrough]];
case MVT::i32:
if (!UseImm)
CmpOpc = IsZExt ? PPC::CMPLW : PPC::CMPW;
Expand Down
44 changes: 22 additions & 22 deletions llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2772,7 +2772,7 @@ class IntegerCompareEliminator {
if (CmpInGPR == ICGPR_Sext || CmpInGPR == ICGPR_SextI32 ||
CmpInGPR == ICGPR_SextI64)
return nullptr;
LLVM_FALLTHROUGH;
[[fallthrough]];
case ISD::SIGN_EXTEND:
if (CmpInGPR == ICGPR_Zext || CmpInGPR == ICGPR_ZextI32 ||
CmpInGPR == ICGPR_ZextI64)
Expand Down Expand Up @@ -3200,7 +3200,7 @@ IntegerCompareEliminator::get32BitZExtCompare(SDValue LHS, SDValue RHS,
std::swap(LHS, RHS);
ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
IsRHSZero = RHSConst && RHSConst->isZero();
LLVM_FALLTHROUGH;
[[fallthrough]];
}
case ISD::SETLE: {
if (CmpInGPR == ICGPR_NonExtIn)
Expand Down Expand Up @@ -3251,7 +3251,7 @@ IntegerCompareEliminator::get32BitZExtCompare(SDValue LHS, SDValue RHS,
ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
IsRHSZero = RHSConst && RHSConst->isZero();
IsRHSOne = RHSConst && RHSConst->getSExtValue() == 1;
LLVM_FALLTHROUGH;
[[fallthrough]];
}
case ISD::SETLT: {
// (zext (setcc %a, %b, setlt)) -> (lshr (sub %a, %b), 63)
Expand Down Expand Up @@ -3286,7 +3286,7 @@ IntegerCompareEliminator::get32BitZExtCompare(SDValue LHS, SDValue RHS,
// (zext (setcc %a, %b, setuge)) -> (xor (lshr (sub %b, %a), 63), 1)
// (zext (setcc %a, %b, setule)) -> (xor (lshr (sub %a, %b), 63), 1)
std::swap(LHS, RHS);
LLVM_FALLTHROUGH;
[[fallthrough]];
case ISD::SETULE: {
if (CmpInGPR == ICGPR_NonExtIn)
return SDValue();
Expand All @@ -3306,7 +3306,7 @@ IntegerCompareEliminator::get32BitZExtCompare(SDValue LHS, SDValue RHS,
// (zext (setcc %a, %b, setugt)) -> (lshr (sub %b, %a), 63)
// (zext (setcc %a, %b, setult)) -> (lshr (sub %a, %b), 63)
std::swap(LHS, RHS);
LLVM_FALLTHROUGH;
[[fallthrough]];
case ISD::SETULT: {
if (CmpInGPR == ICGPR_NonExtIn)
return SDValue();
Expand Down Expand Up @@ -3384,7 +3384,7 @@ IntegerCompareEliminator::get32BitSExtCompare(SDValue LHS, SDValue RHS,
std::swap(LHS, RHS);
ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
IsRHSZero = RHSConst && RHSConst->isZero();
LLVM_FALLTHROUGH;
[[fallthrough]];
}
case ISD::SETLE: {
if (CmpInGPR == ICGPR_NonExtIn)
Expand Down Expand Up @@ -3430,7 +3430,7 @@ IntegerCompareEliminator::get32BitSExtCompare(SDValue LHS, SDValue RHS,
ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
IsRHSZero = RHSConst && RHSConst->isZero();
IsRHSOne = RHSConst && RHSConst->getSExtValue() == 1;
LLVM_FALLTHROUGH;
[[fallthrough]];
}
case ISD::SETLT: {
// (sext (setcc %a, %b, setgt)) -> (ashr (sub %a, %b), 63)
Expand Down Expand Up @@ -3459,7 +3459,7 @@ IntegerCompareEliminator::get32BitSExtCompare(SDValue LHS, SDValue RHS,
// (sext (setcc %a, %b, setuge)) -> (add (lshr (sub %a, %b), 63), -1)
// (sext (setcc %a, %b, setule)) -> (add (lshr (sub %b, %a), 63), -1)
std::swap(LHS, RHS);
LLVM_FALLTHROUGH;
[[fallthrough]];
case ISD::SETULE: {
if (CmpInGPR == ICGPR_NonExtIn)
return SDValue();
Expand All @@ -3479,7 +3479,7 @@ IntegerCompareEliminator::get32BitSExtCompare(SDValue LHS, SDValue RHS,
// (sext (setcc %a, %b, setugt)) -> (ashr (sub %b, %a), 63)
// (sext (setcc %a, %b, setugt)) -> (ashr (sub %a, %b), 63)
std::swap(LHS, RHS);
LLVM_FALLTHROUGH;
[[fallthrough]];
case ISD::SETULT: {
if (CmpInGPR == ICGPR_NonExtIn)
return SDValue();
Expand Down Expand Up @@ -3542,7 +3542,7 @@ IntegerCompareEliminator::get64BitZExtCompare(SDValue LHS, SDValue RHS,
std::swap(LHS, RHS);
ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
IsRHSZero = RHSConst && RHSConst->isZero();
LLVM_FALLTHROUGH;
[[fallthrough]];
}
case ISD::SETLE: {
// {subc.reg, subc.CA} = (subcarry %b, %a)
Expand Down Expand Up @@ -3585,7 +3585,7 @@ IntegerCompareEliminator::get64BitZExtCompare(SDValue LHS, SDValue RHS,
ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
IsRHSZero = RHSConst && RHSConst->isZero();
IsRHSOne = RHSConst && RHSConst->getSExtValue() == 1;
LLVM_FALLTHROUGH;
[[fallthrough]];
}
case ISD::SETLT: {
// {subc.reg, subc.CA} = (subcarry %a, %b)
Expand Down Expand Up @@ -3618,7 +3618,7 @@ IntegerCompareEliminator::get64BitZExtCompare(SDValue LHS, SDValue RHS,
// {subc.reg, subc.CA} = (subcarry %a, %b)
// (zext (setcc %a, %b, setuge)) -> (add (sube %b, %b, subc.CA), 1)
std::swap(LHS, RHS);
LLVM_FALLTHROUGH;
[[fallthrough]];
case ISD::SETULE: {
// {subc.reg, subc.CA} = (subcarry %b, %a)
// (zext (setcc %a, %b, setule)) -> (add (sube %a, %a, subc.CA), 1)
Expand All @@ -3635,7 +3635,7 @@ IntegerCompareEliminator::get64BitZExtCompare(SDValue LHS, SDValue RHS,
// {subc.reg, subc.CA} = (subcarry %b, %a)
// (zext (setcc %a, %b, setugt)) -> -(sube %b, %b, subc.CA)
std::swap(LHS, RHS);
LLVM_FALLTHROUGH;
[[fallthrough]];
case ISD::SETULT: {
// {subc.reg, subc.CA} = (subcarry %a, %b)
// (zext (setcc %a, %b, setult)) -> -(sube %a, %a, subc.CA)
Expand Down Expand Up @@ -3701,7 +3701,7 @@ IntegerCompareEliminator::get64BitSExtCompare(SDValue LHS, SDValue RHS,
std::swap(LHS, RHS);
ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
IsRHSZero = RHSConst && RHSConst->isZero();
LLVM_FALLTHROUGH;
[[fallthrough]];
}
case ISD::SETLE: {
// {subc.reg, subc.CA} = (subcarry %b, %a)
Expand Down Expand Up @@ -3745,7 +3745,7 @@ IntegerCompareEliminator::get64BitSExtCompare(SDValue LHS, SDValue RHS,
ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
IsRHSZero = RHSConst && RHSConst->isZero();
IsRHSOne = RHSConst && RHSConst->getSExtValue() == 1;
LLVM_FALLTHROUGH;
[[fallthrough]];
}
case ISD::SETLT: {
// {subc.reg, subc.CA} = (subcarry %a, %b)
Expand Down Expand Up @@ -3781,7 +3781,7 @@ IntegerCompareEliminator::get64BitSExtCompare(SDValue LHS, SDValue RHS,
// {subc.reg, subc.CA} = (subcarry %a, %b)
// (sext (setcc %a, %b, setuge)) -> ~(sube %b, %b, subc.CA)
std::swap(LHS, RHS);
LLVM_FALLTHROUGH;
[[fallthrough]];
case ISD::SETULE: {
// {subc.reg, subc.CA} = (subcarry %b, %a)
// (sext (setcc %a, %b, setule)) -> ~(sube %a, %a, subc.CA)
Expand All @@ -3798,7 +3798,7 @@ IntegerCompareEliminator::get64BitSExtCompare(SDValue LHS, SDValue RHS,
// {subc.reg, subc.CA} = (subcarry %b, %a)
// (sext (setcc %a, %b, setugt)) -> (sube %b, %b, subc.CA)
std::swap(LHS, RHS);
LLVM_FALLTHROUGH;
[[fallthrough]];
case ISD::SETULT: {
// {subc.reg, subc.CA} = (subcarry %a, %b)
// (sext (setcc %a, %b, setult)) -> (sube %a, %a, subc.CA)
Expand Down Expand Up @@ -4604,7 +4604,7 @@ static bool mayUseP9Setb(SDNode *N, const ISD::CondCode &CC, SelectionDAG *DAG,
if (!IsUnCmp && InnerCC != ISD::SETNE)
return false;
IsUnCmp = true;
LLVM_FALLTHROUGH;
[[fallthrough]];
case ISD::SETLT:
if (InnerCC == ISD::SETNE || (InnerCC == ISD::SETGT && !InnerSwapped) ||
(InnerCC == ISD::SETLT && InnerSwapped))
Expand All @@ -4623,7 +4623,7 @@ static bool mayUseP9Setb(SDNode *N, const ISD::CondCode &CC, SelectionDAG *DAG,
if (!IsUnCmp && InnerCC != ISD::SETNE)
return false;
IsUnCmp = true;
LLVM_FALLTHROUGH;
[[fallthrough]];
case ISD::SETGT:
if (InnerCC == ISD::SETNE || (InnerCC == ISD::SETLT && !InnerSwapped) ||
(InnerCC == ISD::SETGT && InnerSwapped))
Expand Down Expand Up @@ -6488,7 +6488,7 @@ void PPCDAGToDAGISel::PeepholeCROps() {
Op.getOperand(0) == Op.getOperand(1))
Op2Not = true;
}
LLVM_FALLTHROUGH;
[[fallthrough]];
}
case PPC::BC:
case PPC::BCn:
Expand Down Expand Up @@ -7306,7 +7306,7 @@ void PPCDAGToDAGISel::PeepholePPC64() {
case PPC::DFLOADf64:
case PPC::DFLOADf32:
RequiresMod4Offset = true;
LLVM_FALLTHROUGH;
[[fallthrough]];
case PPC::LBZ:
case PPC::LBZ8:
case PPC::LFD:
Expand All @@ -7324,7 +7324,7 @@ void PPCDAGToDAGISel::PeepholePPC64() {
case PPC::DFSTOREf64:
case PPC::DFSTOREf32:
RequiresMod4Offset = true;
LLVM_FALLTHROUGH;
[[fallthrough]];
case PPC::STB:
case PPC::STB8:
case PPC::STFD:
Expand Down
14 changes: 7 additions & 7 deletions llvm/lib/Target/PowerPC/PPCISelLowering.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6646,7 +6646,7 @@ static bool CC_AIX(unsigned ValNo, MVT ValVT, MVT LocVT,
case MVT::i64:
// i64 arguments should have been split to i32 for PPC32.
assert(IsPPC64 && "PPC32 should have split i64 values.");
LLVM_FALLTHROUGH;
[[fallthrough]];
case MVT::i1:
case MVT::i32: {
const unsigned Offset = State.AllocateStack(PtrAlign.value(), PtrAlign);
Expand Down Expand Up @@ -7945,7 +7945,7 @@ SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
default: break; // SETUO etc aren't handled by fsel.
case ISD::SETNE:
std::swap(TV, FV);
LLVM_FALLTHROUGH;
[[fallthrough]];
case ISD::SETEQ:
if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
Expand All @@ -7957,7 +7957,7 @@ SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
case ISD::SETULT:
case ISD::SETLT:
std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
LLVM_FALLTHROUGH;
[[fallthrough]];
case ISD::SETOGE:
case ISD::SETGE:
if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
Expand All @@ -7966,7 +7966,7 @@ SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
case ISD::SETUGT:
case ISD::SETGT:
std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
LLVM_FALLTHROUGH;
[[fallthrough]];
case ISD::SETOLE:
case ISD::SETLE:
if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
Expand All @@ -7980,7 +7980,7 @@ SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
default: break; // SETUO etc aren't handled by fsel.
case ISD::SETNE:
std::swap(TV, FV);
LLVM_FALLTHROUGH;
[[fallthrough]];
case ISD::SETEQ:
Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, Flags);
if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
Expand Down Expand Up @@ -15140,7 +15140,7 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
case ISD::SETCC:
if (SDValue CSCC = combineSetCC(N, DCI))
return CSCC;
LLVM_FALLTHROUGH;
[[fallthrough]];
case ISD::SELECT_CC:
return DAGCombineTruncBoolExt(N, DCI);
case ISD::SINT_TO_FP:
Expand Down Expand Up @@ -16957,7 +16957,7 @@ bool PPCTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
// we can materialize all immediatess via XXSPLTI32DX and XXSPLTIDP.
return true;
}
LLVM_FALLTHROUGH;
[[fallthrough]];
case MVT::ppcf128:
return Imm.isPosZero();
}
Expand Down
10 changes: 5 additions & 5 deletions llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3022,7 +3022,7 @@ bool PPCInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
// BUILD_UACC is expanded to 4 copies of the underlying vsx registers.
// So after building the 4 copies, we can replace the BUILD_UACC instruction
// with a NOP.
LLVM_FALLTHROUGH;
[[fallthrough]];
}
case PPC::KILL_PAIR: {
MI.setDesc(get(PPC::UNENCODED_NOP));
Expand Down Expand Up @@ -4259,7 +4259,7 @@ bool PPCInstrInfo::instrHasImmForm(unsigned Opc, bool IsVFReg,
}
break;
}
LLVM_FALLTHROUGH;
[[fallthrough]];
case PPC::XFLOADf32:
III.ImmOpcode = PPC::DFLOADf32;
break;
Expand All @@ -4273,7 +4273,7 @@ bool PPCInstrInfo::instrHasImmForm(unsigned Opc, bool IsVFReg,
}
break;
}
LLVM_FALLTHROUGH;
[[fallthrough]];
case PPC::XFLOADf64:
III.ImmOpcode = PPC::DFLOADf64;
break;
Expand All @@ -4291,7 +4291,7 @@ bool PPCInstrInfo::instrHasImmForm(unsigned Opc, bool IsVFReg,
}
break;
}
LLVM_FALLTHROUGH;
[[fallthrough]];
case PPC::XFSTOREf32:
III.ImmOpcode = PPC::DFSTOREf32;
break;
Expand All @@ -4305,7 +4305,7 @@ bool PPCInstrInfo::instrHasImmForm(unsigned Opc, bool IsVFReg,
}
break;
}
LLVM_FALLTHROUGH;
[[fallthrough]];
case PPC::XFSTOREf64:
III.ImmOpcode = PPC::DFSTOREf64;
break;
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -256,12 +256,12 @@ InstructionCost PPCTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx,
return TTI::TCC_Free;
case Instruction::And:
RunFree = true; // (for the rotate-and-mask instructions)
LLVM_FALLTHROUGH;
[[fallthrough]];
case Instruction::Add:
case Instruction::Or:
case Instruction::Xor:
ShiftedFree = true;
LLVM_FALLTHROUGH;
[[fallthrough]];
case Instruction::Sub:
case Instruction::Mul:
case Instruction::Shl:
Expand All @@ -273,7 +273,7 @@ InstructionCost PPCTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx,
UnsignedFree = true;
ImmIdx = 1;
// Zero comparisons can use record-form instructions.
LLVM_FALLTHROUGH;
[[fallthrough]];
case Instruction::Select:
ZeroFree = true;
break;
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7110,7 +7110,7 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,

return;
}
LLVM_FALLTHROUGH;
[[fallthrough]];
}
case ISD::ADD:
case ISD::SUB:
Expand Down Expand Up @@ -9406,7 +9406,7 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
case ISD::SRA:
if (SDValue V = performSRACombine(N, DAG, Subtarget))
return V;
LLVM_FALLTHROUGH;
[[fallthrough]];
case ISD::SRL:
case ISD::SHL: {
SDValue ShAmt = N->getOperand(1);
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -275,7 +275,7 @@ static bool isSignExtendingOpW(MachineInstr &MI, MachineRegisterInfo &MRI,
// SLLIW reads the lowest 5 bits, while SLLI reads lowest 6 bits
if (MI.getOperand(2).getImm() >= 32)
return false;
LLVM_FALLTHROUGH;
[[fallthrough]];
case RISCV::ADD:
case RISCV::LD:
case RISCV::LWU:
Expand Down Expand Up @@ -337,7 +337,7 @@ static bool isSignExtendedW(MachineInstr &OrigMI, MachineRegisterInfo &MRI,
case RISCV::BSETI:
if (MI->getOperand(2).getImm() >= 31)
return false;
LLVM_FALLTHROUGH;
[[fallthrough]];
case RISCV::REM:
case RISCV::ANDI:
case RISCV::ORI:
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -67,7 +67,7 @@ InstructionCost RISCVTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx,
// zext.w
if (Imm == UINT64_C(0xffffffff) && ST->hasStdExtZba())
return TTI::TCC_Free;
LLVM_FALLTHROUGH;
[[fallthrough]];
case Instruction::Add:
case Instruction::Or:
case Instruction::Xor:
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -279,7 +279,7 @@ namespace {
case Sparc::fixup_sparc_wplt30:
if (Target.getSymA()->getSymbol().isTemporary())
return false;
LLVM_FALLTHROUGH;
[[fallthrough]];
case Sparc::fixup_sparc_tls_gd_hi22:
case Sparc::fixup_sparc_tls_gd_lo10:
case Sparc::fixup_sparc_tls_gd_add:
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -227,7 +227,7 @@ void SparcMCExpr::fixELFSymbolsInTLSFixups(MCAssembler &Asm) const {
auto ELFSymbol = cast<MCSymbolELF>(Symbol);
if (!ELFSymbol->isBindingSet())
ELFSymbol->setBinding(ELF::STB_GLOBAL);
LLVM_FALLTHROUGH;
[[fallthrough]];
}
case VK_Sparc_TLS_GD_HI22:
case VK_Sparc_TLS_GD_LO10:
Expand Down
26 changes: 13 additions & 13 deletions llvm/lib/Target/Sparc/SparcInstrInfo.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -117,19 +117,19 @@ static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)

case SPCC::CPCC_A: return SPCC::CPCC_N;
case SPCC::CPCC_N: return SPCC::CPCC_A;
case SPCC::CPCC_3: LLVM_FALLTHROUGH;
case SPCC::CPCC_2: LLVM_FALLTHROUGH;
case SPCC::CPCC_23: LLVM_FALLTHROUGH;
case SPCC::CPCC_1: LLVM_FALLTHROUGH;
case SPCC::CPCC_13: LLVM_FALLTHROUGH;
case SPCC::CPCC_12: LLVM_FALLTHROUGH;
case SPCC::CPCC_123: LLVM_FALLTHROUGH;
case SPCC::CPCC_0: LLVM_FALLTHROUGH;
case SPCC::CPCC_03: LLVM_FALLTHROUGH;
case SPCC::CPCC_02: LLVM_FALLTHROUGH;
case SPCC::CPCC_023: LLVM_FALLTHROUGH;
case SPCC::CPCC_01: LLVM_FALLTHROUGH;
case SPCC::CPCC_013: LLVM_FALLTHROUGH;
case SPCC::CPCC_3: [[fallthrough]];
case SPCC::CPCC_2: [[fallthrough]];
case SPCC::CPCC_23: [[fallthrough]];
case SPCC::CPCC_1: [[fallthrough]];
case SPCC::CPCC_13: [[fallthrough]];
case SPCC::CPCC_12: [[fallthrough]];
case SPCC::CPCC_123: [[fallthrough]];
case SPCC::CPCC_0: [[fallthrough]];
case SPCC::CPCC_03: [[fallthrough]];
case SPCC::CPCC_02: [[fallthrough]];
case SPCC::CPCC_023: [[fallthrough]];
case SPCC::CPCC_01: [[fallthrough]];
case SPCC::CPCC_013: [[fallthrough]];
case SPCC::CPCC_012:
// "Opposite" code is not meaningful, as we don't know
// what the CoProc condition means here. The cond-code will
Expand Down
8 changes: 4 additions & 4 deletions llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -860,7 +860,7 @@ bool SystemZDAGToDAGISel::expandRxSBG(RxSBGOperands &RxSBG) const {
RxSBG.Input = N.getOperand(0);
return true;
}
LLVM_FALLTHROUGH;
[[fallthrough]];

case ISD::SIGN_EXTEND: {
// Check that the extension bits are don't-care (i.e. are masked out
Expand Down Expand Up @@ -1349,7 +1349,7 @@ bool SystemZDAGToDAGISel::tryFoldLoadStoreIntoMemOperand(SDNode *Node) {
return false;
case SystemZISD::SSUBO:
NegateOperand = true;
LLVM_FALLTHROUGH;
[[fallthrough]];
case SystemZISD::SADDO:
if (MemVT == MVT::i32)
NewOpc = SystemZ::ASI;
Expand All @@ -1360,7 +1360,7 @@ bool SystemZDAGToDAGISel::tryFoldLoadStoreIntoMemOperand(SDNode *Node) {
break;
case SystemZISD::USUBO:
NegateOperand = true;
LLVM_FALLTHROUGH;
[[fallthrough]];
case SystemZISD::UADDO:
if (MemVT == MVT::i32)
NewOpc = SystemZ::ALSI;
Expand Down Expand Up @@ -1562,7 +1562,7 @@ void SystemZDAGToDAGISel::Select(SDNode *Node) {
if (Node->getOperand(1).getOpcode() != ISD::Constant)
if (tryRxSBG(Node, SystemZ::RNSBG))
return;
LLVM_FALLTHROUGH;
[[fallthrough]];
case ISD::ROTL:
case ISD::SHL:
case ISD::SRL:
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3037,7 +3037,7 @@ SDValue SystemZTargetLowering::lowerVectorSETCC(SelectionDAG &DAG,
// Handle tests for order using (or (ogt y x) (oge x y)).
case ISD::SETUO:
Invert = true;
LLVM_FALLTHROUGH;
[[fallthrough]];
case ISD::SETO: {
assert(IsFP && "Unexpected integer comparison");
SDValue LT = getVectorCmp(DAG, getVectorComparison(ISD::SETOGT, Mode),
Expand All @@ -3054,7 +3054,7 @@ SDValue SystemZTargetLowering::lowerVectorSETCC(SelectionDAG &DAG,
// Handle <> tests using (or (ogt y x) (ogt x y)).
case ISD::SETUEQ:
Invert = true;
LLVM_FALLTHROUGH;
[[fallthrough]];
case ISD::SETONE: {
assert(IsFP && "Unexpected integer comparison");
SDValue LT = getVectorCmp(DAG, getVectorComparison(ISD::SETOGT, Mode),
Expand Down Expand Up @@ -7320,7 +7320,7 @@ SystemZTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
case Intrinsic::s390_vupllh:
case Intrinsic::s390_vupllf:
IsLogical = true;
LLVM_FALLTHROUGH;
[[fallthrough]];
case Intrinsic::s390_vuphb: // VECTOR UNPACK HIGH
case Intrinsic::s390_vuphh:
case Intrinsic::s390_vuphf:
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -629,7 +629,7 @@ bool SystemZInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
switch (UseOpc) {
case SystemZ::SELRMux:
TieOps = true;
LLVM_FALLTHROUGH;
[[fallthrough]];
case SystemZ::LOCRMux:
if (!STI.hasLoadStoreOnCond2())
return false;
Expand All @@ -643,7 +643,7 @@ bool SystemZInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
break;
case SystemZ::SELGR:
TieOps = true;
LLVM_FALLTHROUGH;
[[fallthrough]];
case SystemZ::LOCGR:
if (!STI.hasLoadStoreOnCond2())
return false;
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1056,7 +1056,7 @@ isFoldableLoad(const LoadInst *Ld, const Instruction *&FoldedValue) {
case Instruction::ICmp:
if (LoadedBits == 32 && ZExtBits == 64)
return true;
LLVM_FALLTHROUGH;
[[fallthrough]];
case Instruction::Mul: // SE: 16->32, 32->64, z14:16->64
if (UserI->getOpcode() != Instruction::ICmp) {
if (LoadedBits == 16 &&
Expand All @@ -1066,11 +1066,11 @@ isFoldableLoad(const LoadInst *Ld, const Instruction *&FoldedValue) {
if (LoadOrTruncBits == 16)
return true;
}
LLVM_FALLTHROUGH;
[[fallthrough]];
case Instruction::SDiv:// SE: 32->64
if (LoadedBits == 32 && SExtBits == 64)
return true;
LLVM_FALLTHROUGH;
[[fallthrough]];
case Instruction::UDiv:
case Instruction::And:
case Instruction::Or:
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/VE/VEISelLowering.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2710,7 +2710,7 @@ static bool isI32Insn(const SDNode *User, const SDNode *N) {
if (User->getOperand(2).getNode() != N &&
User->getOperand(3).getNode() != N)
return true;
LLVM_FALLTHROUGH;
[[fallthrough]];
case ISD::AND:
case ISD::OR:
case ISD::XOR:
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmTypeCheck.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -184,7 +184,7 @@ bool WebAssemblyAsmTypeCheck::getGlobal(SMLoc ErrorLoc, const MCInst &Inst,
default:
break;
}
LLVM_FALLTHROUGH;
[[fallthrough]];
default:
return typeError(ErrorLoc, StringRef("symbol ") + WasmSym->getName() +
" missing .globaltype");
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1501,7 +1501,7 @@ void WebAssemblyCFGStackify::fixEndsAtEndOfFunction(MachineFunction &MF) {
std::next(WebAssembly::findCatch(EHPad)->getReverseIterator());
if (NextIt != EHPad->rend())
Worklist.push_back(NextIt);
LLVM_FALLTHROUGH;
[[fallthrough]];
}
case WebAssembly::END_BLOCK:
case WebAssembly::END_LOOP:
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1260,7 +1260,7 @@ bool WebAssemblyFastISel::selectStore(const Instruction *I) {
switch (getSimpleType(Store->getValueOperand()->getType())) {
case MVT::i1:
VTIsi1 = true;
LLVM_FALLTHROUGH;
[[fallthrough]];
case MVT::i8:
Opc = A64 ? WebAssembly::STORE8_I32_A64 : WebAssembly::STORE8_I32_A32;
break;
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1921,7 +1921,7 @@ bool X86AsmParser::ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End) {
break;
return Error(Tok.getLoc(), "unknown token in expression");
}
LLVM_FALLTHROUGH;
[[fallthrough]];
case AsmToken::String: {
if (Parser.isParsingMasm()) {
// MASM parsers handle strings in expressions as constants.
Expand All @@ -1937,7 +1937,7 @@ bool X86AsmParser::ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End) {
return Error(ValueLoc, ErrMsg);
break;
}
LLVM_FALLTHROUGH;
[[fallthrough]];
}
case AsmToken::At:
case AsmToken::Identifier: {
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -713,7 +713,7 @@ static int readModRM(struct InternalInstruction *insn) {
break;
case 0x1:
insn->displacementSize = 1;
LLVM_FALLTHROUGH;
[[fallthrough]];
case 0x2:
insn->eaDisplacement = (mod == 0x1 ? EA_DISP_8 : EA_DISP_32);
switch (rm & 7) {
Expand Down
150 changes: 75 additions & 75 deletions llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
View file

Large diffs are not rendered by default.

2 changes: 1 addition & 1 deletion llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1373,7 +1373,7 @@ void X86MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
OpcodeOffset = MI.getOperand(NumOps - 1).getImm();
assert(OpcodeOffset < 16 && "Unexpected opcode offset!");
--NumOps; // Drop the operand from the end.
LLVM_FALLTHROUGH;
[[fallthrough]];
case X86II::RawFrm:
emitByte(BaseOpcode + OpcodeOffset, OS);

Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/X86/X86AsmPrinter.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -474,7 +474,7 @@ static bool printAsmMRegister(const X86AsmPrinter &P, const MachineOperand &MO,
break;
case 'V':
EmitPercent = false;
LLVM_FALLTHROUGH;
[[fallthrough]];
case 'q':
// Print 64-bit register names if 64-bit integer registers are available.
// Otherwise, print 32-bit register names.
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/X86/X86DynAllocaExpander.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -231,7 +231,7 @@ void X86DynAllocaExpander::lower(MachineInstr *MI, Lowering L) {
break;

// Fall through to make any remaining adjustment.
LLVM_FALLTHROUGH;
[[fallthrough]];
}
case Sub:
assert(Amount > 0);
Expand Down
18 changes: 9 additions & 9 deletions llvm/lib/Target/X86/X86FastISel.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -188,15 +188,15 @@ getX86SSEConditionCode(CmpInst::Predicate Predicate) {
switch (Predicate) {
default: llvm_unreachable("Unexpected predicate");
case CmpInst::FCMP_OEQ: CC = 0; break;
case CmpInst::FCMP_OGT: NeedSwap = true; LLVM_FALLTHROUGH;
case CmpInst::FCMP_OGT: NeedSwap = true; [[fallthrough]];
case CmpInst::FCMP_OLT: CC = 1; break;
case CmpInst::FCMP_OGE: NeedSwap = true; LLVM_FALLTHROUGH;
case CmpInst::FCMP_OGE: NeedSwap = true; [[fallthrough]];
case CmpInst::FCMP_OLE: CC = 2; break;
case CmpInst::FCMP_UNO: CC = 3; break;
case CmpInst::FCMP_UNE: CC = 4; break;
case CmpInst::FCMP_ULE: NeedSwap = true; LLVM_FALLTHROUGH;
case CmpInst::FCMP_ULE: NeedSwap = true; [[fallthrough]];
case CmpInst::FCMP_UGE: CC = 5; break;
case CmpInst::FCMP_ULT: NeedSwap = true; LLVM_FALLTHROUGH;
case CmpInst::FCMP_ULT: NeedSwap = true; [[fallthrough]];
case CmpInst::FCMP_UGT: CC = 6; break;
case CmpInst::FCMP_ORD: CC = 7; break;
case CmpInst::FCMP_UEQ: CC = 8; break;
Expand Down Expand Up @@ -500,7 +500,7 @@ bool X86FastISel::X86FastEmitStore(EVT VT, unsigned ValReg, X86AddressMode &AM,
TII.get(X86::AND8ri), AndResult)
.addReg(ValReg).addImm(1);
ValReg = AndResult;
LLVM_FALLTHROUGH; // handle i1 as i8.
[[fallthrough]]; // handle i1 as i8.
}
case MVT::i8: Opc = X86::MOV8mr; break;
case MVT::i16: Opc = X86::MOV16mr; break;
Expand Down Expand Up @@ -666,7 +666,7 @@ bool X86FastISel::X86FastEmitStore(EVT VT, const Value *Val,
default: break;
case MVT::i1:
Signed = false;
LLVM_FALLTHROUGH; // Handle as i8.
[[fallthrough]]; // Handle as i8.
case MVT::i8: Opc = X86::MOV8mi; break;
case MVT::i16: Opc = X86::MOV16mi; break;
case MVT::i32: Opc = X86::MOV32mi; break;
Expand Down Expand Up @@ -1688,7 +1688,7 @@ bool X86FastISel::X86SelectBranch(const Instruction *I) {
default: break;
case CmpInst::FCMP_OEQ:
std::swap(TrueMBB, FalseMBB);
LLVM_FALLTHROUGH;
[[fallthrough]];
case CmpInst::FCMP_UNE:
NeedExtraBranch = true;
Predicate = CmpInst::FCMP_ONE;
Expand Down Expand Up @@ -3117,7 +3117,7 @@ bool X86FastISel::fastLowerArguments() {
default: llvm_unreachable("Unexpected value type.");
case MVT::i32: SrcReg = GPR32ArgRegs[GPRIdx++]; break;
case MVT::i64: SrcReg = GPR64ArgRegs[GPRIdx++]; break;
case MVT::f32: LLVM_FALLTHROUGH;
case MVT::f32: [[fallthrough]];
case MVT::f64: SrcReg = XMMArgRegs[FPRIdx++]; break;
}
Register DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC);
Expand Down Expand Up @@ -3697,7 +3697,7 @@ unsigned X86FastISel::X86MaterializeInt(const ConstantInt *CI, MVT VT) {
default: llvm_unreachable("Unexpected value type");
case MVT::i1:
VT = MVT::i8;
LLVM_FALLTHROUGH;
[[fallthrough]];
case MVT::i8: Opc = X86::MOV8ri; break;
case MVT::i16: Opc = X86::MOV16ri; break;
case MVT::i32: Opc = X86::MOV32ri; break;
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/X86/X86FrameLowering.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1533,7 +1533,7 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF,
.addUse(X86::NoRegister);
break;
}
LLVM_FALLTHROUGH;
[[fallthrough]];

case SwiftAsyncFramePointerMode::Always:
BuildMI(MBB, MBBI, DL, TII.get(X86::BTS64ri8), MachineFramePtr)
Expand Down
14 changes: 7 additions & 7 deletions llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2313,7 +2313,7 @@ bool X86DAGToDAGISel::matchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
case ISD::UMUL_LOHI:
// A mul_lohi where we need the low part can be folded as a plain multiply.
if (N.getResNo() != 0) break;
LLVM_FALLTHROUGH;
[[fallthrough]];
case ISD::MUL:
case X86ISD::MUL_IMM:
// X*[3,5,9] -> X+X*[2,4,8]
Expand Down Expand Up @@ -3310,7 +3310,7 @@ bool X86DAGToDAGISel::foldLoadStoreIntoMemOperand(SDNode *Node) {
MVT::Other, Ops);
break;
}
LLVM_FALLTHROUGH;
[[fallthrough]];
case X86ISD::ADD:
// Try to match inc/dec.
if (!Subtarget->slowIncDec() || CurDAG->shouldOptForSize()) {
Expand All @@ -3328,7 +3328,7 @@ bool X86DAGToDAGISel::foldLoadStoreIntoMemOperand(SDNode *Node) {
break;
}
}
LLVM_FALLTHROUGH;
[[fallthrough]];
case X86ISD::ADC:
case X86ISD::SBB:
case X86ISD::AND:
Expand Down Expand Up @@ -4962,7 +4962,7 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
case ISD::SRL:
if (matchBitExtract(Node))
return;
LLVM_FALLTHROUGH;
[[fallthrough]];
case ISD::SRA:
case ISD::SHL:
if (tryShiftAmountMod(Node))
Expand Down Expand Up @@ -5005,7 +5005,7 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
if (AndImmShrink && shrinkAndImmediate(Node))
return;

LLVM_FALLTHROUGH;
[[fallthrough]];
case ISD::OR:
case ISD::XOR:
if (tryShrinkShlLogicImm(Node))
Expand All @@ -5015,7 +5015,7 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
if (tryVPTERNLOG(Node))
return;

LLVM_FALLTHROUGH;
[[fallthrough]];
case ISD::ADD:
case ISD::SUB: {
// Try to avoid folding immediates with multiple uses for optsize.
Expand Down Expand Up @@ -5126,7 +5126,7 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
// i16/i32/i64 are handled with isel patterns.
if (NVT != MVT::i8)
break;
LLVM_FALLTHROUGH;
[[fallthrough]];
case X86ISD::UMUL: {
SDValue N0 = Node->getOperand(0);
SDValue N1 = Node->getOperand(1);
Expand Down
80 changes: 40 additions & 40 deletions llvm/lib/Target/X86/X86ISelLowering.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -12803,11 +12803,11 @@ static SDValue lowerShuffleAsBlend(const SDLoc &DL, MVT VT, SDValue V1,
case MVT::v4i64:
case MVT::v8i32:
assert(Subtarget.hasAVX2() && "256-bit integer blends require AVX2!");
LLVM_FALLTHROUGH;
[[fallthrough]];
case MVT::v4f64:
case MVT::v8f32:
assert(Subtarget.hasAVX() && "256-bit float blends require AVX!");
LLVM_FALLTHROUGH;
[[fallthrough]];
case MVT::v2f64:
case MVT::v2i64:
case MVT::v4f32:
Expand Down Expand Up @@ -12843,11 +12843,11 @@ static SDValue lowerShuffleAsBlend(const SDLoc &DL, MVT VT, SDValue V1,
MVT::v16i16, DL, Lo, Hi,
{0, 1, 2, 3, 4, 5, 6, 7, 24, 25, 26, 27, 28, 29, 30, 31});
}
LLVM_FALLTHROUGH;
[[fallthrough]];
}
case MVT::v32i8:
assert(Subtarget.hasAVX2() && "256-bit byte-blends require AVX2!");
LLVM_FALLTHROUGH;
[[fallthrough]];
case MVT::v16i8: {
assert(Subtarget.hasSSE41() && "128-bit byte-blends require SSE41!");

Expand Down Expand Up @@ -23615,7 +23615,7 @@ static SDValue EmitTest(SDValue Op, unsigned X86CC, const SDLoc &dl,
case ISD::SHL:
if (Op.getNode()->getFlags().hasNoSignedWrap())
break;
LLVM_FALLTHROUGH;
[[fallthrough]];
default:
NeedOF = true;
break;
Expand Down Expand Up @@ -23646,7 +23646,7 @@ static SDValue EmitTest(SDValue Op, unsigned X86CC, const SDLoc &dl,
if (!hasNonFlagsUse(Op))
break;

LLVM_FALLTHROUGH;
[[fallthrough]];
case ISD::ADD:
case ISD::SUB:
case ISD::OR:
Expand Down Expand Up @@ -24057,19 +24057,19 @@ static unsigned translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
case ISD::SETOEQ:
case ISD::SETEQ: SSECC = 0; break;
case ISD::SETOGT:
case ISD::SETGT: Swap = true; LLVM_FALLTHROUGH;
case ISD::SETGT: Swap = true; [[fallthrough]];
case ISD::SETLT:
case ISD::SETOLT: SSECC = 1; break;
case ISD::SETOGE:
case ISD::SETGE: Swap = true; LLVM_FALLTHROUGH;
case ISD::SETGE: Swap = true; [[fallthrough]];
case ISD::SETLE:
case ISD::SETOLE: SSECC = 2; break;
case ISD::SETUO: SSECC = 3; break;
case ISD::SETUNE:
case ISD::SETNE: SSECC = 4; break;
case ISD::SETULE: Swap = true; LLVM_FALLTHROUGH;
case ISD::SETULE: Swap = true; [[fallthrough]];
case ISD::SETUGE: SSECC = 5; break;
case ISD::SETULT: Swap = true; LLVM_FALLTHROUGH;
case ISD::SETULT: Swap = true; [[fallthrough]];
case ISD::SETUGT: SSECC = 6; break;
case ISD::SETO: SSECC = 7; break;
case ISD::SETUEQ: SSECC = 8; break;
Expand Down Expand Up @@ -24521,9 +24521,9 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget &Subtarget,
unsigned Opc;
switch (Cond) {
default: llvm_unreachable("Unexpected condition code");
case ISD::SETUGT: Invert = true; LLVM_FALLTHROUGH;
case ISD::SETUGT: Invert = true; [[fallthrough]];
case ISD::SETULE: Opc = ISD::UMIN; break;
case ISD::SETULT: Invert = true; LLVM_FALLTHROUGH;
case ISD::SETULT: Invert = true; [[fallthrough]];
case ISD::SETUGE: Opc = ISD::UMAX; break;
}

Expand Down Expand Up @@ -27164,7 +27164,7 @@ SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
case Intrinsic::x86_avx_vtestz_ps_256:
case Intrinsic::x86_avx_vtestz_pd_256:
TestOpc = X86ISD::TESTP;
LLVM_FALLTHROUGH;
[[fallthrough]];
case Intrinsic::x86_sse41_ptestz:
case Intrinsic::x86_avx_ptestz_256:
// ZF = 1
Expand All @@ -27175,7 +27175,7 @@ SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
case Intrinsic::x86_avx_vtestc_ps_256:
case Intrinsic::x86_avx_vtestc_pd_256:
TestOpc = X86ISD::TESTP;
LLVM_FALLTHROUGH;
[[fallthrough]];
case Intrinsic::x86_sse41_ptestc:
case Intrinsic::x86_avx_ptestc_256:
// CF = 1
Expand All @@ -27186,7 +27186,7 @@ SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
case Intrinsic::x86_avx_vtestnzc_ps_256:
case Intrinsic::x86_avx_vtestnzc_pd_256:
TestOpc = X86ISD::TESTP;
LLVM_FALLTHROUGH;
[[fallthrough]];
case Intrinsic::x86_sse41_ptestnzc:
case Intrinsic::x86_avx_ptestnzc_256:
// ZF and CF = 0
Expand Down Expand Up @@ -39518,7 +39518,7 @@ combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,

Chain.push_back(V);

LLVM_FALLTHROUGH;
[[fallthrough]];
case ISD::BITCAST:
V = V.getOperand(0);
continue;
Expand Down Expand Up @@ -39663,7 +39663,7 @@ static SDValue canonicalizeShuffleWithBinOps(SDValue N, SelectionDAG &DAG,
if (!getTargetShuffleMask(N.getNode(), ShuffleVT.getSimpleVT(), false, Ops,
Mask))
break;
LLVM_FALLTHROUGH;
[[fallthrough]];
}
case X86ISD::VBROADCAST:
case X86ISD::MOVDDUP:
Expand Down Expand Up @@ -39708,7 +39708,7 @@ static SDValue canonicalizeShuffleWithBinOps(SDValue N, SelectionDAG &DAG,
unsigned ZeroMask = InsertPSMask & 0xF;
if (ZeroMask != 0)
break;
LLVM_FALLTHROUGH;
[[fallthrough]];
}
case X86ISD::MOVSD:
case X86ISD::MOVSS:
Expand Down Expand Up @@ -39793,7 +39793,7 @@ static SDValue canonicalizeLaneShuffleWithRepeatedOps(SDValue V,
if ((Mask & 0x3) != ((Mask >> 2) & 0x3))
break;
}
LLVM_FALLTHROUGH;
[[fallthrough]];
case X86ISD::VSHLI:
case X86ISD::VSRLI:
case X86ISD::VSRAI:
Expand Down Expand Up @@ -40968,7 +40968,7 @@ bool X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(
if (SimplifyDemandedVectorElts(Amt, AmtElts, AmtUndef, AmtZero, TLO,
Depth + 1, AssumeSingleUse))
return true;
LLVM_FALLTHROUGH;
[[fallthrough]];
}
case X86ISD::VSHLI:
case X86ISD::VSRLI:
Expand Down Expand Up @@ -42157,7 +42157,7 @@ static bool checkBitcastSrcVectorSize(SDValue Src, unsigned Size,
case ISD::TRUNCATE:
if (!AllowTruncate)
return false;
LLVM_FALLTHROUGH;
[[fallthrough]];
case ISD::SETCC:
return Src.getOperand(0).getValueSizeInBits() == Size;
case ISD::AND:
Expand Down Expand Up @@ -44609,7 +44609,7 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
// Converting this to a min would handle both negative zeros and NaNs
// incorrectly, but we can swap the operands to fix both.
std::swap(LHS, RHS);
LLVM_FALLTHROUGH;
[[fallthrough]];
case ISD::SETOLT:
case ISD::SETLT:
case ISD::SETLE:
Expand Down Expand Up @@ -44641,7 +44641,7 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
// Converting this to a max would handle both negative zeros and NaNs
// incorrectly, but we can swap the operands to fix both.
std::swap(LHS, RHS);
LLVM_FALLTHROUGH;
[[fallthrough]];
case ISD::SETOGT:
case ISD::SETGT:
case ISD::SETGE:
Expand Down Expand Up @@ -44676,7 +44676,7 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
// Converting this to a min would handle both negative zeros and NaNs
// incorrectly, but we can swap the operands to fix both.
std::swap(LHS, RHS);
LLVM_FALLTHROUGH;
[[fallthrough]];
case ISD::SETOGT:
case ISD::SETGT:
case ISD::SETGE:
Expand Down Expand Up @@ -44706,7 +44706,7 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
// Converting this to a max would handle both negative zeros and NaNs
// incorrectly, but we can swap the operands to fix both.
std::swap(LHS, RHS);
LLVM_FALLTHROUGH;
[[fallthrough]];
case ISD::SETOLT:
case ISD::SETLT:
case ISD::SETLE:
Expand Down Expand Up @@ -45218,7 +45218,7 @@ static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
break;
assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
"Invalid use of SETCC_CARRY!");
LLVM_FALLTHROUGH;
[[fallthrough]];
case X86ISD::SETCC:
// Set the condition code or opposite one if necessary.
CC = X86::CondCode(SetCC.getConstantOperandVal(0));
Expand Down Expand Up @@ -45291,7 +45291,7 @@ static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
case ISD::AND:
case X86ISD::AND:
isAnd = true;
LLVM_FALLTHROUGH;
[[fallthrough]];
case ISD::OR:
case X86ISD::OR:
SetCC0 = Cond->getOperand(0);
Expand Down Expand Up @@ -50114,7 +50114,7 @@ static SDValue combineTruncatedArithmetic(SDNode *N, SelectionDAG &DAG,
TLI.isOperationLegal(SrcOpcode, VT) &&
!TLI.isOperationLegal(SrcOpcode, SrcVT))
return TruncateArithmetic(Src.getOperand(0), Src.getOperand(1));
LLVM_FALLTHROUGH;
[[fallthrough]];
case ISD::AND:
case ISD::XOR:
case ISD::OR:
Expand Down Expand Up @@ -53967,7 +53967,7 @@ static SDValue combineConcatVectorOps(const SDLoc &DL, MVT VT,
return DAG.getNode(Op0.getOpcode(), DL, VT,
ConcatSubOperand(VT, Ops, 0), Op0.getOperand(1));
}
LLVM_FALLTHROUGH;
[[fallthrough]];
case X86ISD::VPERMILPI:
if (!IsSplat && NumOps == 2 && (VT == MVT::v8f32 || VT == MVT::v8i32) &&
Op0.getOperand(1) == Ops[1].getOperand(1)) {
Expand Down Expand Up @@ -54043,7 +54043,7 @@ static SDValue combineConcatVectorOps(const SDLoc &DL, MVT VT,
}
return DAG.getBitcast(VT, Res);
}
LLVM_FALLTHROUGH;
[[fallthrough]];
case X86ISD::VSRAI:
case X86ISD::VSHL:
case X86ISD::VSRL:
Expand Down Expand Up @@ -55328,7 +55328,7 @@ bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
case ISD::OR:
case ISD::XOR:
Commute = true;
LLVM_FALLTHROUGH;
[[fallthrough]];
case ISD::SUB: {
SDValue N0 = Op.getOperand(0);
SDValue N1 = Op.getOperand(1);
Expand Down Expand Up @@ -55581,7 +55581,7 @@ TargetLowering::ConstraintWeight
switch (*constraint) {
default:
weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
LLVM_FALLTHROUGH;
[[fallthrough]];
case 'R':
case 'q':
case 'Q':
Expand Down Expand Up @@ -55640,7 +55640,7 @@ TargetLowering::ConstraintWeight
case 'v':
if ((type->getPrimitiveSizeInBits() == 512) && Subtarget.hasAVX512())
weight = CW_Register;
LLVM_FALLTHROUGH;
[[fallthrough]];
case 'x':
if (((type->getPrimitiveSizeInBits() == 128) && Subtarget.hasSSE1()) ||
((type->getPrimitiveSizeInBits() == 256) && Subtarget.hasAVX()))
Expand Down Expand Up @@ -55978,7 +55978,7 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
return std::make_pair(0U, &X86::GR64RegClass);
break;
}
LLVM_FALLTHROUGH;
[[fallthrough]];
// 32-bit fallthrough
case 'Q': // Q_REGS
if (VT == MVT::i8 || VT == MVT::i1)
Expand Down Expand Up @@ -56060,7 +56060,7 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
case MVT::v8f16:
if (!Subtarget.hasFP16())
break;
LLVM_FALLTHROUGH;
[[fallthrough]];
case MVT::f128:
case MVT::v16i8:
case MVT::v8i16:
Expand All @@ -56075,7 +56075,7 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
case MVT::v16f16:
if (!Subtarget.hasFP16())
break;
LLVM_FALLTHROUGH;
[[fallthrough]];
case MVT::v32i8:
case MVT::v16i16:
case MVT::v8i32:
Expand All @@ -56090,7 +56090,7 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
case MVT::v32f16:
if (!Subtarget.hasFP16())
break;
LLVM_FALLTHROUGH;
[[fallthrough]];
case MVT::v64i8:
case MVT::v32i16:
case MVT::v8f64:
Expand Down Expand Up @@ -56133,7 +56133,7 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
case MVT::v8f16:
if (!Subtarget.hasFP16())
break;
LLVM_FALLTHROUGH;
[[fallthrough]];
case MVT::f128:
case MVT::v16i8:
case MVT::v8i16:
Expand All @@ -56146,7 +56146,7 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
case MVT::v16f16:
if (!Subtarget.hasFP16())
break;
LLVM_FALLTHROUGH;
[[fallthrough]];
case MVT::v32i8:
case MVT::v16i16:
case MVT::v8i32:
Expand All @@ -56159,7 +56159,7 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
case MVT::v32f16:
if (!Subtarget.hasFP16())
break;
LLVM_FALLTHROUGH;
[[fallthrough]];
case MVT::v64i8:
case MVT::v32i16:
case MVT::v8f64:
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/X86/X86IndirectBranchTracking.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -118,7 +118,7 @@ static bool needsPrologueENDBR(MachineFunction &MF, const Module *M) {
return F.hasAddressTaken();
}
// if !IBTSeal, fall into default case.
LLVM_FALLTHROUGH;
[[fallthrough]];
// Address taken or externally linked functions may be reachable.
default:
return (F.hasAddressTaken() || !F.hasLocalLinkage());
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -135,7 +135,7 @@ static Value *simplifyX86immShift(const IntrinsicInst &II,
case Intrinsic::x86_avx512_psrai_q_512:
case Intrinsic::x86_avx512_psrai_w_512:
IsImm = true;
LLVM_FALLTHROUGH;
[[fallthrough]];
case Intrinsic::x86_sse2_psra_d:
case Intrinsic::x86_sse2_psra_w:
case Intrinsic::x86_avx2_psra_d:
Expand All @@ -158,7 +158,7 @@ static Value *simplifyX86immShift(const IntrinsicInst &II,
case Intrinsic::x86_avx512_psrli_q_512:
case Intrinsic::x86_avx512_psrli_w_512:
IsImm = true;
LLVM_FALLTHROUGH;
[[fallthrough]];
case Intrinsic::x86_sse2_psrl_d:
case Intrinsic::x86_sse2_psrl_q:
case Intrinsic::x86_sse2_psrl_w:
Expand All @@ -181,7 +181,7 @@ static Value *simplifyX86immShift(const IntrinsicInst &II,
case Intrinsic::x86_avx512_pslli_q_512:
case Intrinsic::x86_avx512_pslli_w_512:
IsImm = true;
LLVM_FALLTHROUGH;
[[fallthrough]];
case Intrinsic::x86_sse2_psll_d:
case Intrinsic::x86_sse2_psll_q:
case Intrinsic::x86_sse2_psll_w:
Expand Down
24 changes: 12 additions & 12 deletions llvm/lib/Target/X86/X86InstrInfo.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -105,7 +105,7 @@ X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
// It's not always legal to reference the low 8-bit of the larger
// register in 32-bit mode.
return false;
LLVM_FALLTHROUGH;
[[fallthrough]];
case X86::MOVSX32rr16:
case X86::MOVZX32rr16:
case X86::MOVSX64rr16:
Expand Down Expand Up @@ -1395,7 +1395,7 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
}
case X86::SHL8ri:
Is8BitOp = true;
LLVM_FALLTHROUGH;
[[fallthrough]];
case X86::SHL16ri: {
assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
unsigned ShAmt = getTruncatedShiftCount(MI, 2);
Expand Down Expand Up @@ -1456,7 +1456,7 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
case X86::DEC8r:
case X86::INC8r:
Is8BitOp = true;
LLVM_FALLTHROUGH;
[[fallthrough]];
case X86::DEC16r:
case X86::INC16r:
return convertToThreeAddressWithLEA(MIOpc, MI, LV, LIS, Is8BitOp);
Expand Down Expand Up @@ -1512,7 +1512,7 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
case X86::ADD8rr:
case X86::ADD8rr_DB:
Is8BitOp = true;
LLVM_FALLTHROUGH;
[[fallthrough]];
case X86::ADD16rr:
case X86::ADD16rr_DB:
return convertToThreeAddressWithLEA(MIOpc, MI, LV, LIS, Is8BitOp);
Expand Down Expand Up @@ -1554,7 +1554,7 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
case X86::ADD8ri:
case X86::ADD8ri_DB:
Is8BitOp = true;
LLVM_FALLTHROUGH;
[[fallthrough]];
case X86::ADD16ri:
case X86::ADD16ri8:
case X86::ADD16ri_DB:
Expand Down Expand Up @@ -2047,7 +2047,7 @@ MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
OpIdx1, OpIdx2);
}
}
LLVM_FALLTHROUGH;
[[fallthrough]];
case X86::PBLENDWrri:
case X86::VBLENDPDYrri:
case X86::VBLENDPSYrri:
Expand Down Expand Up @@ -2798,18 +2798,18 @@ X86::getX86ConditionCode(CmpInst::Predicate Predicate) {
default: break;
// Floating-point Predicates
case CmpInst::FCMP_UEQ: CC = X86::COND_E; break;
case CmpInst::FCMP_OLT: NeedSwap = true; LLVM_FALLTHROUGH;
case CmpInst::FCMP_OLT: NeedSwap = true; [[fallthrough]];
case CmpInst::FCMP_OGT: CC = X86::COND_A; break;
case CmpInst::FCMP_OLE: NeedSwap = true; LLVM_FALLTHROUGH;
case CmpInst::FCMP_OLE: NeedSwap = true; [[fallthrough]];
case CmpInst::FCMP_OGE: CC = X86::COND_AE; break;
case CmpInst::FCMP_UGT: NeedSwap = true; LLVM_FALLTHROUGH;
case CmpInst::FCMP_UGT: NeedSwap = true; [[fallthrough]];
case CmpInst::FCMP_ULT: CC = X86::COND_B; break;
case CmpInst::FCMP_UGE: NeedSwap = true; LLVM_FALLTHROUGH;
case CmpInst::FCMP_UGE: NeedSwap = true; [[fallthrough]];
case CmpInst::FCMP_ULE: CC = X86::COND_BE; break;
case CmpInst::FCMP_ONE: CC = X86::COND_NE; break;
case CmpInst::FCMP_UNO: CC = X86::COND_P; break;
case CmpInst::FCMP_ORD: CC = X86::COND_NP; break;
case CmpInst::FCMP_OEQ: LLVM_FALLTHROUGH;
case CmpInst::FCMP_OEQ: [[fallthrough]];
case CmpInst::FCMP_UNE: CC = X86::COND_INVALID; break;

// Integer Predicates
Expand Down Expand Up @@ -4494,7 +4494,7 @@ bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
// can't do the optimization.
if (NoSignFlag)
return false;
LLVM_FALLTHROUGH;
[[fallthrough]];
case X86::COND_O: case X86::COND_NO:
// If OF is used, the instruction needs to clear it like CmpZero does.
if (!ClearsOverflowFlag)
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/X86/X86MCInstLower.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2500,7 +2500,7 @@ void X86AsmPrinter::emitInstruction(const MachineInstr *MI) {
case X86::TAILJMPd64:
if (IndCSPrefix && MI->hasRegisterImplicitUseOperand(X86::R11))
EmitAndCountInstruction(MCInstBuilder(X86::CS_PREFIX));
LLVM_FALLTHROUGH;
[[fallthrough]];
case X86::TAILJMPr:
case X86::TAILJMPm:
case X86::TAILJMPd:
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/X86/X86TargetTransformInfo.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -109,7 +109,7 @@ llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity(
// - Kabylake
switch (Level) {
case TargetTransformInfo::CacheLevel::L1D:
LLVM_FALLTHROUGH;
[[fallthrough]];
case TargetTransformInfo::CacheLevel::L2D:
return 8;
}
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/XCore/XCoreAsmPrinter.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -134,7 +134,7 @@ void XCoreAsmPrinter::emitGlobalVariable(const GlobalVariable *GV) {
if (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
GV->hasCommonLinkage())
OutStreamer->emitSymbolAttribute(GVSym, MCSA_Weak);
LLVM_FALLTHROUGH;
[[fallthrough]];
case GlobalValue::InternalLinkage:
case GlobalValue::PrivateLinkage:
break;
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/TextAPI/TextStubCommon.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -64,17 +64,17 @@ void ScalarTraits<PlatformSet>::output(const PlatformSet &Values, void *IO,
OS << "macosx";
break;
case PLATFORM_IOSSIMULATOR:
LLVM_FALLTHROUGH;
[[fallthrough]];
case PLATFORM_IOS:
OS << "ios";
break;
case PLATFORM_WATCHOSSIMULATOR:
LLVM_FALLTHROUGH;
[[fallthrough]];
case PLATFORM_WATCHOS:
OS << "watchos";
break;
case PLATFORM_TVOSSIMULATOR:
LLVM_FALLTHROUGH;
[[fallthrough]];
case PLATFORM_TVOS:
OS << "tvos";
break;
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Transforms/IPO/Attributor.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2803,7 +2803,7 @@ void InformationCache::initializeInformationCache(const Function &CF,
if (const Function *Callee = cast<CallInst>(I).getCalledFunction())
getFunctionInfo(*Callee).CalledViaMustTail = true;
}
LLVM_FALLTHROUGH;
[[fallthrough]];
case Instruction::CallBr:
case Instruction::Invoke:
case Instruction::CleanupRet:
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Transforms/IPO/AttributorAttributes.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6346,7 +6346,7 @@ ChangeStatus AAHeapToStackFunction::updateImpl(Attributor &A) {
if (UsesCheck(AI))
break;
AI.Status = AllocationInfo::STACK_DUE_TO_FREE;
LLVM_FALLTHROUGH;
[[fallthrough]];
case AllocationInfo::STACK_DUE_TO_FREE:
if (FreeCheck(AI))
break;
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Transforms/IPO/FunctionAttrs.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1146,7 +1146,7 @@ static bool isFunctionMallocLike(Function *F, const SCCNodeSet &SCCNodes) {
break;
if (CB.getCalledFunction() && SCCNodes.count(CB.getCalledFunction()))
break;
LLVM_FALLTHROUGH;
[[fallthrough]];
}
default:
return false; // Did not come from an allocation.
Expand Down
20 changes: 10 additions & 10 deletions llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1301,7 +1301,7 @@ Instruction *InstCombinerImpl::visitCallInst(CallInst &CI) {
Value *Cmp = Builder.CreateICmpNE(I0, Zero);
return CastInst::Create(Instruction::ZExt, Cmp, II->getType());
}
LLVM_FALLTHROUGH;
[[fallthrough]];
}
case Intrinsic::umax: {
Value *I0 = II->getArgOperand(0), *I1 = II->getArgOperand(1);
Expand All @@ -1322,7 +1322,7 @@ Instruction *InstCombinerImpl::visitCallInst(CallInst &CI) {
}
// If both operands of unsigned min/max are sign-extended, it is still ok
// to narrow the operation.
LLVM_FALLTHROUGH;
[[fallthrough]];
}
case Intrinsic::smax:
case Intrinsic::smin: {
Expand Down Expand Up @@ -1850,7 +1850,7 @@ Instruction *InstCombinerImpl::visitCallInst(CallInst &CI) {
return FAdd;
}

LLVM_FALLTHROUGH;
[[fallthrough]];
}
case Intrinsic::fma: {
// fma fneg(x), fneg(y), z -> fma x, y, z
Expand Down Expand Up @@ -1940,7 +1940,7 @@ Instruction *InstCombinerImpl::visitCallInst(CallInst &CI) {
return replaceOperand(*II, 0, TVal);
}

LLVM_FALLTHROUGH;
[[fallthrough]];
}
case Intrinsic::ceil:
case Intrinsic::floor:
Expand Down Expand Up @@ -2504,7 +2504,7 @@ Instruction *InstCombinerImpl::visitCallInst(CallInst &CI) {
return replaceInstUsesWith(CI, Res);
}
}
LLVM_FALLTHROUGH;
[[fallthrough]];
}
case Intrinsic::vector_reduce_add: {
if (IID == Intrinsic::vector_reduce_add) {
Expand All @@ -2531,7 +2531,7 @@ Instruction *InstCombinerImpl::visitCallInst(CallInst &CI) {
}
}
}
LLVM_FALLTHROUGH;
[[fallthrough]];
}
case Intrinsic::vector_reduce_xor: {
if (IID == Intrinsic::vector_reduce_xor) {
Expand All @@ -2555,7 +2555,7 @@ Instruction *InstCombinerImpl::visitCallInst(CallInst &CI) {
}
}
}
LLVM_FALLTHROUGH;
[[fallthrough]];
}
case Intrinsic::vector_reduce_mul: {
if (IID == Intrinsic::vector_reduce_mul) {
Expand All @@ -2577,7 +2577,7 @@ Instruction *InstCombinerImpl::visitCallInst(CallInst &CI) {
}
}
}
LLVM_FALLTHROUGH;
[[fallthrough]];
}
case Intrinsic::vector_reduce_umin:
case Intrinsic::vector_reduce_umax: {
Expand All @@ -2604,7 +2604,7 @@ Instruction *InstCombinerImpl::visitCallInst(CallInst &CI) {
}
}
}
LLVM_FALLTHROUGH;
[[fallthrough]];
}
case Intrinsic::vector_reduce_smin:
case Intrinsic::vector_reduce_smax: {
Expand Down Expand Up @@ -2642,7 +2642,7 @@ Instruction *InstCombinerImpl::visitCallInst(CallInst &CI) {
}
}
}
LLVM_FALLTHROUGH;
[[fallthrough]];
}
case Intrinsic::vector_reduce_fmax:
case Intrinsic::vector_reduce_fmin:
Expand Down
10 changes: 5 additions & 5 deletions llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3479,7 +3479,7 @@ Instruction *InstCombinerImpl::foldICmpBinOpWithConstant(ICmpInst &Cmp,
case Instruction::UDiv:
if (Instruction *I = foldICmpUDivConstant(Cmp, BO, C))
return I;
LLVM_FALLTHROUGH;
[[fallthrough]];
case Instruction::SDiv:
if (Instruction *I = foldICmpDivConstant(Cmp, BO, C))
return I;
Expand Down Expand Up @@ -5947,31 +5947,31 @@ static Instruction *canonicalizeICmpBool(ICmpInst &I,
case ICmpInst::ICMP_UGT:
// icmp ugt -> icmp ult
std::swap(A, B);
LLVM_FALLTHROUGH;
[[fallthrough]];
case ICmpInst::ICMP_ULT:
// icmp ult i1 A, B -> ~A & B
return BinaryOperator::CreateAnd(Builder.CreateNot(A), B);

case ICmpInst::ICMP_SGT:
// icmp sgt -> icmp slt
std::swap(A, B);
LLVM_FALLTHROUGH;
[[fallthrough]];
case ICmpInst::ICMP_SLT:
// icmp slt i1 A, B -> A & ~B
return BinaryOperator::CreateAnd(Builder.CreateNot(B), A);

case ICmpInst::ICMP_UGE:
// icmp uge -> icmp ule
std::swap(A, B);
LLVM_FALLTHROUGH;
[[fallthrough]];
case ICmpInst::ICMP_ULE:
// icmp ule i1 A, B -> ~A | B
return BinaryOperator::CreateOr(Builder.CreateNot(A), B);

case ICmpInst::ICMP_SGE:
// icmp sge -> icmp sle
std::swap(A, B);
LLVM_FALLTHROUGH;
[[fallthrough]];
case ICmpInst::ICMP_SLE:
// icmp sle i1 A, B -> A | ~B
return BinaryOperator::CreateOr(Builder.CreateNot(B), A);
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -399,7 +399,7 @@ std::array<Value *, 2> Negator::getSortedOperandsOfBinOp(Instruction *I) {
if (match(Ops[1], m_One()))
return Builder.CreateNot(Ops[0], I->getName() + ".neg");
// Else, just defer to Instruction::Add handling.
LLVM_FALLTHROUGH;
[[fallthrough]];
}
case Instruction::Add: {
// `add` is negatible if both of its operands are negatible.
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1371,7 +1371,7 @@ static Value *canonicalizeClampLike(SelectInst &Sel0, ICmpInst &Cmp0,
C2->getType()->getScalarSizeInBits()))))
return nullptr; // Can't do, have signed max element[s].
C2 = InstCombiner::AddOne(C2);
LLVM_FALLTHROUGH;
[[fallthrough]];
case ICmpInst::Predicate::ICMP_SGE:
// Also non-canonical, but here we don't need to change C2,
// so we don't have any restrictions on C2, so we can just handle it.
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -397,7 +397,7 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
}
}
}
LLVM_FALLTHROUGH;
[[fallthrough]];
case Instruction::ZExt: {
unsigned SrcBitWidth = I->getOperand(0)->getType()->getScalarSizeInBits();

Expand Down Expand Up @@ -498,7 +498,7 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
return Builder.CreateSExt(Or, VTy);
}
}
LLVM_FALLTHROUGH;
[[fallthrough]];
case Instruction::Sub: {
APInt DemandedFromOps;
if (simplifyOperandsBasedOnUnusedHighBits(DemandedFromOps))
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1653,7 +1653,7 @@ static bool canEvaluateShuffled(Value *V, ArrayRef<int> Mask,
// from an undefined element in an operand.
if (llvm::is_contained(Mask, -1))
return false;
LLVM_FALLTHROUGH;
[[fallthrough]];
case Instruction::Add:
case Instruction::FAdd:
case Instruction::Sub:
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2778,7 +2778,7 @@ static bool isAllocSiteRemovable(Instruction *AI,
MemIntrinsic *MI = cast<MemIntrinsic>(II);
if (MI->isVolatile() || MI->getRawDest() != PI)
return false;
LLVM_FALLTHROUGH;
[[fallthrough]];
}
case Intrinsic::assume:
case Intrinsic::invariant_start:
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Transforms/Instrumentation/ThreadSanitizer.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -676,7 +676,7 @@ static ConstantInt *createOrdering(IRBuilder<> *IRB, AtomicOrdering ord) {
switch (ord) {
case AtomicOrdering::NotAtomic:
llvm_unreachable("unexpected atomic ordering!");
case AtomicOrdering::Unordered: LLVM_FALLTHROUGH;
case AtomicOrdering::Unordered: [[fallthrough]];
case AtomicOrdering::Monotonic: v = 0; break;
// Not specified yet:
// case AtomicOrdering::Consume: v = 1; break;
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Transforms/ObjCARC/ObjCARCContract.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -428,7 +428,7 @@ bool ObjCARCContract::tryToPeepholeInstruction(
if (!optimizeRetainCall(F, Inst))
return false;
// If we succeed in our optimization, fall through.
LLVM_FALLTHROUGH;
[[fallthrough]];
case ARCInstKind::RetainRV:
case ARCInstKind::UnsafeClaimRV: {
// Return true if this is a bundled retainRV/claimRV call, which is always
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Transforms/ObjCARC/PtrState.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -212,7 +212,7 @@ bool BottomUpPtrState::MatchWithRetain() {
// imprecise release, clear our reverse insertion points.
if (OldSeq != S_Use || IsTrackingImpreciseReleases())
ClearReverseInsertPts();
LLVM_FALLTHROUGH;
[[fallthrough]];
case S_CanRelease:
return true;
case S_None:
Expand Down Expand Up @@ -360,7 +360,7 @@ bool TopDownPtrState::MatchWithRelease(ARCMDKindCache &Cache,
case S_CanRelease:
if (OldSeq == S_Retain || ReleaseMetadata != nullptr)
ClearReverseInsertPts();
LLVM_FALLTHROUGH;
[[fallthrough]];
case S_Use:
SetReleaseMetadata(ReleaseMetadata);
SetTailCallRelease(cast<CallInst>(Release)->isTailCall());
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Transforms/Scalar/IndVarSimplify.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -675,7 +675,7 @@ static PHINode *getLoopPhiForCounter(Value *IncV, Loop *L) {
// An IV counter must preserve its type.
if (IncI->getNumOperands() == 2)
break;
LLVM_FALLTHROUGH;
[[fallthrough]];
default:
return nullptr;
}
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -307,7 +307,7 @@ InductiveRangeCheck::parseRangeCheckICmp(Loop *L, ICmpInst *ICI,

case ICmpInst::ICMP_SLE:
std::swap(LHS, RHS);
LLVM_FALLTHROUGH;
[[fallthrough]];
case ICmpInst::ICMP_SGE:
IsSigned = true;
if (match(RHS, m_ConstantInt<0>())) {
Expand All @@ -318,7 +318,7 @@ InductiveRangeCheck::parseRangeCheckICmp(Loop *L, ICmpInst *ICI,

case ICmpInst::ICMP_SLT:
std::swap(LHS, RHS);
LLVM_FALLTHROUGH;
[[fallthrough]];
case ICmpInst::ICMP_SGT:
IsSigned = true;
if (match(RHS, m_ConstantInt<-1>())) {
Expand All @@ -335,7 +335,7 @@ InductiveRangeCheck::parseRangeCheckICmp(Loop *L, ICmpInst *ICI,

case ICmpInst::ICMP_ULT:
std::swap(LHS, RHS);
LLVM_FALLTHROUGH;
[[fallthrough]];
case ICmpInst::ICMP_UGT:
IsSigned = false;
if (IsLoopInvariant(LHS)) {
Expand Down
14 changes: 7 additions & 7 deletions llvm/lib/Transforms/Utils/BuildLibCalls.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -316,7 +316,7 @@ bool llvm::inferNonMandatoryLibFuncAttrs(Function &F,
case LibFunc_strcpy:
case LibFunc_strncpy:
Changed |= setReturnedArg(F, 0);
LLVM_FALLTHROUGH;
[[fallthrough]];
case LibFunc_stpcpy:
case LibFunc_stpncpy:
Changed |= setOnlyAccessesArgMemory(F);
Expand Down Expand Up @@ -386,7 +386,7 @@ bool llvm::inferNonMandatoryLibFuncAttrs(Function &F,
break;
case LibFunc_strndup:
Changed |= setArgNoUndef(F, 1);
LLVM_FALLTHROUGH;
[[fallthrough]];
case LibFunc_strdup:
Changed |= setAllocFamily(F, "malloc");
Changed |= setOnlyAccessesInaccessibleMemOrArgMem(F);
Expand Down Expand Up @@ -448,7 +448,7 @@ bool llvm::inferNonMandatoryLibFuncAttrs(Function &F,
Changed |= setAlignedAllocParam(F, 0);
Changed |= setAllocSize(F, 1, None);
Changed |= setAllocKind(F, AllocFnKind::Alloc | AllocFnKind::Uninitialized | AllocFnKind::Aligned);
LLVM_FALLTHROUGH;
[[fallthrough]];
case LibFunc_valloc:
case LibFunc_malloc:
case LibFunc_vec_malloc:
Expand Down Expand Up @@ -507,7 +507,7 @@ bool llvm::inferNonMandatoryLibFuncAttrs(Function &F,
case LibFunc_mempcpy:
case LibFunc_memccpy:
Changed |= setWillReturn(F);
LLVM_FALLTHROUGH;
[[fallthrough]];
case LibFunc_memcpy_chk:
Changed |= setDoesNotThrow(F);
Changed |= setOnlyAccessesArgMemory(F);
Expand Down Expand Up @@ -985,7 +985,7 @@ bool llvm::inferNonMandatoryLibFuncAttrs(Function &F,
break;
case LibFunc_dunder_strndup:
Changed |= setArgNoUndef(F, 1);
LLVM_FALLTHROUGH;
[[fallthrough]];
case LibFunc_dunder_strdup:
Changed |= setDoesNotThrow(F);
Changed |= setRetDoesNotAlias(F);
Expand Down Expand Up @@ -1078,10 +1078,10 @@ bool llvm::inferNonMandatoryLibFuncAttrs(Function &F,
Changed |= setDoesNotCapture(F, 0);
Changed |= setDoesNotCapture(F, 1);
Changed |= setOnlyReadsMemory(F, 1);
LLVM_FALLTHROUGH;
[[fallthrough]];
case LibFunc_memset:
Changed |= setWillReturn(F);
LLVM_FALLTHROUGH;
[[fallthrough]];
case LibFunc_memset_chk:
Changed |= setOnlyAccessesArgMemory(F);
Changed |= setOnlyWritesMemory(F, 0);
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Transforms/Utils/LoopRotationUtils.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -713,7 +713,7 @@ static bool shouldSpeculateInstrs(BasicBlock::iterator Begin,
if (!cast<GEPOperator>(I)->hasAllConstantIndices())
return false;
// fall-thru to increment case
LLVM_FALLTHROUGH;
[[fallthrough]];
case Instruction::Add:
case Instruction::Sub:
case Instruction::And:
Expand Down
8 changes: 4 additions & 4 deletions llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5007,7 +5007,7 @@ LoopVectorizationCostModel::computeMaxVF(ElementCount UserVF, unsigned UserIC) {
case CM_ScalarEpilogueAllowed:
return computeFeasibleMaxVF(TC, UserVF, false);
case CM_ScalarEpilogueNotAllowedUsePredicate:
LLVM_FALLTHROUGH;
[[fallthrough]];
case CM_ScalarEpilogueNotNeededUsePredicate:
LLVM_DEBUG(
dbgs() << "LV: vector predicate hint/switch found.\n"
Expand Down Expand Up @@ -7072,7 +7072,7 @@ LoopVectorizationCostModel::getInstructionCost(Instruction *I, ElementCount VF,
// likely.
return Cost / getReciprocalPredBlockProb();
}
LLVM_FALLTHROUGH;
[[fallthrough]];
case Instruction::Add:
case Instruction::FAdd:
case Instruction::Sub:
Expand Down Expand Up @@ -7178,7 +7178,7 @@ LoopVectorizationCostModel::getInstructionCost(Instruction *I, ElementCount VF,
case Instruction::BitCast:
if (I->getType()->isPointerTy())
return 0;
LLVM_FALLTHROUGH;
[[fallthrough]];
case Instruction::ZExt:
case Instruction::SExt:
case Instruction::FPToUI:
Expand Down Expand Up @@ -7287,7 +7287,7 @@ LoopVectorizationCostModel::getInstructionCost(Instruction *I, ElementCount VF,
// the result would need to be a vector of pointers.
if (VF.isScalable())
return InstructionCost::getInvalid();
LLVM_FALLTHROUGH;
[[fallthrough]];
default:
// This opcode is unknown. Assume that it is the same as 'mul'.
return TTI.getArithmeticInstrCost(Instruction::Mul, VectorTy, CostKind);
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -644,7 +644,7 @@ static bool InTreeUserNeedToExtract(Value *Scalar, Instruction *UserInst,
if (isVectorIntrinsicWithScalarOpAtArg(ID, i))
return (CI->getArgOperand(i) == Scalar);
}
LLVM_FALLTHROUGH;
[[fallthrough]];
}
default:
return false;
Expand Down
2 changes: 1 addition & 1 deletion llvm/tools/llvm-ar/llvm-ar.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1218,7 +1218,7 @@ static void runMRIScript() {
break;
case MRICommand::CreateThin:
Thin = true;
LLVM_FALLTHROUGH;
[[fallthrough]];
case MRICommand::Create:
Create = true;
if (!ArchiveName.empty())
Expand Down
2 changes: 1 addition & 1 deletion llvm/tools/llvm-config/llvm-config.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -660,7 +660,7 @@ int main(int argc, char **argv) {
}
WithColor::error(errs(), "llvm-config")
<< "component libraries and shared library\n\n";
LLVM_FALLTHROUGH;
[[fallthrough]];
case LinkModeStatic:
for (auto &Lib : MissingLibs)
WithColor::error(errs(), "llvm-config") << "missing: " << Lib << "\n";
Expand Down
2 changes: 1 addition & 1 deletion llvm/tools/llvm-exegesis/lib/SerialSnippetGenerator.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -96,7 +96,7 @@ static void appendCodeTemplates(const LLVMState &State,
switch (ExecutionModeBit) {
case ExecutionMode::ALWAYS_SERIAL_IMPLICIT_REGS_ALIAS:
// Nothing to do, the instruction is always serial.
LLVM_FALLTHROUGH;
[[fallthrough]];
case ExecutionMode::ALWAYS_SERIAL_TIED_REGS_ALIAS: {
// Picking whatever value for the tied variable will make the instruction
// serial.
Expand Down
2 changes: 1 addition & 1 deletion llvm/tools/llvm-mc/Disassembler.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -65,7 +65,7 @@ static bool PrintInsts(const MCDisassembler &DisAsm,
SM.PrintMessage(SMLoc::getFromPointer(Bytes.second[Index]),
SourceMgr::DK_Warning,
"potentially undefined instruction encoding");
LLVM_FALLTHROUGH;
[[fallthrough]];

case MCDisassembler::Success:
Streamer.emitInstruction(Inst, STI);
Expand Down
2 changes: 1 addition & 1 deletion llvm/tools/llvm-ml/Disassembler.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -61,7 +61,7 @@ static bool PrintInsts(const MCDisassembler &DisAsm, const ByteArrayTy &Bytes,
SM.PrintMessage(SMLoc::getFromPointer(Bytes.second[Index]),
SourceMgr::DK_Warning,
"potentially undefined instruction encoding");
LLVM_FALLTHROUGH;
[[fallthrough]];

case MCDisassembler::Success:
Streamer.emitInstruction(Inst, STI);
Expand Down
4 changes: 2 additions & 2 deletions llvm/tools/llvm-readobj/ELFDumper.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2329,7 +2329,7 @@ std::string ELFDumper<ELFT>::getDynamicEntry(uint64_t Type,
return "REL";
if (Value == DT_RELA)
return "RELA";
LLVM_FALLTHROUGH;
[[fallthrough]];
case DT_PLTGOT:
case DT_HASH:
case DT_STRTAB:
Expand Down Expand Up @@ -6499,7 +6499,7 @@ template <class ELFT> void LLVMELFDumper<ELFT>::printFileHeaders() {
break;
case 0:
// ELFOSABI_AMDGPU_PAL, ELFOSABI_AMDGPU_MESA3D support *_V3 flags.
LLVM_FALLTHROUGH;
[[fallthrough]];
case ELF::ELFABIVERSION_AMDGPU_HSA_V3:
W.printFlags("Flags", E.e_flags,
makeArrayRef(ElfHeaderAMDGPUFlagsABIVersion3),
Expand Down
4 changes: 2 additions & 2 deletions llvm/tools/llvm-remark-size-diff/RemarkSizeDiff.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -404,13 +404,13 @@ getFunctionDiffListAsJSON(const SmallVector<FunctionDiff> &FunctionDiffs,
InstCountA = InstCountB = StackSizeA = StackSizeB = 0;
switch (WhichFiles) {
case BOTH:
LLVM_FALLTHROUGH;
[[fallthrough]];
case A:
InstCountA = Diff.getInstCountA();
StackSizeA = Diff.getStackSizeA();
if (WhichFiles != BOTH)
break;
LLVM_FALLTHROUGH;
[[fallthrough]];
case B:
InstCountB = Diff.getInstCountB();
StackSizeB = Diff.getStackSizeB();
Expand Down
4 changes: 2 additions & 2 deletions llvm/tools/obj2yaml/macho2yaml.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -386,7 +386,7 @@ void MachODumper::dumpRebaseOpcodes(std::unique_ptr<MachOYAML::Object> &Y) {
ULEB = decodeULEB128(OpCode + 1, &Count);
RebaseOp.ExtraData.push_back(ULEB);
OpCode += Count;
LLVM_FALLTHROUGH;
[[fallthrough]];
// Intentionally no break here -- This opcode has two ULEB values
case MachO::REBASE_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB:
case MachO::REBASE_OPCODE_ADD_ADDR_ULEB:
Expand Down Expand Up @@ -434,7 +434,7 @@ void MachODumper::dumpBindOpcodes(
ULEB = decodeULEB128(OpCode + 1, &Count);
BindOp.ULEBExtraData.push_back(ULEB);
OpCode += Count;
LLVM_FALLTHROUGH;
[[fallthrough]];
// Intentionally no break here -- this opcode has two ULEB values

case MachO::BIND_OPCODE_SET_DYLIB_ORDINAL_ULEB:
Expand Down
16 changes: 8 additions & 8 deletions llvm/utils/TableGen/IntrinsicEmitter.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -361,10 +361,10 @@ static void EncodeFixedType(Record *R, std::vector<unsigned char> &ArgCodes,
unsigned Tmp = 0;
switch (VT) {
default: break;
case MVT::iPTRAny: ++Tmp; LLVM_FALLTHROUGH;
case MVT::vAny: ++Tmp; LLVM_FALLTHROUGH;
case MVT::fAny: ++Tmp; LLVM_FALLTHROUGH;
case MVT::iAny: ++Tmp; LLVM_FALLTHROUGH;
case MVT::iPTRAny: ++Tmp; [[fallthrough]];
case MVT::vAny: ++Tmp; [[fallthrough]];
case MVT::fAny: ++Tmp; [[fallthrough]];
case MVT::iAny: ++Tmp; [[fallthrough]];
case MVT::Any: {
// If this is an "any" valuetype, then the type is the type of the next
// type in the list specified to getIntrinsic().
Expand Down Expand Up @@ -444,16 +444,16 @@ static void UpdateArgCodes(Record *R, std::vector<unsigned char> &ArgCodes,
break;
case MVT::iPTRAny:
++Tmp;
LLVM_FALLTHROUGH;
[[fallthrough]];
case MVT::vAny:
++Tmp;
LLVM_FALLTHROUGH;
[[fallthrough]];
case MVT::fAny:
++Tmp;
LLVM_FALLTHROUGH;
[[fallthrough]];
case MVT::iAny:
++Tmp;
LLVM_FALLTHROUGH;
[[fallthrough]];
case MVT::Any:
unsigned OriginalIdx = ArgCodes.size() - NumInserted;
assert(OriginalIdx >= Mapping.size());
Expand Down