52 changes: 26 additions & 26 deletions llvm/test/CodeGen/AArch64/arm64-ldp-cluster.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -6,13 +6,13 @@
; CHECK: ********** MI Scheduling **********
; CHECK-LABEL: ldr_int:%bb.0
; CHECK: Cluster ld/st SU(1) - SU(2)
; CHECK: SU(1): %{{[0-9]+}}<def> = LDRWui
; CHECK: SU(2): %{{[0-9]+}}<def> = LDRWui
; CHECK: SU(1): %{{[0-9]+}}:gpr32 = LDRWui
; CHECK: SU(2): %{{[0-9]+}}:gpr32 = LDRWui
; EXYNOS: ********** MI Scheduling **********
; EXYNOS-LABEL: ldr_int:%bb.0
; EXYNOS: Cluster ld/st SU(1) - SU(2)
; EXYNOS: SU(1): %{{[0-9]+}}<def> = LDRWui
; EXYNOS: SU(2): %{{[0-9]+}}<def> = LDRWui
; EXYNOS: SU(1): %{{[0-9]+}}:gpr32 = LDRWui
; EXYNOS: SU(2): %{{[0-9]+}}:gpr32 = LDRWui
define i32 @ldr_int(i32* %a) nounwind {
%p1 = getelementptr inbounds i32, i32* %a, i32 1
%tmp1 = load i32, i32* %p1, align 2
Expand All @@ -26,13 +26,13 @@ define i32 @ldr_int(i32* %a) nounwind {
; CHECK: ********** MI Scheduling **********
; CHECK-LABEL: ldp_sext_int:%bb.0
; CHECK: Cluster ld/st SU(1) - SU(2)
; CHECK: SU(1): %{{[0-9]+}}<def> = LDRSWui
; CHECK: SU(2): %{{[0-9]+}}<def> = LDRSWui
; CHECK: SU(1): %{{[0-9]+}}:gpr64 = LDRSWui
; CHECK: SU(2): %{{[0-9]+}}:gpr64 = LDRSWui
; EXYNOS: ********** MI Scheduling **********
; EXYNOS-LABEL: ldp_sext_int:%bb.0
; EXYNOS: Cluster ld/st SU(1) - SU(2)
; EXYNOS: SU(1): %{{[0-9]+}}<def> = LDRSWui
; EXYNOS: SU(2): %{{[0-9]+}}<def> = LDRSWui
; EXYNOS: SU(1): %{{[0-9]+}}:gpr64 = LDRSWui
; EXYNOS: SU(2): %{{[0-9]+}}:gpr64 = LDRSWui
define i64 @ldp_sext_int(i32* %p) nounwind {
%tmp = load i32, i32* %p, align 4
%add.ptr = getelementptr inbounds i32, i32* %p, i64 1
Expand All @@ -47,13 +47,13 @@ define i64 @ldp_sext_int(i32* %p) nounwind {
; CHECK: ********** MI Scheduling **********
; CHECK-LABEL: ldur_int:%bb.0
; CHECK: Cluster ld/st SU(2) - SU(1)
; CHECK: SU(1): %{{[0-9]+}}<def> = LDURWi
; CHECK: SU(2): %{{[0-9]+}}<def> = LDURWi
; CHECK: SU(1): %{{[0-9]+}}:gpr32 = LDURWi
; CHECK: SU(2): %{{[0-9]+}}:gpr32 = LDURWi
; EXYNOS: ********** MI Scheduling **********
; EXYNOS-LABEL: ldur_int:%bb.0
; EXYNOS: Cluster ld/st SU(2) - SU(1)
; EXYNOS: SU(1): %{{[0-9]+}}<def> = LDURWi
; EXYNOS: SU(2): %{{[0-9]+}}<def> = LDURWi
; EXYNOS: SU(1): %{{[0-9]+}}:gpr32 = LDURWi
; EXYNOS: SU(2): %{{[0-9]+}}:gpr32 = LDURWi
define i32 @ldur_int(i32* %a) nounwind {
%p1 = getelementptr inbounds i32, i32* %a, i32 -1
%tmp1 = load i32, i32* %p1, align 2
Expand All @@ -67,13 +67,13 @@ define i32 @ldur_int(i32* %a) nounwind {
; CHECK: ********** MI Scheduling **********
; CHECK-LABEL: ldp_half_sext_zext_int:%bb.0
; CHECK: Cluster ld/st SU(3) - SU(4)
; CHECK: SU(3): %{{[0-9]+}}<def> = LDRSWui
; CHECK: SU(4): %{{[0-9]+}}:sub_32<def,read-undef> = LDRWui
; CHECK: SU(3): %{{[0-9]+}}:gpr64 = LDRSWui
; CHECK: SU(4): undef %{{[0-9]+}}.sub_32:gpr64 = LDRWui
; EXYNOS: ********** MI Scheduling **********
; EXYNOS-LABEL: ldp_half_sext_zext_int:%bb.0
; EXYNOS: Cluster ld/st SU(3) - SU(4)
; EXYNOS: SU(3): %{{[0-9]+}}<def> = LDRSWui
; EXYNOS: SU(4): %{{[0-9]+}}:sub_32<def,read-undef> = LDRWui
; EXYNOS: SU(3): %{{[0-9]+}}:gpr64 = LDRSWui
; EXYNOS: SU(4): undef %{{[0-9]+}}.sub_32:gpr64 = LDRWui
define i64 @ldp_half_sext_zext_int(i64* %q, i32* %p) nounwind {
%tmp0 = load i64, i64* %q, align 4
%tmp = load i32, i32* %p, align 4
Expand All @@ -90,13 +90,13 @@ define i64 @ldp_half_sext_zext_int(i64* %q, i32* %p) nounwind {
; CHECK: ********** MI Scheduling **********
; CHECK-LABEL: ldp_half_zext_sext_int:%bb.0
; CHECK: Cluster ld/st SU(3) - SU(4)
; CHECK: SU(3): %{{[0-9]+}}:sub_32<def,read-undef> = LDRWui
; CHECK: SU(4): %{{[0-9]+}}<def> = LDRSWui
; CHECK: SU(3): undef %{{[0-9]+}}.sub_32:gpr64 = LDRWui
; CHECK: SU(4): %{{[0-9]+}}:gpr64 = LDRSWui
; EXYNOS: ********** MI Scheduling **********
; EXYNOS-LABEL: ldp_half_zext_sext_int:%bb.0
; EXYNOS: Cluster ld/st SU(3) - SU(4)
; EXYNOS: SU(3): %{{[0-9]+}}:sub_32<def,read-undef> = LDRWui
; EXYNOS: SU(4): %{{[0-9]+}}<def> = LDRSWui
; EXYNOS: SU(3): undef %{{[0-9]+}}.sub_32:gpr64 = LDRWui
; EXYNOS: SU(4): %{{[0-9]+}}:gpr64 = LDRSWui
define i64 @ldp_half_zext_sext_int(i64* %q, i32* %p) nounwind {
%tmp0 = load i64, i64* %q, align 4
%tmp = load i32, i32* %p, align 4
Expand All @@ -113,13 +113,13 @@ define i64 @ldp_half_zext_sext_int(i64* %q, i32* %p) nounwind {
; CHECK: ********** MI Scheduling **********
; CHECK-LABEL: ldr_int_volatile:%bb.0
; CHECK-NOT: Cluster ld/st
; CHECK: SU(1): %{{[0-9]+}}<def> = LDRWui
; CHECK: SU(2): %{{[0-9]+}}<def> = LDRWui
; CHECK: SU(1): %{{[0-9]+}}:gpr32 = LDRWui
; CHECK: SU(2): %{{[0-9]+}}:gpr32 = LDRWui
; EXYNOS: ********** MI Scheduling **********
; EXYNOS-LABEL: ldr_int_volatile:%bb.0
; EXYNOS-NOT: Cluster ld/st
; EXYNOS: SU(1): %{{[0-9]+}}<def> = LDRWui
; EXYNOS: SU(2): %{{[0-9]+}}<def> = LDRWui
; EXYNOS: SU(1): %{{[0-9]+}}:gpr32 = LDRWui
; EXYNOS: SU(2): %{{[0-9]+}}:gpr32 = LDRWui
define i32 @ldr_int_volatile(i32* %a) nounwind {
%p1 = getelementptr inbounds i32, i32* %a, i32 1
%tmp1 = load volatile i32, i32* %p1, align 2
Expand All @@ -133,8 +133,8 @@ define i32 @ldr_int_volatile(i32* %a) nounwind {
; CHECK: ********** MI Scheduling **********
; CHECK-LABEL: ldq_cluster:%bb.0
; CHECK: Cluster ld/st SU(1) - SU(3)
; CHECK: SU(1): %{{[0-9]+}}<def> = LDRQui
; CHECK: SU(3): %{{[0-9]+}}<def> = LDRQui
; CHECK: SU(1): %{{[0-9]+}}:fpr128 = LDRQui
; CHECK: SU(3): %{{[0-9]+}}:fpr128 = LDRQui
; EXYNOS: ********** MI Scheduling **********
; EXYNOS-LABEL: ldq_cluster:%bb.0
; EXYNOS-NOT: Cluster ld/st
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@
;
; CHECK: ********** MI Scheduling **********
; CHECK: shiftable
; CHECK: SU(2): %2<def> = SUBXri %1, 20, 0
; CHECK: SU(2): %2:gpr64common = SUBXri %1, 20, 0
; CHECK: Successors:
; CHECK-NEXT: SU(4): Data Latency=1 Reg=%2
; CHECK-NEXT: SU(3): Data Latency=2 Reg=%2
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -5,15 +5,15 @@
;
; CHECK: ********** MI Scheduling **********
; CHECK: misched_bug:%bb.0 entry
; CHECK: SU(2): %2<def> = LDRWui %0, 1; mem:LD4[%ptr1_plus1] GPR32:%2 GPR64common:%0
; CHECK: SU(2): %2:gpr32 = LDRWui %0, 1; mem:LD4[%ptr1_plus1] GPR32:%2 GPR64common:%0
; CHECK: Successors:
; CHECK-NEXT: SU(5): Data Latency=4 Reg=%2
; CHECK-NEXT: SU(4): Ord Latency=0
; CHECK: SU(3): STRWui %wzr, %0, 0; mem:ST4[%ptr1] GPR64common:%0
; CHECK: Successors:
; CHECK: SU(4): Ord Latency=0
; CHECK: SU(4): STRWui %wzr, %1, 0; mem:ST4[%ptr2] GPR64common:%1
; CHECK: SU(5): %w0<def> = COPY %2; GPR32:%2
; CHECK: SU(5): %w0 = COPY %2; GPR32:%2
; CHECK: ** ScheduleDAGMI::schedule picking next node
define i32 @misched_bug(i32* %ptr1, i32* %ptr2) {
entry:
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AArch64/arm64-misched-multimmo.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@
; Check that no scheduling dependencies are created between the paired loads and the store during post-RA MI scheduling.
;
; CHECK-LABEL: # Machine code for function foo:
; CHECK: SU(2): %w{{[0-9]+}}<def>, %w{{[0-9]+}}<def> = LDPWi
; CHECK: SU(2): %w{{[0-9]+}}, %w{{[0-9]+}} = LDPWi
; CHECK: Successors:
; CHECK-NOT: ch SU(4)
; CHECK: SU(3)
Expand Down
78 changes: 39 additions & 39 deletions llvm/test/CodeGen/AArch64/loh.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -22,14 +22,14 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK: Adding MCLOH_AdrpAdrp:
; CHECK-NEXT: %x1<def> = ADRP <ga:@g3>
; CHECK-NEXT: %x1<def> = ADRP <ga:@g4>
; CHECK-NEXT: %x1 = ADRP <ga:@g3>
; CHECK-NEXT: %x1 = ADRP <ga:@g4>
; CHECK-NEXT: Adding MCLOH_AdrpAdrp:
; CHECK-NEXT: %x1<def> = ADRP <ga:@g2>
; CHECK-NEXT: %x1<def> = ADRP <ga:@g3>
; CHECK-NEXT: %x1 = ADRP <ga:@g2>
; CHECK-NEXT: %x1 = ADRP <ga:@g3>
; CHECK-NEXT: Adding MCLOH_AdrpAdrp:
; CHECK-NEXT: %x0<def> = ADRP <ga:@g0>
; CHECK-NEXT: %x0<def> = ADRP <ga:@g1>
; CHECK-NEXT: %x0 = ADRP <ga:@g0>
; CHECK-NEXT: %x0 = ADRP <ga:@g1>
%x0 = ADRP target-flags(aarch64-page) @g0
%x0 = ADRP target-flags(aarch64-page) @g1
%x1 = ADRP target-flags(aarch64-page) @g2
Expand All @@ -38,11 +38,11 @@ body: |
bb.1:
; CHECK-NEXT: Adding MCLOH_AdrpAdd:
; CHECK-NEXT: %x20<def> = ADRP <ga:@g0>
; CHECK-NEXT: %x3<def> = ADDXri %x20, <ga:@g0>
; CHECK-NEXT: %x20 = ADRP <ga:@g0>
; CHECK-NEXT: %x3 = ADDXri %x20, <ga:@g0>
; CHECK-NEXT: Adding MCLOH_AdrpAdd:
; CHECK-NEXT: %x1<def> = ADRP <ga:@g0>
; CHECK-NEXT: %x1<def> = ADDXri %x1, <ga:@g0>
; CHECK-NEXT: %x1 = ADRP <ga:@g0>
; CHECK-NEXT: %x1 = ADDXri %x1, <ga:@g0>
%x1 = ADRP target-flags(aarch64-page) @g0
%x9 = SUBXri undef %x11, 5, 0 ; should not affect MCLOH formation
%x1 = ADDXri %x1, target-flags(aarch64-pageoff) @g0, 0
Expand Down Expand Up @@ -73,23 +73,23 @@ body: |
bb.5:
; CHECK-NEXT: Adding MCLOH_AdrpLdr:
; CHECK-NEXT: %x5<def> = ADRP <ga:@g2>
; CHECK-NEXT: %s6<def> = LDRSui %x5, <ga:@g2>
; CHECK-NEXT: %x5 = ADRP <ga:@g2>
; CHECK-NEXT: %s6 = LDRSui %x5, <ga:@g2>
; CHECK-NEXT: Adding MCLOH_AdrpLdr:
; CHECK-NEXT: %x4<def> = ADRP <ga:@g2>
; CHECK-NEXT: %x4<def> = LDRXui %x4, <ga:@g2>
; CHECK-NEXT: %x4 = ADRP <ga:@g2>
; CHECK-NEXT: %x4 = LDRXui %x4, <ga:@g2>
%x4 = ADRP target-flags(aarch64-page) @g2
%x4 = LDRXui %x4, target-flags(aarch64-pageoff) @g2
%x5 = ADRP target-flags(aarch64-page) @g2
%s6 = LDRSui %x5, target-flags(aarch64-pageoff) @g2
bb.6:
; CHECK-NEXT: Adding MCLOH_AdrpLdrGot:
; CHECK-NEXT: %x5<def> = ADRP <ga:@g2>
; CHECK-NEXT: %x6<def> = LDRXui %x5, <ga:@g2>
; CHECK-NEXT: %x5 = ADRP <ga:@g2>
; CHECK-NEXT: %x6 = LDRXui %x5, <ga:@g2>
; CHECK-NEXT: Adding MCLOH_AdrpLdrGot:
; CHECK-NEXT: %x4<def> = ADRP <ga:@g2>
; CHECK-NEXT: %x4<def> = LDRXui %x4, <ga:@g2>
; CHECK-NEXT: %x4 = ADRP <ga:@g2>
; CHECK-NEXT: %x4 = LDRXui %x4, <ga:@g2>
%x4 = ADRP target-flags(aarch64-page, aarch64-got) @g2
%x4 = LDRXui %x4, target-flags(aarch64-pageoff, aarch64-got) @g2
%x5 = ADRP target-flags(aarch64-page, aarch64-got) @g2
Expand All @@ -104,23 +104,23 @@ body: |
bb.8:
; CHECK-NEXT: Adding MCLOH_AdrpAddLdr:
; CHECK-NEXT: %x7<def> = ADRP <ga:@g3>[TF=1]
; CHECK-NEXT: %x8<def> = ADDXri %x7, <ga:@g3>
; CHECK-NEXT: %d1<def> = LDRDui %x8, 8
; CHECK-NEXT: %x7 = ADRP <ga:@g3>[TF=1]
; CHECK-NEXT: %x8 = ADDXri %x7, <ga:@g3>
; CHECK-NEXT: %d1 = LDRDui %x8, 8
%x7 = ADRP target-flags(aarch64-page) @g3
%x8 = ADDXri %x7, target-flags(aarch64-pageoff) @g3, 0
%d1 = LDRDui %x8, 8
bb.9:
; CHECK-NEXT: Adding MCLOH_AdrpAdd:
; CHECK-NEXT: %x3<def> = ADRP <ga:@g3>
; CHECK-NEXT: %x3<def> = ADDXri %x3, <ga:@g3>
; CHECK-NEXT: %x3 = ADRP <ga:@g3>
; CHECK-NEXT: %x3 = ADDXri %x3, <ga:@g3>
; CHECK-NEXT: Adding MCLOH_AdrpAdd:
; CHECK-NEXT: %x5<def> = ADRP <ga:@g3>
; CHECK-NEXT: %x2<def> = ADDXri %x5, <ga:@g3>
; CHECK-NEXT: %x5 = ADRP <ga:@g3>
; CHECK-NEXT: %x2 = ADDXri %x5, <ga:@g3>
; CHECK-NEXT: Adding MCLOH_AdrpAddStr:
; CHECK-NEXT: %x1<def> = ADRP <ga:@g3>
; CHECK-NEXT: %x1<def> = ADDXri %x1, <ga:@g3>
; CHECK-NEXT: %x1 = ADRP <ga:@g3>
; CHECK-NEXT: %x1 = ADDXri %x1, <ga:@g3>
; CHECK-NEXT: STRXui %xzr, %x1, 16
%x1 = ADRP target-flags(aarch64-page) @g3
%x1 = ADDXri %x1, target-flags(aarch64-pageoff) @g3, 0
Expand All @@ -138,12 +138,12 @@ body: |
bb.10:
; CHECK-NEXT: Adding MCLOH_AdrpLdr:
; CHECK-NEXT: %x2<def> = ADRP <ga:@g3>
; CHECK-NEXT: %x2<def> = LDRXui %x2, <ga:@g3>
; CHECK-NEXT: %x2 = ADRP <ga:@g3>
; CHECK-NEXT: %x2 = LDRXui %x2, <ga:@g3>
; CHECK-NEXT: Adding MCLOH_AdrpLdrGotLdr:
; CHECK-NEXT: %x1<def> = ADRP <ga:@g4>
; CHECK-NEXT: %x1<def> = LDRXui %x1, <ga:@g4>
; CHECK-NEXT: %x1<def> = LDRXui %x1, 24
; CHECK-NEXT: %x1 = ADRP <ga:@g4>
; CHECK-NEXT: %x1 = LDRXui %x1, <ga:@g4>
; CHECK-NEXT: %x1 = LDRXui %x1, 24
%x1 = ADRP target-flags(aarch64-page, aarch64-got) @g4
%x1 = LDRXui %x1, target-flags(aarch64-pageoff, aarch64-got) @g4
%x1 = LDRXui %x1, 24
Expand All @@ -154,11 +154,11 @@ body: |
bb.11:
; CHECK-NEXT: Adding MCLOH_AdrpLdr
; CHECK-NEXT: %x5<def> = ADRP <ga:@g1>
; CHECK-NEXT: %x5<def> = LDRXui %x5, <ga:@g1>
; CHECK-NEXT: %x5 = ADRP <ga:@g1>
; CHECK-NEXT: %x5 = LDRXui %x5, <ga:@g1>
; CHECK-NEXT: Adding MCLOH_AdrpLdrGotStr:
; CHECK-NEXT: %x1<def> = ADRP <ga:@g4>
; CHECK-NEXT: %x1<def> = LDRXui %x1, <ga:@g4>
; CHECK-NEXT: %x1 = ADRP <ga:@g4>
; CHECK-NEXT: %x1 = LDRXui %x1, <ga:@g4>
; CHECK-NEXT: STRXui %xzr, %x1, 32
%x1 = ADRP target-flags(aarch64-page, aarch64-got) @g4
%x1 = LDRXui %x1, target-flags(aarch64-pageoff, aarch64-got) @g4
Expand All @@ -171,9 +171,9 @@ body: |
bb.12:
; CHECK-NOT: MCLOH_AdrpAdrp
; CHECK: Adding MCLOH_AdrpAddLdr
; %x9<def> = ADRP <ga:@g4>
; %x9<def> = ADDXri %x9, <ga:@g4>
; %x5<def> = LDRXui %x9, 0
; %x9 = ADRP <ga:@g4>
; %x9 = ADDXri %x9, <ga:@g4>
; %x5 = LDRXui %x9, 0
%x9 = ADRP target-flags(aarch64-page, aarch64-got) @g4
%x9 = ADDXri %x9, target-flags(aarch64-pageoff, aarch64-got) @g4, 0
%x5 = LDRXui %x9, 0
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/AArch64/machine-copy-prop.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -2,18 +2,18 @@

; This file check a bug in MachineCopyPropagation pass. The last COPY will be
; incorrectly removed if the machine instructions are as follows:
; %q5_q6<def> = COPY %q2_q3
; %d5<def> =
; %d3<def> =
; %d3<def> = COPY %d6
; %q5_q6 = COPY %q2_q3
; %d5 =
; %d3 =
; %d3 = COPY %d6
; This is caused by a bug in function SourceNoLongerAvailable(), which fails to
; remove the relationship of D6 and "%q5_q6<def> = COPY %q2_q3".
; remove the relationship of D6 and "%q5_q6 = COPY %q2_q3".

@failed = internal unnamed_addr global i1 false

; CHECK-LABEL: foo:
; CHECK: ld2
; CHECK-NOT: // kill: D{{[0-9]+}}<def> D{{[0-9]+}}<kill>
; CHECK-NOT: // kill: def D{{[0-9]+}} killed D{{[0-9]+}}
define void @foo(<2 x i32> %shuffle251, <8 x i8> %vtbl1.i, i8* %t2, <2 x i32> %vrsubhn_v2.i1364) {
entry:
%val0 = alloca [2 x i64], align 8
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/AArch64/scheduledag-constreg.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -7,16 +7,16 @@
# Check that the instructions are not dependent on each other, even though
# they all read/write to the zero register.
# CHECK-LABEL: MI Scheduling
# CHECK: SU(0): %wzr<def,dead> = SUBSWri %w1, 0, 0, %nzcv<imp-def,dead>
# CHECK: SU(0): dead %wzr = SUBSWri %w1, 0, 0, implicit-def dead %nzcv
# CHECK: # succs left : 0
# CHECK-NOT: Successors:
# CHECK: SU(1): %w2<def> = COPY %wzr
# CHECK: SU(1): %w2 = COPY %wzr
# CHECK: # succs left : 0
# CHECK-NOT: Successors:
# CHECK: SU(2): %wzr<def,dead> = SUBSWri %w3, 0, 0, %nzcv<imp-def,dead>
# CHECK: SU(2): dead %wzr = SUBSWri %w3, 0, 0, implicit-def dead %nzcv
# CHECK: # succs left : 0
# CHECK-NOT: Successors:
# CHECK: SU(3): %w4<def> = COPY %wzr
# CHECK: SU(3): %w4 = COPY %wzr
# CHECK: # succs left : 0
# CHECK-NOT: Successors:
name: func
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/AArch64/tailcall_misched_graph.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -26,15 +26,15 @@ declare void @callee2(i8*, i8*, i8*, i8*, i8*,
; CHECK: fi#-2: {{.*}} fixed, at location [SP+8]
; CHECK: fi#-1: {{.*}} fixed, at location [SP]

; CHECK: [[VRA:%.*]]<def> = LDRXui <fi#-1>
; CHECK: [[VRB:%.*]]<def> = LDRXui <fi#-2>
; CHECK: [[VRA:%.*]]:gpr64 = LDRXui <fi#-1>
; CHECK: [[VRB:%.*]]:gpr64 = LDRXui <fi#-2>
; CHECK: STRXui %{{.*}}, <fi#-4>
; CHECK: STRXui [[VRB]], <fi#-3>

; Make sure that there is an dependence edge between fi#-2 and fi#-4.
; Without this edge the scheduler would be free to move the store accross the load.

; CHECK: SU({{.*}}): [[VRB]]<def> = LDRXui <fi#-2>
; CHECK: SU({{.*}}): [[VRB]]:gpr64 = LDRXui <fi#-2>
; CHECK-NOT: SU
; CHECK: Successors:
; CHECK: SU([[DEPSTOREB:.*]]): Ord Latency=0
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
; NOOPT: s_load_dwordx2 s[4:5]

; FIXME: Why is the SGPR4_SGPR5 reference being removed from DBG_VALUE?
; NOOPT: ; kill: %sgpr8_sgpr9<def> %sgpr4_sgpr5<kill>
; NOOPT: ; kill: def %sgpr8_sgpr9 killed %sgpr4_sgpr5
; NOOPT-NEXT: ;DEBUG_VALUE: test_debug_value:globalptr_arg <- undef

; GCN: flat_store_dword
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/schedule-regpressure.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@
# Check there is no SReg_32 pressure created by DS_* instructions because of M0 use

# CHECK: ScheduleDAGMILive::schedule starting
# CHECK: SU({{.*}} = DS_READ_B32 {{.*}} %m0<imp-use>, %exec<imp-use>
# CHECK: SU({{.*}} = DS_READ_B32 {{.*}} implicit %m0, implicit %exec
# CHECK: Pressure Diff : {{$}}
# CHECK: SU({{.*}} DS_WRITE_B32

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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -4,8 +4,8 @@ target triple = "thumbv7-apple-darwin10"

; This tests the fast register allocator's handling of partial redefines:
;
; %reg1028:dsub_0<def>, %reg1028:dsub_1<def> = VLD1q64 %reg1025...
; %reg1030:dsub_1<def> = COPY %reg1028:dsub_0<kill>
; %reg1028:dsub_0, %reg1028:dsub_1 = VLD1q64 %reg1025...
; %reg1030:dsub_1 = COPY killed %reg1028:dsub_0
;
; %reg1028 gets allocated %Q0, and if %reg1030 is reloaded for the partial
; redef, it cannot also get %Q0.
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/ARM/2011-11-14-EarlyClobber.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@ target triple = "thumbv7-apple-ios"
;
; The early-clobber instruction is an str:
;
; %12<earlyclobber,def> = t2STR_PRE %6, %12, 32, pred:14, pred:%noreg
; early-clobber %12 = t2STR_PRE %6, %12, 32, pred:14, pred:%noreg
;
; This tests that shrinkToUses handles the EC redef correctly.

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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@
define void @vst(i8* %m, [4 x i64] %v) {
entry:
; CHECK: vst:
; CHECK: VST1d64Q %r{{[0-9]+}}<kill>, 8, %d{{[0-9]+}}, pred:14, pred:%noreg, %q{{[0-9]+}}_q{{[0-9]+}}<imp-use,kill>
; CHECK: VST1d64Q killed %r{{[0-9]+}}, 8, %d{{[0-9]+}}, pred:14, pred:%noreg, implicit killed %q{{[0-9]+}}_q{{[0-9]+}}

%v0 = extractvalue [4 x i64] %v, 0
%v1 = extractvalue [4 x i64] %v, 1
Expand Down Expand Up @@ -37,7 +37,7 @@ entry:
%struct.__neon_int8x8x4_t = type { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> }
define <8 x i8> @vtbx4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B, <8 x i8>* %C) nounwind {
; CHECK: vtbx4:
; CHECK: VTBX4 {{.*}}, pred:14, pred:%noreg, %q{{[0-9]+}}_q{{[0-9]+}}<imp-use>
; CHECK: VTBX4 {{.*}}, pred:14, pred:%noreg, implicit %q{{[0-9]+}}_q{{[0-9]+}}
%tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load %struct.__neon_int8x8x4_t, %struct.__neon_int8x8x4_t* %B
%tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/ARM/Windows/vla-cpsr.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -9,5 +9,5 @@ entry:
ret void
}

; CHECK: tBL pred:14, pred:%noreg, <es:__chkstk>, %lr<imp-def>, %sp<imp-use>, %r4<imp-use,kill>, %r4<imp-def>, %r12<imp-def,dead>, %cpsr<imp-def,dead>
; CHECK: tBL pred:14, pred:%noreg, <es:__chkstk>, implicit-def %lr, implicit %sp, implicit killed %r4, implicit-def %r4, implicit-def dead %r12, implicit-def dead %cpsr

2 changes: 1 addition & 1 deletion llvm/test/CodeGen/ARM/crash-greedy.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -61,7 +61,7 @@ for.end: ; preds = %cond.end

; CHECK: insert_elem
; This test has a sub-register copy with a kill flag:
; %6:ssub_3<def> = COPY %6:ssub_2<kill>; QPR_VFP2:%6
; %6:ssub_3 = COPY killed %6:ssub_2; QPR_VFP2:%6
; The rewriter must do something sensible with that, or the scavenger crashes.
define void @insert_elem() nounwind {
entry:
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/ARM/ifcvt-dead-def.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@ target triple = "thumbv7-unknown-unknown"
%struct.gs_color_s = type { i16, i16, i16, i16, i8, i8 }

; In this case, the if converter was cloning the return instruction so that we had
; r2<def> = ...
; r2 = ...
; return [pred] r2<dead,def>
; ldr <r2, kill>
; return
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6 changes: 3 additions & 3 deletions llvm/test/CodeGen/ARM/misched-copy-arm.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -33,9 +33,9 @@ for.end: ; preds = %for.body, %entry
; This case was a crasher in constrainLocalCopy.
; The problem was the t2LDR_PRE defining both the global and local lrg.
; CHECK-LABEL: *** Final schedule for %bb.5 ***
; CHECK: %[[R4:[0-9]+]]<def>, %[[R1:[0-9]+]]<def,tied2> = t2LDR_PRE %[[R1]]<tied1>
; CHECK: %{{[0-9]+}}<def> = COPY %[[R1]]
; CHECK: %{{[0-9]+}}<def> = COPY %[[R4]]
; CHECK: %[[R4:[0-9]+]]:gpr, %[[R1:[0-9]+]]:gpr = t2LDR_PRE %[[R1]]
; CHECK: %{{[0-9]+}}:gpr = COPY %[[R1]]
; CHECK: %{{[0-9]+}}:gpr = COPY %[[R4]]
; CHECK-LABEL: MACHINEINSTRS
%struct.rtx_def = type { [4 x i8], [1 x %union.rtunion_def] }
%union.rtunion_def = type { i64 }
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22 changes: 11 additions & 11 deletions llvm/test/CodeGen/ARM/misched-int-basic-thumb2.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -37,22 +37,22 @@
}
#
# CHECK: ********** MI Scheduling **********
# CHECK: SU(2): %2<def> = t2MOVi32imm <ga:@g1>; rGPR:%2
# CHECK: SU(2): %2:rgpr = t2MOVi32imm <ga:@g1>; rGPR:%2
# CHECK_A9: Latency : 2
# CHECK_SWIFT: Latency : 2
# CHECK_R52: Latency : 2
#
# CHECK: SU(3): %3<def> = t2LDRi12 %2, 0, pred:14, pred:%noreg; mem:LD4[@g1](dereferenceable) rGPR:%3,%2
# CHECK: SU(3): %3:rgpr = t2LDRi12 %2, 0, pred:14, pred:%noreg; mem:LD4[@g1](dereferenceable) rGPR:%3,%2
# CHECK_A9: Latency : 1
# CHECK_SWIFT: Latency : 3
# CHECK_R52: Latency : 4
#
# CHECK : SU(6): %6<def> = t2ADDrr %3, %3, pred:14, pred:%noreg, opt:%noreg; rGPR:%6,%3,%3
# CHECK : SU(6): %6 = t2ADDrr %3, %3, pred:14, pred:%noreg, opt:%noreg; rGPR:%6,%3,%3
# CHECK_A9: Latency : 1
# CHECK_SWIFT: Latency : 1
# CHECK_R52: Latency : 3

# CHECK: SU(7): %7<def> = t2SDIV %6, %5, pred:14, pred:%noreg; rGPR:%7,%6,%5
# CHECK: SU(7): %7:rgpr = t2SDIV %6, %5, pred:14, pred:%noreg; rGPR:%7,%6,%5
# CHECK_A9: Latency : 0
# CHECK_SWIFT: Latency : 14
# CHECK_R52: Latency : 8
Expand All @@ -62,37 +62,37 @@
# CHECK_SWIFT: Latency : 0
# CHECK_R52: Latency : 4
#
# CHECK: SU(9): %8<def> = t2SMULBB %1, %1, pred:14, pred:%noreg; rGPR:%8,%1,%1
# CHECK: SU(9): %8:rgpr = t2SMULBB %1, %1, pred:14, pred:%noreg; rGPR:%8,%1,%1
# CHECK_A9: Latency : 2
# CHECK_SWIFT: Latency : 4
# CHECK_R52: Latency : 4
#
# CHECK: SU(10): %9<def> = t2SMLABB %0, %0, %8, pred:14, pred:%noreg; rGPR:%9,%0,%0,%8
# CHECK: SU(10): %9:rgpr = t2SMLABB %0, %0, %8, pred:14, pred:%noreg; rGPR:%9,%0,%0,%8
# CHECK_A9: Latency : 2
# CHECK_SWIFT: Latency : 4
# CHECK_R52: Latency : 4
#
# CHECK: SU(11): %10<def> = t2UXTH %9, 0, pred:14, pred:%noreg; rGPR:%10,%9
# CHECK: SU(11): %10:rgpr = t2UXTH %9, 0, pred:14, pred:%noreg; rGPR:%10,%9
# CHECK_A9: Latency : 1
# CHECK_SWIFT: Latency : 1
# CHECK_R52: Latency : 3
#
# CHECK: SU(12): %11<def> = t2MUL %10, %7, pred:14, pred:%noreg; rGPR:%11,%10,%7
# CHECK: SU(12): %11:rgpr = t2MUL %10, %7, pred:14, pred:%noreg; rGPR:%11,%10,%7
# CHECK_A9: Latency : 2
# CHECK_SWIFT: Latency : 4
# CHECK_R52: Latency : 4
#
# CHECK: SU(13): %12<def> = t2MLA %11, %11, %11, pred:14, pred:%noreg; rGPR:%12,%11,%11,%11
# CHECK: SU(13): %12:rgpr = t2MLA %11, %11, %11, pred:14, pred:%noreg; rGPR:%12,%11,%11,%11
# CHECK_A9: Latency : 2
# CHECK_SWIFT: Latency : 4
# CHECK_R52: Latency : 4
#
# CHECK: SU(14): %13<def>, %14<def> = t2UMULL %12, %12, pred:14, pred:%noreg; rGPR:%13,%14,%12,%12
# CHECK: SU(14): %13:rgpr, %14:rgpr = t2UMULL %12, %12, pred:14, pred:%noreg; rGPR:%13,%14,%12,%12
# CHECK_A9: Latency : 3
# CHECK_SWIFT: Latency : 5
# CHECK_R52: Latency : 4
#
# CHECK: SU(18): %19<def,tied4>, %20<def,tied5> = t2UMLAL %12, %12, %19<tied0>, %20<tied1>, pred:14, pred:%noreg; rGPR:%19,%20,%12,%12,%20
# CHECK: SU(18): %19:rgpr, %20:rgpr = t2UMLAL %12, %12, %19, %20, pred:14, pred:%noreg; rGPR:%19,%20,%12,%12,%20
# CHECK_A9: Latency : 3
# CHECK_SWIFT: Latency : 7
# CHECK_R52: Latency : 4
Expand Down
14 changes: 7 additions & 7 deletions llvm/test/CodeGen/ARM/misched-int-basic.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -28,37 +28,37 @@
}

# CHECK: ********** MI Scheduling **********
# CHECK: SU(2): %2<def> = SMULBB %1, %1, pred:14, pred:%noreg; GPR:%2,%1,%1
# CHECK: SU(2): %2:gpr = SMULBB %1, %1, pred:14, pred:%noreg; GPR:%2,%1,%1
# CHECK_A9: Latency : 2
# CHECK_SWIFT: Latency : 4
# CHECK_R52: Latency : 4
#
# CHECK: SU(3): %3<def> = SMLABB %0, %0, %2, pred:14, pred:%noreg; GPRnopc:%3,%0,%0 GPR:%2
# CHECK: SU(3): %3:gprnopc = SMLABB %0, %0, %2, pred:14, pred:%noreg; GPRnopc:%3,%0,%0 GPR:%2
# CHECK_A9: Latency : 2
# CHECK_SWIFT: Latency : 4
# CHECK_R52: Latency : 4
#
# CHECK: SU(4): %4<def> = UXTH %3, 0, pred:14, pred:%noreg; GPRnopc:%4,%3
# CHECK: SU(4): %4:gprnopc = UXTH %3, 0, pred:14, pred:%noreg; GPRnopc:%4,%3
# CHECK_A9: Latency : 1
# CHECK_SWIFT: Latency : 1
# CHECK_R52: Latency : 3
#
# CHECK: SU(5): %5<def> = MUL %4, %4, pred:14, pred:%noreg, opt:%noreg; GPRnopc:%5,%4,%4
# CHECK: SU(5): %5:gprnopc = MUL %4, %4, pred:14, pred:%noreg, opt:%noreg; GPRnopc:%5,%4,%4
# CHECK_A9: Latency : 2
# CHECK_SWIFT: Latency : 4
# CHECK_R52: Latency : 4
#
# CHECK: SU(6): %6<def> = MLA %5, %5, %5, pred:14, pred:%noreg, opt:%noreg; GPRnopc:%6,%5,%5,%5
# CHECK: SU(6): %6:gprnopc = MLA %5, %5, %5, pred:14, pred:%noreg, opt:%noreg; GPRnopc:%6,%5,%5,%5
# CHECK_A9: Latency : 2
# CHECK_SWIFT: Latency : 4
# CHECK_R52: Latency : 4
#
# CHECK: SU(7): %7<def>, %8<def> = UMULL %6, %6, pred:14, pred:%noreg, opt:%noreg; GPRnopc:%7,%8,%6,%6
# CHECK: SU(7): %7:gprnopc, %8:gprnopc = UMULL %6, %6, pred:14, pred:%noreg, opt:%noreg; GPRnopc:%7,%8,%6,%6
# CHECK_A9: Latency : 3
# CHECK_SWIFT: Latency : 5
# CHECK_R52: Latency : 4
#
# CHECK: SU(11): %13<def,tied4>, %14<def,tied5> = UMLAL %6, %6, %13<tied0>, %14<tied1>, pred:14, pred:%noreg, opt:%noreg; GPR:%13 GPRnopc:%14,%6,%6
# CHECK: SU(11): %13:gpr, %14:gprnopc = UMLAL %6, %6, %13, %14, pred:14, pred:%noreg, opt:%noreg; GPR:%13 GPRnopc:%14,%6,%6
# CHECK_SWIFT: Latency : 7
# CHECK_A9: Latency : 3
# CHECK_R52: Latency : 4
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/ARM/sched-it-debug-nodes.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -32,9 +32,9 @@
; debug value as KILL'ed, resulting in a DEBUG_VALUE node changing codegen! (or
; hopefully, triggering an assert).

; CHECK: BUNDLE %itstate<imp-def,dead>
; CHECK: * DBG_VALUE %r1, %noreg, !"u"
; CHECK-NOT: * DBG_VALUE %r1<kill>, %noreg, !"u"
; CHECK: BUNDLE implicit-def dead %itstate
; CHECK: * DBG_VALUE debug-use %r1, debug-use %noreg, !"u"
; CHECK-NOT: * DBG_VALUE killed %r1, %noreg, !"u"

declare arm_aapcscc void @g(%struct.s*, i8*, i32) #1

Expand Down
14 changes: 7 additions & 7 deletions llvm/test/CodeGen/ARM/single-issue-r52.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -20,22 +20,22 @@

# CHECK: ********** MI Scheduling **********
# CHECK: ScheduleDAGMILive::schedule starting
# CHECK: SU(1): %1<def> = VLD4d8Pseudo %0, 8, pred:14, pred:%noreg; mem:LD32[%A](align=8) QQPR:%1 GPR:%0
# CHECK: SU(1): %1:qqpr = VLD4d8Pseudo %0, 8, pred:14, pred:%noreg; mem:LD32[%A](align=8) QQPR:%1 GPR:%0
# CHECK: Latency : 8
# CHECK: Single Issue : true;
# CHECK: SU(2): %4<def> = VADDv8i8 %1:dsub_0, %1:dsub_1, pred:14, pred:%noreg; DPR:%4 QQPR:%1
# CHECK: SU(2): %4:dpr = VADDv8i8 %1.dsub_0, %1.dsub_1, pred:14, pred:%noreg; DPR:%4 QQPR:%1
# CHECK: Latency : 5
# CHECK: Single Issue : false;
# CHECK: SU(3): %5<def>, %6<def> = VMOVRRD %4, pred:14, pred:%noreg; GPR:%5,%6 DPR:%4
# CHECK: SU(3): %5:gpr, %6:gpr = VMOVRRD %4, pred:14, pred:%noreg; GPR:%5,%6 DPR:%4
# CHECK: Latency : 4
# CHECK: Single Issue : false;

# TOPDOWN: Scheduling SU(1) %1<def> = VLD4d8Pseudo
# TOPDOWN: Scheduling SU(1) %1:qqpr = VLD4d8Pseudo
# TOPDOWN: Bump cycle to end group
# TOPDOWN: Scheduling SU(2) %4<def> = VADDv8i8
# TOPDOWN: Scheduling SU(2) %4:dpr = VADDv8i8

# BOTTOMUP: Scheduling SU(2) %4<def> = VADDv8i8
# BOTTOMUP: Scheduling SU(1) %1<def> = VLD4d8Pseudo
# BOTTOMUP: Scheduling SU(2) %4:dpr = VADDv8i8
# BOTTOMUP: Scheduling SU(1) %1:qqpr = VLD4d8Pseudo
# BOTTOMUP: Bump cycle to begin group

...
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/ARM/subreg-remat.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,8 +4,8 @@ target triple = "thumbv7-apple-ios"
;
; The vector %v2 is built like this:
;
; %6:ssub_1<def> = ...
; %6:ssub_0<def> = VLDRS <cp#0>, 0, pred:14, pred:%noreg; mem:LD4[ConstantPool] DPR_VFP2:%6
; %6:ssub_1 = ...
; %6:ssub_0 = VLDRS <cp#0>, 0, pred:14, pred:%noreg; mem:LD4[ConstantPool] DPR_VFP2:%6
;
; When %6 spills, the VLDRS constant pool load cannot be rematerialized
; since it implicitly reads the ssub_1 sub-register.
Expand All @@ -31,7 +31,7 @@ define void @f1(float %x, <2 x float>* %p) {
; because the bits are undef, we should rematerialize. The vector is now built
; like this:
;
; %2:ssub_0<def> = VLDRS <cp#0>, 0, pred:14, pred:%noreg, %2<imp-def>; mem:LD4[ConstantPool]
; %2:ssub_0 = VLDRS <cp#0>, 0, pred:14, pred:%noreg, implicit-def %2; mem:LD4[ConstantPool]
;
; The extra <imp-def> operand indicates that the instruction fully defines the
; virtual register. It doesn't read the old value.
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/ARM/vldm-liveness.mir
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Original file line number Diff line number Diff line change
@@ -1,9 +1,9 @@
# RUN: llc -run-pass arm-ldst-opt -verify-machineinstrs %s -o - | FileCheck %s
# ARM load store optimizer was dealing with a sequence like:
# s1 = VLDRS [r0, 1], Q0<imp-def>
# s3 = VLDRS [r0, 2], Q0<imp-use,kill>, Q0<imp-def>
# s0 = VLDRS [r0, 0], Q0<imp-use,kill>, Q0<imp-def>
# s2 = VLDRS [r0, 4], Q0<imp-use,kill>, Q0<imp-def>
# s1 = VLDRS [r0, 1], implicit-def Q0
# s3 = VLDRS [r0, 2], implicit killed Q0, implicit-def Q0
# s0 = VLDRS [r0, 0], implicit killed Q0, implicit-def Q0
# s2 = VLDRS [r0, 4], implicit killed Q0, implicit-def Q0
#
# It decided to combine the {s0, s1} loads into a single instruction in the
# third position. However, this leaves the instruction defining s3 with a stray
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/AVR/select-must-add-unconditional-jump.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -11,11 +11,11 @@
;
; %bb.2: derived from LLVM BB %finish
; Predecessors according to CFG: %bb.0 %bb.1
; %0<def> = PHI %3, <%bb.0>, %5, <%bb.1>
; %7<def> = LDIRdK 2
; %8<def> = LDIRdK 1
; CPRdRr %2, %0, %SREG<imp-def>
; BREQk <%bb.6>, %SREG<imp-use>
; %0 = PHI %3, <%bb.0>, %5, <%bb.1>
; %7 = LDIRdK 2
; %8 = LDIRdK 1
; CPRdRr %2, %0, implicit-def %SREG
; BREQk <%bb.6>, implicit %SREG
; Successors according to CFG: %bb.5(?%) %bb.6(?%)
;
; The code assumes it the fallthrough block after this is %bb.5, but
Expand Down
14 changes: 7 additions & 7 deletions llvm/test/CodeGen/Hexagon/branch-folder-hoist-kills.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -6,19 +6,19 @@
# that were no longer live-in.
# This could cause if-converter to generate incorrect code.
#
# In this testcase, the "r1 = A2_sxth r0<kill>" was hoisted, and since r0
# In this testcase, the "r1 = A2_sxth killed r0" was hoisted, and since r0
# was killed, it was no longer live-in in either successor. The if-converter
# then created code, where the first predicated instruction has incorrect
# implicit use of r0:
#
# %bb.0:
# Live Ins: %R0
# %R1<def> = A2_sxth %R0<kill> ; hoisted, kills r0
# A2_nop %P0<imp-def>
# %R0<def> = C2_cmoveit %P0, 2, %R0<imp-use> ; predicated A2_tfrsi
# %R0<def> = C2_cmoveif killed %P0, 1, %R0<imp-use> ; predicated A2_tfrsi
# %R0<def> = A2_add %R0<kill>, %R1<kill>
# J2_jumpr %R31, %PC<imp-def,dead>
# %R1 = A2_sxth killed %R0 ; hoisted, kills r0
# A2_nop implicit-def %P0
# %R0 = C2_cmoveit %P0, 2, implicit %R0 ; predicated A2_tfrsi
# %R0 = C2_cmoveif killed %P0, 1, implicit %R0 ; predicated A2_tfrsi
# %R0 = A2_add killed %R0, killed %R1
# J2_jumpr %R31, implicit dead %PC
#

# CHECK: %r1 = A2_sxth killed %r0
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Hexagon/post-inc-aa-metadata.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@

; Check that the generated post-increment load has TBAA information.
; CHECK-LABEL: Machine code for function fred:
; CHECK: = V6_vL32b_pi %{{[0-9]+}}<tied1>, 64; mem:LD64[{{.*}}](tbaa=
; CHECK: = V6_vL32b_pi %{{[0-9]+}}, 64; mem:LD64[{{.*}}](tbaa=

target triple = "hexagon"

Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Lanai/lanai-misched-trivial-disjoint.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -36,7 +36,7 @@ entry:
; CHECK-LABEL: SU({{.*}}): SW_RI{{.*}}, 4,
; CHECK: # preds left : 2
; CHECK: # succs left : 0
; CHECK-LABEL: SU({{.*}}): %{{.*}}<def> = LDW_RI{{.*}}, 12,
; CHECK-LABEL: SU({{.*}}): %{{.*}} = LDW_RI{{.*}}, 12,
; CHECK: # preds left : 1
; CHECK: # succs left : 4
; CHECK-LABEL: SU({{.*}}): STH_RI{{.*}}, 10,
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/PowerPC/byval-agg-info.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -13,5 +13,5 @@ entry:

; Make sure that the MMO on the store has no offset from the byval
; variable itself (we used to have mem:ST8[%v+64]).
; CHECK: STD %x5<kill>, 176, %x1; mem:ST8[%v](align=16)
; CHECK: STD killed %x5, 176, %x1; mem:ST8[%v](align=16)

16 changes: 8 additions & 8 deletions llvm/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,11 +7,11 @@ define signext i32 @fn1(i32 %baz) {
%2 = zext i32 %1 to i64
%3 = shl i64 %2, 48
%4 = ashr exact i64 %3, 48
; CHECK: ANDIo8 {{[^,]+}}, 65520, %cr0<imp-def,dead>;
; CHECK: ANDIo8 killed {{[^,]+}}, 65520, implicit-def dead %cr0;
; CHECK: CMPLDI
; CHECK: BCC

; CHECK: ANDIo8 {{[^,]+}}, 65520, %cr0<imp-def>;
; CHECK: ANDIo8 {{[^,]+}}, 65520, implicit-def %cr0;
; CHECK: COPY %cr0
; CHECK: BCC
%5 = icmp eq i64 %4, 0
Expand All @@ -26,9 +26,9 @@ bar:

; CHECK-LABEL: fn2
define signext i32 @fn2(i64 %a, i64 %b) {
; CHECK: OR8o {{[^, ]+}}, {{[^, ]+}}, %cr0<imp-def>;
; CHECK: [[CREG:[^, ]+]]<def> = COPY %cr0
; CHECK: BCC 12, [[CREG]]<kill>
; CHECK: OR8o {{[^, ]+}}, {{[^, ]+}}, implicit-def %cr0;
; CHECK: [[CREG:[^, ]+]]:crrc = COPY killed %cr0
; CHECK: BCC 12, killed [[CREG]]
%1 = or i64 %b, %a
%2 = icmp sgt i64 %1, -1
br i1 %2, label %foo, label %bar
Expand All @@ -42,9 +42,9 @@ bar:

; CHECK-LABEL: fn3
define signext i32 @fn3(i32 %a) {
; CHECK: ANDIo {{[^, ]+}}, 10, %cr0<imp-def>;
; CHECK: [[CREG:[^, ]+]]<def> = COPY %cr0
; CHECK: BCC 76, [[CREG]]<kill>
; CHECK: ANDIo killed {{[%0-9]+}}, 10, implicit-def %cr0;
; CHECK: [[CREG:[^, ]+]]:crrc = COPY %cr0
; CHECK: BCC 76, killed [[CREG]]
%1 = and i32 %a, 10
%2 = icmp ne i32 %1, 0
br i1 %2, label %foo, label %bar
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/PowerPC/quadint-return.ll
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Expand Up @@ -14,6 +14,6 @@ entry:

; CHECK: ********** Function: foo
; CHECK: ********** FAST REGISTER ALLOCATION **********
; CHECK: %x3<def> = COPY %{{[0-9]+}}
; CHECK-NEXT: %x4<def> = COPY %{{[0-9]+}}
; CHECK: %x3 = COPY %{{[0-9]+}}
; CHECK-NEXT: %x4 = COPY %{{[0-9]+}}
; CHECK-NEXT: BLR
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/SystemZ/pr32505.ll
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Expand Up @@ -10,8 +10,8 @@ define <2 x float> @pr32505(<2 x i8> * %a) {
; CHECK-NEXT: lbh %r1, 0(%r2)
; CHECK-NEXT: ldgr %f0, %r1
; CHECK-NEXT: ldgr %f2, %r0
; CHECK-NEXT: # kill: %f0s<def> %f0s<kill> %f0d<kill>
; CHECK-NEXT: # kill: %f2s<def> %f2s<kill> %f2d<kill>
; CHECK-NEXT: # kill: def %f0s killed %f0s killed %f0d
; CHECK-NEXT: # kill: def %f2s killed %f2s killed %f2d
; CHECK-NEXT: br %r14
%L17 = load <2 x i8>, <2 x i8>* %a
%Se21 = sext <2 x i8> %L17 to <2 x i32>
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/SystemZ/regalloc-fast-invalid-kill-flag.mir
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Expand Up @@ -21,7 +21,7 @@ registers:
# CHECK-NEXT: %r0l = COPY %r1l
# Although R0L partially redefines R0Q, it must not mark R0Q as kill
# because R1D is still live through that instruction.
# CHECK-NOT: %r0q<imp-use,kill>
# CHECK-NOT: implicit killed %r0q
# CHECK-NEXT: %r2d = COPY %r1d
# CHECK-NEXT: LARL
body: |
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll
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Expand Up @@ -5,8 +5,8 @@ target triple = "thumbv7-apple-darwin10"
; This is a case where the coalescer was too eager. These two copies were
; considered equivalent and coalescable:
;
; 140 %reg1038:dsub_0<def> = VMOVD %reg1047:dsub_0, pred:14, pred:%reg0
; 148 %reg1038:dsub_1<def> = VMOVD %reg1047:dsub_0, pred:14, pred:%reg0
; 140 %reg1038:dsub_0 = VMOVD %reg1047:dsub_0, pred:14, pred:%reg0
; 148 %reg1038:dsub_1 = VMOVD %reg1047:dsub_0, pred:14, pred:%reg0
;
; Only one can be coalesced.

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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/X86/2010-02-12-CoalescerBug-Impdef.ll
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Expand Up @@ -4,15 +4,15 @@
; Tricky coalescer bug:
; After coalescing %RAX with a virtual register, this instruction was rematted:
;
; %EAX<def> = MOV32rr %reg1070<kill>
; %EAX = MOV32rr killed %reg1070
;
; This instruction silently defined %RAX, and when rematting removed the
; instruction, the live interval for %RAX was not properly updated. The valno
; referred to a deleted instruction and bad things happened.
;
; The fix is to implicitly define %RAX when coalescing:
;
; %EAX<def> = MOV32rr %reg1070<kill>, %RAX<imp-def>
; %EAX = MOV32rr killed %reg1070, implicit-def %RAX
;

target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/X86/2010-02-23-RematImplicitSubreg.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@
;
; This test produces a move instruction with an implicitly defined super-register:
;
; %DL<def> = MOV8rr %reg1038<kill>, %RDX<imp-def>
; %DL = MOV8rr killed %reg1038, implicit-def %RDX
;
; When %DL is rematerialized, we must remember to update live intervals for
; sub-registers %DX and %EDX.
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/X86/2010-04-08-CoalescerBug.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -2,8 +2,8 @@
; rdar://7842028

; Do not delete partially dead copy instructions.
; %rdi<def,dead> = MOV64rr %rax<kill>, %edi<imp-def>
; REP_MOVSD %ecx<imp-def,dead>, %edi<imp-def,dead>, %esi<imp-def,dead>, %ecx<imp-use,kill>, %edi<imp-use,kill>, %esi<imp-use,kill>
; dead %rdi = MOV64rr killed %rax, implicit-def %edi
; REP_MOVSD implicit dead %ecx, implicit dead %edi, implicit dead %esi, implicit killed %ecx, implicit killed %edi, implicit killed %esi


%struct.F = type { %struct.FC*, i32, i32, i8, i32, i32, i32 }
Expand Down
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/X86/2010-05-12-FastAllocKills.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -5,24 +5,24 @@ target triple = "x86_64-apple-darwin"
; This test causes a virtual FP register to be redefined while it is live:
;%bb.5: derived from LLVM BB %bb10
; Predecessors according to CFG: %bb.4 %bb.5
; %reg1024<def> = MOV_Fp8080 %reg1034
; %reg1025<def> = MUL_Fp80m32 %reg1024, %rip, 1, %reg0, <cp#0>, %reg0; mem:LD4[ConstantPool]
; %reg1034<def> = MOV_Fp8080 %reg1025
; FP_REG_KILL %fp0<imp-def>, %fp1<imp-def>, %fp2<imp-def>, %fp3<imp-def>, %fp4<imp-def>, %fp5<imp-def>, %fp6<imp-def>
; %reg1024 = MOV_Fp8080 %reg1034
; %reg1025 = MUL_Fp80m32 %reg1024, %rip, 1, %reg0, <cp#0>, %reg0; mem:LD4[ConstantPool]
; %reg1034 = MOV_Fp8080 %reg1025
; FP_REG_KILL implicit-def %fp0, implicit-def %fp1, implicit-def %fp2, implicit-def %fp3, implicit-def %fp4, implicit-def %fp5, implicit-def %fp6
; JMP_4 <%bb.5>
; Successors according to CFG: %bb.5
;
; The X86FP pass needs good kill flags, like on %fp0 representing %reg1034:
;%bb.5: derived from LLVM BB %bb10
; Predecessors according to CFG: %bb.4 %bb.5
; %fp0<def> = LD_Fp80m <fi#3>, 1, %reg0, 0, %reg0; mem:LD10[FixedStack3](align=4)
; %fp1<def> = MOV_Fp8080 %fp0<kill>
; %fp2<def> = MUL_Fp80m32 %fp1, %rip, 1, %reg0, <cp#0>, %reg0; mem:LD4[ConstantPool]
; %fp0<def> = MOV_Fp8080 %fp2
; ST_FpP80m <fi#3>, 1, %reg0, 0, %reg0, %fp0<kill>; mem:ST10[FixedStack3](align=4)
; ST_FpP80m <fi#4>, 1, %reg0, 0, %reg0, %fp1<kill>; mem:ST10[FixedStack4](align=4)
; ST_FpP80m <fi#5>, 1, %reg0, 0, %reg0, %fp2<kill>; mem:ST10[FixedStack5](align=4)
; FP_REG_KILL %fp0<imp-def>, %fp1<imp-def>, %fp2<imp-def>, %fp3<imp-def>, %fp4<imp-def>, %fp5<imp-def>, %fp6<imp-def>
; %fp0 = LD_Fp80m <fi#3>, 1, %reg0, 0, %reg0; mem:LD10[FixedStack3](align=4)
; %fp1 = MOV_Fp8080 killed %fp0
; %fp2 = MUL_Fp80m32 %fp1, %rip, 1, %reg0, <cp#0>, %reg0; mem:LD4[ConstantPool]
; %fp0 = MOV_Fp8080 %fp2
; ST_FpP80m <fi#3>, 1, %reg0, 0, %reg0, killed %fp0; mem:ST10[FixedStack3](align=4)
; ST_FpP80m <fi#4>, 1, %reg0, 0, %reg0, killed %fp1; mem:ST10[FixedStack4](align=4)
; ST_FpP80m <fi#5>, 1, %reg0, 0, %reg0, killed %fp2; mem:ST10[FixedStack5](align=4)
; FP_REG_KILL implicit-def %fp0, implicit-def %fp1, implicit-def %fp2, implicit-def %fp3, implicit-def %fp4, implicit-def %fp5, implicit-def %fp6
; JMP_4 <%bb.5>
; Successors according to CFG: %bb.5

Expand Down
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/X86/GlobalISel/add-scalar.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -28,8 +28,8 @@ define i64 @test_add_i64(i64 %arg1, i64 %arg2) {
define i32 @test_add_i32(i32 %arg1, i32 %arg2) {
; X64-LABEL: test_add_i32:
; X64: # %bb.0:
; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; X64-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
; X64-NEXT: # kill: def %edi killed %edi def %rdi
; X64-NEXT: # kill: def %esi killed %esi def %rsi
; X64-NEXT: leal (%rsi,%rdi), %eax
; X64-NEXT: retq
;
Expand All @@ -45,10 +45,10 @@ define i32 @test_add_i32(i32 %arg1, i32 %arg2) {
define i16 @test_add_i16(i16 %arg1, i16 %arg2) {
; X64-LABEL: test_add_i16:
; X64: # %bb.0:
; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; X64-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
; X64-NEXT: # kill: def %edi killed %edi def %rdi
; X64-NEXT: # kill: def %esi killed %esi def %rsi
; X64-NEXT: leal (%rsi,%rdi), %eax
; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; X64-NEXT: # kill: def %ax killed %ax killed %eax
; X64-NEXT: retq
;
; X32-LABEL: test_add_i16:
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/X86/GlobalISel/ext-x86-64.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@
define i64 @test_zext_i1(i8 %a) {
; X64-LABEL: test_zext_i1:
; X64: # %bb.0:
; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def>
; X64-NEXT: # kill: def %edi killed %edi def %rdi
; X64-NEXT: andq $1, %rdi
; X64-NEXT: movq %rdi, %rax
; X64-NEXT: retq
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/X86/GlobalISel/ext.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ define i8 @test_zext_i1toi8(i32 %a) {
; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: andb $1, %al
; X32-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; X32-NEXT: # kill: def %al killed %al killed %eax
; X32-NEXT: retl
%val = trunc i32 %a to i1
%r = zext i1 %val to i8
Expand All @@ -31,7 +31,7 @@ define i16 @test_zext_i1toi16(i32 %a) {
; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: andw $1, %ax
; X32-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; X32-NEXT: # kill: def %ax killed %ax killed %eax
; X32-NEXT: retl
%val = trunc i32 %a to i1
%r = zext i1 %val to i16
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/X86/GlobalISel/gep.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ define i32* @test_gep_i8(i32 *%arr, i8 %ind) {
;
; X64-LABEL: test_gep_i8:
; X64: # %bb.0:
; X64-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
; X64-NEXT: # kill: def %esi killed %esi def %rsi
; X64-NEXT: movsbq %sil, %rax
; X64-NEXT: leaq (%rdi,%rax,4), %rax
; X64-NEXT: retq
Expand Down Expand Up @@ -47,7 +47,7 @@ define i32* @test_gep_i16(i32 *%arr, i16 %ind) {
;
; X64-LABEL: test_gep_i16:
; X64: # %bb.0:
; X64-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
; X64-NEXT: # kill: def %esi killed %esi def %rsi
; X64-NEXT: movswq %si, %rax
; X64-NEXT: leaq (%rdi,%rax,4), %rax
; X64-NEXT: retq
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/X86/GlobalISel/x86_64-fallback.ll
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Expand Up @@ -8,7 +8,7 @@
; the fallback path.

; Check that we fallback on invoke translation failures.
; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_STORE %1, %0; mem:ST10[%ptr](align=16) (in function: test_x86_fp80_dump)
; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_STORE %1(s80), %0(p0); mem:ST10[%ptr](align=16) (in function: test_x86_fp80_dump)
; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for test_x86_fp80_dump
; FALLBACK-WITH-REPORT-OUT-LABEL: test_x86_fp80_dump:
define void @test_x86_fp80_dump(x86_fp80* %ptr){
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/X86/add-sub-nsw-nuw.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@ define i8 @PR30841(i64 %argc) {
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: negl %eax
; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill>
; CHECK-NEXT: ## kill: def %al killed %al killed %eax
; CHECK-NEXT: retl
entry:
%or = or i64 %argc, -4294967296
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/X86/add.ll
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Expand Up @@ -176,14 +176,14 @@ define i64 @test6(i64 %A, i32 %B) nounwind {
;
; X64-LINUX-LABEL: test6:
; X64-LINUX: # %bb.0: # %entry
; X64-LINUX-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
; X64-LINUX-NEXT: # kill: def %esi killed %esi def %rsi
; X64-LINUX-NEXT: shlq $32, %rsi
; X64-LINUX-NEXT: leaq (%rsi,%rdi), %rax
; X64-LINUX-NEXT: retq
;
; X64-WIN32-LABEL: test6:
; X64-WIN32: # %bb.0: # %entry
; X64-WIN32-NEXT: # kill: %edx<def> %edx<kill> %rdx<def>
; X64-WIN32-NEXT: # kill: def %edx killed %edx def %rdx
; X64-WIN32-NEXT: shlq $32, %rdx
; X64-WIN32-NEXT: leaq (%rdx,%rcx), %rax
; X64-WIN32-NEXT: retq
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/X86/addcarry.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -84,7 +84,7 @@ entry:
define i8 @e(i32* nocapture %a, i32 %b) nounwind {
; CHECK-LABEL: e:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: %esi<def> %esi<kill> %rsi<def>
; CHECK-NEXT: # kill: def %esi killed %esi def %rsi
; CHECK-NEXT: movl (%rdi), %ecx
; CHECK-NEXT: leal (%rsi,%rcx), %edx
; CHECK-NEXT: addl %esi, %edx
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/X86/anyext.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@ define i32 @foo(i32 %p, i8 zeroext %x) nounwind {
; X32-LABEL: foo:
; X32: # %bb.0:
; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X32-NEXT: # kill: %eax<def> %eax<kill> %ax<def>
; X32-NEXT: # kill: def %eax killed %eax def %ax
; X32-NEXT: divb {{[0-9]+}}(%esp)
; X32-NEXT: movzbl %al, %eax
; X32-NEXT: andl $1, %eax
Expand All @@ -17,7 +17,7 @@ define i32 @foo(i32 %p, i8 zeroext %x) nounwind {
; X64-LABEL: foo:
; X64: # %bb.0:
; X64-NEXT: movzbl %dil, %eax
; X64-NEXT: # kill: %eax<def> %eax<kill> %ax<def>
; X64-NEXT: # kill: def %eax killed %eax def %ax
; X64-NEXT: divb %sil
; X64-NEXT: movzbl %al, %eax
; X64-NEXT: andl $1, %eax
Expand All @@ -35,7 +35,7 @@ define i32 @bar(i32 %p, i16 zeroext %x) nounwind {
; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: xorl %edx, %edx
; X32-NEXT: divw {{[0-9]+}}(%esp)
; X32-NEXT: # kill: %ax<def> %ax<kill> %eax<def>
; X32-NEXT: # kill: def %ax killed %ax def %eax
; X32-NEXT: andl $1, %eax
; X32-NEXT: retl
;
Expand All @@ -44,7 +44,7 @@ define i32 @bar(i32 %p, i16 zeroext %x) nounwind {
; X64-NEXT: xorl %edx, %edx
; X64-NEXT: movl %edi, %eax
; X64-NEXT: divw %si
; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<def>
; X64-NEXT: # kill: def %ax killed %ax def %eax
; X64-NEXT: andl $1, %eax
; X64-NEXT: retq
%q = trunc i32 %p to i16
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/X86/atomic-eflags-reuse.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -93,7 +93,7 @@ define i8 @test_add_1_setcc_slt(i64* %p) #0 {
; CHECK-NEXT: movl $1, %eax
; CHECK-NEXT: lock xaddq %rax, (%rdi)
; CHECK-NEXT: shrq $63, %rax
; CHECK-NEXT: # kill: %al<def> %al<kill> %rax<kill>
; CHECK-NEXT: # kill: def %al killed %al killed %rax
; CHECK-NEXT: retq
entry:
%tmp0 = atomicrmw add i64* %p, i64 1 seq_cst
Expand Down
14 changes: 7 additions & 7 deletions llvm/test/CodeGen/X86/avx-cast.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@
define <8 x float> @castA(<4 x float> %m) nounwind uwtable readnone ssp {
; AVX-LABEL: castA:
; AVX: ## %bb.0:
; AVX-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; AVX-NEXT: ## kill: def %xmm0 killed %xmm0 def %ymm0
; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7]
; AVX-NEXT: retq
Expand All @@ -20,7 +20,7 @@ define <8 x float> @castA(<4 x float> %m) nounwind uwtable readnone ssp {
define <4 x double> @castB(<2 x double> %m) nounwind uwtable readnone ssp {
; AVX-LABEL: castB:
; AVX: ## %bb.0:
; AVX-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; AVX-NEXT: ## kill: def %xmm0 killed %xmm0 def %ymm0
; AVX-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; AVX-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3]
; AVX-NEXT: retq
Expand All @@ -33,14 +33,14 @@ define <4 x double> @castB(<2 x double> %m) nounwind uwtable readnone ssp {
define <4 x i64> @castC(<2 x i64> %m) nounwind uwtable readnone ssp {
; AVX1-LABEL: castC:
; AVX1: ## %bb.0:
; AVX1-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; AVX1-NEXT: ## kill: def %xmm0 killed %xmm0 def %ymm0
; AVX1-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3]
; AVX1-NEXT: retq
;
; AVX2-LABEL: castC:
; AVX2: ## %bb.0:
; AVX2-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; AVX2-NEXT: ## kill: def %xmm0 killed %xmm0 def %ymm0
; AVX2-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7]
; AVX2-NEXT: retq
Expand All @@ -54,7 +54,7 @@ define <4 x i64> @castC(<2 x i64> %m) nounwind uwtable readnone ssp {
define <4 x float> @castD(<8 x float> %m) nounwind uwtable readnone ssp {
; AVX-LABEL: castD:
; AVX: ## %bb.0:
; AVX-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; AVX-NEXT: ## kill: def %xmm0 killed %xmm0 killed %ymm0
; AVX-NEXT: vzeroupper
; AVX-NEXT: retq
%shuffle.i = shufflevector <8 x float> %m, <8 x float> %m, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
Expand All @@ -64,7 +64,7 @@ define <4 x float> @castD(<8 x float> %m) nounwind uwtable readnone ssp {
define <2 x i64> @castE(<4 x i64> %m) nounwind uwtable readnone ssp {
; AVX-LABEL: castE:
; AVX: ## %bb.0:
; AVX-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; AVX-NEXT: ## kill: def %xmm0 killed %xmm0 killed %ymm0
; AVX-NEXT: vzeroupper
; AVX-NEXT: retq
%shuffle.i = shufflevector <4 x i64> %m, <4 x i64> %m, <2 x i32> <i32 0, i32 1>
Expand All @@ -74,7 +74,7 @@ define <2 x i64> @castE(<4 x i64> %m) nounwind uwtable readnone ssp {
define <2 x double> @castF(<4 x double> %m) nounwind uwtable readnone ssp {
; AVX-LABEL: castF:
; AVX: ## %bb.0:
; AVX-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; AVX-NEXT: ## kill: def %xmm0 killed %xmm0 killed %ymm0
; AVX-NEXT: vzeroupper
; AVX-NEXT: retq
%shuffle.i = shufflevector <4 x double> %m, <4 x double> %m, <2 x i32> <i32 0, i32 1>
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/X86/avx-cmp.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -197,7 +197,7 @@ define i32 @scalarcmpA() uwtable ssp {
; CHECK-NEXT: vcmpeqsd %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovq %xmm0, %rax
; CHECK-NEXT: andl $1, %eax
; CHECK-NEXT: # kill: %eax<def> %eax<kill> %rax<kill>
; CHECK-NEXT: # kill: def %eax killed %eax killed %rax
; CHECK-NEXT: retq
%cmp29 = fcmp oeq double undef, 0.000000e+00
%res = zext i1 %cmp29 to i32
Expand Down
56 changes: 28 additions & 28 deletions llvm/test/CodeGen/X86/avx-intrinsics-fast-isel.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -316,12 +316,12 @@ define <4 x i64> @test_mm256_castpd_si256(<4 x double> %a0) nounwind {
define <4 x double> @test_mm256_castpd128_pd256(<2 x double> %a0) nounwind {
; X32-LABEL: test_mm256_castpd128_pd256:
; X32: # %bb.0:
; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; X32-NEXT: # kill: def %xmm0 killed %xmm0 def %ymm0
; X32-NEXT: retl
;
; X64-LABEL: test_mm256_castpd128_pd256:
; X64: # %bb.0:
; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; X64-NEXT: # kill: def %xmm0 killed %xmm0 def %ymm0
; X64-NEXT: retq
%res = shufflevector <2 x double> %a0, <2 x double> %a0, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
ret <4 x double> %res
Expand All @@ -330,13 +330,13 @@ define <4 x double> @test_mm256_castpd128_pd256(<2 x double> %a0) nounwind {
define <2 x double> @test_mm256_castpd256_pd128(<4 x double> %a0) nounwind {
; X32-LABEL: test_mm256_castpd256_pd128:
; X32: # %bb.0:
; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; X32-NEXT: # kill: def %xmm0 killed %xmm0 killed %ymm0
; X32-NEXT: vzeroupper
; X32-NEXT: retl
;
; X64-LABEL: test_mm256_castpd256_pd128:
; X64: # %bb.0:
; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; X64-NEXT: # kill: def %xmm0 killed %xmm0 killed %ymm0
; X64-NEXT: vzeroupper
; X64-NEXT: retq
%res = shufflevector <4 x double> %a0, <4 x double> %a0, <2 x i32> <i32 0, i32 1>
Expand Down Expand Up @@ -370,12 +370,12 @@ define <4 x i64> @test_mm256_castps_si256(<8 x float> %a0) nounwind {
define <8 x float> @test_mm256_castps128_ps256(<4 x float> %a0) nounwind {
; X32-LABEL: test_mm256_castps128_ps256:
; X32: # %bb.0:
; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; X32-NEXT: # kill: def %xmm0 killed %xmm0 def %ymm0
; X32-NEXT: retl
;
; X64-LABEL: test_mm256_castps128_ps256:
; X64: # %bb.0:
; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; X64-NEXT: # kill: def %xmm0 killed %xmm0 def %ymm0
; X64-NEXT: retq
%res = shufflevector <4 x float> %a0, <4 x float> %a0, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
ret <8 x float> %res
Expand All @@ -384,13 +384,13 @@ define <8 x float> @test_mm256_castps128_ps256(<4 x float> %a0) nounwind {
define <4 x float> @test_mm256_castps256_ps128(<8 x float> %a0) nounwind {
; X32-LABEL: test_mm256_castps256_ps128:
; X32: # %bb.0:
; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; X32-NEXT: # kill: def %xmm0 killed %xmm0 killed %ymm0
; X32-NEXT: vzeroupper
; X32-NEXT: retl
;
; X64-LABEL: test_mm256_castps256_ps128:
; X64: # %bb.0:
; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; X64-NEXT: # kill: def %xmm0 killed %xmm0 killed %ymm0
; X64-NEXT: vzeroupper
; X64-NEXT: retq
%res = shufflevector <8 x float> %a0, <8 x float> %a0, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
Expand All @@ -400,12 +400,12 @@ define <4 x float> @test_mm256_castps256_ps128(<8 x float> %a0) nounwind {
define <4 x i64> @test_mm256_castsi128_si256(<2 x i64> %a0) nounwind {
; X32-LABEL: test_mm256_castsi128_si256:
; X32: # %bb.0:
; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; X32-NEXT: # kill: def %xmm0 killed %xmm0 def %ymm0
; X32-NEXT: retl
;
; X64-LABEL: test_mm256_castsi128_si256:
; X64: # %bb.0:
; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; X64-NEXT: # kill: def %xmm0 killed %xmm0 def %ymm0
; X64-NEXT: retq
%res = shufflevector <2 x i64> %a0, <2 x i64> %a0, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
ret <4 x i64> %res
Expand Down Expand Up @@ -438,13 +438,13 @@ define <8 x float> @test_mm256_castsi256_ps(<4 x i64> %a0) nounwind {
define <2 x i64> @test_mm256_castsi256_si128(<4 x i64> %a0) nounwind {
; X32-LABEL: test_mm256_castsi256_si128:
; X32: # %bb.0:
; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; X32-NEXT: # kill: def %xmm0 killed %xmm0 killed %ymm0
; X32-NEXT: vzeroupper
; X32-NEXT: retl
;
; X64-LABEL: test_mm256_castsi256_si128:
; X64: # %bb.0:
; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; X64-NEXT: # kill: def %xmm0 killed %xmm0 killed %ymm0
; X64-NEXT: vzeroupper
; X64-NEXT: retq
%res = shufflevector <4 x i64> %a0, <4 x i64> %a0, <2 x i32> <i32 0, i32 1>
Expand Down Expand Up @@ -1043,13 +1043,13 @@ define <4 x i64> @test_mm256_insert_epi64(<4 x i64> %a0, i64 %a1) nounwind {
define <4 x double> @test_mm256_insertf128_pd(<4 x double> %a0, <2 x double> %a1) nounwind {
; X32-LABEL: test_mm256_insertf128_pd:
; X32: # %bb.0:
; X32-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def>
; X32-NEXT: # kill: def %xmm1 killed %xmm1 def %ymm1
; X32-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3]
; X32-NEXT: retl
;
; X64-LABEL: test_mm256_insertf128_pd:
; X64: # %bb.0:
; X64-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def>
; X64-NEXT: # kill: def %xmm1 killed %xmm1 def %ymm1
; X64-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3]
; X64-NEXT: retq
%ext = shufflevector <2 x double> %a1, <2 x double> %a1, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
Expand All @@ -1075,13 +1075,13 @@ define <8 x float> @test_mm256_insertf128_ps(<8 x float> %a0, <4 x float> %a1) n
define <4 x i64> @test_mm256_insertf128_si256(<4 x i64> %a0, <2 x i64> %a1) nounwind {
; X32-LABEL: test_mm256_insertf128_si256:
; X32: # %bb.0:
; X32-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def>
; X32-NEXT: # kill: def %xmm1 killed %xmm1 def %ymm1
; X32-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3]
; X32-NEXT: retl
;
; X64-LABEL: test_mm256_insertf128_si256:
; X64: # %bb.0:
; X64-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def>
; X64-NEXT: # kill: def %xmm1 killed %xmm1 def %ymm1
; X64-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3]
; X64-NEXT: retq
%ext = shufflevector <2 x i64> %a1, <2 x i64> %a1, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
Expand Down Expand Up @@ -2188,13 +2188,13 @@ define <4 x i64> @test_mm256_set_epi64x(i64 %a0, i64 %a1, i64 %a2, i64 %a3) noun
define <8 x float> @test_mm256_set_m128(<4 x float> %a0, <4 x float> %a1) nounwind {
; X32-LABEL: test_mm256_set_m128:
; X32: # %bb.0:
; X32-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def>
; X32-NEXT: # kill: def %xmm1 killed %xmm1 def %ymm1
; X32-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; X32-NEXT: retl
;
; X64-LABEL: test_mm256_set_m128:
; X64: # %bb.0:
; X64-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def>
; X64-NEXT: # kill: def %xmm1 killed %xmm1 def %ymm1
; X64-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; X64-NEXT: retq
%res = shufflevector <4 x float> %a1, <4 x float> %a0, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
Expand All @@ -2204,13 +2204,13 @@ define <8 x float> @test_mm256_set_m128(<4 x float> %a0, <4 x float> %a1) nounwi
define <4 x double> @test_mm256_set_m128d(<2 x double> %a0, <2 x double> %a1) nounwind {
; X32-LABEL: test_mm256_set_m128d:
; X32: # %bb.0:
; X32-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def>
; X32-NEXT: # kill: def %xmm1 killed %xmm1 def %ymm1
; X32-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; X32-NEXT: retl
;
; X64-LABEL: test_mm256_set_m128d:
; X64: # %bb.0:
; X64-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def>
; X64-NEXT: # kill: def %xmm1 killed %xmm1 def %ymm1
; X64-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; X64-NEXT: retq
%arg0 = bitcast <2 x double> %a0 to <4 x float>
Expand All @@ -2223,13 +2223,13 @@ define <4 x double> @test_mm256_set_m128d(<2 x double> %a0, <2 x double> %a1) no
define <4 x i64> @test_mm256_set_m128i(<2 x i64> %a0, <2 x i64> %a1) nounwind {
; X32-LABEL: test_mm256_set_m128i:
; X32: # %bb.0:
; X32-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def>
; X32-NEXT: # kill: def %xmm1 killed %xmm1 def %ymm1
; X32-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; X32-NEXT: retl
;
; X64-LABEL: test_mm256_set_m128i:
; X64: # %bb.0:
; X64-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def>
; X64-NEXT: # kill: def %xmm1 killed %xmm1 def %ymm1
; X64-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; X64-NEXT: retq
%arg0 = bitcast <2 x i64> %a0 to <4 x float>
Expand Down Expand Up @@ -2825,13 +2825,13 @@ define <4 x i64> @test_mm256_setr_epi64x(i64 %a0, i64 %a1, i64 %a2, i64 %a3) nou
define <8 x float> @test_mm256_setr_m128(<4 x float> %a0, <4 x float> %a1) nounwind {
; X32-LABEL: test_mm256_setr_m128:
; X32: # %bb.0:
; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; X32-NEXT: # kill: def %xmm0 killed %xmm0 def %ymm0
; X32-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; X32-NEXT: retl
;
; X64-LABEL: test_mm256_setr_m128:
; X64: # %bb.0:
; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; X64-NEXT: # kill: def %xmm0 killed %xmm0 def %ymm0
; X64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; X64-NEXT: retq
%res = shufflevector <4 x float> %a0, <4 x float> %a1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
Expand All @@ -2841,13 +2841,13 @@ define <8 x float> @test_mm256_setr_m128(<4 x float> %a0, <4 x float> %a1) nounw
define <4 x double> @test_mm256_setr_m128d(<2 x double> %a0, <2 x double> %a1) nounwind {
; X32-LABEL: test_mm256_setr_m128d:
; X32: # %bb.0:
; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; X32-NEXT: # kill: def %xmm0 killed %xmm0 def %ymm0
; X32-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; X32-NEXT: retl
;
; X64-LABEL: test_mm256_setr_m128d:
; X64: # %bb.0:
; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; X64-NEXT: # kill: def %xmm0 killed %xmm0 def %ymm0
; X64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; X64-NEXT: retq
%arg0 = bitcast <2 x double> %a0 to <4 x float>
Expand All @@ -2860,13 +2860,13 @@ define <4 x double> @test_mm256_setr_m128d(<2 x double> %a0, <2 x double> %a1) n
define <4 x i64> @test_mm256_setr_m128i(<2 x i64> %a0, <2 x i64> %a1) nounwind {
; X32-LABEL: test_mm256_setr_m128i:
; X32: # %bb.0:
; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; X32-NEXT: # kill: def %xmm0 killed %xmm0 def %ymm0
; X32-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; X32-NEXT: retl
;
; X64-LABEL: test_mm256_setr_m128i:
; X64: # %bb.0:
; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; X64-NEXT: # kill: def %xmm0 killed %xmm0 def %ymm0
; X64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; X64-NEXT: retq
%arg0 = bitcast <2 x i64> %a0 to <4 x float>
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -39,7 +39,7 @@ define <8 x i32> @test_x86_avx_vinsertf128_si_256_1(<8 x i32> %a0, <4 x i32> %a1
define <8 x i32> @test_x86_avx_vinsertf128_si_256_2(<8 x i32> %a0, <4 x i32> %a1) {
; CHECK-LABEL: test_x86_avx_vinsertf128_si_256_2:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def>
; CHECK-NEXT: # kill: def %xmm1 killed %xmm1 def %ymm1
; CHECK-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3]
; CHECK-NEXT: ret{{[l|q]}}
%res = call <8 x i32> @llvm.x86.avx.vinsertf128.si.256(<8 x i32> %a0, <4 x i32> %a1, i8 2)
Expand Down Expand Up @@ -88,7 +88,7 @@ declare <4 x i32> @llvm.x86.avx.vextractf128.si.256(<8 x i32>, i8) nounwind read
define <2 x double> @test_x86_avx_extractf128_pd_256_2(<4 x double> %a0) {
; CHECK-LABEL: test_x86_avx_extractf128_pd_256_2:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; CHECK-NEXT: # kill: def %xmm0 killed %xmm0 killed %ymm0
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: ret{{[l|q]}}
%res = call <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double> %a0, i8 2)
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/X86/avx-vinsertf128.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -75,7 +75,7 @@ define <8 x i32> @DAGCombineB(<8 x i32> %v1, <8 x i32> %v2) nounwind readonly {
define <4 x double> @insert_undef_pd(<4 x double> %a0, <2 x double> %a1) {
; CHECK-LABEL: insert_undef_pd:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def>
; CHECK-NEXT: # kill: def %xmm1 killed %xmm1 def %ymm1
; CHECK-NEXT: vmovaps %ymm1, %ymm0
; CHECK-NEXT: retq
%res = call <4 x double> @llvm.x86.avx.vinsertf128.pd.256(<4 x double> undef, <2 x double> %a1, i8 0)
Expand All @@ -86,7 +86,7 @@ declare <4 x double> @llvm.x86.avx.vinsertf128.pd.256(<4 x double>, <2 x double>
define <8 x float> @insert_undef_ps(<8 x float> %a0, <4 x float> %a1) {
; CHECK-LABEL: insert_undef_ps:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def>
; CHECK-NEXT: # kill: def %xmm1 killed %xmm1 def %ymm1
; CHECK-NEXT: vmovaps %ymm1, %ymm0
; CHECK-NEXT: retq
%res = call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> undef, <4 x float> %a1, i8 0)
Expand All @@ -97,7 +97,7 @@ declare <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float>, <4 x float>, i
define <8 x i32> @insert_undef_si(<8 x i32> %a0, <4 x i32> %a1) {
; CHECK-LABEL: insert_undef_si:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def>
; CHECK-NEXT: # kill: def %xmm1 killed %xmm1 def %ymm1
; CHECK-NEXT: vmovaps %ymm1, %ymm0
; CHECK-NEXT: retq
%res = call <8 x i32> @llvm.x86.avx.vinsertf128.si.256(<8 x i32> undef, <4 x i32> %a1, i8 0)
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/X86/avx-vzeroupper.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -82,14 +82,14 @@ define <4 x float> @test02(<8 x float> %a, <8 x float> %b) nounwind {
; VZ-LABEL: test02:
; VZ: # %bb.0:
; VZ-NEXT: vaddps %ymm1, %ymm0, %ymm0
; VZ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; VZ-NEXT: # kill: def %xmm0 killed %xmm0 killed %ymm0
; VZ-NEXT: vzeroupper
; VZ-NEXT: jmp do_sse # TAILCALL
;
; NO-VZ-LABEL: test02:
; NO-VZ: # %bb.0:
; NO-VZ-NEXT: vaddps %ymm1, %ymm0, %ymm0
; NO-VZ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; NO-VZ-NEXT: # kill: def %xmm0 killed %xmm0 killed %ymm0
; NO-VZ-NEXT: jmp do_sse # TAILCALL
%add.i = fadd <8 x float> %a, %b
%add.low = call <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float> %add.i, i8 0)
Expand Down Expand Up @@ -222,21 +222,21 @@ define <4 x float> @test04(<4 x float> %a, <4 x float> %b) nounwind {
; VZ-LABEL: test04:
; VZ: # %bb.0:
; VZ-NEXT: pushq %rax
; VZ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; VZ-NEXT: # kill: def %xmm0 killed %xmm0 def %ymm0
; VZ-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; VZ-NEXT: callq do_avx
; VZ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; VZ-NEXT: # kill: def %xmm0 killed %xmm0 killed %ymm0
; VZ-NEXT: popq %rax
; VZ-NEXT: vzeroupper
; VZ-NEXT: retq
;
; NO-VZ-LABEL: test04:
; NO-VZ: # %bb.0:
; NO-VZ-NEXT: pushq %rax
; NO-VZ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; NO-VZ-NEXT: # kill: def %xmm0 killed %xmm0 def %ymm0
; NO-VZ-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; NO-VZ-NEXT: callq do_avx
; NO-VZ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; NO-VZ-NEXT: # kill: def %xmm0 killed %xmm0 killed %ymm0
; NO-VZ-NEXT: popq %rax
; NO-VZ-NEXT: retq
%shuf = shufflevector <4 x float> %a, <4 x float> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/X86/avx2-conversions.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,15 +7,15 @@ define <4 x i32> @trunc4(<4 x i64> %A) nounwind {
; X32: # %bb.0:
; X32-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
; X32-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,2,3]
; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; X32-NEXT: # kill: def %xmm0 killed %xmm0 killed %ymm0
; X32-NEXT: vzeroupper
; X32-NEXT: retl
;
; X64-LABEL: trunc4:
; X64: # %bb.0:
; X64-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
; X64-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,2,3]
; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; X64-NEXT: # kill: def %xmm0 killed %xmm0 killed %ymm0
; X64-NEXT: vzeroupper
; X64-NEXT: retq
%B = trunc <4 x i64> %A to <4 x i32>
Expand All @@ -27,15 +27,15 @@ define <8 x i16> @trunc8(<8 x i32> %A) nounwind {
; X32: # %bb.0:
; X32-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
; X32-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; X32-NEXT: # kill: def %xmm0 killed %xmm0 killed %ymm0
; X32-NEXT: vzeroupper
; X32-NEXT: retl
;
; X64-LABEL: trunc8:
; X64: # %bb.0:
; X64-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
; X64-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; X64-NEXT: # kill: def %xmm0 killed %xmm0 killed %ymm0
; X64-NEXT: vzeroupper
; X64-NEXT: retq
%B = trunc <8 x i32> %A to <8 x i16>
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/X86/avx2-intrinsics-fast-isel.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -355,7 +355,7 @@ define <4 x double> @test_mm256_broadcastsd_pd(<4 x double> %a0) {
define <4 x i64> @test_mm256_broadcastsi128_si256(<2 x i64> %a0) {
; CHECK-LABEL: test_mm256_broadcastsi128_si256:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; CHECK-NEXT: # kill: def %xmm0 killed %xmm0 def %ymm0
; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
; CHECK-NEXT: ret{{[l|q]}}
%res = shufflevector <2 x i64> %a0, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
Expand Down Expand Up @@ -1447,7 +1447,7 @@ define <4 x float> @test_mm256_mask_i64gather_ps(<4 x float> %a0, float *%a1, <4
define <4 x i64> @test0_mm256_inserti128_si256(<4 x i64> %a0, <2 x i64> %a1) nounwind {
; CHECK-LABEL: test0_mm256_inserti128_si256:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def>
; CHECK-NEXT: # kill: def %xmm1 killed %xmm1 def %ymm1
; CHECK-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7]
; CHECK-NEXT: ret{{[l|q]}}
%ext = shufflevector <2 x i64> %a1, <2 x i64> %a1, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/X86/avx2-shift.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -532,7 +532,7 @@ define <8 x i16> @variable_shl16(<8 x i16> %lhs, <8 x i16> %rhs) {
; X32-NEXT: vpsllvd %ymm1, %ymm0, %ymm0
; X32-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
; X32-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; X32-NEXT: # kill: def %xmm0 killed %xmm0 killed %ymm0
; X32-NEXT: vzeroupper
; X32-NEXT: retl
;
Expand All @@ -543,7 +543,7 @@ define <8 x i16> @variable_shl16(<8 x i16> %lhs, <8 x i16> %rhs) {
; X64-NEXT: vpsllvd %ymm1, %ymm0, %ymm0
; X64-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
; X64-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; X64-NEXT: # kill: def %xmm0 killed %xmm0 killed %ymm0
; X64-NEXT: vzeroupper
; X64-NEXT: retq
%res = shl <8 x i16> %lhs, %rhs
Expand Down Expand Up @@ -582,7 +582,7 @@ define <8 x i16> @variable_lshr16(<8 x i16> %lhs, <8 x i16> %rhs) {
; X32-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0
; X32-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
; X32-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; X32-NEXT: # kill: def %xmm0 killed %xmm0 killed %ymm0
; X32-NEXT: vzeroupper
; X32-NEXT: retl
;
Expand All @@ -593,7 +593,7 @@ define <8 x i16> @variable_lshr16(<8 x i16> %lhs, <8 x i16> %rhs) {
; X64-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0
; X64-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
; X64-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; X64-NEXT: # kill: def %xmm0 killed %xmm0 killed %ymm0
; X64-NEXT: vzeroupper
; X64-NEXT: retq
%res = lshr <8 x i16> %lhs, %rhs
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/X86/avx2-vector-shifts.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -409,7 +409,7 @@ define <8 x i16> @shl_8i16(<8 x i16> %r, <8 x i16> %a) nounwind {
; X32-NEXT: vpsllvd %ymm1, %ymm0, %ymm0
; X32-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
; X32-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; X32-NEXT: # kill: def %xmm0 killed %xmm0 killed %ymm0
; X32-NEXT: vzeroupper
; X32-NEXT: retl
;
Expand All @@ -420,7 +420,7 @@ define <8 x i16> @shl_8i16(<8 x i16> %r, <8 x i16> %a) nounwind {
; X64-NEXT: vpsllvd %ymm1, %ymm0, %ymm0
; X64-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
; X64-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; X64-NEXT: # kill: def %xmm0 killed %xmm0 killed %ymm0
; X64-NEXT: vzeroupper
; X64-NEXT: retq
%shl = shl <8 x i16> %r, %a
Expand Down Expand Up @@ -617,7 +617,7 @@ define <8 x i16> @lshr_8i16(<8 x i16> %r, <8 x i16> %a) nounwind {
; X32-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0
; X32-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
; X32-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; X32-NEXT: # kill: def %xmm0 killed %xmm0 killed %ymm0
; X32-NEXT: vzeroupper
; X32-NEXT: retl
;
Expand All @@ -628,7 +628,7 @@ define <8 x i16> @lshr_8i16(<8 x i16> %r, <8 x i16> %a) nounwind {
; X64-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0
; X64-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
; X64-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; X64-NEXT: # kill: def %xmm0 killed %xmm0 killed %ymm0
; X64-NEXT: vzeroupper
; X64-NEXT: retq
%lshr = lshr <8 x i16> %r, %a
Expand Down
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/X86/avx512-arith.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -176,10 +176,10 @@ define <4 x i64> @imulq256(<4 x i64> %y, <4 x i64> %x) {
;
; AVX512DQ-LABEL: imulq256:
; AVX512DQ: # %bb.0:
; AVX512DQ-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; AVX512DQ-NEXT: # kill: def %ymm1 killed %ymm1 def %zmm1
; AVX512DQ-NEXT: # kill: def %ymm0 killed %ymm0 def %zmm0
; AVX512DQ-NEXT: vpmullq %zmm0, %zmm1, %zmm0
; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; AVX512DQ-NEXT: # kill: def %ymm0 killed %ymm0 killed %zmm0
; AVX512DQ-NEXT: retq
;
; SKX-LABEL: imulq256:
Expand Down Expand Up @@ -229,10 +229,10 @@ define <2 x i64> @imulq128(<2 x i64> %y, <2 x i64> %x) {
;
; AVX512DQ-LABEL: imulq128:
; AVX512DQ: # %bb.0:
; AVX512DQ-NEXT: # kill: %xmm1<def> %xmm1<kill> %zmm1<def>
; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def>
; AVX512DQ-NEXT: # kill: def %xmm1 killed %xmm1 def %zmm1
; AVX512DQ-NEXT: # kill: def %xmm0 killed %xmm0 def %zmm0
; AVX512DQ-NEXT: vpmullq %zmm0, %zmm1, %zmm0
; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
; AVX512DQ-NEXT: # kill: def %xmm0 killed %xmm0 killed %zmm0
; AVX512DQ-NEXT: vzeroupper
; AVX512DQ-NEXT: retq
;
Expand Down Expand Up @@ -717,7 +717,7 @@ define <16 x float> @test_mask_vminps(<16 x float> %dst, <16 x float> %i,
define <8 x double> @test_mask_vminpd(<8 x double> %dst, <8 x double> %i,
; AVX512F-LABEL: test_mask_vminpd:
; AVX512F: # %bb.0:
; AVX512F-NEXT: # kill: %ymm3<def> %ymm3<kill> %zmm3<def>
; AVX512F-NEXT: # kill: def %ymm3 killed %ymm3 def %zmm3
; AVX512F-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX512F-NEXT: vpcmpneqd %zmm4, %zmm3, %k1
; AVX512F-NEXT: vminpd %zmm2, %zmm1, %zmm0 {%k1}
Expand All @@ -732,15 +732,15 @@ define <8 x double> @test_mask_vminpd(<8 x double> %dst, <8 x double> %i,
;
; AVX512BW-LABEL: test_mask_vminpd:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: # kill: %ymm3<def> %ymm3<kill> %zmm3<def>
; AVX512BW-NEXT: # kill: def %ymm3 killed %ymm3 def %zmm3
; AVX512BW-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX512BW-NEXT: vpcmpneqd %zmm4, %zmm3, %k1
; AVX512BW-NEXT: vminpd %zmm2, %zmm1, %zmm0 {%k1}
; AVX512BW-NEXT: retq
;
; AVX512DQ-LABEL: test_mask_vminpd:
; AVX512DQ: # %bb.0:
; AVX512DQ-NEXT: # kill: %ymm3<def> %ymm3<kill> %zmm3<def>
; AVX512DQ-NEXT: # kill: def %ymm3 killed %ymm3 def %zmm3
; AVX512DQ-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX512DQ-NEXT: vpcmpneqd %zmm4, %zmm3, %k1
; AVX512DQ-NEXT: vminpd %zmm2, %zmm1, %zmm0 {%k1}
Expand Down Expand Up @@ -780,7 +780,7 @@ define <16 x float> @test_mask_vmaxps(<16 x float> %dst, <16 x float> %i,
define <8 x double> @test_mask_vmaxpd(<8 x double> %dst, <8 x double> %i,
; AVX512F-LABEL: test_mask_vmaxpd:
; AVX512F: # %bb.0:
; AVX512F-NEXT: # kill: %ymm3<def> %ymm3<kill> %zmm3<def>
; AVX512F-NEXT: # kill: def %ymm3 killed %ymm3 def %zmm3
; AVX512F-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX512F-NEXT: vpcmpneqd %zmm4, %zmm3, %k1
; AVX512F-NEXT: vmaxpd %zmm2, %zmm1, %zmm0 {%k1}
Expand All @@ -795,15 +795,15 @@ define <8 x double> @test_mask_vmaxpd(<8 x double> %dst, <8 x double> %i,
;
; AVX512BW-LABEL: test_mask_vmaxpd:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: # kill: %ymm3<def> %ymm3<kill> %zmm3<def>
; AVX512BW-NEXT: # kill: def %ymm3 killed %ymm3 def %zmm3
; AVX512BW-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX512BW-NEXT: vpcmpneqd %zmm4, %zmm3, %k1
; AVX512BW-NEXT: vmaxpd %zmm2, %zmm1, %zmm0 {%k1}
; AVX512BW-NEXT: retq
;
; AVX512DQ-LABEL: test_mask_vmaxpd:
; AVX512DQ: # %bb.0:
; AVX512DQ-NEXT: # kill: %ymm3<def> %ymm3<kill> %zmm3<def>
; AVX512DQ-NEXT: # kill: def %ymm3 killed %ymm3 def %zmm3
; AVX512DQ-NEXT: vpxor %xmm4, %xmm4, %xmm4
; AVX512DQ-NEXT: vpcmpneqd %zmm4, %zmm3, %k1
; AVX512DQ-NEXT: vmaxpd %zmm2, %zmm1, %zmm0 {%k1}
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/X86/avx512-build-vector.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,7 @@ define <16 x i32> @test2(<16 x i32> %x) {
define <16 x float> @test3(<4 x float> %a) {
; CHECK-LABEL: test3:
; CHECK: ## %bb.0:
; CHECK-NEXT: ## kill: %xmm0<def> %xmm0<kill> %zmm0<def>
; CHECK-NEXT: ## kill: def %xmm0 killed %xmm0 def %zmm0
; CHECK-NEXT: vmovaps {{.*#+}} zmm2 = [0,1,2,3,4,18,16,7,8,9,10,11,12,13,14,15]
; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
; CHECK-NEXT: vpermt2ps %zmm0, %zmm2, %zmm1
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/X86/avx512-calling-conv.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -65,7 +65,7 @@ define <8 x i1> @test3(<8 x i1>%a, <8 x i1>%b) {
; KNL-NEXT: vptestmq %zmm1, %zmm1, %k1 {%k1}
; KNL-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; KNL-NEXT: vpmovdw %zmm0, %ymm0
; KNL-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; KNL-NEXT: ## kill: def %xmm0 killed %xmm0 killed %ymm0
; KNL-NEXT: retq
;
; SKX-LABEL: test3:
Expand All @@ -88,7 +88,7 @@ define <8 x i1> @test3(<8 x i1>%a, <8 x i1>%b) {
; KNL_X32-NEXT: vptestmq %zmm1, %zmm1, %k1 {%k1}
; KNL_X32-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; KNL_X32-NEXT: vpmovdw %zmm0, %ymm0
; KNL_X32-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; KNL_X32-NEXT: ## kill: def %xmm0 killed %xmm0 killed %ymm0
; KNL_X32-NEXT: retl
%c = and <8 x i1>%a, %b
ret <8 x i1> %c
Expand Down Expand Up @@ -126,7 +126,7 @@ define <8 x i32> @test5(<8 x i32>%a, <8 x i32>%b) {
; KNL-NEXT: .cfi_def_cfa_offset 16
; KNL-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0
; KNL-NEXT: vpmovdw %zmm0, %ymm0
; KNL-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; KNL-NEXT: ## kill: def %xmm0 killed %xmm0 killed %ymm0
; KNL-NEXT: callq _func8xi1
; KNL-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; KNL-NEXT: vpslld $31, %ymm0, %ymm0
Expand Down Expand Up @@ -154,7 +154,7 @@ define <8 x i32> @test5(<8 x i32>%a, <8 x i32>%b) {
; KNL_X32-NEXT: .cfi_def_cfa_offset 16
; KNL_X32-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0
; KNL_X32-NEXT: vpmovdw %zmm0, %ymm0
; KNL_X32-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; KNL_X32-NEXT: ## kill: def %xmm0 killed %xmm0 killed %ymm0
; KNL_X32-NEXT: calll _func8xi1
; KNL_X32-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; KNL_X32-NEXT: vpslld $31, %ymm0, %ymm0
Expand Down Expand Up @@ -266,7 +266,7 @@ define <8 x i1> @test7a(<8 x i32>%a, <8 x i32>%b) {
; KNL-NEXT: .cfi_def_cfa_offset 16
; KNL-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0
; KNL-NEXT: vpmovdw %zmm0, %ymm0
; KNL-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; KNL-NEXT: ## kill: def %xmm0 killed %xmm0 killed %ymm0
; KNL-NEXT: callq _func8xi1
; KNL-NEXT: vpmovsxwq %xmm0, %zmm0
; KNL-NEXT: vpsllq $63, %zmm0, %zmm0
Expand All @@ -275,7 +275,7 @@ define <8 x i1> @test7a(<8 x i32>%a, <8 x i32>%b) {
; KNL-NEXT: vptestmq %zmm0, %zmm0, %k1 {%k1}
; KNL-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; KNL-NEXT: vpmovdw %zmm0, %ymm0
; KNL-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; KNL-NEXT: ## kill: def %xmm0 killed %xmm0 killed %ymm0
; KNL-NEXT: popq %rax
; KNL-NEXT: retq
;
Expand All @@ -302,7 +302,7 @@ define <8 x i1> @test7a(<8 x i32>%a, <8 x i32>%b) {
; KNL_X32-NEXT: .cfi_def_cfa_offset 16
; KNL_X32-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0
; KNL_X32-NEXT: vpmovdw %zmm0, %ymm0
; KNL_X32-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; KNL_X32-NEXT: ## kill: def %xmm0 killed %xmm0 killed %ymm0
; KNL_X32-NEXT: calll _func8xi1
; KNL_X32-NEXT: vpmovsxwq %xmm0, %zmm0
; KNL_X32-NEXT: vpsllq $63, %zmm0, %zmm0
Expand All @@ -311,7 +311,7 @@ define <8 x i1> @test7a(<8 x i32>%a, <8 x i32>%b) {
; KNL_X32-NEXT: vptestmq %zmm0, %zmm0, %k1 {%k1}
; KNL_X32-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; KNL_X32-NEXT: vpmovdw %zmm0, %ymm0
; KNL_X32-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; KNL_X32-NEXT: ## kill: def %xmm0 killed %xmm0 killed %ymm0
; KNL_X32-NEXT: addl $12, %esp
; KNL_X32-NEXT: retl
%cmpRes = icmp sgt <8 x i32>%a, %b
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/X86/avx512-cmp-kor-sequence.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -19,7 +19,7 @@ define zeroext i16 @cmp_kor_seq_16(<16 x float> %a, <16 x float> %b, <16 x float
; CHECK-NEXT: korw %k2, %k1, %k1
; CHECK-NEXT: korw %k1, %k0, %k0
; CHECK-NEXT: kmovw %k0, %eax
; CHECK-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; CHECK-NEXT: # kill: def %ax killed %ax killed %eax
; CHECK-NEXT: retq
entry:
%0 = tail call i16 @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %a, <16 x float> %x, i32 13, i16 -1, i32 4)
Expand Down
66 changes: 33 additions & 33 deletions llvm/test/CodeGen/X86/avx512-cvt.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -80,9 +80,9 @@ define <4 x double> @slto4f64(<4 x i64> %a) {
;
; AVX512DQ-LABEL: slto4f64:
; AVX512DQ: # %bb.0:
; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; AVX512DQ-NEXT: # kill: def %ymm0 killed %ymm0 def %zmm0
; AVX512DQ-NEXT: vcvtqq2pd %zmm0, %zmm0
; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; AVX512DQ-NEXT: # kill: def %ymm0 killed %ymm0 killed %zmm0
; AVX512DQ-NEXT: retq
%b = sitofp <4 x i64> %a to <4 x double>
ret <4 x double> %b
Expand All @@ -105,9 +105,9 @@ define <2 x double> @slto2f64(<2 x i64> %a) {
;
; AVX512DQ-LABEL: slto2f64:
; AVX512DQ: # %bb.0:
; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def>
; AVX512DQ-NEXT: # kill: def %xmm0 killed %xmm0 def %zmm0
; AVX512DQ-NEXT: vcvtqq2pd %zmm0, %zmm0
; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
; AVX512DQ-NEXT: # kill: def %xmm0 killed %xmm0 killed %zmm0
; AVX512DQ-NEXT: vzeroupper
; AVX512DQ-NEXT: retq
%b = sitofp <2 x i64> %a to <2 x double>
Expand All @@ -133,9 +133,9 @@ define <2 x float> @sltof2f32(<2 x i64> %a) {
;
; AVX512DQ-LABEL: sltof2f32:
; AVX512DQ: # %bb.0:
; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def>
; AVX512DQ-NEXT: # kill: def %xmm0 killed %xmm0 def %zmm0
; AVX512DQ-NEXT: vcvtqq2ps %zmm0, %ymm0
; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; AVX512DQ-NEXT: # kill: def %xmm0 killed %xmm0 killed %ymm0
; AVX512DQ-NEXT: vzeroupper
; AVX512DQ-NEXT: retq
%b = sitofp <2 x i64> %a to <2 x float>
Expand Down Expand Up @@ -170,7 +170,7 @@ define <4 x float> @slto4f32_mem(<4 x i64>* %a) {
; AVX512DQ: # %bb.0:
; AVX512DQ-NEXT: vmovups (%rdi), %ymm0
; AVX512DQ-NEXT: vcvtqq2ps %zmm0, %ymm0
; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; AVX512DQ-NEXT: # kill: def %xmm0 killed %xmm0 killed %ymm0
; AVX512DQ-NEXT: vzeroupper
; AVX512DQ-NEXT: retq
%a1 = load <4 x i64>, <4 x i64>* %a, align 8
Expand Down Expand Up @@ -204,9 +204,9 @@ define <4 x i64> @f64to4sl(<4 x double> %a) {
;
; AVX512DQ-LABEL: f64to4sl:
; AVX512DQ: # %bb.0:
; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; AVX512DQ-NEXT: # kill: def %ymm0 killed %ymm0 def %zmm0
; AVX512DQ-NEXT: vcvttpd2qq %zmm0, %zmm0
; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; AVX512DQ-NEXT: # kill: def %ymm0 killed %ymm0 killed %zmm0
; AVX512DQ-NEXT: retq
%b = fptosi <4 x double> %a to <4 x i64>
ret <4 x i64> %b
Expand Down Expand Up @@ -238,9 +238,9 @@ define <4 x i64> @f32to4sl(<4 x float> %a) {
;
; AVX512DQ-LABEL: f32to4sl:
; AVX512DQ: # %bb.0:
; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; AVX512DQ-NEXT: # kill: def %xmm0 killed %xmm0 def %ymm0
; AVX512DQ-NEXT: vcvttps2qq %ymm0, %zmm0
; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; AVX512DQ-NEXT: # kill: def %ymm0 killed %ymm0 killed %zmm0
; AVX512DQ-NEXT: retq
%b = fptosi <4 x float> %a to <4 x i64>
ret <4 x i64> %b
Expand Down Expand Up @@ -272,9 +272,9 @@ define <4 x float> @slto4f32(<4 x i64> %a) {
;
; AVX512DQ-LABEL: slto4f32:
; AVX512DQ: # %bb.0:
; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; AVX512DQ-NEXT: # kill: def %ymm0 killed %ymm0 def %zmm0
; AVX512DQ-NEXT: vcvtqq2ps %zmm0, %ymm0
; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; AVX512DQ-NEXT: # kill: def %xmm0 killed %xmm0 killed %ymm0
; AVX512DQ-NEXT: vzeroupper
; AVX512DQ-NEXT: retq
%b = sitofp <4 x i64> %a to <4 x float>
Expand Down Expand Up @@ -307,9 +307,9 @@ define <4 x float> @ulto4f32(<4 x i64> %a) {
;
; AVX512DQ-LABEL: ulto4f32:
; AVX512DQ: # %bb.0:
; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; AVX512DQ-NEXT: # kill: def %ymm0 killed %ymm0 def %zmm0
; AVX512DQ-NEXT: vcvtuqq2ps %zmm0, %ymm0
; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; AVX512DQ-NEXT: # kill: def %xmm0 killed %xmm0 killed %ymm0
; AVX512DQ-NEXT: vzeroupper
; AVX512DQ-NEXT: retq
%b = uitofp <4 x i64> %a to <4 x float>
Expand Down Expand Up @@ -484,9 +484,9 @@ define <16 x i16> @f32to16us(<16 x float> %f) {
define <8 x i32> @f32to8ui(<8 x float> %a) nounwind {
; NOVL-LABEL: f32to8ui:
; NOVL: # %bb.0:
; NOVL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NOVL-NEXT: # kill: def %ymm0 killed %ymm0 def %zmm0
; NOVL-NEXT: vcvttps2udq %zmm0, %zmm0
; NOVL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; NOVL-NEXT: # kill: def %ymm0 killed %ymm0 killed %zmm0
; NOVL-NEXT: retq
;
; VL-LABEL: f32to8ui:
Expand All @@ -500,9 +500,9 @@ define <8 x i32> @f32to8ui(<8 x float> %a) nounwind {
define <4 x i32> @f32to4ui(<4 x float> %a) nounwind {
; NOVL-LABEL: f32to4ui:
; NOVL: # %bb.0:
; NOVL-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def>
; NOVL-NEXT: # kill: def %xmm0 killed %xmm0 def %zmm0
; NOVL-NEXT: vcvttps2udq %zmm0, %zmm0
; NOVL-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
; NOVL-NEXT: # kill: def %xmm0 killed %xmm0 killed %zmm0
; NOVL-NEXT: vzeroupper
; NOVL-NEXT: retq
;
Expand All @@ -528,7 +528,7 @@ define <8 x i16> @f64to8us(<8 x double> %f) {
; NOVL: # %bb.0:
; NOVL-NEXT: vcvttpd2dq %zmm0, %ymm0
; NOVL-NEXT: vpmovdw %zmm0, %ymm0
; NOVL-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; NOVL-NEXT: # kill: def %xmm0 killed %xmm0 killed %ymm0
; NOVL-NEXT: vzeroupper
; NOVL-NEXT: retq
;
Expand All @@ -547,7 +547,7 @@ define <8 x i8> @f64to8uc(<8 x double> %f) {
; NOVL: # %bb.0:
; NOVL-NEXT: vcvttpd2dq %zmm0, %ymm0
; NOVL-NEXT: vpmovdw %zmm0, %ymm0
; NOVL-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; NOVL-NEXT: # kill: def %xmm0 killed %xmm0 killed %ymm0
; NOVL-NEXT: vzeroupper
; NOVL-NEXT: retq
;
Expand All @@ -564,9 +564,9 @@ define <8 x i8> @f64to8uc(<8 x double> %f) {
define <4 x i32> @f64to4ui(<4 x double> %a) nounwind {
; NOVL-LABEL: f64to4ui:
; NOVL: # %bb.0:
; NOVL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NOVL-NEXT: # kill: def %ymm0 killed %ymm0 def %zmm0
; NOVL-NEXT: vcvttpd2udq %zmm0, %ymm0
; NOVL-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; NOVL-NEXT: # kill: def %xmm0 killed %xmm0 killed %ymm0
; NOVL-NEXT: vzeroupper
; NOVL-NEXT: retq
;
Expand Down Expand Up @@ -1287,9 +1287,9 @@ define <8 x double> @uito8f64_maskz(<8 x i32> %a, i8 %b) nounwind {
define <4 x double> @uito4f64(<4 x i32> %a) nounwind {
; NOVL-LABEL: uito4f64:
; NOVL: # %bb.0:
; NOVL-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def>
; NOVL-NEXT: # kill: def %xmm0 killed %xmm0 def %ymm0
; NOVL-NEXT: vcvtudq2pd %ymm0, %zmm0
; NOVL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; NOVL-NEXT: # kill: def %ymm0 killed %ymm0 killed %zmm0
; NOVL-NEXT: retq
;
; VL-LABEL: uito4f64:
Expand Down Expand Up @@ -1321,9 +1321,9 @@ define <8 x double> @uito8f64(<8 x i32> %a) {
define <8 x float> @uito8f32(<8 x i32> %a) nounwind {
; NOVL-LABEL: uito8f32:
; NOVL: # %bb.0:
; NOVL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NOVL-NEXT: # kill: def %ymm0 killed %ymm0 def %zmm0
; NOVL-NEXT: vcvtudq2ps %zmm0, %zmm0
; NOVL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; NOVL-NEXT: # kill: def %ymm0 killed %ymm0 killed %zmm0
; NOVL-NEXT: retq
;
; VL-LABEL: uito8f32:
Expand All @@ -1337,9 +1337,9 @@ define <8 x float> @uito8f32(<8 x i32> %a) nounwind {
define <4 x float> @uito4f32(<4 x i32> %a) nounwind {
; NOVL-LABEL: uito4f32:
; NOVL: # %bb.0:
; NOVL-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def>
; NOVL-NEXT: # kill: def %xmm0 killed %xmm0 def %zmm0
; NOVL-NEXT: vcvtudq2ps %zmm0, %zmm0
; NOVL-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
; NOVL-NEXT: # kill: def %xmm0 killed %xmm0 killed %zmm0
; NOVL-NEXT: vzeroupper
; NOVL-NEXT: retq
;
Expand Down Expand Up @@ -1553,7 +1553,7 @@ define <8 x double> @sbto8f64(<8 x double> %a) {
define <8 x float> @sbto8f32(<8 x float> %a) {
; NOVLDQ-LABEL: sbto8f32:
; NOVLDQ: # %bb.0:
; NOVLDQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NOVLDQ-NEXT: # kill: def %ymm0 killed %ymm0 def %zmm0
; NOVLDQ-NEXT: vxorps %xmm1, %xmm1, %xmm1
; NOVLDQ-NEXT: vcmpltps %zmm0, %zmm1, %k1
; NOVLDQ-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
Expand All @@ -1579,7 +1579,7 @@ define <8 x float> @sbto8f32(<8 x float> %a) {
;
; AVX512DQ-LABEL: sbto8f32:
; AVX512DQ: # %bb.0:
; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; AVX512DQ-NEXT: # kill: def %ymm0 killed %ymm0 def %zmm0
; AVX512DQ-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX512DQ-NEXT: vcmpltps %zmm0, %zmm1, %k0
; AVX512DQ-NEXT: vpmovm2d %k0, %zmm0
Expand Down Expand Up @@ -1885,7 +1885,7 @@ define <16 x double> @ubto16f64(<16 x i32> %a) {
define <8 x float> @ubto8f32(<8 x i32> %a) {
; NOVL-LABEL: ubto8f32:
; NOVL: # %bb.0:
; NOVL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NOVL-NEXT: # kill: def %ymm0 killed %ymm0 def %zmm0
; NOVL-NEXT: vpxor %xmm1, %xmm1, %xmm1
; NOVL-NEXT: vpcmpgtd %zmm0, %zmm1, %k1
; NOVL-NEXT: vpbroadcastd {{.*}}(%rip), %zmm0 {%k1} {z}
Expand All @@ -1907,7 +1907,7 @@ define <8 x float> @ubto8f32(<8 x i32> %a) {
define <8 x double> @ubto8f64(<8 x i32> %a) {
; NOVL-LABEL: ubto8f64:
; NOVL: # %bb.0:
; NOVL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
; NOVL-NEXT: # kill: def %ymm0 killed %ymm0 def %zmm0
; NOVL-NEXT: vpxor %xmm1, %xmm1, %xmm1
; NOVL-NEXT: vpcmpgtd %zmm0, %zmm1, %k1
; NOVL-NEXT: vpbroadcastd {{.*}}(%rip), %zmm0 {%k1} {z}
Expand Down
28 changes: 14 additions & 14 deletions llvm/test/CodeGen/X86/avx512-ext.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -348,7 +348,7 @@ define <8 x i32> @zext_8x8mem_to_8x32(<8 x i8> *%i , <8 x i1> %mask) nounwind re
; KNL-NEXT: vpmovzxbd {{.*#+}} ymm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero
; KNL-NEXT: vpxor %xmm0, %xmm0, %xmm0
; KNL-NEXT: vmovdqa32 %zmm1, %zmm0 {%k1}
; KNL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; KNL-NEXT: # kill: def %ymm0 killed %ymm0 killed %zmm0
; KNL-NEXT: retq
;
; SKX-LABEL: zext_8x8mem_to_8x32:
Expand All @@ -372,7 +372,7 @@ define <8 x i32> @sext_8x8mem_to_8x32(<8 x i8> *%i , <8 x i1> %mask) nounwind re
; KNL-NEXT: vpmovsxbd (%rdi), %ymm1
; KNL-NEXT: vpxor %xmm0, %xmm0, %xmm0
; KNL-NEXT: vmovdqa32 %zmm1, %zmm0 {%k1}
; KNL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; KNL-NEXT: # kill: def %ymm0 killed %ymm0 killed %zmm0
; KNL-NEXT: retq
;
; SKX-LABEL: sext_8x8mem_to_8x32:
Expand Down Expand Up @@ -705,7 +705,7 @@ define <8 x i32> @zext_8x16mem_to_8x32(<8 x i16> *%i , <8 x i1> %mask) nounwind
; KNL-NEXT: vpmovzxwd {{.*#+}} ymm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
; KNL-NEXT: vpxor %xmm0, %xmm0, %xmm0
; KNL-NEXT: vmovdqa32 %zmm1, %zmm0 {%k1}
; KNL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; KNL-NEXT: # kill: def %ymm0 killed %ymm0 killed %zmm0
; KNL-NEXT: retq
;
; SKX-LABEL: zext_8x16mem_to_8x32:
Expand All @@ -729,7 +729,7 @@ define <8 x i32> @sext_8x16mem_to_8x32mask(<8 x i16> *%i , <8 x i1> %mask) nounw
; KNL-NEXT: vpmovsxwd (%rdi), %ymm1
; KNL-NEXT: vpxor %xmm0, %xmm0, %xmm0
; KNL-NEXT: vmovdqa32 %zmm1, %zmm0 {%k1}
; KNL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; KNL-NEXT: # kill: def %ymm0 killed %ymm0 killed %zmm0
; KNL-NEXT: retq
;
; SKX-LABEL: sext_8x16mem_to_8x32mask:
Expand Down Expand Up @@ -763,7 +763,7 @@ define <8 x i32> @zext_8x16_to_8x32mask(<8 x i16> %a , <8 x i1> %mask) nounwind
; KNL-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; KNL-NEXT: vpxor %xmm0, %xmm0, %xmm0
; KNL-NEXT: vmovdqa32 %zmm1, %zmm0 {%k1}
; KNL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; KNL-NEXT: # kill: def %ymm0 killed %ymm0 killed %zmm0
; KNL-NEXT: retq
;
; SKX-LABEL: zext_8x16_to_8x32mask:
Expand Down Expand Up @@ -1328,15 +1328,15 @@ define i16 @trunc_16i8_to_16i1(<16 x i8> %a) {
; KNL-NEXT: vpslld $31, %zmm0, %zmm0
; KNL-NEXT: vptestmd %zmm0, %zmm0, %k0
; KNL-NEXT: kmovw %k0, %eax
; KNL-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; KNL-NEXT: # kill: def %ax killed %ax killed %eax
; KNL-NEXT: retq
;
; SKX-LABEL: trunc_16i8_to_16i1:
; SKX: # %bb.0:
; SKX-NEXT: vpsllw $7, %xmm0, %xmm0
; SKX-NEXT: vpmovb2m %xmm0, %k0
; SKX-NEXT: kmovd %k0, %eax
; SKX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; SKX-NEXT: # kill: def %ax killed %ax killed %eax
; SKX-NEXT: retq
%mask_b = trunc <16 x i8>%a to <16 x i1>
%mask = bitcast <16 x i1> %mask_b to i16
Expand All @@ -1349,15 +1349,15 @@ define i16 @trunc_16i32_to_16i1(<16 x i32> %a) {
; KNL-NEXT: vpslld $31, %zmm0, %zmm0
; KNL-NEXT: vptestmd %zmm0, %zmm0, %k0
; KNL-NEXT: kmovw %k0, %eax
; KNL-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; KNL-NEXT: # kill: def %ax killed %ax killed %eax
; KNL-NEXT: retq
;
; SKX-LABEL: trunc_16i32_to_16i1:
; SKX: # %bb.0:
; SKX-NEXT: vpslld $31, %zmm0, %zmm0
; SKX-NEXT: vptestmd %zmm0, %zmm0, %k0
; SKX-NEXT: kmovd %k0, %eax
; SKX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; SKX-NEXT: # kill: def %ax killed %ax killed %eax
; SKX-NEXT: vzeroupper
; SKX-NEXT: retq
%mask_b = trunc <16 x i32>%a to <16 x i1>
Expand Down Expand Up @@ -1396,15 +1396,15 @@ define i8 @trunc_8i16_to_8i1(<8 x i16> %a) {
; KNL-NEXT: vpsllq $63, %zmm0, %zmm0
; KNL-NEXT: vptestmq %zmm0, %zmm0, %k0
; KNL-NEXT: kmovw %k0, %eax
; KNL-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; KNL-NEXT: # kill: def %al killed %al killed %eax
; KNL-NEXT: retq
;
; SKX-LABEL: trunc_8i16_to_8i1:
; SKX: # %bb.0:
; SKX-NEXT: vpsllw $15, %xmm0, %xmm0
; SKX-NEXT: vpmovw2m %xmm0, %k0
; SKX-NEXT: kmovd %k0, %eax
; SKX-NEXT: # kill: %al<def> %al<kill> %eax<kill>
; SKX-NEXT: # kill: def %al killed %al killed %eax
; SKX-NEXT: retq
%mask_b = trunc <8 x i16>%a to <8 x i1>
%mask = bitcast <8 x i1> %mask_b to i8
Expand Down Expand Up @@ -1442,7 +1442,7 @@ define i16 @trunc_i32_to_i1(i32 %a) {
; KNL-NEXT: kmovw %edi, %k1
; KNL-NEXT: korw %k1, %k0, %k0
; KNL-NEXT: kmovw %k0, %eax
; KNL-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; KNL-NEXT: # kill: def %ax killed %ax killed %eax
; KNL-NEXT: retq
;
; SKX-LABEL: trunc_i32_to_i1:
Expand All @@ -1455,7 +1455,7 @@ define i16 @trunc_i32_to_i1(i32 %a) {
; SKX-NEXT: kmovw %edi, %k1
; SKX-NEXT: korw %k1, %k0, %k0
; SKX-NEXT: kmovd %k0, %eax
; SKX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill>
; SKX-NEXT: # kill: def %ax killed %ax killed %eax
; SKX-NEXT: retq
%a_i = trunc i32 %a to i1
%maskv = insertelement <16 x i1> <i1 true, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i1 %a_i, i32 0
Expand All @@ -1468,7 +1468,7 @@ define <8 x i16> @sext_8i1_8i16(<8 x i32> %a1, <8 x i32> %a2) nounwind {
; KNL: # %bb.0:
; KNL-NEXT: vpcmpgtd %ymm0, %ymm1, %ymm0
; KNL-NEXT: vpmovdw %zmm0, %ymm0
; KNL-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
; KNL-NEXT: # kill: def %xmm0 killed %xmm0 killed %ymm0
; KNL-NEXT: retq
;
; SKX-LABEL: sext_8i1_8i16:
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/X86/avx512-extract-subvector.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,7 @@ define <8 x i16> @extract_subvector128_v32i16(<32 x i16> %x) nounwind {
define <8 x i16> @extract_subvector128_v32i16_first_element(<32 x i16> %x) nounwind {
; SKX-LABEL: extract_subvector128_v32i16_first_element:
; SKX: ## %bb.0:
; SKX-NEXT: ## kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
; SKX-NEXT: ## kill: def %xmm0 killed %xmm0 killed %zmm0
; SKX-NEXT: vzeroupper
; SKX-NEXT: retq
%r1 = shufflevector <32 x i16> %x, <32 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
Expand All @@ -35,7 +35,7 @@ define <16 x i8> @extract_subvector128_v64i8(<64 x i8> %x) nounwind {
define <16 x i8> @extract_subvector128_v64i8_first_element(<64 x i8> %x) nounwind {
; SKX-LABEL: extract_subvector128_v64i8_first_element:
; SKX: ## %bb.0:
; SKX-NEXT: ## kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
; SKX-NEXT: ## kill: def %xmm0 killed %xmm0 killed %zmm0
; SKX-NEXT: vzeroupper
; SKX-NEXT: retq
%r1 = shufflevector <64 x i8> %x, <64 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
Expand Down
20 changes: 10 additions & 10 deletions llvm/test/CodeGen/X86/avx512-hadd-hsub.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -63,7 +63,7 @@ define float @fhadd_16(<16 x float> %x225) {
; KNL-NEXT: vaddps %zmm1, %zmm0, %zmm0
; KNL-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; KNL-NEXT: vaddps %zmm1, %zmm0, %zmm0
; KNL-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
; KNL-NEXT: # kill: def %xmm0 killed %xmm0 killed %zmm0
; KNL-NEXT: retq
;
; SKX-LABEL: fhadd_16:
Expand All @@ -72,7 +72,7 @@ define float @fhadd_16(<16 x float> %x225) {
; SKX-NEXT: vaddps %zmm1, %zmm0, %zmm0
; SKX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SKX-NEXT: vaddps %zmm1, %zmm0, %zmm0
; SKX-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
; SKX-NEXT: # kill: def %xmm0 killed %xmm0 killed %zmm0
; SKX-NEXT: vzeroupper
; SKX-NEXT: retq
%x226 = shufflevector <16 x float> %x225, <16 x float> undef, <16 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
Expand All @@ -90,7 +90,7 @@ define float @fhsub_16(<16 x float> %x225) {
; KNL-NEXT: vaddps %zmm1, %zmm0, %zmm0
; KNL-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; KNL-NEXT: vsubps %zmm1, %zmm0, %zmm0
; KNL-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
; KNL-NEXT: # kill: def %xmm0 killed %xmm0 killed %zmm0
; KNL-NEXT: retq
;
; SKX-LABEL: fhsub_16:
Expand All @@ -99,7 +99,7 @@ define float @fhsub_16(<16 x float> %x225) {
; SKX-NEXT: vaddps %zmm1, %zmm0, %zmm0
; SKX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SKX-NEXT: vsubps %zmm1, %zmm0, %zmm0
; SKX-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
; SKX-NEXT: # kill: def %xmm0 killed %xmm0 killed %zmm0
; SKX-NEXT: vzeroupper
; SKX-NEXT: retq
%x226 = shufflevector <16 x float> %x225, <16 x float> undef, <16 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
Expand Down Expand Up @@ -181,15 +181,15 @@ define <4 x double> @fadd_noundef_low(<8 x double> %x225, <8 x double> %x227) {
; KNL-NEXT: vunpcklpd {{.*#+}} zmm2 = zmm0[0],zmm1[0],zmm0[2],zmm1[2],zmm0[4],zmm1[4],zmm0[6],zmm1[6]
; KNL-NEXT: vunpckhpd {{.*#+}} zmm0 = zmm0[1],zmm1[1],zmm0[3],zmm1[3],zmm0[5],zmm1[5],zmm0[7],zmm1[7]
; KNL-NEXT: vaddpd %zmm0, %zmm2, %zmm0
; KNL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; KNL-NEXT: # kill: def %ymm0 killed %ymm0 killed %zmm0
; KNL-NEXT: retq
;
; SKX-LABEL: fadd_noundef_low:
; SKX: # %bb.0:
; SKX-NEXT: vunpcklpd {{.*#+}} zmm2 = zmm0[0],zmm1[0],zmm0[2],zmm1[2],zmm0[4],zmm1[4],zmm0[6],zmm1[6]
; SKX-NEXT: vunpckhpd {{.*#+}} zmm0 = zmm0[1],zmm1[1],zmm0[3],zmm1[3],zmm0[5],zmm1[5],zmm0[7],zmm1[7]
; SKX-NEXT: vaddpd %zmm0, %zmm2, %zmm0
; SKX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; SKX-NEXT: # kill: def %ymm0 killed %ymm0 killed %zmm0
; SKX-NEXT: retq
%x226 = shufflevector <8 x double> %x225, <8 x double> %x227, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
%x228 = shufflevector <8 x double> %x225, <8 x double> %x227, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5 ,i32 13, i32 7, i32 15>
Expand Down Expand Up @@ -228,15 +228,15 @@ define <8 x i32> @hadd_16_3_sv(<16 x i32> %x225, <16 x i32> %x227) {
; KNL-NEXT: vshufps {{.*#+}} zmm2 = zmm0[0,2],zmm1[0,2],zmm0[4,6],zmm1[4,6],zmm0[8,10],zmm1[8,10],zmm0[12,14],zmm1[12,14]
; KNL-NEXT: vshufps {{.*#+}} zmm0 = zmm0[1,3],zmm1[1,3],zmm0[5,7],zmm1[5,7],zmm0[9,11],zmm1[9,11],zmm0[13,15],zmm1[13,15]
; KNL-NEXT: vpaddd %zmm0, %zmm2, %zmm0
; KNL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; KNL-NEXT: # kill: def %ymm0 killed %ymm0 killed %zmm0
; KNL-NEXT: retq
;
; SKX-LABEL: hadd_16_3_sv:
; SKX: # %bb.0:
; SKX-NEXT: vshufps {{.*#+}} zmm2 = zmm0[0,2],zmm1[0,2],zmm0[4,6],zmm1[4,6],zmm0[8,10],zmm1[8,10],zmm0[12,14],zmm1[12,14]
; SKX-NEXT: vshufps {{.*#+}} zmm0 = zmm0[1,3],zmm1[1,3],zmm0[5,7],zmm1[5,7],zmm0[9,11],zmm1[9,11],zmm0[13,15],zmm1[13,15]
; SKX-NEXT: vpaddd %zmm0, %zmm2, %zmm0
; SKX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill>
; SKX-NEXT: # kill: def %ymm0 killed %ymm0 killed %zmm0
; SKX-NEXT: retq
%x226 = shufflevector <16 x i32> %x225, <16 x i32> %x227, <16 x i32> <i32 0, i32 2, i32 16, i32 18
, i32 4, i32 6, i32 20, i32 22, i32 8, i32 10, i32 24, i32 26, i32 12, i32 14, i32 28, i32 30>
Expand All @@ -255,15 +255,15 @@ define double @fadd_noundef_eel(<8 x double> %x225, <8 x double> %x227) {
; KNL-NEXT: vunpcklpd {{.*#+}} zmm2 = zmm0[0],zmm1[0],zmm0[2],zmm1[2],zmm0[4],zmm1[4],zmm0[6],zmm1[6]
; KNL-NEXT: vunpckhpd {{.*#+}} zmm0 = zmm0[1],zmm1[1],zmm0[3],zmm1[3],zmm0[5],zmm1[5],zmm0[7],zmm1[7]
; KNL-NEXT: vaddpd %zmm0, %zmm2, %zmm0
; KNL-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
; KNL-NEXT: # kill: def %xmm0 killed %xmm0 killed %zmm0
; KNL-NEXT: retq
;
; SKX-LABEL: fadd_noundef_eel:
; SKX: # %bb.0:
; SKX-NEXT: vunpcklpd {{.*#+}} zmm2 = zmm0[0],zmm1[0],zmm0[2],zmm1[2],zmm0[4],zmm1[4],zmm0[6],zmm1[6]
; SKX-NEXT: vunpckhpd {{.*#+}} zmm0 = zmm0[1],zmm1[1],zmm0[3],zmm1[3],zmm0[5],zmm1[5],zmm0[7],zmm1[7]
; SKX-NEXT: vaddpd %zmm0, %zmm2, %zmm0
; SKX-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill>
; SKX-NEXT: # kill: def %xmm0 killed %xmm0 killed %zmm0
; SKX-NEXT: vzeroupper
; SKX-NEXT: retq
%x226 = shufflevector <8 x double> %x225, <8 x double> %x227, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
Expand Down
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