8 changes: 4 additions & 4 deletions llvm/test/CodeGen/AMDGPU/fptoui.f16.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -387,14 +387,14 @@ define amdgpu_kernel void @fptoui_v2f16_to_v2i64(
; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0
; SI-NEXT: s_mov_b32 s4, s0
; SI-NEXT: s_mov_b32 s5, s1
; SI-NEXT: v_mov_b32_e32 v3, 0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
; SI-NEXT: v_cvt_u32_f32_e32 v0, v0
; SI-NEXT: v_cvt_u32_f32_e32 v2, v1
; SI-NEXT: v_mov_b32_e32 v1, 0
; SI-NEXT: v_mov_b32_e32 v3, v1
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; SI-NEXT: s_endpgm
;
Expand All @@ -411,13 +411,13 @@ define amdgpu_kernel void @fptoui_v2f16_to_v2i64(
; VI-NEXT: buffer_load_dword v0, off, s[8:11], 0
; VI-NEXT: s_mov_b32 s4, s0
; VI-NEXT: s_mov_b32 s5, s1
; VI-NEXT: v_mov_b32_e32 v3, 0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_cvt_f32_f16_e32 v1, v0
; VI-NEXT: v_cvt_f32_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; VI-NEXT: v_cvt_u32_f32_e32 v0, v1
; VI-NEXT: v_cvt_u32_f32_e32 v2, v2
; VI-NEXT: v_mov_b32_e32 v1, 0
; VI-NEXT: v_mov_b32_e32 v3, v1
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; VI-NEXT: s_endpgm
;
Expand All @@ -428,7 +428,6 @@ define amdgpu_kernel void @fptoui_v2f16_to_v2i64(
; GFX11-NEXT: s_mov_b32 s7, 0x31016000
; GFX11-NEXT: s_mov_b32 s10, s6
; GFX11-NEXT: s_mov_b32 s11, s7
; GFX11-NEXT: v_mov_b32_e32 v3, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s8, s2
; GFX11-NEXT: s_mov_b32 s9, s3
Expand All @@ -442,8 +441,9 @@ define amdgpu_kernel void @fptoui_v2f16_to_v2i64(
; GFX11-NEXT: v_cvt_f32_f16_e32 v2, v1
; GFX11-NEXT: v_mov_b32_e32 v1, 0
; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX11-NEXT: v_mov_b32_e32 v3, v1
; GFX11-NEXT: buffer_store_b128 v[0:3], off, s[4:7], 0
; GFX11-NEXT: s_nop 0
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
Expand Down
786 changes: 409 additions & 377 deletions llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx90a.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -163,7 +163,7 @@ bb:

; GCN-LABEL: {{^}}test_mfma_f64_16x16x4f64_splat_lit:
; GCN-DAG: v_accvgpr_write_b32 a{{[0-9]+}}, 0{{$}}
; GCN-DAG: s_mov_b32 s{{[0-9]+}}, 0x405ec000
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x405ec000
; GFX90A: v_mfma_f64_16x16x4f64 a[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], a[{{[0-9]+:[0-9]+}}]{{$}}
; GFX940: v_mfma_f64_16x16x4_f64 a[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], a[{{[0-9]+:[0-9]+}}]{{$}}
; GCN: global_store_dwordx4
Expand Down
6 changes: 2 additions & 4 deletions llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -595,8 +595,7 @@ bb:
}

; GCN-LABEL: {{^}}test_mfma_f32_4x4x1f32_lit_splat:
; GFX908: v_mov_b32_e32 [[TMP:v[0-9]+]], 0x42f60000
; GFX90A_40: s_mov_b32 [[TMP:s[0-9]+]], 0x42f60000
; GCN: v_mov_b32_e32 [[TMP:v[0-9]+]], 0x42f60000
; GCN: v_accvgpr_write_b32 [[TTMPA:a[0-9]+]], [[TMP]]
; GFX908: v_accvgpr_write_b32 a{{[0-9]+}}, [[TMP]]
; GFX908: v_accvgpr_write_b32 a{{[0-9]+}}, [[TMP]]
Expand All @@ -621,8 +620,7 @@ bb:
}

; GCN-LABEL: {{^}}test_mfma_f32_4x4x1f32_lit_splat_bad_code:
; GFX908: v_mov_b32_e32 [[TMP0:v[0-9]+]], 0x42f60000
; GFX90A_40:s_mov_b32 [[TMP0:s[0-9]+]], 0x42f60000
; GCN: v_mov_b32_e32 [[TMP0:v[0-9]+]], 0x42f60000
; GCN: v_accvgpr_write_b32 [[AGPR:a[0-9]+]], [[TMP0]]
; GFX90A_40-COUNT-3: v_accvgpr_mov_b32 a{{[0-9]+}}, [[AGPR]]
; GFX908-NEXT: v_accvgpr_write_b32 a{{[0-9]+}}, [[TMP0]]
Expand Down
1,190 changes: 584 additions & 606 deletions llvm/test/CodeGen/AMDGPU/llvm.exp.ll
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198 changes: 87 additions & 111 deletions llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
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120 changes: 72 additions & 48 deletions llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -228,19 +228,19 @@ define { <2 x half>, <2 x i32> } @test_frexp_v2f16_v2i32(<2 x half> %a) {
; GFX6-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX6-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX6-GISEL-NEXT: s_mov_b32 s4, 0x7f800000
; GFX6-GISEL-NEXT: v_frexp_mant_f32_e32 v3, v0
; GFX6-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
; GFX6-GISEL-NEXT: v_frexp_mant_f32_e32 v4, v0
; GFX6-GISEL-NEXT: v_frexp_exp_i32_f32_e32 v2, v0
; GFX6-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
; GFX6-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
; GFX6-GISEL-NEXT: v_frexp_mant_f32_e32 v4, v1
; GFX6-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s4
; GFX6-GISEL-NEXT: v_frexp_exp_i32_f32_e32 v3, v1
; GFX6-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v3
; GFX6-GISEL-NEXT: v_frexp_exp_i32_f32_e32 v5, v1
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX6-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX6-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v5, vcc
; GFX6-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-GISEL-LABEL: test_frexp_v2f16_v2i32:
Expand Down Expand Up @@ -320,13 +320,13 @@ define <2 x half> @test_frexp_v2f16_v2i32_only_use_fract(<2 x half> %a) {
; GFX6-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX6-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX6-GISEL-NEXT: s_mov_b32 s4, 0x7f800000
; GFX6-GISEL-NEXT: v_frexp_mant_f32_e32 v2, v0
; GFX6-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX6-GISEL-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX6-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s4
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX6-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
; GFX6-GISEL-NEXT: v_frexp_mant_f32_e32 v3, v0
; GFX6-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX6-GISEL-NEXT: v_frexp_mant_f32_e32 v3, v1
; GFX6-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v2
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX6-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX6-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1
; GFX6-GISEL-NEXT: s_setpc_b64 s[30:31]
Expand Down Expand Up @@ -395,13 +395,13 @@ define <2 x i32> @test_frexp_v2f16_v2i32_only_use_exp(<2 x half> %a) {
; GFX6-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX6-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX6-GISEL-NEXT: s_mov_b32 s4, 0x7f800000
; GFX6-GISEL-NEXT: v_frexp_exp_i32_f32_e32 v2, v0
; GFX6-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX6-GISEL-NEXT: v_frexp_exp_i32_f32_e32 v2, v1
; GFX6-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s4
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
; GFX6-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
; GFX6-GISEL-NEXT: v_frexp_exp_i32_f32_e32 v3, v0
; GFX6-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
; GFX6-GISEL-NEXT: v_frexp_exp_i32_f32_e32 v3, v1
; GFX6-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v2
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; GFX6-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-GISEL-LABEL: test_frexp_v2f16_v2i32_only_use_exp:
Expand Down Expand Up @@ -778,17 +778,17 @@ define { <2 x float>, <2 x i32> } @test_frexp_v2f32_v2i32(<2 x float> %a) {
; GFX6-GISEL-LABEL: test_frexp_v2f32_v2i32:
; GFX6-GISEL: ; %bb.0:
; GFX6-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-GISEL-NEXT: s_mov_b32 s4, 0x7f800000
; GFX6-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000
; GFX6-GISEL-NEXT: v_frexp_mant_f32_e32 v3, v0
; GFX6-GISEL-NEXT: v_frexp_exp_i32_f32_e32 v2, v0
; GFX6-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
; GFX6-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v4
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX6-GISEL-NEXT: v_frexp_mant_f32_e32 v4, v1
; GFX6-GISEL-NEXT: v_frexp_mant_f32_e32 v5, v1
; GFX6-GISEL-NEXT: v_frexp_exp_i32_f32_e32 v3, v1
; GFX6-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s4
; GFX6-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v4
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX6-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-GISEL-LABEL: test_frexp_v2f32_v2i32:
Expand Down Expand Up @@ -817,17 +817,17 @@ define { <2 x float>, <2 x i32> } @test_frexp_v2f32_v2i32(<2 x float> %a) {
}

define <2 x float> @test_frexp_v2f32_v2i32_only_use_fract(<2 x float> %a) {
; GFX6-LABEL: test_frexp_v2f32_v2i32_only_use_fract:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: s_mov_b32 s4, 0x7f800000
; GFX6-NEXT: v_frexp_mant_f32_e32 v2, v0
; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX6-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s4
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
; GFX6-SDAG-LABEL: test_frexp_v2f32_v2i32_only_use_fract:
; GFX6-SDAG: ; %bb.0:
; GFX6-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; GFX6-SDAG-NEXT: v_frexp_mant_f32_e32 v2, v0
; GFX6-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX6-SDAG-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX6-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s4
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX6-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_frexp_v2f32_v2i32_only_use_fract:
; GFX8: ; %bb.0:
Expand All @@ -849,23 +849,35 @@ define <2 x float> @test_frexp_v2f32_v2i32_only_use_fract(<2 x float> %a) {
; GFX11-NEXT: v_frexp_mant_f32_e32 v0, v0
; GFX11-NEXT: v_frexp_mant_f32_e32 v1, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-GISEL-LABEL: test_frexp_v2f32_v2i32_only_use_fract:
; GFX6-GISEL: ; %bb.0:
; GFX6-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
; GFX6-GISEL-NEXT: v_frexp_mant_f32_e32 v2, v0
; GFX6-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX6-GISEL-NEXT: v_frexp_mant_f32_e32 v2, v1
; GFX6-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v3
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX6-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float> %a)
%result.0 = extractvalue { <2 x float>, <2 x i32> } %result, 0
ret <2 x float> %result.0
}

define <2 x i32> @test_frexp_v2f32_v2i32_only_use_exp(<2 x float> %a) {
; GFX6-LABEL: test_frexp_v2f32_v2i32_only_use_exp:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: s_mov_b32 s4, 0x7f800000
; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v2, v0
; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX6-NEXT: v_frexp_exp_i32_f32_e32 v2, v1
; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s4
; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
; GFX6-SDAG-LABEL: test_frexp_v2f32_v2i32_only_use_exp:
; GFX6-SDAG: ; %bb.0:
; GFX6-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
; GFX6-SDAG-NEXT: v_frexp_exp_i32_f32_e32 v2, v0
; GFX6-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX6-SDAG-NEXT: v_frexp_exp_i32_f32_e32 v2, v1
; GFX6-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s4
; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
; GFX6-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_frexp_v2f32_v2i32_only_use_exp:
; GFX8: ; %bb.0:
Expand All @@ -887,6 +899,18 @@ define <2 x i32> @test_frexp_v2f32_v2i32_only_use_exp(<2 x float> %a) {
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v0, v0
; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v1, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX6-GISEL-LABEL: test_frexp_v2f32_v2i32_only_use_exp:
; GFX6-GISEL: ; %bb.0:
; GFX6-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
; GFX6-GISEL-NEXT: v_frexp_exp_i32_f32_e32 v2, v0
; GFX6-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX6-GISEL-NEXT: v_frexp_exp_i32_f32_e32 v2, v1
; GFX6-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v3
; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
; GFX6-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float> %a)
%result.1 = extractvalue { <2 x float>, <2 x i32> } %result, 1
ret <2 x i32> %result.1
Expand Down
118 changes: 59 additions & 59 deletions llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -894,9 +894,9 @@ define i1 @not_isnan_f16(half %x) {
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: s_movk_i32 s4, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, s4, v0
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], s4, v0
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v0, v1
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
Expand Down Expand Up @@ -954,12 +954,12 @@ define <2 x i1> @isnan_v2f16(<2 x half> %x) nounwind {
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: s_movk_i32 s4, 0x7c00
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v1
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s4, v0
; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v0, v2
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s4, v1
; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v1, v2
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
;
Expand Down Expand Up @@ -1032,16 +1032,16 @@ define <3 x i1> @isnan_v3f16(<3 x half> %x) nounwind {
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: s_movk_i32 s4, 0x7c00
; GFX7GLISEL-NEXT: v_mov_b32_e32 v3, 0x7c00
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v1
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX7GLISEL-NEXT: v_and_b32_e32 v2, 0x7fff, v2
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s4, v0
; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v0, v3
; GFX7GLISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s4, v1
; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v1, v3
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s4, v2
; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v2, v3
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
;
Expand Down Expand Up @@ -1180,20 +1180,20 @@ define <4 x i1> @isnan_v4f16(<4 x half> %x) nounwind {
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: s_movk_i32 s4, 0x7c00
; GFX7GLISEL-NEXT: v_mov_b32_e32 v4, 0x7c00
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v1
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX7GLISEL-NEXT: v_and_b32_e32 v2, 0x7fff, v2
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s4, v0
; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v0, v4
; GFX7GLISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX7GLISEL-NEXT: v_and_b32_e32 v3, 0x7fff, v3
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s4, v1
; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v1, v4
; GFX7GLISEL-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s4, v2
; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v2, v4
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s4, v3
; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v3, v4
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
;
Expand Down Expand Up @@ -1538,9 +1538,9 @@ define i1 @not_issubnormal_or_zero_f16(half %x) {
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v0
; GFX7GLISEL-NEXT: s_movk_i32 s4, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, s4, v1
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e64 s[4:5], s4, v1
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
; GFX7GLISEL-NEXT: v_cmp_gt_u32_e64 s[4:5], v1, v2
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0x400, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
Expand Down Expand Up @@ -1660,12 +1660,12 @@ define i1 @not_isnormal_f16(half %x) {
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7c00, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v1
; GFX7GLISEL-NEXT: s_movk_i32 s6, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], s6, v0
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v0, v2
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s6, v0
; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v0, v2
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
Expand Down Expand Up @@ -1724,19 +1724,19 @@ define i1 @not_is_plus_normal_f16(half %x) {
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v2, 0xffff, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7c00, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v3, 0xffff, v1
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7c00, v0
; GFX7GLISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], v2, v3
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: s_movk_i32 s8, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[6:7], s8, v3
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[6:7], v3, v2
; GFX7GLISEL-NEXT: s_or_b64 s[6:7], vcc, s[6:7]
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s8, v3
; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v3, v2
; GFX7GLISEL-NEXT: s_or_b64 s[6:7], s[6:7], vcc
; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0x400, v1
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7800
; GFX7GLISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], v2, v3
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
; GFX7GLISEL-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[6:7], s[4:5]
Expand Down Expand Up @@ -1797,19 +1797,19 @@ define i1 @not_is_neg_normal_f16(half %x) {
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v2, 0xffff, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7c00, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v3, 0xffff, v1
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7c00, v0
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v2, v3
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: s_movk_i32 s8, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[6:7], s8, v3
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[6:7], v3, v2
; GFX7GLISEL-NEXT: s_or_b64 s[6:7], vcc, s[6:7]
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s8, v3
; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v3, v2
; GFX7GLISEL-NEXT: s_or_b64 s[6:7], s[6:7], vcc
; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0x400, v1
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7800
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v2, v3
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
; GFX7GLISEL-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[6:7], s[4:5]
Expand Down Expand Up @@ -1922,11 +1922,11 @@ define i1 @not_issubnormal_f16(half %x) {
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v0
; GFX7GLISEL-NEXT: s_movk_i32 s6, 0x7c00
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], s6, v1
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v1, v2
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s6, v1
; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v1, v2
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0x400, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
Expand Down Expand Up @@ -2040,10 +2040,10 @@ define i1 @not_iszero_f16(half %x) {
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x3ff
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v1, v2
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v0
; GFX7GLISEL-NEXT: s_movk_i32 s6, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], s6, v1
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v1, v2
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s6, v1
; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v1, v2
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0x400, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
Expand Down Expand Up @@ -2100,9 +2100,9 @@ define i1 @ispositive_f16(half %x) {
; GFX7GLISEL: ; %bb.0:
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: s_movk_i32 s4, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, s4, v0
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], s4, v0
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v0, v1
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
Expand Down Expand Up @@ -2165,14 +2165,14 @@ define i1 @not_ispositive_f16(half %x) {
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX7GLISEL-NEXT: s_movk_i32 s6, 0x7c00
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1
; GFX7GLISEL-NEXT: v_cmp_gt_u32_e64 s[4:5], s6, v1
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0xfc00
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e64 s[4:5], v1, v2
; GFX7GLISEL-NEXT: v_mov_b32_e32 v3, 0xfc00
; GFX7GLISEL-NEXT: s_and_b64 s[4:5], s[4:5], vcc
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, v0, v2
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, v0, v3
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s6, v1
; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v1, v2
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
Expand Down Expand Up @@ -2291,12 +2291,12 @@ define i1 @not_isnegative_f16(half %x) {
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: s_movk_i32 s6, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, s6, v0
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], s6, v0
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v2
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v0, v2
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v1
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s6, v0
; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v0, v2
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
Expand Down Expand Up @@ -2870,11 +2870,11 @@ define i1 @not_iszero_or_qnan_f16(half %x) {
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x3ff
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v1, v2
; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v0
; GFX7GLISEL-NEXT: s_movk_i32 s8, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], s8, v1
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7e00
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v1, v2
; GFX7GLISEL-NEXT: s_or_b64 s[6:7], vcc, s[4:5]
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s8, v1
; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v1, v2
; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7e00
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e64 s[4:5], v1, v2
; GFX7GLISEL-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0x400, v0
Expand Down Expand Up @@ -3016,9 +3016,9 @@ define i1 @isinf_or_nan_f16(half %x) {
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: s_movk_i32 s4, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, s4, v0
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e64 s[4:5], s4, v0
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
; GFX7GLISEL-NEXT: v_cmp_gt_u32_e64 s[4:5], v0, v1
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
Expand Down Expand Up @@ -3128,9 +3128,9 @@ define i1 @isfinite_or_nan_f(half %x) {
; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX7GLISEL-NEXT: s_movk_i32 s4, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, s4, v0
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e64 s[4:5], s4, v0
; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
; GFX7GLISEL-NEXT: v_cmp_gt_u32_e64 s[4:5], v0, v1
; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
Expand Down
917 changes: 441 additions & 476 deletions llvm/test/CodeGen/AMDGPU/llvm.log.ll
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917 changes: 441 additions & 476 deletions llvm/test/CodeGen/AMDGPU/llvm.log10.ll
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198 changes: 87 additions & 111 deletions llvm/test/CodeGen/AMDGPU/llvm.log2.ll
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798 changes: 392 additions & 406 deletions llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
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902 changes: 458 additions & 444 deletions llvm/test/CodeGen/AMDGPU/load-global-i16.ll
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144 changes: 87 additions & 57 deletions llvm/test/CodeGen/AMDGPU/mad-mix.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -1030,15 +1030,15 @@ define float @v_mad_mix_f32_f16lo_f16lo_cvtf16imm63(half %src0, half %src1) #0 {
}

define <2 x float> @v_mad_mix_v2f32_f32imm1(<2 x half> %src0, <2 x half> %src1) #0 {
; GFX1100-LABEL: v_mad_mix_v2f32_f32imm1:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_mov_b32 s0, 1.0
; GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1100-NEXT: v_fma_mix_f32 v2, v0, v1, s0 op_sel_hi:[1,1,0]
; GFX1100-NEXT: v_fma_mix_f32 v1, v0, v1, s0 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; GFX1100-NEXT: v_mov_b32_e32 v0, v2
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; SDAG-GFX1100-LABEL: v_mad_mix_v2f32_f32imm1:
; SDAG-GFX1100: ; %bb.0:
; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SDAG-GFX1100-NEXT: s_mov_b32 s0, 1.0
; SDAG-GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; SDAG-GFX1100-NEXT: v_fma_mix_f32 v2, v0, v1, s0 op_sel_hi:[1,1,0]
; SDAG-GFX1100-NEXT: v_fma_mix_f32 v1, v0, v1, s0 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; SDAG-GFX1100-NEXT: v_mov_b32_e32 v0, v2
; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX900-LABEL: v_mad_mix_v2f32_f32imm1:
; SDAG-GFX900: ; %bb.0:
Expand Down Expand Up @@ -1084,21 +1084,31 @@ define <2 x float> @v_mad_mix_v2f32_f32imm1(<2 x half> %src0, <2 x half> %src1)
; SDAG-CI-NEXT: v_mad_f32 v1, v1, v3, 1.0
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX1100-LABEL: v_mad_mix_v2f32_f32imm1:
; GISEL-GFX1100: ; %bb.0:
; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX1100-NEXT: v_mov_b32_e32 v3, 1.0
; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GISEL-GFX1100-NEXT: v_fma_mix_f32 v2, v0, v1, v3 op_sel_hi:[1,1,0]
; GISEL-GFX1100-NEXT: v_fma_mix_f32 v1, v0, v1, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; GISEL-GFX1100-NEXT: v_mov_b32_e32 v0, v2
; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX900-LABEL: v_mad_mix_v2f32_f32imm1:
; GISEL-GFX900: ; %bb.0:
; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX900-NEXT: s_mov_b32 s4, 1.0
; GISEL-GFX900-NEXT: v_mad_mix_f32 v2, v0, v1, s4 op_sel_hi:[1,1,0]
; GISEL-GFX900-NEXT: v_mad_mix_f32 v1, v0, v1, s4 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; GISEL-GFX900-NEXT: v_mov_b32_e32 v3, 1.0
; GISEL-GFX900-NEXT: v_mad_mix_f32 v2, v0, v1, v3 op_sel_hi:[1,1,0]
; GISEL-GFX900-NEXT: v_mad_mix_f32 v1, v0, v1, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; GISEL-GFX900-NEXT: v_mov_b32_e32 v0, v2
; GISEL-GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX906-LABEL: v_mad_mix_v2f32_f32imm1:
; GISEL-GFX906: ; %bb.0:
; GISEL-GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX906-NEXT: s_mov_b32 s4, 1.0
; GISEL-GFX906-NEXT: v_fma_mix_f32 v2, v0, v1, s4 op_sel_hi:[1,1,0]
; GISEL-GFX906-NEXT: v_fma_mix_f32 v1, v0, v1, s4 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; GISEL-GFX906-NEXT: v_mov_b32_e32 v3, 1.0
; GISEL-GFX906-NEXT: v_fma_mix_f32 v2, v0, v1, v3 op_sel_hi:[1,1,0]
; GISEL-GFX906-NEXT: v_fma_mix_f32 v1, v0, v1, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; GISEL-GFX906-NEXT: v_mov_b32_e32 v0, v2
; GISEL-GFX906-NEXT: s_setpc_b64 s[30:31]
;
Expand Down Expand Up @@ -1130,15 +1140,15 @@ define <2 x float> @v_mad_mix_v2f32_f32imm1(<2 x half> %src0, <2 x half> %src1)
}

define <2 x float> @v_mad_mix_v2f32_cvtf16imminv2pi(<2 x half> %src0, <2 x half> %src1) #0 {
; GFX1100-LABEL: v_mad_mix_v2f32_cvtf16imminv2pi:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_mov_b32 s0, 0x3e230000
; GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1100-NEXT: v_fma_mix_f32 v2, v0, v1, s0 op_sel_hi:[1,1,0]
; GFX1100-NEXT: v_fma_mix_f32 v1, v0, v1, s0 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; GFX1100-NEXT: v_mov_b32_e32 v0, v2
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; SDAG-GFX1100-LABEL: v_mad_mix_v2f32_cvtf16imminv2pi:
; SDAG-GFX1100: ; %bb.0:
; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SDAG-GFX1100-NEXT: s_mov_b32 s0, 0x3e230000
; SDAG-GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; SDAG-GFX1100-NEXT: v_fma_mix_f32 v2, v0, v1, s0 op_sel_hi:[1,1,0]
; SDAG-GFX1100-NEXT: v_fma_mix_f32 v1, v0, v1, s0 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; SDAG-GFX1100-NEXT: v_mov_b32_e32 v0, v2
; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX900-LABEL: v_mad_mix_v2f32_cvtf16imminv2pi:
; SDAG-GFX900: ; %bb.0:
Expand Down Expand Up @@ -1186,21 +1196,31 @@ define <2 x float> @v_mad_mix_v2f32_cvtf16imminv2pi(<2 x half> %src0, <2 x half>
; SDAG-CI-NEXT: v_mac_f32_e32 v1, v4, v3
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX1100-LABEL: v_mad_mix_v2f32_cvtf16imminv2pi:
; GISEL-GFX1100: ; %bb.0:
; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX1100-NEXT: v_mov_b32_e32 v3, 0x3e230000
; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GISEL-GFX1100-NEXT: v_fma_mix_f32 v2, v0, v1, v3 op_sel_hi:[1,1,0]
; GISEL-GFX1100-NEXT: v_fma_mix_f32 v1, v0, v1, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; GISEL-GFX1100-NEXT: v_mov_b32_e32 v0, v2
; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX900-LABEL: v_mad_mix_v2f32_cvtf16imminv2pi:
; GISEL-GFX900: ; %bb.0:
; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX900-NEXT: s_mov_b32 s4, 0x3e230000
; GISEL-GFX900-NEXT: v_mad_mix_f32 v2, v0, v1, s4 op_sel_hi:[1,1,0]
; GISEL-GFX900-NEXT: v_mad_mix_f32 v1, v0, v1, s4 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; GISEL-GFX900-NEXT: v_mov_b32_e32 v3, 0x3e230000
; GISEL-GFX900-NEXT: v_mad_mix_f32 v2, v0, v1, v3 op_sel_hi:[1,1,0]
; GISEL-GFX900-NEXT: v_mad_mix_f32 v1, v0, v1, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; GISEL-GFX900-NEXT: v_mov_b32_e32 v0, v2
; GISEL-GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX906-LABEL: v_mad_mix_v2f32_cvtf16imminv2pi:
; GISEL-GFX906: ; %bb.0:
; GISEL-GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX906-NEXT: s_mov_b32 s4, 0x3e230000
; GISEL-GFX906-NEXT: v_fma_mix_f32 v2, v0, v1, s4 op_sel_hi:[1,1,0]
; GISEL-GFX906-NEXT: v_fma_mix_f32 v1, v0, v1, s4 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; GISEL-GFX906-NEXT: v_mov_b32_e32 v3, 0x3e230000
; GISEL-GFX906-NEXT: v_fma_mix_f32 v2, v0, v1, v3 op_sel_hi:[1,1,0]
; GISEL-GFX906-NEXT: v_fma_mix_f32 v1, v0, v1, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; GISEL-GFX906-NEXT: v_mov_b32_e32 v0, v2
; GISEL-GFX906-NEXT: s_setpc_b64 s[30:31]
;
Expand All @@ -1210,22 +1230,22 @@ define <2 x float> @v_mad_mix_v2f32_cvtf16imminv2pi(<2 x half> %src0, <2 x half>
; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v2, v0
; GISEL-VI-NEXT: v_cvt_f32_f16_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v0, v1
; GISEL-VI-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GISEL-VI-NEXT: s_mov_b32 s4, 0x3e230000
; GISEL-VI-NEXT: v_mad_f32 v0, v2, v0, s4
; GISEL-VI-NEXT: v_mad_f32 v1, v3, v1, s4
; GISEL-VI-NEXT: v_cvt_f32_f16_sdwa v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GISEL-VI-NEXT: v_mov_b32_e32 v1, 0x3e230000
; GISEL-VI-NEXT: v_madak_f32 v0, v2, v0, 0x3e230000
; GISEL-VI-NEXT: v_mac_f32_e32 v1, v3, v4
; GISEL-VI-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-CI-LABEL: v_mad_mix_v2f32_cvtf16imminv2pi:
; GISEL-CI: ; %bb.0:
; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v0, v0
; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1
; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v4, v1
; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v2, v2
; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v3, v3
; GISEL-CI-NEXT: s_mov_b32 s4, 0x3e230000
; GISEL-CI-NEXT: v_mad_f32 v0, v0, v2, s4
; GISEL-CI-NEXT: v_mad_f32 v1, v1, v3, s4
; GISEL-CI-NEXT: v_mov_b32_e32 v1, 0x3e230000
; GISEL-CI-NEXT: v_madak_f32 v0, v0, v2, 0x3e230000
; GISEL-CI-NEXT: v_mac_f32_e32 v1, v4, v3
; GISEL-CI-NEXT: s_setpc_b64 s[30:31]
%src0.ext = fpext <2 x half> %src0 to <2 x float>
%src1.ext = fpext <2 x half> %src1 to <2 x float>
Expand All @@ -1235,15 +1255,15 @@ define <2 x float> @v_mad_mix_v2f32_cvtf16imminv2pi(<2 x half> %src0, <2 x half>
}

define <2 x float> @v_mad_mix_v2f32_f32imminv2pi(<2 x half> %src0, <2 x half> %src1) #0 {
; GFX1100-LABEL: v_mad_mix_v2f32_f32imminv2pi:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_mov_b32 s0, 0.15915494
; GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1100-NEXT: v_fma_mix_f32 v2, v0, v1, s0 op_sel_hi:[1,1,0]
; GFX1100-NEXT: v_fma_mix_f32 v1, v0, v1, s0 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; GFX1100-NEXT: v_mov_b32_e32 v0, v2
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; SDAG-GFX1100-LABEL: v_mad_mix_v2f32_f32imminv2pi:
; SDAG-GFX1100: ; %bb.0:
; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SDAG-GFX1100-NEXT: s_mov_b32 s0, 0.15915494
; SDAG-GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; SDAG-GFX1100-NEXT: v_fma_mix_f32 v2, v0, v1, s0 op_sel_hi:[1,1,0]
; SDAG-GFX1100-NEXT: v_fma_mix_f32 v1, v0, v1, s0 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; SDAG-GFX1100-NEXT: v_mov_b32_e32 v0, v2
; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; SDAG-GFX900-LABEL: v_mad_mix_v2f32_f32imminv2pi:
; SDAG-GFX900: ; %bb.0:
Expand Down Expand Up @@ -1290,21 +1310,31 @@ define <2 x float> @v_mad_mix_v2f32_f32imminv2pi(<2 x half> %src0, <2 x half> %s
; SDAG-CI-NEXT: v_mac_f32_e32 v1, v4, v3
; SDAG-CI-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX1100-LABEL: v_mad_mix_v2f32_f32imminv2pi:
; GISEL-GFX1100: ; %bb.0:
; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX1100-NEXT: v_mov_b32_e32 v3, 0.15915494
; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GISEL-GFX1100-NEXT: v_fma_mix_f32 v2, v0, v1, v3 op_sel_hi:[1,1,0]
; GISEL-GFX1100-NEXT: v_fma_mix_f32 v1, v0, v1, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; GISEL-GFX1100-NEXT: v_mov_b32_e32 v0, v2
; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX900-LABEL: v_mad_mix_v2f32_f32imminv2pi:
; GISEL-GFX900: ; %bb.0:
; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX900-NEXT: s_mov_b32 s4, 0.15915494
; GISEL-GFX900-NEXT: v_mad_mix_f32 v2, v0, v1, s4 op_sel_hi:[1,1,0]
; GISEL-GFX900-NEXT: v_mad_mix_f32 v1, v0, v1, s4 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; GISEL-GFX900-NEXT: v_mov_b32_e32 v3, 0.15915494
; GISEL-GFX900-NEXT: v_mad_mix_f32 v2, v0, v1, v3 op_sel_hi:[1,1,0]
; GISEL-GFX900-NEXT: v_mad_mix_f32 v1, v0, v1, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; GISEL-GFX900-NEXT: v_mov_b32_e32 v0, v2
; GISEL-GFX900-NEXT: s_setpc_b64 s[30:31]
;
; GISEL-GFX906-LABEL: v_mad_mix_v2f32_f32imminv2pi:
; GISEL-GFX906: ; %bb.0:
; GISEL-GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-GFX906-NEXT: s_mov_b32 s4, 0.15915494
; GISEL-GFX906-NEXT: v_fma_mix_f32 v2, v0, v1, s4 op_sel_hi:[1,1,0]
; GISEL-GFX906-NEXT: v_fma_mix_f32 v1, v0, v1, s4 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; GISEL-GFX906-NEXT: v_mov_b32_e32 v3, 0.15915494
; GISEL-GFX906-NEXT: v_fma_mix_f32 v2, v0, v1, v3 op_sel_hi:[1,1,0]
; GISEL-GFX906-NEXT: v_fma_mix_f32 v1, v0, v1, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0]
; GISEL-GFX906-NEXT: v_mov_b32_e32 v0, v2
; GISEL-GFX906-NEXT: s_setpc_b64 s[30:31]
;
Expand All @@ -1323,12 +1353,12 @@ define <2 x float> @v_mad_mix_v2f32_f32imminv2pi(<2 x half> %src0, <2 x half> %s
; GISEL-CI: ; %bb.0:
; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v0, v0
; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1
; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v4, v1
; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v2, v2
; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v3, v3
; GISEL-CI-NEXT: s_mov_b32 s4, 0x3e22f983
; GISEL-CI-NEXT: v_mad_f32 v0, v0, v2, s4
; GISEL-CI-NEXT: v_mad_f32 v1, v1, v3, s4
; GISEL-CI-NEXT: v_mov_b32_e32 v1, 0x3e22f983
; GISEL-CI-NEXT: v_madak_f32 v0, v0, v2, 0x3e22f983
; GISEL-CI-NEXT: v_mac_f32_e32 v1, v4, v3
; GISEL-CI-NEXT: s_setpc_b64 s[30:31]
%src0.ext = fpext <2 x half> %src0 to <2 x float>
%src1.ext = fpext <2 x half> %src1 to <2 x float>
Expand Down
3 changes: 1 addition & 2 deletions llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2465,8 +2465,7 @@ define hidden amdgpu_kernel void @negativeoffset(ptr addrspace(1) nocapture %buf
; GFX9-NEXT: v_lshlrev_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v0
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
; GFX9-NEXT: s_movk_i32 s0, 0x1000
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v2
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v2
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v3, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 0, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, -1, v3, vcc
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/remat-fp64-constants.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,8 +3,8 @@

; GCN-LABEL: {{^}}test_remat_sgpr:
; GCN-NOT: v_writelane_b32
; GCN: {{^}}[[LOOP:.LBB[0-9_]+]]:
; GCN-COUNT-6: s_mov_b32 s{{[0-9]+}}, 0x
; GCN: {{^}}[[LOOP:.LBB[0-9_]+]]:
; GCN-NOT: v_writelane_b32
; GCN: s_cbranch_{{[^ ]+}} [[LOOP]]
; GCN: .sgpr_spill_count: 0
Expand Down
33 changes: 14 additions & 19 deletions llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2591,11 +2591,10 @@ define amdgpu_kernel void @v_test_v2i16_x_add_neg32_neg32(ptr addrspace(1) %out,
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; SI-GISEL-NEXT: s_mov_b64 s[4:5], s[2:3]
; SI-GISEL-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
; SI-GISEL-NEXT: s_movk_i32 s2, 0xffe0
; SI-GISEL-NEXT: s_waitcnt vmcnt(0)
; SI-GISEL-NEXT: v_lshrrev_b32_e32 v3, 16, v2
; SI-GISEL-NEXT: v_add_i32_e32 v2, vcc, s2, v2
; SI-GISEL-NEXT: v_add_i32_e32 v3, vcc, s2, v3
; SI-GISEL-NEXT: v_add_i32_e32 v2, vcc, 0xffffffe0, v2
; SI-GISEL-NEXT: v_add_i32_e32 v3, vcc, 0xffffffe0, v3
; SI-GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-GISEL-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-GISEL-NEXT: v_lshlrev_b32_e32 v3, 16, v3
Expand Down Expand Up @@ -3554,11 +3553,10 @@ define amdgpu_kernel void @v_test_v2i16_x_add_neg_fpone(ptr addrspace(1) %out, p
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; SI-GISEL-NEXT: s_mov_b64 s[4:5], s[2:3]
; SI-GISEL-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
; SI-GISEL-NEXT: s_movk_i32 s2, 0xc400
; SI-GISEL-NEXT: s_waitcnt vmcnt(0)
; SI-GISEL-NEXT: v_lshrrev_b32_e32 v3, 16, v2
; SI-GISEL-NEXT: v_add_i32_e32 v2, vcc, s2, v2
; SI-GISEL-NEXT: v_add_i32_e32 v3, vcc, s2, v3
; SI-GISEL-NEXT: v_add_i32_e32 v2, vcc, 0xffffc400, v2
; SI-GISEL-NEXT: v_add_i32_e32 v3, vcc, 0xffffc400, v3
; SI-GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-GISEL-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-GISEL-NEXT: v_lshlrev_b32_e32 v3, 16, v3
Expand Down Expand Up @@ -3720,11 +3718,10 @@ define amdgpu_kernel void @v_test_v2i16_x_add_neg_negfpone(ptr addrspace(1) %out
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; SI-GISEL-NEXT: s_mov_b64 s[4:5], s[2:3]
; SI-GISEL-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
; SI-GISEL-NEXT: s_movk_i32 s2, 0x4400
; SI-GISEL-NEXT: s_waitcnt vmcnt(0)
; SI-GISEL-NEXT: v_lshrrev_b32_e32 v3, 16, v2
; SI-GISEL-NEXT: v_add_i32_e32 v2, vcc, s2, v2
; SI-GISEL-NEXT: v_add_i32_e32 v3, vcc, s2, v3
; SI-GISEL-NEXT: v_add_i32_e32 v2, vcc, 0x4400, v2
; SI-GISEL-NEXT: v_add_i32_e32 v3, vcc, 0x4400, v3
; SI-GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-GISEL-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-GISEL-NEXT: v_lshlrev_b32_e32 v3, 16, v3
Expand Down Expand Up @@ -3886,11 +3883,10 @@ define amdgpu_kernel void @v_test_v2i16_x_add_neg_fptwo(ptr addrspace(1) %out, p
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; SI-GISEL-NEXT: s_mov_b64 s[4:5], s[2:3]
; SI-GISEL-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
; SI-GISEL-NEXT: s_movk_i32 s2, 0x4000
; SI-GISEL-NEXT: s_waitcnt vmcnt(0)
; SI-GISEL-NEXT: v_lshrrev_b32_e32 v3, 16, v2
; SI-GISEL-NEXT: v_add_i32_e32 v2, vcc, s2, v2
; SI-GISEL-NEXT: v_add_i32_e32 v3, vcc, s2, v3
; SI-GISEL-NEXT: v_add_i32_e32 v2, vcc, 0x4000, v2
; SI-GISEL-NEXT: v_add_i32_e32 v3, vcc, 0x4000, v3
; SI-GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-GISEL-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-GISEL-NEXT: v_lshlrev_b32_e32 v3, 16, v3
Expand Down Expand Up @@ -4052,11 +4048,10 @@ define amdgpu_kernel void @v_test_v2i16_x_add_neg_negfptwo(ptr addrspace(1) %out
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; SI-GISEL-NEXT: s_mov_b64 s[4:5], s[2:3]
; SI-GISEL-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
; SI-GISEL-NEXT: s_movk_i32 s2, 0xc000
; SI-GISEL-NEXT: s_waitcnt vmcnt(0)
; SI-GISEL-NEXT: v_lshrrev_b32_e32 v3, 16, v2
; SI-GISEL-NEXT: v_add_i32_e32 v2, vcc, s2, v2
; SI-GISEL-NEXT: v_add_i32_e32 v3, vcc, s2, v3
; SI-GISEL-NEXT: v_add_i32_e32 v2, vcc, 0xffffc000, v2
; SI-GISEL-NEXT: v_add_i32_e32 v3, vcc, 0xffffc000, v3
; SI-GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2
; SI-GISEL-NEXT: v_and_b32_e32 v3, 0xffff, v3
; SI-GISEL-NEXT: v_lshlrev_b32_e32 v3, 16, v3
Expand Down Expand Up @@ -4280,11 +4275,11 @@ define amdgpu_kernel void @v_test_v2i16_x_add_undef_neg32(ptr addrspace(1) %out,
; GFX9-GISEL: ; %bb.0:
; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0xffe00000
; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-GISEL-NEXT: global_load_dword v1, v0, s[2:3]
; GFX9-GISEL-NEXT: s_mov_b32 s2, 0xffe00000
; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX9-GISEL-NEXT: v_pk_add_u16 v1, v1, s2
; GFX9-GISEL-NEXT: v_pk_add_u16 v1, v1, v2
; GFX9-GISEL-NEXT: global_store_dword v0, v1, s[0:1]
; GFX9-GISEL-NEXT: s_endpgm
;
Expand All @@ -4306,7 +4301,7 @@ define amdgpu_kernel void @v_test_v2i16_x_add_undef_neg32(ptr addrspace(1) %out,
; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-GISEL-NEXT: global_load_dword v1, v0, s[2:3]
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX10-GISEL-NEXT: v_pk_add_u16 v1, v1, 0xffe0 op_sel:[0,1] op_sel_hi:[1,0]
; GFX10-GISEL-NEXT: v_pk_add_u16 v1, 0xffe0, v1 op_sel:[1,0] op_sel_hi:[0,1]
; GFX10-GISEL-NEXT: global_store_dword v0, v1, s[0:1]
; GFX10-GISEL-NEXT: s_endpgm
;
Expand All @@ -4330,7 +4325,7 @@ define amdgpu_kernel void @v_test_v2i16_x_add_undef_neg32(ptr addrspace(1) %out,
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: global_load_b32 v1, v0, s[2:3]
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX11-GISEL-NEXT: v_pk_add_u16 v1, v1, 0xffe0 op_sel:[0,1] op_sel_hi:[1,0]
; GFX11-GISEL-NEXT: v_pk_add_u16 v1, 0xffe0, v1 op_sel:[1,0] op_sel_hi:[0,1]
; GFX11-GISEL-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX11-GISEL-NEXT: s_nop 0
; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -50,8 +50,8 @@ define <2 x i16> @basic_smax_smin(i16 %src0, i16 %src1) {
; GISEL-VI: ; %bb.0:
; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-VI-NEXT: v_max_i16_e32 v0, 0, v0
; GISEL-VI-NEXT: v_max_i16_e32 v1, 0, v1
; GISEL-VI-NEXT: v_mov_b32_e32 v2, 0xff
; GISEL-VI-NEXT: v_max_i16_e32 v1, 0, v1
; GISEL-VI-NEXT: v_min_i16_e32 v0, 0xff, v0
; GISEL-VI-NEXT: v_min_i16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GISEL-VI-NEXT: v_or_b32_e32 v0, v0, v1
Expand Down Expand Up @@ -312,9 +312,9 @@ define <2 x i16> @basic_smin_smax_combined(i16 %src0, i16 %src1) {
; GISEL-VI-LABEL: basic_smin_smax_combined:
; GISEL-VI: ; %bb.0:
; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-VI-NEXT: v_mov_b32_e32 v2, 0xff
; GISEL-VI-NEXT: v_min_i16_e32 v0, 0xff, v0
; GISEL-VI-NEXT: v_max_i16_e32 v1, 0, v1
; GISEL-VI-NEXT: v_mov_b32_e32 v2, 0xff
; GISEL-VI-NEXT: v_max_i16_e32 v0, 0, v0
; GISEL-VI-NEXT: v_min_i16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GISEL-VI-NEXT: v_or_b32_e32 v0, v0, v1
Expand Down Expand Up @@ -559,11 +559,11 @@ define <2 x i16> @vec_smin_smax(<2 x i16> %src) {
; GISEL-VI-LABEL: vec_smin_smax:
; GISEL-VI: ; %bb.0:
; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-VI-NEXT: v_mov_b32_e32 v2, 0xff
; GISEL-VI-NEXT: v_min_i16_e32 v1, 0xff, v0
; GISEL-VI-NEXT: v_min_i16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GISEL-VI-NEXT: v_mov_b32_e32 v1, 0xff
; GISEL-VI-NEXT: v_min_i16_e32 v2, 0xff, v0
; GISEL-VI-NEXT: v_min_i16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GISEL-VI-NEXT: v_max_i16_e32 v1, 0, v2
; GISEL-VI-NEXT: v_mov_b32_e32 v2, 0
; GISEL-VI-NEXT: v_max_i16_e32 v1, 0, v1
; GISEL-VI-NEXT: v_max_i16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GISEL-VI-NEXT: v_or_b32_e32 v0, v1, v0
; GISEL-VI-NEXT: s_setpc_b64 s[30:31]
Expand Down