48 changes: 24 additions & 24 deletions llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -102,9 +102,9 @@ def V2Write_2cyc_1M0 : SchedWriteRes<[V2UnitM0]> { let Latency = 2; }
def V2Write_3cyc_1M0 : SchedWriteRes<[V2UnitM0]> { let Latency = 3; }
def V2Write_5cyc_1M0 : SchedWriteRes<[V2UnitM0]> { let Latency = 5; }
def V2Write_12cyc_1M0 : SchedWriteRes<[V2UnitM0]> { let Latency = 12;
let ResourceCycles = [12]; }
let ReleaseAtCycles = [12]; }
def V2Write_20cyc_1M0 : SchedWriteRes<[V2UnitM0]> { let Latency = 20;
let ResourceCycles = [20]; }
let ReleaseAtCycles = [20]; }
def V2Write_4cyc_1L : SchedWriteRes<[V2UnitL]> { let Latency = 4; }
def V2Write_6cyc_1L : SchedWriteRes<[V2UnitL]> { let Latency = 6; }
def V2Write_2cyc_1V : SchedWriteRes<[V2UnitV]> { let Latency = 2; }
Expand All @@ -113,7 +113,7 @@ def V2Write_2cyc_1V01 : SchedWriteRes<[V2UnitV01]> { let Latency = 2; }
def V2Write_2cyc_1V23 : SchedWriteRes<[V2UnitV23]> { let Latency = 2; }
def V2Write_3cyc_1V : SchedWriteRes<[V2UnitV]> { let Latency = 3; }
def V2Write_3cyc_1V01 : SchedWriteRes<[V2UnitV01]> { let Latency = 3;
let ResourceCycles = [2]; }
let ReleaseAtCycles = [2]; }
def V2Write_3cyc_1V23 : SchedWriteRes<[V2UnitV23]> { let Latency = 3; }
def V2Write_4cyc_1V : SchedWriteRes<[V2UnitV]> { let Latency = 4; }
def V2Write_5cyc_1V : SchedWriteRes<[V2UnitV]> { let Latency = 5; }
Expand All @@ -124,26 +124,26 @@ def V2Write_3cyc_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 3; }
def V2Write_4cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 4; }
def V2Write_4cyc_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 4; }
def V2Write_7cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 7;
let ResourceCycles = [7]; }
let ReleaseAtCycles = [7]; }
def V2Write_7cyc_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 7;
let ResourceCycles = [2]; }
let ReleaseAtCycles = [2]; }
def V2Write_9cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 9; }
def V2Write_9cyc_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 9;
let ResourceCycles = [2]; }
let ReleaseAtCycles = [2]; }
def V2Write_10cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 10; }
def V2Write_10cyc_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 10;
let ResourceCycles = [2]; }
let ReleaseAtCycles = [2]; }
def V2Write_12cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 12;
let ResourceCycles = [11]; }
let ReleaseAtCycles = [11]; }
def V2Write_13cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 13; }
def V2Write_15cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 15; }
def V2Write_15cyc_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 15;
let ResourceCycles = [8]; }
let ReleaseAtCycles = [8]; }
def V2Write_16cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 16; }
def V2Write_16cyc_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 16;
let ResourceCycles = [8]; }
let ReleaseAtCycles = [8]; }
def V2Write_20cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 20;
let ResourceCycles = [20]; }
let ReleaseAtCycles = [20]; }
def V2Write_2cyc_1V1 : SchedWriteRes<[V2UnitV1]> { let Latency = 2; }
def V2Write_2cyc_1V13 : SchedWriteRes<[V2UnitV13]> { let Latency = 2; }
def V2Write_3cyc_1V1 : SchedWriteRes<[V2UnitV1]> { let Latency = 3; }
Expand Down Expand Up @@ -1054,19 +1054,19 @@ def V2Rd_ZBFMAL : SchedReadAdvance<3, [V2Wr_ZBFMAL]>;
//===----------------------------------------------------------------------===//
// Define types with long resource cycles (rc)

def V2Write_6cyc_1V1_5rc : SchedWriteRes<[V2UnitV1]> { let Latency = 6; let ResourceCycles = [ 5]; }
def V2Write_7cyc_1V02_7rc : SchedWriteRes<[V2UnitV02]> { let Latency = 7; let ResourceCycles = [ 7]; }
def V2Write_10cyc_1V02_5rc : SchedWriteRes<[V2UnitV02]> { let Latency = 10; let ResourceCycles = [ 5]; }
def V2Write_10cyc_1V02_9rc : SchedWriteRes<[V2UnitV02]> { let Latency = 10; let ResourceCycles = [ 9]; }
def V2Write_10cyc_1V02_10rc : SchedWriteRes<[V2UnitV02]> { let Latency = 10; let ResourceCycles = [10]; }
def V2Write_10cyc_1V0_9rc : SchedWriteRes<[V2UnitV0]> { let Latency = 10; let ResourceCycles = [ 9]; }
def V2Write_10cyc_1V1_9rc : SchedWriteRes<[V2UnitV1]> { let Latency = 10; let ResourceCycles = [ 9]; }
def V2Write_13cyc_1V0_12rc : SchedWriteRes<[V2UnitV0]> { let Latency = 13; let ResourceCycles = [12]; }
def V2Write_13cyc_1V02_12rc : SchedWriteRes<[V2UnitV02]> { let Latency = 13; let ResourceCycles = [12]; }
def V2Write_13cyc_1V02_13rc : SchedWriteRes<[V2UnitV02]> { let Latency = 13; let ResourceCycles = [13]; }
def V2Write_15cyc_1V02_14rc : SchedWriteRes<[V2UnitV02]> { let Latency = 15; let ResourceCycles = [14]; }
def V2Write_16cyc_1V02_15rc : SchedWriteRes<[V2UnitV02]> { let Latency = 16; let ResourceCycles = [15]; }
def V2Write_16cyc_1V0_14rc : SchedWriteRes<[V2UnitV0]> { let Latency = 16; let ResourceCycles = [14]; }
def V2Write_6cyc_1V1_5rc : SchedWriteRes<[V2UnitV1]> { let Latency = 6; let ReleaseAtCycles = [ 5]; }
def V2Write_7cyc_1V02_7rc : SchedWriteRes<[V2UnitV02]> { let Latency = 7; let ReleaseAtCycles = [ 7]; }
def V2Write_10cyc_1V02_5rc : SchedWriteRes<[V2UnitV02]> { let Latency = 10; let ReleaseAtCycles = [ 5]; }
def V2Write_10cyc_1V02_9rc : SchedWriteRes<[V2UnitV02]> { let Latency = 10; let ReleaseAtCycles = [ 9]; }
def V2Write_10cyc_1V02_10rc : SchedWriteRes<[V2UnitV02]> { let Latency = 10; let ReleaseAtCycles = [10]; }
def V2Write_10cyc_1V0_9rc : SchedWriteRes<[V2UnitV0]> { let Latency = 10; let ReleaseAtCycles = [ 9]; }
def V2Write_10cyc_1V1_9rc : SchedWriteRes<[V2UnitV1]> { let Latency = 10; let ReleaseAtCycles = [ 9]; }
def V2Write_13cyc_1V0_12rc : SchedWriteRes<[V2UnitV0]> { let Latency = 13; let ReleaseAtCycles = [12]; }
def V2Write_13cyc_1V02_12rc : SchedWriteRes<[V2UnitV02]> { let Latency = 13; let ReleaseAtCycles = [12]; }
def V2Write_13cyc_1V02_13rc : SchedWriteRes<[V2UnitV02]> { let Latency = 13; let ReleaseAtCycles = [13]; }
def V2Write_15cyc_1V02_14rc : SchedWriteRes<[V2UnitV02]> { let Latency = 15; let ReleaseAtCycles = [14]; }
def V2Write_16cyc_1V02_15rc : SchedWriteRes<[V2UnitV02]> { let Latency = 16; let ReleaseAtCycles = [15]; }
def V2Write_16cyc_1V0_14rc : SchedWriteRes<[V2UnitV0]> { let Latency = 16; let ReleaseAtCycles = [14]; }

// Miscellaneous
// -----------------------------------------------------------------------------
Expand Down
28 changes: 14 additions & 14 deletions llvm/lib/Target/AArch64/AArch64SchedTSV110.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -66,9 +66,9 @@ def : WriteRes<WriteIS, [TSV110UnitALUAB]> { let Latency = 1; }

// Integer Mul/MAC/Div
def : WriteRes<WriteID32, [TSV110UnitMDU]> { let Latency = 12;
let ResourceCycles = [12]; }
let ReleaseAtCycles = [12]; }
def : WriteRes<WriteID64, [TSV110UnitMDU]> { let Latency = 20;
let ResourceCycles = [20]; }
let ReleaseAtCycles = [20]; }
def : WriteRes<WriteIM32, [TSV110UnitMDU]> { let Latency = 3; }
def : WriteRes<WriteIM64, [TSV110UnitMDU]> { let Latency = 4; }

Expand All @@ -94,7 +94,7 @@ def : WriteRes<WriteFImm, [TSV110UnitF]> { let Latency = 2; }
def : WriteRes<WriteFMul, [TSV110UnitF]> { let Latency = 5; }

// FP Div, Sqrt
def : WriteRes<WriteFDiv, [TSV110UnitFSU1]> { let Latency = 18; let ResourceCycles = [18]; }
def : WriteRes<WriteFDiv, [TSV110UnitFSU1]> { let Latency = 18; let ReleaseAtCycles = [18]; }

def : WriteRes<WriteVd, [TSV110UnitF]> { let Latency = 4; }
def : WriteRes<WriteVq, [TSV110UnitF]> { let Latency = 4; }
Expand Down Expand Up @@ -146,7 +146,7 @@ def TSV110Wr_1cyc_1ALU : SchedWriteRes<[TSV110UnitALU]> { let Latency = 1; }
def TSV110Wr_1cyc_1ALUAB : SchedWriteRes<[TSV110UnitALUAB]> { let Latency = 1; }
def TSV110Wr_1cyc_1LdSt : SchedWriteRes<[TSV110UnitLd0St]> { let Latency = 1; }

def TSV110Wr_2cyc_1AB : SchedWriteRes<[TSV110UnitAB]> { let Latency = 2; let ResourceCycles = [2]; }
def TSV110Wr_2cyc_1AB : SchedWriteRes<[TSV110UnitAB]> { let Latency = 2; let ReleaseAtCycles = [2]; }
def TSV110Wr_2cyc_1ALU : SchedWriteRes<[TSV110UnitALU]> { let Latency = 2; }
def TSV110Wr_2cyc_1MDU : SchedWriteRes<[TSV110UnitMDU]> { let Latency = 2; }
def TSV110Wr_2cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 2; }
Expand All @@ -172,25 +172,25 @@ def TSV110Wr_7cyc_1F : SchedWriteRes<[TSV110UnitF]> { let Latency = 7; }

def TSV110Wr_8cyc_1F : SchedWriteRes<[TSV110UnitF]> { let Latency = 8; }

def TSV110Wr_11cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 11; let ResourceCycles = [11]; }
def TSV110Wr_11cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 11; let ReleaseAtCycles = [11]; }

def TSV110Wr_12cyc_1MDU : SchedWriteRes<[TSV110UnitMDU]> { let Latency = 12; let ResourceCycles = [12]; }
def TSV110Wr_12cyc_1MDU : SchedWriteRes<[TSV110UnitMDU]> { let Latency = 12; let ReleaseAtCycles = [12]; }

def TSV110Wr_17cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]> { let Latency = 17; let ResourceCycles = [17]; }
def TSV110Wr_17cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]> { let Latency = 17; let ReleaseAtCycles = [17]; }

def TSV110Wr_18cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 18; let ResourceCycles = [18]; }
def TSV110Wr_18cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 18; let ReleaseAtCycles = [18]; }

def TSV110Wr_20cyc_1MDU : SchedWriteRes<[TSV110UnitMDU]> { let Latency = 20; let ResourceCycles = [20]; }
def TSV110Wr_20cyc_1MDU : SchedWriteRes<[TSV110UnitMDU]> { let Latency = 20; let ReleaseAtCycles = [20]; }

def TSV110Wr_24cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 24; let ResourceCycles = [24]; }
def TSV110Wr_24cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 24; let ReleaseAtCycles = [24]; }

def TSV110Wr_31cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]> { let Latency = 31; let ResourceCycles = [31]; }
def TSV110Wr_31cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]> { let Latency = 31; let ReleaseAtCycles = [31]; }

def TSV110Wr_36cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]> { let Latency = 36; let ResourceCycles = [36]; }
def TSV110Wr_36cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]> { let Latency = 36; let ReleaseAtCycles = [36]; }

def TSV110Wr_38cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 38; let ResourceCycles = [38]; }
def TSV110Wr_38cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 38; let ReleaseAtCycles = [38]; }

def TSV110Wr_64cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]> { let Latency = 64; let ResourceCycles = [64]; }
def TSV110Wr_64cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]> { let Latency = 64; let ReleaseAtCycles = [64]; }

//===----------------------------------------------------------------------===//
// Define Generic 2 micro-op types
Expand Down
34 changes: 17 additions & 17 deletions llvm/lib/Target/AArch64/AArch64SchedThunderX.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -59,23 +59,23 @@ def : WriteRes<WriteExtr, [THXT8XUnitALU]> { let Latency = 2; }
// MAC
def : WriteRes<WriteIM32, [THXT8XUnitMAC]> {
let Latency = 4;
let ResourceCycles = [1];
let ReleaseAtCycles = [1];
}

def : WriteRes<WriteIM64, [THXT8XUnitMAC]> {
let Latency = 4;
let ResourceCycles = [1];
let ReleaseAtCycles = [1];
}

// Div
def : WriteRes<WriteID32, [THXT8XUnitDiv]> {
let Latency = 12;
let ResourceCycles = [6];
let ReleaseAtCycles = [6];
}

def : WriteRes<WriteID64, [THXT8XUnitDiv]> {
let Latency = 14;
let ResourceCycles = [8];
let ReleaseAtCycles = [8];
}

// Load
Expand All @@ -86,32 +86,32 @@ def : WriteRes<WriteLDHi, [THXT8XUnitLdSt]> { let Latency = 3; }
// Vector Load
def : WriteRes<WriteVLD, [THXT8XUnitLdSt]> {
let Latency = 8;
let ResourceCycles = [3];
let ReleaseAtCycles = [3];
}

def THXT8XWriteVLD1 : SchedWriteRes<[THXT8XUnitLdSt]> {
let Latency = 6;
let ResourceCycles = [1];
let ReleaseAtCycles = [1];
}

def THXT8XWriteVLD2 : SchedWriteRes<[THXT8XUnitLdSt]> {
let Latency = 11;
let ResourceCycles = [7];
let ReleaseAtCycles = [7];
}

def THXT8XWriteVLD3 : SchedWriteRes<[THXT8XUnitLdSt]> {
let Latency = 12;
let ResourceCycles = [8];
let ReleaseAtCycles = [8];
}

def THXT8XWriteVLD4 : SchedWriteRes<[THXT8XUnitLdSt]> {
let Latency = 13;
let ResourceCycles = [9];
let ReleaseAtCycles = [9];
}

def THXT8XWriteVLD5 : SchedWriteRes<[THXT8XUnitLdSt]> {
let Latency = 13;
let ResourceCycles = [9];
let ReleaseAtCycles = [9];
}

// Pre/Post Indexing
Expand All @@ -129,12 +129,12 @@ def THXT8XWriteVST1 : SchedWriteRes<[THXT8XUnitLdSt]>;

def THXT8XWriteVST2 : SchedWriteRes<[THXT8XUnitLdSt]> {
let Latency = 10;
let ResourceCycles = [9];
let ReleaseAtCycles = [9];
}

def THXT8XWriteVST3 : SchedWriteRes<[THXT8XUnitLdSt]> {
let Latency = 11;
let ResourceCycles = [10];
let ReleaseAtCycles = [10];
}

def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
Expand Down Expand Up @@ -162,29 +162,29 @@ def : WriteRes<WriteVq, [THXT8XUnitFPALU]> { let Latency = 6; }
def : WriteRes<WriteFMul, [THXT8XUnitFPMDS]> { let Latency = 6; }
def : WriteRes<WriteFDiv, [THXT8XUnitFPMDS]> {
let Latency = 22;
let ResourceCycles = [19];
let ReleaseAtCycles = [19];
}

def THXT8XWriteFMAC : SchedWriteRes<[THXT8XUnitFPMDS]> { let Latency = 10; }

def THXT8XWriteFDivSP : SchedWriteRes<[THXT8XUnitFPMDS]> {
let Latency = 12;
let ResourceCycles = [9];
let ReleaseAtCycles = [9];
}

def THXT8XWriteFDivDP : SchedWriteRes<[THXT8XUnitFPMDS]> {
let Latency = 22;
let ResourceCycles = [19];
let ReleaseAtCycles = [19];
}

def THXT8XWriteFSqrtSP : SchedWriteRes<[THXT8XUnitFPMDS]> {
let Latency = 17;
let ResourceCycles = [14];
let ReleaseAtCycles = [14];
}

def THXT8XWriteFSqrtDP : SchedWriteRes<[THXT8XUnitFPMDS]> {
let Latency = 31;
let ResourceCycles = [28];
let ReleaseAtCycles = [28];
}

//===----------------------------------------------------------------------===//
Expand Down
40 changes: 20 additions & 20 deletions llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -113,14 +113,14 @@ def THX2T99Write_4Cyc_I1 : SchedWriteRes<[THX2T99I1]> {
// 23 cycles on I1.
def THX2T99Write_23Cyc_I1 : SchedWriteRes<[THX2T99I1]> {
let Latency = 23;
let ResourceCycles = [13, 23];
let ReleaseAtCycles = [13, 23];
let NumMicroOps = 4;
}

// 39 cycles on I1.
def THX2T99Write_39Cyc_I1 : SchedWriteRes<[THX2T99I1]> {
let Latency = 39;
let ResourceCycles = [13, 39];
let ReleaseAtCycles = [13, 39];
let NumMicroOps = 4;
}

Expand Down Expand Up @@ -200,14 +200,14 @@ def THX2T99Write_10Cyc_F01 : SchedWriteRes<[THX2T99F01]> {
def THX2T99Write_16Cyc_F01 : SchedWriteRes<[THX2T99F01]> {
let Latency = 16;
let NumMicroOps = 3;
let ResourceCycles = [8];
let ReleaseAtCycles = [8];
}

// 23 cycles on F0 or F1.
def THX2T99Write_23Cyc_F01 : SchedWriteRes<[THX2T99F01]> {
let Latency = 23;
let NumMicroOps = 3;
let ResourceCycles = [11];
let ReleaseAtCycles = [11];
}

// 1 cycles on LS0 or LS1.
Expand Down Expand Up @@ -418,7 +418,7 @@ def : InstRW<[THX2T99Write_1Cyc_I2],
// Address generation
def : WriteRes<WriteI, [THX2T99I012]> {
let Latency = 1;
let ResourceCycles = [1];
let ReleaseAtCycles = [1];
let NumMicroOps = 2;
}

Expand All @@ -440,7 +440,7 @@ def : InstRW<[WriteI], (instrs COPY)>;
// ALU, extend and/or shift
def : WriteRes<WriteISReg, [THX2T99I012]> {
let Latency = 2;
let ResourceCycles = [2];
let ReleaseAtCycles = [2];
let NumMicroOps = 2;
}

Expand All @@ -459,7 +459,7 @@ def : InstRW<[WriteISReg],

def : WriteRes<WriteIEReg, [THX2T99I012]> {
let Latency = 1;
let ResourceCycles = [1];
let ReleaseAtCycles = [1];
let NumMicroOps = 2;
}

Expand Down Expand Up @@ -502,14 +502,14 @@ def : WriteRes<WriteIS, [THX2T99I012]> {
// Latency range of 13-23/13-39.
def : WriteRes<WriteID32, [THX2T99I1]> {
let Latency = 39;
let ResourceCycles = [39];
let ReleaseAtCycles = [39];
let NumMicroOps = 4;
}

// Divide, X-form
def : WriteRes<WriteID64, [THX2T99I1]> {
let Latency = 23;
let ResourceCycles = [23];
let ReleaseAtCycles = [23];
let NumMicroOps = 4;
}

Expand Down Expand Up @@ -1110,36 +1110,36 @@ def : WriteRes<WriteFCmp, [THX2T99F01]> {
// FP Mul, Div, Sqrt
def : WriteRes<WriteFDiv, [THX2T99F01]> {
let Latency = 22;
let ResourceCycles = [19];
let ReleaseAtCycles = [19];
}

def THX2T99XWriteFDiv : SchedWriteRes<[THX2T99F01]> {
let Latency = 16;
let ResourceCycles = [8];
let ReleaseAtCycles = [8];
let NumMicroOps = 4;
}

def THX2T99XWriteFDivSP : SchedWriteRes<[THX2T99F01]> {
let Latency = 16;
let ResourceCycles = [8];
let ReleaseAtCycles = [8];
let NumMicroOps = 4;
}

def THX2T99XWriteFDivDP : SchedWriteRes<[THX2T99F01]> {
let Latency = 23;
let ResourceCycles = [12];
let ReleaseAtCycles = [12];
let NumMicroOps = 4;
}

def THX2T99XWriteFSqrtSP : SchedWriteRes<[THX2T99F01]> {
let Latency = 16;
let ResourceCycles = [8];
let ReleaseAtCycles = [8];
let NumMicroOps = 4;
}

def THX2T99XWriteFSqrtDP : SchedWriteRes<[THX2T99F01]> {
let Latency = 23;
let ResourceCycles = [12];
let ReleaseAtCycles = [12];
let NumMicroOps = 4;
}

Expand All @@ -1163,19 +1163,19 @@ def : InstRW<[THX2T99Write_23Cyc_F01], (instregex "^FDIVDrr", "^FSQRTDr")>;
// FP multiply accumulate
def : WriteRes<WriteFMul, [THX2T99F01]> {
let Latency = 6;
let ResourceCycles = [2];
let ReleaseAtCycles = [2];
let NumMicroOps = 3;
}

def THX2T99XWriteFMul : SchedWriteRes<[THX2T99F01]> {
let Latency = 6;
let ResourceCycles = [2];
let ReleaseAtCycles = [2];
let NumMicroOps = 3;
}

def THX2T99XWriteFMulAcc : SchedWriteRes<[THX2T99F01]> {
let Latency = 6;
let ResourceCycles = [2];
let ReleaseAtCycles = [2];
let NumMicroOps = 3;
}

Expand Down Expand Up @@ -1254,12 +1254,12 @@ def : InstRW<[THX2T99Write_5Cyc_F01], (instrs FMOVXDHighr, FMOVDXHighr)>;
def : WriteRes<WriteVd, [THX2T99F01]> {
let Latency = 7;
let NumMicroOps = 4;
let ResourceCycles = [4];
let ReleaseAtCycles = [4];
}
def : WriteRes<WriteVq, [THX2T99F01]> {
let Latency = 7;
let NumMicroOps = 4;
let ResourceCycles = [4];
let ReleaseAtCycles = [4];
}

// ASIMD arith, reduce, 4H/4S
Expand Down
48 changes: 24 additions & 24 deletions llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -143,14 +143,14 @@ def THX3T110Write_7Cyc_I1 : SchedWriteRes<[THX3T110I1]> {
// 23 cycles on I1.
def THX3T110Write_23Cyc_I1 : SchedWriteRes<[THX3T110I1]> {
let Latency = 23;
let ResourceCycles = [13, 23];
let ReleaseAtCycles = [13, 23];
let NumMicroOps = 4;
}

// 39 cycles on I1.
def THX3T110Write_39Cyc_I1 : SchedWriteRes<[THX3T110I1]> {
let Latency = 39;
let ResourceCycles = [13, 39];
let ReleaseAtCycles = [13, 39];
let NumMicroOps = 4;
}

Expand Down Expand Up @@ -278,14 +278,14 @@ def THX3T110Write_10Cyc_F01 : SchedWriteRes<[THX3T110FP0123]> {
def THX3T110Write_16Cyc_F01 : SchedWriteRes<[THX3T110FP0123]> {
let Latency = 16;
let NumMicroOps = 3;
let ResourceCycles = [8];
let ReleaseAtCycles = [8];
}

// 23 cycles on F0/F1/F2/F3.
def THX3T110Write_23Cyc_F01 : SchedWriteRes<[THX3T110FP0123]> {
let Latency = 23;
let NumMicroOps = 3;
let ResourceCycles = [11];
let ReleaseAtCycles = [11];
}

// 1 cycle on LS0/LS1.
Expand All @@ -304,7 +304,7 @@ def THX3T110Write_2Cyc_LS01 : SchedWriteRes<[THX3T110LS]> {
def THX3T110Write_4Cyc_LS01 : SchedWriteRes<[THX3T110LS]> {
let Latency = 4;
let NumMicroOps = 2;
let ResourceCycles = [2];
let ReleaseAtCycles = [2];
}

// 5 cycles on LS0/LS1.
Expand All @@ -326,7 +326,7 @@ def THX3T110Write_6Cyc_LS01 : SchedWriteRes<[THX3T110LS]> {
def THX3T110Write_4_5Cyc_LS01 : SchedWriteRes<[THX3T110LS]> {
let Latency = 4;
let NumMicroOps = 2;
let ResourceCycles = [4, 5];
let ReleaseAtCycles = [4, 5];
}

// 4 + 8 cycles on LS0/LS1.
Expand All @@ -336,7 +336,7 @@ def THX3T110Write_4_5Cyc_LS01 : SchedWriteRes<[THX3T110LS]> {
def THX3T110Write_4_8Cyc_LS01 : SchedWriteRes<[THX3T110LS]> {
let Latency = 4;
let NumMicroOps = 2;
let ResourceCycles = [4, 8];
let ReleaseAtCycles = [4, 8];
}

// 11 cycles on LS0/LS1 and I1.
Expand Down Expand Up @@ -607,7 +607,7 @@ def THX3T110Write_3_4Cyc_F23_F0123 :
SchedWriteRes<[THX3T110FP23, THX3T110FP0123]> {
let Latency = 3;
let NumMicroOps = 2;
let ResourceCycles = [3, 4];
let ReleaseAtCycles = [3, 4];
}


Expand Down Expand Up @@ -678,7 +678,7 @@ def : InstRW<[THX3T110Write_1Cyc_I23],
// Address generation
def : WriteRes<WriteI, [THX3T110I0123]> {
let Latency = 1;
let ResourceCycles = [1];
let ReleaseAtCycles = [1];
let NumMicroOps = 2;
}

Expand All @@ -700,7 +700,7 @@ def : InstRW<[WriteI], (instrs COPY)>;
// ALU, extend and/or shift
def : WriteRes<WriteISReg, [THX3T110I0123]> {
let Latency = 2;
let ResourceCycles = [2];
let ReleaseAtCycles = [2];
let NumMicroOps = 2;
}

Expand All @@ -719,7 +719,7 @@ def : InstRW<[WriteISReg],

def : WriteRes<WriteIEReg, [THX3T110I0123]> {
let Latency = 1;
let ResourceCycles = [1];
let ReleaseAtCycles = [1];
let NumMicroOps = 2;
}

Expand Down Expand Up @@ -762,14 +762,14 @@ def : WriteRes<WriteIS, [THX3T110I0123]> {
// Latency range of 13-23/13-39.
def : WriteRes<WriteID32, [THX3T110I1]> {
let Latency = 39;
let ResourceCycles = [39];
let ReleaseAtCycles = [39];
let NumMicroOps = 4;
}

// Divide, X-form
def : WriteRes<WriteID64, [THX3T110I1]> {
let Latency = 23;
let ResourceCycles = [23];
let ReleaseAtCycles = [23];
let NumMicroOps = 4;
}

Expand Down Expand Up @@ -1218,36 +1218,36 @@ def : WriteRes<WriteFCmp, [THX3T110FP0123]> {
// FP Mul, Div, Sqrt
def : WriteRes<WriteFDiv, [THX3T110FP0123]> {
let Latency = 22;
let ResourceCycles = [19];
let ReleaseAtCycles = [19];
}

def THX3T110XWriteFDiv : SchedWriteRes<[THX3T110FP0123]> {
let Latency = 16;
let ResourceCycles = [8];
let ReleaseAtCycles = [8];
let NumMicroOps = 4;
}

def THX3T110XWriteFDivSP : SchedWriteRes<[THX3T110FP0123]> {
let Latency = 16;
let ResourceCycles = [8];
let ReleaseAtCycles = [8];
let NumMicroOps = 4;
}

def THX3T110XWriteFDivDP : SchedWriteRes<[THX3T110FP0123]> {
let Latency = 23;
let ResourceCycles = [12];
let ReleaseAtCycles = [12];
let NumMicroOps = 4;
}

def THX3T110XWriteFSqrtSP : SchedWriteRes<[THX3T110FP0123]> {
let Latency = 16;
let ResourceCycles = [8];
let ReleaseAtCycles = [8];
let NumMicroOps = 4;
}

def THX3T110XWriteFSqrtDP : SchedWriteRes<[THX3T110FP0123]> {
let Latency = 23;
let ResourceCycles = [12];
let ReleaseAtCycles = [12];
let NumMicroOps = 4;
}

Expand All @@ -1271,19 +1271,19 @@ def : InstRW<[THX3T110Write_23Cyc_F01], (instregex "^FDIVDrr", "^FSQRTDr")>;
// FP multiply accumulate
def : WriteRes<WriteFMul, [THX3T110FP0123]> {
let Latency = 6;
let ResourceCycles = [2];
let ReleaseAtCycles = [2];
let NumMicroOps = 3;
}

def THX3T110XWriteFMul : SchedWriteRes<[THX3T110FP0123]> {
let Latency = 6;
let ResourceCycles = [2];
let ReleaseAtCycles = [2];
let NumMicroOps = 3;
}

def THX3T110XWriteFMulAcc : SchedWriteRes<[THX3T110FP0123]> {
let Latency = 6;
let ResourceCycles = [2];
let ReleaseAtCycles = [2];
let NumMicroOps = 3;
}

Expand Down Expand Up @@ -1362,12 +1362,12 @@ def : InstRW<[THX3T110Write_5Cyc_F01], (instrs FMOVXDHighr, FMOVDXHighr)>;
def : WriteRes<WriteVd, [THX3T110FP0123]> {
let Latency = 5;
let NumMicroOps = 4;
let ResourceCycles = [4];
let ReleaseAtCycles = [4];
}
def : WriteRes<WriteVq, [THX3T110FP0123]> {
let Latency = 5;
let NumMicroOps = 4;
let ResourceCycles = [4];
let ReleaseAtCycles = [4];
}

// ASIMD arith, reduce, 4H/4S
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -271,7 +271,7 @@ GCNHazardRecognizer::getMFMAPipelineWaitStates(const MachineInstr &MI) const {
const MCSchedClassDesc *SC = TSchedModel.resolveSchedClass(&MI);
assert(TSchedModel.getWriteProcResBegin(SC) !=
TSchedModel.getWriteProcResEnd(SC));
return TSchedModel.getWriteProcResBegin(SC)->Cycles;
return TSchedModel.getWriteProcResBegin(SC)->ReleaseAtCycle;
}

void GCNHazardRecognizer::processBundle() {
Expand Down
8 changes: 4 additions & 4 deletions llvm/lib/Target/AMDGPU/SISchedule.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -157,13 +157,13 @@ multiclass SICommonWriteRes {
def : HWVALUWriteRes<Write4PassDGEMM, 4>;
def : HWVALUWriteRes<Write8PassDGEMM, 16>;

let ResourceCycles = [2] in
let ReleaseAtCycles = [2] in
def : HWWriteRes<Write2PassMAI, [HWXDL], 2>;
let ResourceCycles = [4] in
let ReleaseAtCycles = [4] in
def : HWWriteRes<Write4PassMAI, [HWXDL], 4>;
let ResourceCycles = [8] in
let ReleaseAtCycles = [8] in
def : HWWriteRes<Write8PassMAI, [HWXDL], 8>;
let ResourceCycles = [16] in
let ReleaseAtCycles = [16] in
def : HWWriteRes<Write16PassMAI, [HWXDL], 16>;
} // End RetireOOO = 1

Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/ARM/ARMSchedule.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -49,7 +49,7 @@
// NumMicroOps = 2; // Dispatch 2 micro-ops.
// // The two instances of resource P01 are occupied for one cycle. It is one
// // cycle because these resources happen to be pipelined.
// ResourceCycles = [1, 1];
// ReleaseAtCycles = [1, 1];
// }
// def : ReadAdvance<ReadAdvanceALUsr, 3>;

Expand Down Expand Up @@ -195,7 +195,7 @@ class BranchWriteRes<int lat, int uops, list<ProcResourceKind> resl,
list<int> rcl, SchedWriteRes wr> :
SchedWriteRes<!listconcat(wr.ProcResources, resl)> {
let Latency = !add(wr.Latency, lat);
let ResourceCycles = !listconcat(wr.ResourceCycles, rcl);
let ReleaseAtCycles = !listconcat(wr.ReleaseAtCycles, rcl);
let NumMicroOps = !add(wr.NumMicroOps, uops);
SchedWriteRes BaseWr = wr;
}
Expand Down
24 changes: 12 additions & 12 deletions llvm/lib/Target/ARM/ARMScheduleA57WriteRes.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -28,30 +28,30 @@ def A57Write_5cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 5; }
def A57Write_5cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 5; }
def A57Write_10cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 10; }
def A57Write_17cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 17;
let ResourceCycles = [17]; }
let ReleaseAtCycles = [17]; }
def A57Write_18cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 18;
let ResourceCycles = [18]; }
let ReleaseAtCycles = [18]; }
def A57Write_19cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 19;
let ResourceCycles = [19]; }
let ReleaseAtCycles = [19]; }
def A57Write_20cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 20;
let ResourceCycles = [20]; }
let ReleaseAtCycles = [20]; }
def A57Write_1cyc_1B : SchedWriteRes<[A57UnitB]> { let Latency = 1; }
def A57Write_1cyc_1I : SchedWriteRes<[A57UnitI]> { let Latency = 1;
let ResourceCycles = [1]; }
let ReleaseAtCycles = [1]; }
def A57Write_2cyc_1I : SchedWriteRes<[A57UnitI]> { let Latency = 2;
let ResourceCycles = [1]; }
let ReleaseAtCycles = [1]; }
def A57Write_3cyc_1I : SchedWriteRes<[A57UnitI]> { let Latency = 3; }
def A57Write_1cyc_1S : SchedWriteRes<[A57UnitS]> { let Latency = 1; }
def A57Write_2cyc_1S : SchedWriteRes<[A57UnitS]> { let Latency = 2; }
def A57Write_3cyc_1S : SchedWriteRes<[A57UnitS]> { let Latency = 3; }
def A57Write_2cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 2;
let ResourceCycles = [1]; }
let ReleaseAtCycles = [1]; }
def A57Write_32cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 32;
let ResourceCycles = [32]; }
let ReleaseAtCycles = [32]; }
def A57Write_32cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 32;
let ResourceCycles = [32]; }
let ReleaseAtCycles = [32]; }
def A57Write_35cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 35;
let ResourceCycles = [35]; }
let ReleaseAtCycles = [35]; }
def A57Write_3cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 3; }
def A57Write_3cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 3; }
def A57Write_3cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 3; }
Expand Down Expand Up @@ -89,7 +89,7 @@ def A57Write_6cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 6; }
def A57Write_64cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
let Latency = 64;
let NumMicroOps = 2;
let ResourceCycles = [32, 32];
let ReleaseAtCycles = [32, 32];
}
def A57Write_6cyc_1I_1L : SchedWriteRes<[A57UnitI,
A57UnitL]> {
Expand Down Expand Up @@ -224,7 +224,7 @@ def A57Write_2cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
def A57Write_36cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
let Latency = 36;
let NumMicroOps = 2;
let ResourceCycles = [18, 18];
let ReleaseAtCycles = [18, 18];
}
def A57Write_3cyc_1I_1M : SchedWriteRes<[A57UnitI,
A57UnitM]> {
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/ARM/ARMScheduleA9.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1995,15 +1995,15 @@ def : WriteRes<WriteVST4, []>;
// Reserve A9UnitFP for 2 consecutive cycles.
def A9Write2V4 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> {
let Latency = 4;
let ResourceCycles = [2, 1];
let ReleaseAtCycles = [2, 1];
}
def A9Write2V7 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> {
let Latency = 7;
let ResourceCycles = [2, 1];
let ReleaseAtCycles = [2, 1];
}
def A9Write2V9 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> {
let Latency = 9;
let ResourceCycles = [2, 1];
let ReleaseAtCycles = [2, 1];
}

// Branches don't have a def operand but still consume resources.
Expand Down
26 changes: 13 additions & 13 deletions llvm/lib/Target/ARM/ARMScheduleM55.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -46,7 +46,7 @@
//
// For this schedule, we currently model latencies and pipelines well for each
// instruction. MVE instruction take two beats, modelled using
// ResourceCycles=[2].
// ReleaseAtCycles=[2].
//
//
// Dual Issue
Expand Down Expand Up @@ -245,39 +245,39 @@ def : ReadAdvance<ReadMAC, 0>;
// MVE and VFP //
//=============//

// The Writes that take ResourceCycles=[2] are MVE instruction, the others VFP.
// The Writes that take ReleaseAtCycles=[2] are MVE instruction, the others VFP.

let SingleIssue = 1, Latency = 1 in {
def M55WriteLSE2 : SchedWriteRes<[M55UnitLoadStore]>;
def M55WriteIntE2 : SchedWriteRes<[M55UnitVecALU]>;
def M55WriteFloatE2 : SchedWriteRes<[M55UnitVecFPALU]>;
def M55WriteSysE2 : SchedWriteRes<[M55UnitVecSys]>;

def M55Write2LSE2 : SchedWriteRes<[M55UnitLoadStore]> { let ResourceCycles=[2]; }
def M55Write2IntE2 : SchedWriteRes<[M55UnitVecALU]> { let ResourceCycles=[2]; }
def M55Write2FloatE2 : SchedWriteRes<[M55UnitVecFPALU]> { let ResourceCycles=[2]; }
def M55Write2IntFPE2 : SchedWriteRes<[M55UnitVecIntFP]> { let ResourceCycles=[2]; }
def M55Write2LSE2 : SchedWriteRes<[M55UnitLoadStore]> { let ReleaseAtCycles=[2]; }
def M55Write2IntE2 : SchedWriteRes<[M55UnitVecALU]> { let ReleaseAtCycles=[2]; }
def M55Write2FloatE2 : SchedWriteRes<[M55UnitVecFPALU]> { let ReleaseAtCycles=[2]; }
def M55Write2IntFPE2 : SchedWriteRes<[M55UnitVecIntFP]> { let ReleaseAtCycles=[2]; }
}

let SingleIssue = 1, Latency = 2 in {
def M55WriteLSE3 : SchedWriteRes<[M55UnitLoadStore]>;
def M55WriteIntE3 : SchedWriteRes<[M55UnitVecALU]>;
def M55WriteFloatE3 : SchedWriteRes<[M55UnitVecFPALU]>;

def M55Write2LSE3 : SchedWriteRes<[M55UnitLoadStore]> { let ResourceCycles=[2]; }
def M55Write2IntE3 : SchedWriteRes<[M55UnitVecALU]> { let ResourceCycles=[2]; }
def M55Write2FloatE3 : SchedWriteRes<[M55UnitVecFPALU]> { let ResourceCycles=[2]; }
def M55Write2LSE3 : SchedWriteRes<[M55UnitLoadStore]> { let ReleaseAtCycles=[2]; }
def M55Write2IntE3 : SchedWriteRes<[M55UnitVecALU]> { let ReleaseAtCycles=[2]; }
def M55Write2FloatE3 : SchedWriteRes<[M55UnitVecFPALU]> { let ReleaseAtCycles=[2]; }
}

let SingleIssue = 1, Latency = 3 in {
def M55Write2IntE3Plus1 : SchedWriteRes<[M55UnitVecALU]> { let ResourceCycles=[2]; }
def M55Write2IntE3Plus1 : SchedWriteRes<[M55UnitVecALU]> { let ReleaseAtCycles=[2]; }

// Same as M55Write2IntE3/M55Write2FloatE3 above, but longer latency and no forwarding into stores
def M55Write2IntE4NoFwd : SchedWriteRes<[M55UnitVecALU]> { let ResourceCycles=[2]; }
def M55Write2FloatE4NoFwd : SchedWriteRes<[M55UnitVecFPALU]> { let ResourceCycles=[2]; }
def M55Write2IntE4NoFwd : SchedWriteRes<[M55UnitVecALU]> { let ReleaseAtCycles=[2]; }
def M55Write2FloatE4NoFwd : SchedWriteRes<[M55UnitVecFPALU]> { let ReleaseAtCycles=[2]; }
}
let SingleIssue = 1, Latency = 4 in {
def M55Write2IntE3Plus2 : SchedWriteRes<[M55UnitVecALU]> { let ResourceCycles=[2]; }
def M55Write2IntE3Plus2 : SchedWriteRes<[M55UnitVecALU]> { let ReleaseAtCycles=[2]; }
def M55WriteFloatE3Plus2 : SchedWriteRes<[M55UnitVecFPALU]>;
}
let SingleIssue = 1, Latency = 9 in {
Expand Down
24 changes: 12 additions & 12 deletions llvm/lib/Target/ARM/ARMScheduleM85.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -327,7 +327,7 @@ def M85StoreDP : SchedWriteRes<[M85UnitStoreL, M85UnitStoreH,
M85UnitVPortL, M85UnitVPortH]>;
def M85StoreSys : SchedWriteRes<[M85UnitStore, M85UnitVPort,
M85UnitVFPA, M85UnitVFPB, M85UnitVFPC, M85UnitVFPD]>;
let ResourceCycles = [2,2,1,1], EndGroup = 1 in {
let ReleaseAtCycles = [2,2,1,1], EndGroup = 1 in {
def M85LoadMVE : SchedWriteRes<[M85UnitLoadL, M85UnitLoadH,
M85UnitVPortL, M85UnitVPortH]>;
def M85LoadMVELate : SchedWriteRes<[M85UnitLoadL, M85UnitLoadH,
Expand Down Expand Up @@ -702,49 +702,49 @@ def : InstRW<[M85OverrideVFPLat4, WriteFPMAC64,

let Latency = 4, EndGroup = 1 in {
def M85GrpALat2MveR : SchedWriteRes<[M85UnitVFPAL, M85UnitVFPAH, M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]> {
let ResourceCycles = [2,2,1,1,1];
let ReleaseAtCycles = [2,2,1,1,1];
}
def M85GrpABLat2MveR : SchedWriteRes<[M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]>;
def M85GrpBLat2MveR : SchedWriteRes<[M85UnitVFPBL, M85UnitVFPBH, M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]> {
let ResourceCycles = [2,2,1,1,1];
let ReleaseAtCycles = [2,2,1,1,1];
}
def M85Lat2MveR : SchedWriteRes<[]> { let NumMicroOps = 0; }
def M85GrpBLat4Mve : SchedWriteRes<[M85UnitVFPBL, M85UnitVFPBH, M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]> {
let ResourceCycles = [2,2,1,1,1];
let ReleaseAtCycles = [2,2,1,1,1];
}
}
let Latency = 3, EndGroup = 1 in {
def M85GrpBLat3Mve : SchedWriteRes<[M85UnitVFPBL, M85UnitVFPBH, M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]> {
let ResourceCycles = [2,2,1,1,1];
let ReleaseAtCycles = [2,2,1,1,1];
}
def M85GrpBLat1MveR : SchedWriteRes<[M85UnitVFPBL, M85UnitVFPBH, M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]> {
let ResourceCycles = [2,2,1,1,1];
let ReleaseAtCycles = [2,2,1,1,1];
}
def M85Lat1MveR : SchedWriteRes<[]> { let NumMicroOps = 0; }
}
let Latency = 2, EndGroup = 1 in {
def M85GrpALat2Mve : SchedWriteRes<[M85UnitVFPAL, M85UnitVFPAH, M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]> {
let ResourceCycles = [2,2,1,1,1];
let ReleaseAtCycles = [2,2,1,1,1];
}
def M85GrpABLat2Mve : SchedWriteRes<[M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]>;
def M85GrpBLat2Mve : SchedWriteRes<[M85UnitVFPBL, M85UnitVFPBH, M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]> {
let ResourceCycles = [2,2,1,1,1];
let ReleaseAtCycles = [2,2,1,1,1];
}
def M85Lat2Mve : SchedWriteRes<[]> { let NumMicroOps = 0; }
}
let Latency = 1, EndGroup = 1 in {
def M85GrpALat1Mve : SchedWriteRes<[M85UnitVFPAL, M85UnitVFPAH, M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]> {
let ResourceCycles = [2,2,1,1,1];
let ReleaseAtCycles = [2,2,1,1,1];
}
def M85GrpABLat1Mve : SchedWriteRes<[M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]>;
def M85GrpBLat1Mve : SchedWriteRes<[M85UnitVFPBL, M85UnitVFPBH, M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]> {
let ResourceCycles = [2,2,1,1,1];
let ReleaseAtCycles = [2,2,1,1,1];
}
def M85GrpCLat1Mve : SchedWriteRes<[M85UnitVFPCL, M85UnitVFPCH, M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]> {
let ResourceCycles = [2,2,1,1,1];
let ReleaseAtCycles = [2,2,1,1,1];
}
def M85GrpDLat1Mve : SchedWriteRes<[M85UnitVFPD, M85UnitVPortL, M85UnitVPortH, M85UnitSlot0]> {
let ResourceCycles = [2,1,1,1];
let ReleaseAtCycles = [2,1,1,1];
}
}

Expand Down
48 changes: 24 additions & 24 deletions llvm/lib/Target/ARM/ARMScheduleR52.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -72,7 +72,7 @@ def : WriteRes<WriteCMPsr, [R52UnitALU]> { let Latency = 0; }

// Div - may stall 0-9 cycles depending on input (i.e. WRI+(0-9)/2)
def : WriteRes<WriteDIV, [R52UnitDiv]> {
let Latency = 8; let ResourceCycles = [8]; // non-pipelined
let Latency = 8; let ReleaseAtCycles = [8]; // non-pipelined
}

// Branches - LR written in Late EX2
Expand Down Expand Up @@ -107,12 +107,12 @@ def : WriteRes<WriteFPMAC64, [R52UnitFPMUL, R52UnitFPMUL,

def : WriteRes<WriteFPDIV32, [R52UnitDiv]> {
let Latency = 7; // FP div takes fixed #cycles
let ResourceCycles = [7]; // is not pipelined
let ReleaseAtCycles = [7]; // is not pipelined
}

def : WriteRes<WriteFPDIV64, [R52UnitDiv]> {
let Latency = 17;
let ResourceCycles = [17];
let ReleaseAtCycles = [17];
}

def : WriteRes<WriteFPSQRT32, [R52UnitDiv]> { let Latency = 7; }
Expand Down Expand Up @@ -145,7 +145,7 @@ def R52WriteMACHi : SchedWriteRes<[R52UnitMAC]> {
let Latency = 4; let NumMicroOps = 0;
}
def R52WriteDIV : SchedWriteRes<[R52UnitDiv]> {
let Latency = 8; let ResourceCycles = [8]; // not pipelined
let Latency = 8; let ReleaseAtCycles = [8]; // not pipelined
}
def R52WriteLd : SchedWriteRes<[R52UnitLd]> { let Latency = 4; }
def R52WriteST : SchedWriteRes<[R52UnitLd]> { let Latency = 4; }
Expand Down Expand Up @@ -552,7 +552,7 @@ foreach Num = 1-32 in { // reserve LdSt resource, no dual-issue
def R52ReserveLd#Num#Cy : SchedWriteRes<[R52UnitLd]> {
let Latency = 0;
let NumMicroOps = Num;
let ResourceCycles = [Num];
let ReleaseAtCycles = [Num];
}
}
def R52WriteVLDM : SchedWriteVariant<[
Expand Down Expand Up @@ -639,57 +639,57 @@ def R52WriteVLDM : SchedWriteVariant<[
def R52WriteSTM5 : SchedWriteRes<[R52UnitLd]> {
let Latency = 5;
let NumMicroOps = 2;
let ResourceCycles = [1];
let ReleaseAtCycles = [1];
}
def R52WriteSTM6 : SchedWriteRes<[R52UnitLd]> {
let Latency = 6;
let NumMicroOps = 4;
let ResourceCycles = [2];
let ReleaseAtCycles = [2];
}
def R52WriteSTM7 : SchedWriteRes<[R52UnitLd]> {
let Latency = 7;
let NumMicroOps = 6;
let ResourceCycles = [3];
let ReleaseAtCycles = [3];
}
def R52WriteSTM8 : SchedWriteRes<[R52UnitLd]> {
let Latency = 8;
let NumMicroOps = 8;
let ResourceCycles = [4];
let ReleaseAtCycles = [4];
}
def R52WriteSTM9 : SchedWriteRes<[R52UnitLd]> {
let Latency = 9;
let NumMicroOps = 10;
let ResourceCycles = [5];
let ReleaseAtCycles = [5];
}
def R52WriteSTM10 : SchedWriteRes<[R52UnitLd]> {
let Latency = 10;
let NumMicroOps = 12;
let ResourceCycles = [6];
let ReleaseAtCycles = [6];
}
def R52WriteSTM11 : SchedWriteRes<[R52UnitLd]> {
let Latency = 11;
let NumMicroOps = 14;
let ResourceCycles = [7];
let ReleaseAtCycles = [7];
}
def R52WriteSTM12 : SchedWriteRes<[R52UnitLd]> {
let Latency = 12;
let NumMicroOps = 16;
let ResourceCycles = [8];
let ReleaseAtCycles = [8];
}
def R52WriteSTM13 : SchedWriteRes<[R52UnitLd]> {
let Latency = 13;
let NumMicroOps = 18;
let ResourceCycles = [9];
let ReleaseAtCycles = [9];
}
def R52WriteSTM14 : SchedWriteRes<[R52UnitLd]> {
let Latency = 14;
let NumMicroOps = 20;
let ResourceCycles = [10];
let ReleaseAtCycles = [10];
}
def R52WriteSTM15 : SchedWriteRes<[R52UnitLd]> {
let Latency = 15;
let NumMicroOps = 22;
let ResourceCycles = [11];
let ReleaseAtCycles = [11];
}

def R52WriteSTM : SchedWriteVariant<[
Expand Down Expand Up @@ -719,45 +719,45 @@ def : WriteRes<WriteVLD1, [R52UnitLd]> { let Latency = 5;}
def : WriteRes<WriteVLD2, [R52UnitLd]> {
let Latency = 6;
let NumMicroOps = 3;
let ResourceCycles = [2];
let ReleaseAtCycles = [2];
let SingleIssue = 1;
}
def : WriteRes<WriteVLD3, [R52UnitLd]> {
let Latency = 7;
let NumMicroOps = 5;
let ResourceCycles = [3];
let ReleaseAtCycles = [3];
let SingleIssue = 1;
}
def : WriteRes<WriteVLD4, [R52UnitLd]> {
let Latency = 8;
let NumMicroOps = 7;
let ResourceCycles = [4];
let ReleaseAtCycles = [4];
let SingleIssue = 1;
}
def R52WriteVST1Mem : SchedWriteRes<[R52UnitLd]> {
let Latency = 5;
let NumMicroOps = 1;
let ResourceCycles = [1];
let ReleaseAtCycles = [1];
}
def R52WriteVST2Mem : SchedWriteRes<[R52UnitLd]> {
let Latency = 6;
let NumMicroOps = 3;
let ResourceCycles = [2];
let ReleaseAtCycles = [2];
}
def R52WriteVST3Mem : SchedWriteRes<[R52UnitLd]> {
let Latency = 7;
let NumMicroOps = 5;
let ResourceCycles = [3];
let ReleaseAtCycles = [3];
}
def R52WriteVST4Mem : SchedWriteRes<[R52UnitLd]> {
let Latency = 8;
let NumMicroOps = 7;
let ResourceCycles = [4];
let ReleaseAtCycles = [4];
}
def R52WriteVST5Mem : SchedWriteRes<[R52UnitLd]> {
let Latency = 9;
let NumMicroOps = 9;
let ResourceCycles = [5];
let ReleaseAtCycles = [5];
}


Expand Down
28 changes: 14 additions & 14 deletions llvm/lib/Target/ARM/ARMScheduleSwift.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -88,7 +88,7 @@ let SchedModel = SwiftModel in {
def SwiftWriteP0ThreeCycleThreeUops : SchedWriteRes<[SwiftUnitP0]> {
let Latency = 3;
let NumMicroOps = 3;
let ResourceCycles = [3];
let ReleaseAtCycles = [3];
}
// Plain load without writeback.
def SwiftWriteP2ThreeCycle : SchedWriteRes<[SwiftUnitP2]> {
Expand Down Expand Up @@ -261,7 +261,7 @@ let SchedModel = SwiftModel in {
def SwiftP0P0P01FiveCycle : SchedWriteRes<[SwiftUnitP0, SwiftUnitP01]> {
let Latency = 5;
let NumMicroOps = 3;
let ResourceCycles = [2, 1];
let ReleaseAtCycles = [2, 1];
}
def SwiftWrite1Cycle : SchedWriteRes<[]> {
let Latency = 1;
Expand All @@ -283,7 +283,7 @@ let SchedModel = SwiftModel in {
def Swift2P03P01FiveCycle : SchedWriteRes<[SwiftUnitP0, SwiftUnitP01]> {
let Latency = 7;
let NumMicroOps = 5;
let ResourceCycles = [2, 3];
let ReleaseAtCycles = [2, 3];
}

// Aliasing sub-target specific WriteRes to generic ones
Expand Down Expand Up @@ -313,7 +313,7 @@ let SchedModel = SwiftModel in {
def SwiftDiv : SchedWriteRes<[SwiftUnitP0, SwiftUnitDiv]> {
let NumMicroOps = 1;
let Latency = 14;
let ResourceCycles = [1, 14];
let ReleaseAtCycles = [1, 14];
}
// 4.2.18 Integer Divide
def : WriteRes<WriteDIV, [SwiftUnitDiv]>; // Workaround.
Expand Down Expand Up @@ -653,15 +653,15 @@ let SchedModel = SwiftModel in {
// Serializing instructions.
def SwiftWaitP0For15Cy : SchedWriteRes<[SwiftUnitP0]> {
let Latency = 15;
let ResourceCycles = [15];
let ReleaseAtCycles = [15];
}
def SwiftWaitP1For15Cy : SchedWriteRes<[SwiftUnitP1]> {
let Latency = 15;
let ResourceCycles = [15];
let ReleaseAtCycles = [15];
}
def SwiftWaitP2For15Cy : SchedWriteRes<[SwiftUnitP2]> {
let Latency = 15;
let ResourceCycles = [15];
let ReleaseAtCycles = [15];
}
def : InstRW<[SwiftWaitP0For15Cy, SwiftWaitP1For15Cy, SwiftWaitP2For15Cy],
(instregex "VMRS")>;
Expand All @@ -684,7 +684,7 @@ let SchedModel = SwiftModel in {
def SwiftVLDMPerm#Num : SchedWriteRes<[SwiftUnitP1]> {
let Latency = 0;
let NumMicroOps = Num;
let ResourceCycles = [Num];
let ReleaseAtCycles = [Num];
}
}

Expand Down Expand Up @@ -860,17 +860,17 @@ let SchedModel = SwiftModel in {
// 4.2.43 Advanced SIMD, Element or Structure Load and Store
def SwiftWrite2xP2FourCy : SchedWriteRes<[SwiftUnitP2]> {
let Latency = 4;
let ResourceCycles = [2];
let ReleaseAtCycles = [2];
}
def SwiftWrite3xP2FourCy : SchedWriteRes<[SwiftUnitP2]> {
let Latency = 4;
let ResourceCycles = [3];
let ReleaseAtCycles = [3];
}
foreach Num = 1-2 in {
def SwiftExt#Num#xP0 : SchedWriteRes<[SwiftUnitP0]> {
let Latency = 0;
let NumMicroOps = Num;
let ResourceCycles = [Num];
let ReleaseAtCycles = [Num];
}
}
// VLDx
Expand Down Expand Up @@ -1038,12 +1038,12 @@ let SchedModel = SwiftModel in {
def SwiftDiv17 : SchedWriteRes<[SwiftUnitP0, SwiftUnitDiv]> {
let NumMicroOps = 1;
let Latency = 17;
let ResourceCycles = [1, 15];
let ReleaseAtCycles = [1, 15];
}
def SwiftDiv32 : SchedWriteRes<[SwiftUnitP0, SwiftUnitDiv]> {
let NumMicroOps = 1;
let Latency = 32;
let ResourceCycles = [1, 30];
let ReleaseAtCycles = [1, 30];
}
def : InstRW<[SwiftDiv17], (instregex "VDIVS", "VSQRTS")>;
def : InstRW<[SwiftDiv32], (instregex "VDIVD", "VSQRTD")>;
Expand Down Expand Up @@ -1086,7 +1086,7 @@ let SchedModel = SwiftModel in {
def : InstRW<[SwiftWriteP01OneCycle2x], (instregex "ABS")>;
// Preload.
def : WriteRes<WritePreLd, [SwiftUnitP2]> { let Latency = 0;
let ResourceCycles = [0];
let ReleaseAtCycles = [0];
}

}
22 changes: 11 additions & 11 deletions llvm/lib/Target/Mips/MipsScheduleGeneric.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -160,12 +160,12 @@ def GenericWriteMDUtoGPR : SchedWriteRes<[GenericIssueMDU]> {
def GenericWriteDIV : SchedWriteRes<[GenericIssueDIV]> {
// Estimated worst case
let Latency = 33;
let ResourceCycles = [33];
let ReleaseAtCycles = [33];
}
def GenericWriteDIVU : SchedWriteRes<[GenericIssueDIV]> {
// Estimated worst case
let Latency = 31;
let ResourceCycles = [31];
let ReleaseAtCycles = [31];
}

// mul
Expand Down Expand Up @@ -761,35 +761,35 @@ def GenericWriteFPUMoveGPRFPU : SchedWriteRes<[GenericIssueFPUMove]> {
}
def GenericWriteFPUDivS : SchedWriteRes<[GenericFPUDivSqrt]> {
let Latency = 17;
let ResourceCycles = [ 14 ];
let ReleaseAtCycles = [ 14 ];
}
def GenericWriteFPUDivD : SchedWriteRes<[GenericFPUDivSqrt]> {
let Latency = 32;
let ResourceCycles = [ 29 ];
let ReleaseAtCycles = [ 29 ];
}
def GenericWriteFPURcpS : SchedWriteRes<[GenericFPUDivSqrt]> {
let Latency = 13;
let ResourceCycles = [ 10 ];
let ReleaseAtCycles = [ 10 ];
}
def GenericWriteFPURcpD : SchedWriteRes<[GenericFPUDivSqrt]> {
let Latency = 25;
let ResourceCycles = [ 21 ];
let ReleaseAtCycles = [ 21 ];
}
def GenericWriteFPURsqrtS : SchedWriteRes<[GenericFPUDivSqrt]> {
let Latency = 17;
let ResourceCycles = [ 14 ];
let ReleaseAtCycles = [ 14 ];
}
def GenericWriteFPURsqrtD : SchedWriteRes<[GenericFPUDivSqrt]> {
let Latency = 32;
let ResourceCycles = [ 29 ];
let ReleaseAtCycles = [ 29 ];
}
def GenericWriteFPUSqrtS : SchedWriteRes<[GenericFPUDivSqrt]> {
let Latency = 17;
let ResourceCycles = [ 14 ];
let ReleaseAtCycles = [ 14 ];
}
def GenericWriteFPUSqrtD : SchedWriteRes<[GenericFPUDivSqrt]> {
let Latency = 29;
let ResourceCycles = [ 29 ];
let ReleaseAtCycles = [ 29 ];
}

// Floating point compare and branch
Expand Down Expand Up @@ -1405,7 +1405,7 @@ let Latency = 5;
}
def GenericWriteFPUDivI : SchedWriteRes<[GenericFPQ]> {
let Latency = 33;
let ResourceCycles = [ 33 ];
let ReleaseAtCycles = [ 33 ];
}

// FPUS is also used in moves from floating point and MSA registers to general
Expand Down
24 changes: 12 additions & 12 deletions llvm/lib/Target/Mips/MipsScheduleP5600.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -119,7 +119,7 @@ def P5600WriteCache : SchedWriteRes<[P5600IssueLDST]>;
def P5600WriteStore : SchedWriteRes<[P5600IssueLDST, P5600CTISTD]> {
// FIXME: This is a bit pessimistic. P5600CTISTD is only used during cycle 2
// not during 0, 1, and 2.
let ResourceCycles = [ 1, 3 ];
let ReleaseAtCycles = [ 1, 3 ];
}

def P5600WriteGPRFromBypass : SchedWriteRes<[P5600IssueLDST]> {
Expand Down Expand Up @@ -165,12 +165,12 @@ def P5600WriteAL2CondMov : SchedWriteRes<[P5600IssueAL2, P5600CTISTD]> {
def P5600WriteAL2Div : SchedWriteRes<[P5600IssueAL2, P5600AL2Div]> {
// Estimated worst case
let Latency = 34;
let ResourceCycles = [1, 34];
let ReleaseAtCycles = [1, 34];
}
def P5600WriteAL2DivU : SchedWriteRes<[P5600IssueAL2, P5600AL2Div]> {
// Estimated worst case
let Latency = 34;
let ResourceCycles = [1, 34];
let ReleaseAtCycles = [1, 34];
}
def P5600WriteAL2Mul : SchedWriteRes<[P5600IssueAL2]> { let Latency = 3; }
def P5600WriteAL2Mult: SchedWriteRes<[P5600IssueAL2]> { let Latency = 5; }
Expand Down Expand Up @@ -241,47 +241,47 @@ def P5600WriteFPUL_MADDSUB : SchedWriteRes<[P5600IssueFPUL]> { let Latency = 6;
def P5600WriteFPUDivI : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
// Best/Common/Worst case = 7 / 23 / 27
let Latency = 23; // Using common case
let ResourceCycles = [ 1, 23 ];
let ReleaseAtCycles = [ 1, 23 ];
}
def P5600WriteFPUDivS : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
// Best/Common/Worst case = 7 / 23 / 27
let Latency = 23; // Using common case
let ResourceCycles = [ 1, 23 ];
let ReleaseAtCycles = [ 1, 23 ];
}
def P5600WriteFPUDivD : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
// Best/Common/Worst case = 7 / 31 / 35
let Latency = 31; // Using common case
let ResourceCycles = [ 1, 31 ];
let ReleaseAtCycles = [ 1, 31 ];
}
def P5600WriteFPURcpS : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
// Best/Common/Worst case = 7 / 19 / 23
let Latency = 19; // Using common case
let ResourceCycles = [ 1, 19 ];
let ReleaseAtCycles = [ 1, 19 ];
}
def P5600WriteFPURcpD : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
// Best/Common/Worst case = 7 / 27 / 31
let Latency = 27; // Using common case
let ResourceCycles = [ 1, 27 ];
let ReleaseAtCycles = [ 1, 27 ];
}
def P5600WriteFPURsqrtS : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
// Best/Common/Worst case = 7 / 27 / 27
let Latency = 27; // Using common case
let ResourceCycles = [ 1, 27 ];
let ReleaseAtCycles = [ 1, 27 ];
}
def P5600WriteFPURsqrtD : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
// Best/Common/Worst case = 7 / 27 / 31
let Latency = 27; // Using common case
let ResourceCycles = [ 1, 27 ];
let ReleaseAtCycles = [ 1, 27 ];
}
def P5600WriteFPUSqrtS : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
// Best/Common/Worst case = 7 / 27 / 31
let Latency = 27; // Using common case
let ResourceCycles = [ 1, 27 ];
let ReleaseAtCycles = [ 1, 27 ];
}
def P5600WriteFPUSqrtD : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
// Best/Common/Worst case = 7 / 35 / 39
let Latency = 35; // Using common case
let ResourceCycles = [ 1, 35 ];
let ReleaseAtCycles = [ 1, 35 ];
}
def P5600WriteMSAShortLogic : SchedWriteRes<[P5600IssueFPUS]>;
def P5600WriteMSAShortInt : SchedWriteRes<[P5600IssueFPUS]> { let Latency = 2; }
Expand Down
62 changes: 31 additions & 31 deletions llvm/lib/Target/PowerPC/PPCScheduleP10.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -87,27 +87,27 @@ let SchedModel = P10Model in {
}

def P10W_BF_22C : SchedWriteRes<[P10_BF]> {
let ResourceCycles = [ 5 ];
let ReleaseAtCycles = [ 5 ];
let Latency = 22;
}

def P10W_BF_24C : SchedWriteRes<[P10_BF]> {
let ResourceCycles = [ 8 ];
let ReleaseAtCycles = [ 8 ];
let Latency = 24;
}

def P10W_BF_26C : SchedWriteRes<[P10_BF]> {
let ResourceCycles = [ 5 ];
let ReleaseAtCycles = [ 5 ];
let Latency = 26;
}

def P10W_BF_27C : SchedWriteRes<[P10_BF]> {
let ResourceCycles = [ 7 ];
let ReleaseAtCycles = [ 7 ];
let Latency = 27;
}

def P10W_BF_36C : SchedWriteRes<[P10_BF]> {
let ResourceCycles = [ 10 ];
let ReleaseAtCycles = [ 10 ];
let Latency = 36;
}

Expand All @@ -128,134 +128,134 @@ let SchedModel = P10Model in {
}

def P10W_DF_24C : SchedWriteRes<[P10_DF]> {
let ResourceCycles = [ 16 ];
let ReleaseAtCycles = [ 16 ];
let Latency = 24;
}

def P10W_DF_25C : SchedWriteRes<[P10_DF]> {
let ResourceCycles = [ 17 ];
let ReleaseAtCycles = [ 17 ];
let Latency = 25;
}

def P10W_DF_26C : SchedWriteRes<[P10_DF]> {
let ResourceCycles = [ 18 ];
let ReleaseAtCycles = [ 18 ];
let Latency = 26;
}

def P10W_DF_32C : SchedWriteRes<[P10_DF]> {
let ResourceCycles = [ 22 ];
let ReleaseAtCycles = [ 22 ];
let Latency = 32;
}

def P10W_DF_33C : SchedWriteRes<[P10_DF]> {
let ResourceCycles = [ 25 ];
let ReleaseAtCycles = [ 25 ];
let Latency = 33;
}

def P10W_DF_34C : SchedWriteRes<[P10_DF]> {
let ResourceCycles = [ 25 ];
let ReleaseAtCycles = [ 25 ];
let Latency = 34;
}

def P10W_DF_38C : SchedWriteRes<[P10_DF]> {
let ResourceCycles = [ 30 ];
let ReleaseAtCycles = [ 30 ];
let Latency = 38;
}

def P10W_DF_40C : SchedWriteRes<[P10_DF]> {
let ResourceCycles = [ 17 ];
let ReleaseAtCycles = [ 17 ];
let Latency = 40;
}

def P10W_DF_43C : SchedWriteRes<[P10_DF]> {
let ResourceCycles = [ 34 ];
let ReleaseAtCycles = [ 34 ];
let Latency = 43;
}

def P10W_DF_59C : SchedWriteRes<[P10_DF]> {
let ResourceCycles = [ 49 ];
let ReleaseAtCycles = [ 49 ];
let Latency = 59;
}

def P10W_DF_61C : SchedWriteRes<[P10_DF]> {
let ResourceCycles = [ 12 ];
let ReleaseAtCycles = [ 12 ];
let Latency = 61;
}

def P10W_DF_68C : SchedWriteRes<[P10_DF]> {
let ResourceCycles = [ 15 ];
let ReleaseAtCycles = [ 15 ];
let Latency = 68;
}

def P10W_DF_77C : SchedWriteRes<[P10_DF]> {
let ResourceCycles = [ 67 ];
let ReleaseAtCycles = [ 67 ];
let Latency = 77;
}

def P10W_DF_87C : SchedWriteRes<[P10_DF]> {
let ResourceCycles = [ 12 ];
let ReleaseAtCycles = [ 12 ];
let Latency = 87;
}

def P10W_DF_100C : SchedWriteRes<[P10_DF]> {
let ResourceCycles = [ 32 ];
let ReleaseAtCycles = [ 32 ];
let Latency = 100;
}

def P10W_DF_174C : SchedWriteRes<[P10_DF]> {
let ResourceCycles = [ 33 ];
let ReleaseAtCycles = [ 33 ];
let Latency = 174;
}

// A DV pipeline may take from 20 to 83 cycles to complete.
// Some DV operations may keep the pipeline busy for up to 33 cycles.
def P10W_DV_20C : SchedWriteRes<[P10_DV]> {
let ResourceCycles = [ 10 ];
let ReleaseAtCycles = [ 10 ];
let Latency = 20;
}

def P10W_DV_25C : SchedWriteRes<[P10_DV]> {
let ResourceCycles = [ 10 ];
let ReleaseAtCycles = [ 10 ];
let Latency = 25;
}

def P10W_DV_27C : SchedWriteRes<[P10_DV]> {
let ResourceCycles = [ 10 ];
let ReleaseAtCycles = [ 10 ];
let Latency = 27;
}

def P10W_DV_41C : SchedWriteRes<[P10_DV]> {
let ResourceCycles = [ 10 ];
let ReleaseAtCycles = [ 10 ];
let Latency = 41;
}

def P10W_DV_43C : SchedWriteRes<[P10_DV]> {
let ResourceCycles = [ 21 ];
let ReleaseAtCycles = [ 21 ];
let Latency = 43;
}

def P10W_DV_47C : SchedWriteRes<[P10_DV]> {
let ResourceCycles = [ 21 ];
let ReleaseAtCycles = [ 21 ];
let Latency = 47;
}

def P10W_DV_54C : SchedWriteRes<[P10_DV]> {
let ResourceCycles = [ 33 ];
let ReleaseAtCycles = [ 33 ];
let Latency = 54;
}

def P10W_DV_60C : SchedWriteRes<[P10_DV]> {
let ResourceCycles = [ 33 ];
let ReleaseAtCycles = [ 33 ];
let Latency = 60;
}

def P10W_DV_75C : SchedWriteRes<[P10_DV]> {
let ResourceCycles = [ 21 ];
let ReleaseAtCycles = [ 21 ];
let Latency = 75;
}

def P10W_DV_83C : SchedWriteRes<[P10_DV]> {
let ResourceCycles = [ 33 ];
let ReleaseAtCycles = [ 33 ];
let Latency = 83;
}

Expand Down
40 changes: 20 additions & 20 deletions llvm/lib/Target/PowerPC/PPCScheduleP9.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -227,17 +227,17 @@ let SchedModel = P9Model in {
}

def P9_DIV_16C_8 : SchedWriteRes<[DIV]> {
let ResourceCycles = [8];
let ReleaseAtCycles = [8];
let Latency = 16;
}

def P9_DIV_24C_8 : SchedWriteRes<[DIV]> {
let ResourceCycles = [8];
let ReleaseAtCycles = [8];
let Latency = 24;
}

def P9_DIV_40C_8 : SchedWriteRes<[DIV]> {
let ResourceCycles = [8];
let ReleaseAtCycles = [8];
let Latency = 40;
}

Expand All @@ -261,62 +261,62 @@ let SchedModel = P9Model in {
}

def P9_DP_22C_5 : SchedWriteRes<[DP]> {
let ResourceCycles = [5];
let ReleaseAtCycles = [5];
let Latency = 22;
}

def P9_DPO_24C_8 : SchedWriteRes<[DPO]> {
let ResourceCycles = [8];
let ReleaseAtCycles = [8];
let Latency = 24;
}

def P9_DPE_24C_8 : SchedWriteRes<[DPE]> {
let ResourceCycles = [8];
let ReleaseAtCycles = [8];
let Latency = 24;
}

def P9_DP_26C_5 : SchedWriteRes<[DP]> {
let ResourceCycles = [5];
let ReleaseAtCycles = [5];
let Latency = 22;
}

def P9_DPE_27C_10 : SchedWriteRes<[DP]> {
let ResourceCycles = [10];
let ReleaseAtCycles = [10];
let Latency = 27;
}

def P9_DPO_27C_10 : SchedWriteRes<[DP]> {
let ResourceCycles = [10];
let ReleaseAtCycles = [10];
let Latency = 27;
}

def P9_DP_33C_8 : SchedWriteRes<[DP]> {
let ResourceCycles = [8];
let ReleaseAtCycles = [8];
let Latency = 33;
}

def P9_DPE_33C_8 : SchedWriteRes<[DPE]> {
let ResourceCycles = [8];
let ReleaseAtCycles = [8];
let Latency = 33;
}

def P9_DPO_33C_8 : SchedWriteRes<[DPO]> {
let ResourceCycles = [8];
let ReleaseAtCycles = [8];
let Latency = 33;
}

def P9_DP_36C_10 : SchedWriteRes<[DP]> {
let ResourceCycles = [10];
let ReleaseAtCycles = [10];
let Latency = 36;
}

def P9_DPE_36C_10 : SchedWriteRes<[DP]> {
let ResourceCycles = [10];
let ReleaseAtCycles = [10];
let Latency = 36;
}

def P9_DPO_36C_10 : SchedWriteRes<[DP]> {
let ResourceCycles = [10];
let ReleaseAtCycles = [10];
let Latency = 36;
}

Expand Down Expand Up @@ -358,27 +358,27 @@ let SchedModel = P9Model in {

def P9_DFU_23C : SchedWriteRes<[DFU]> {
let Latency = 23;
let ResourceCycles = [11];
let ReleaseAtCycles = [11];
}

def P9_DFU_24C : SchedWriteRes<[DFU]> {
let Latency = 24;
let ResourceCycles = [12];
let ReleaseAtCycles = [12];
}

def P9_DFU_37C : SchedWriteRes<[DFU]> {
let Latency = 37;
let ResourceCycles = [25];
let ReleaseAtCycles = [25];
}

def P9_DFU_58C : SchedWriteRes<[DFU]> {
let Latency = 58;
let ResourceCycles = [44];
let ReleaseAtCycles = [44];
}

def P9_DFU_76C : SchedWriteRes<[DFU]> {
let Latency = 76;
let ResourceCycles = [62];
let ReleaseAtCycles = [62];
}

// 2 or 5 cycle latencies for the branch unit.
Expand Down
10 changes: 5 additions & 5 deletions llvm/lib/Target/RISCV/RISCVSchedRocket.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -70,11 +70,11 @@ def : WriteRes<WriteIMul32, [RocketUnitIMul]>;
// Worst case latency is used.
def : WriteRes<WriteIDiv32, [RocketUnitIDiv]> {
let Latency = 34;
let ResourceCycles = [34];
let ReleaseAtCycles = [34];
}
def : WriteRes<WriteIDiv, [RocketUnitIDiv]> {
let Latency = 33;
let ResourceCycles = [33];
let ReleaseAtCycles = [33];
}

// Memory
Expand Down Expand Up @@ -157,16 +157,16 @@ def : WriteRes<WriteFMA64, [RocketUnitFPALU]>;

// FP division
// FP division unit on Rocket is not pipelined, so set resource cycles to latency.
let Latency = 20, ResourceCycles = [20] in {
let Latency = 20, ReleaseAtCycles = [20] in {
def : WriteRes<WriteFDiv32, [RocketUnitFPDivSqrt]>;
def : WriteRes<WriteFDiv64, [RocketUnitFPDivSqrt]>;
}

// FP square root unit on Rocket is not pipelined, so set resource cycles to latency.
def : WriteRes<WriteFSqrt32, [RocketUnitFPDivSqrt]> { let Latency = 20;
let ResourceCycles = [20]; }
let ReleaseAtCycles = [20]; }
def : WriteRes<WriteFSqrt64, [RocketUnitFPDivSqrt]> { let Latency = 25;
let ResourceCycles = [25]; }
let ReleaseAtCycles = [25]; }

// Others
def : WriteRes<WriteCSR, []>;
Expand Down
130 changes: 65 additions & 65 deletions llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
View file

Large diffs are not rendered by default.

4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -55,14 +55,14 @@ def : WriteRes<WriteIMul, [SCR1_MUL]>;
def : WriteRes<WriteIMul32, [SCR1_MUL]>;

// Integer division: latency 33, inverse throughput 33
let Latency = 33, ResourceCycles = [33] in {
let Latency = 33, ReleaseAtCycles = [33] in {
def : WriteRes<WriteIDiv32, [SCR1_DIV]>;
def : WriteRes<WriteIDiv, [SCR1_DIV]>;
}

// Load/store instructions on SCR1 have latency 2 and inverse throughput 2
// (SCR1_CFG_RV32IMC_MAX includes TCM)
let Latency = 2, ResourceCycles=[2] in {
let Latency = 2, ReleaseAtCycles=[2] in {
// Memory
def : WriteRes<WriteSTB, [SCR1_LSU]>;
def : WriteRes<WriteSTH, [SCR1_LSU]>;
Expand Down
8 changes: 4 additions & 4 deletions llvm/lib/Target/SystemZ/SystemZHazardRecognizer.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -187,8 +187,8 @@ void SystemZHazardRecognizer::dumpSU(SUnit *SU, raw_ostream &OS) const {
FU = "LSU";
OS << "/" << FU;

if (PI->Cycles > 1)
OS << "(" << PI->Cycles << "cyc)";
if (PI->ReleaseAtCycle> 1)
OS << "(" << PI->ReleaseAtCycle << "cyc)";
}

if (SC->NumMicroOps > 1)
Expand Down Expand Up @@ -301,7 +301,7 @@ EmitInstruction(SUnit *SU) {
continue;
int &CurrCounter =
ProcResourceCounters[PI->ProcResourceIdx];
CurrCounter += PI->Cycles;
CurrCounter += PI->ReleaseAtCycle;
// Check if this is now the new critical resource.
if ((CurrCounter > ProcResCostLim) &&
(CriticalResourceIdx == UINT_MAX ||
Expand Down Expand Up @@ -401,7 +401,7 @@ resourcesCost(SUnit *SU) {
PI = SchedModel->getWriteProcResBegin(SC),
PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI)
if (PI->ProcResourceIdx == CriticalResourceIdx)
Cost = PI->Cycles;
Cost = PI->ReleaseAtCycle;
}

return Cost;
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
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Original file line number Diff line number Diff line change
Expand Up @@ -92,7 +92,7 @@ let NumMicroOps = 0 in {
def : WriteRes<VecMul, [Z13_VecUnit]>;
def : WriteRes<VecStr, [Z13_VecUnit]>;
def : WriteRes<VecXsPm, [Z13_VecUnit]>;
foreach Num = 2-5 in { let ResourceCycles = [Num] in {
foreach Num = 2-5 in { let ReleaseAtCycles = [Num] in {
def : WriteRes<!cast<SchedWrite>("FXa"#Num), [Z13_FXaUnit]>;
def : WriteRes<!cast<SchedWrite>("FXb"#Num), [Z13_FXbUnit]>;
def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z13_LSUnit]>;
Expand All @@ -104,7 +104,7 @@ let NumMicroOps = 0 in {
def : WriteRes<!cast<SchedWrite>("VecXsPm"#Num), [Z13_VecUnit]>;
}}

def : WriteRes<VecFPd, [Z13_VecFPdUnit]> { let ResourceCycles = [30]; }
def : WriteRes<VecFPd, [Z13_VecFPdUnit]> { let ReleaseAtCycles = [30]; }

def : WriteRes<VBU, [Z13_VBUnit]>; // Virtual Branching Unit
}
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
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Original file line number Diff line number Diff line change
Expand Up @@ -92,7 +92,7 @@ let NumMicroOps = 0 in {
def : WriteRes<VecMul, [Z14_VecUnit]>;
def : WriteRes<VecStr, [Z14_VecUnit]>;
def : WriteRes<VecXsPm, [Z14_VecUnit]>;
foreach Num = 2-5 in { let ResourceCycles = [Num] in {
foreach Num = 2-5 in { let ReleaseAtCycles = [Num] in {
def : WriteRes<!cast<SchedWrite>("FXa"#Num), [Z14_FXaUnit]>;
def : WriteRes<!cast<SchedWrite>("FXb"#Num), [Z14_FXbUnit]>;
def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z14_LSUnit]>;
Expand All @@ -104,7 +104,7 @@ let NumMicroOps = 0 in {
def : WriteRes<!cast<SchedWrite>("VecXsPm"#Num), [Z14_VecUnit]>;
}}

def : WriteRes<VecFPd, [Z14_VecFPdUnit]> { let ResourceCycles = [30]; }
def : WriteRes<VecFPd, [Z14_VecFPdUnit]> { let ReleaseAtCycles = [30]; }

def : WriteRes<VBU, [Z14_VBUnit]>; // Virtual Branching Unit
}
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
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Original file line number Diff line number Diff line change
Expand Up @@ -92,7 +92,7 @@ let NumMicroOps = 0 in {
def : WriteRes<VecMul, [Z15_VecUnit]>;
def : WriteRes<VecStr, [Z15_VecUnit]>;
def : WriteRes<VecXsPm, [Z15_VecUnit]>;
foreach Num = 2-5 in { let ResourceCycles = [Num] in {
foreach Num = 2-5 in { let ReleaseAtCycles = [Num] in {
def : WriteRes<!cast<SchedWrite>("FXa"#Num), [Z15_FXaUnit]>;
def : WriteRes<!cast<SchedWrite>("FXb"#Num), [Z15_FXbUnit]>;
def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z15_LSUnit]>;
Expand All @@ -104,7 +104,7 @@ let NumMicroOps = 0 in {
def : WriteRes<!cast<SchedWrite>("VecXsPm"#Num), [Z15_VecUnit]>;
}}

def : WriteRes<VecFPd, [Z15_VecFPdUnit]> { let ResourceCycles = [30]; }
def : WriteRes<VecFPd, [Z15_VecFPdUnit]> { let ReleaseAtCycles = [30]; }

def : WriteRes<VBU, [Z15_VBUnit]>; // Virtual Branching Unit
}
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
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Original file line number Diff line number Diff line change
Expand Up @@ -92,7 +92,7 @@ let NumMicroOps = 0 in {
def : WriteRes<VecMul, [Z16_VecUnit]>;
def : WriteRes<VecStr, [Z16_VecUnit]>;
def : WriteRes<VecXsPm, [Z16_VecUnit]>;
foreach Num = 2-5 in { let ResourceCycles = [Num] in {
foreach Num = 2-5 in { let ReleaseAtCycles = [Num] in {
def : WriteRes<!cast<SchedWrite>("FXa"#Num), [Z16_FXaUnit]>;
def : WriteRes<!cast<SchedWrite>("FXb"#Num), [Z16_FXbUnit]>;
def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z16_LSUnit]>;
Expand All @@ -104,8 +104,8 @@ let NumMicroOps = 0 in {
def : WriteRes<!cast<SchedWrite>("VecXsPm"#Num), [Z16_VecUnit]>;
}}

def : WriteRes<VecFPd, [Z16_VecFPdUnit]> { let ResourceCycles = [30]; }
def : WriteRes<VecFPd20, [Z16_VecFPdUnit]> { let ResourceCycles = [20]; }
def : WriteRes<VecFPd, [Z16_VecFPdUnit]> { let ReleaseAtCycles = [30]; }
def : WriteRes<VecFPd20, [Z16_VecFPdUnit]> { let ReleaseAtCycles = [20]; }

def : WriteRes<VBU, [Z16_VBUnit]>; // Virtual Branching Unit
}
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
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Original file line number Diff line number Diff line change
Expand Up @@ -82,7 +82,7 @@ let NumMicroOps = 0 in {
def : WriteRes<LSU, [Z196_LSUnit]>;
def : WriteRes<FPU, [Z196_FPUnit]>;
def : WriteRes<DFU, [Z196_DFUnit]>;
foreach Num = 2-6 in { let ResourceCycles = [Num] in {
foreach Num = 2-6 in { let ReleaseAtCycles = [Num] in {
def : WriteRes<!cast<SchedWrite>("FXU"#Num), [Z196_FXUnit]>;
def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z196_LSUnit]>;
def : WriteRes<!cast<SchedWrite>("FPU"#Num), [Z196_FPUnit]>;
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
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Original file line number Diff line number Diff line change
Expand Up @@ -83,7 +83,7 @@ let NumMicroOps = 0 in {
def : WriteRes<LSU, [ZEC12_LSUnit]>;
def : WriteRes<FPU, [ZEC12_FPUnit]>;
def : WriteRes<DFU, [ZEC12_DFUnit]>;
foreach Num = 2-6 in { let ResourceCycles = [Num] in {
foreach Num = 2-6 in { let ReleaseAtCycles = [Num] in {
def : WriteRes<!cast<SchedWrite>("FXU"#Num), [ZEC12_FXUnit]>;
def : WriteRes<!cast<SchedWrite>("LSU"#Num), [ZEC12_LSUnit]>;
def : WriteRes<!cast<SchedWrite>("FPU"#Num), [ZEC12_FPUnit]>;
Expand Down
292 changes: 146 additions & 146 deletions llvm/lib/Target/X86/X86SchedAlderlakeP.td
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282 changes: 141 additions & 141 deletions llvm/lib/Target/X86/X86SchedBroadwell.td
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304 changes: 152 additions & 152 deletions llvm/lib/Target/X86/X86SchedHaswell.td
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402 changes: 201 additions & 201 deletions llvm/lib/Target/X86/X86SchedIceLake.td
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186 changes: 93 additions & 93 deletions llvm/lib/Target/X86/X86SchedSandyBridge.td
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640 changes: 320 additions & 320 deletions llvm/lib/Target/X86/X86SchedSapphireRapids.td
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296 changes: 148 additions & 148 deletions llvm/lib/Target/X86/X86SchedSkylakeClient.td
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404 changes: 202 additions & 202 deletions llvm/lib/Target/X86/X86SchedSkylakeServer.td
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4 changes: 2 additions & 2 deletions llvm/lib/Target/X86/X86Schedule.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -27,13 +27,13 @@ def ReadInt2Fpu : SchedRead;
// load + WriteRMW.
def WriteRMW : SchedWrite;

// Helper to set SchedWrite ExePorts/Latency/ResourceCycles/NumMicroOps.
// Helper to set SchedWrite ExePorts/Latency/ReleaseAtCycles/NumMicroOps.
multiclass X86WriteRes<SchedWrite SchedRW,
list<ProcResourceKind> ExePorts,
int Lat, list<int> Res, int UOps> {
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
let ResourceCycles = Res;
let ReleaseAtCycles = Res;
let NumMicroOps = UOps;
}
}
Expand Down
136 changes: 68 additions & 68 deletions llvm/lib/Target/X86/X86ScheduleAtom.td
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134 changes: 67 additions & 67 deletions llvm/lib/Target/X86/X86ScheduleBdVer2.td
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50 changes: 25 additions & 25 deletions llvm/lib/Target/X86/X86ScheduleBtVer2.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -125,15 +125,15 @@ multiclass JWriteResIntPair<X86FoldableSchedWrite SchedRW,
// Register variant is using a single cycle on ExePort.
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
let ResourceCycles = Res;
let ReleaseAtCycles = Res;
let NumMicroOps = UOps;
}

// Memory variant also uses a cycle on JLAGU and adds 3 cycles to the
// latency.
def : WriteRes<SchedRW.Folded, !listconcat([JLAGU], ExePorts)> {
let Latency = !add(Lat, 3);
let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
let ReleaseAtCycles = !if(!empty(Res), [], !listconcat([1], Res));
let NumMicroOps = !add(UOps, LoadUOps);
}
}
Expand All @@ -145,15 +145,15 @@ multiclass JWriteResFpuPair<X86FoldableSchedWrite SchedRW,
// Register variant is using a single cycle on ExePort.
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
let ResourceCycles = Res;
let ReleaseAtCycles = Res;
let NumMicroOps = UOps;
}

// Memory variant also uses a cycle on JLAGU and adds 5 cycles to the
// latency.
def : WriteRes<SchedRW.Folded, !listconcat([JLAGU], ExePorts)> {
let Latency = !add(Lat, 5);
let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
let ReleaseAtCycles = !if(!empty(Res), [], !listconcat([1], Res));
let NumMicroOps = !add(UOps, LoadUOps);
}
}
Expand All @@ -165,15 +165,15 @@ multiclass JWriteResYMMPair<X86FoldableSchedWrite SchedRW,
// Register variant is using a single cycle on ExePort.
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
let ResourceCycles = Res;
let ReleaseAtCycles = Res;
let NumMicroOps = UOps;
}

// Memory variant also uses 2 cycles on JLAGU and adds 5 cycles to the
// latency.
def : WriteRes<SchedRW.Folded, !listconcat([JLAGU], ExePorts)> {
let Latency = !add(Lat, 5);
let ResourceCycles = !listconcat([2], Res);
let ReleaseAtCycles = !listconcat([2], Res);
let NumMicroOps = !add(UOps, LoadUOps);
}
}
Expand Down Expand Up @@ -313,49 +313,49 @@ def : WriteRes<WriteNop, [JALU01]> { let Latency = 1; }

def JWriteCMPXCHG8rr : SchedWriteRes<[JALU01]> {
let Latency = 3;
let ResourceCycles = [3];
let ReleaseAtCycles = [3];
let NumMicroOps = 3;
}

def JWriteLOCK_CMPXCHG8rm : SchedWriteRes<[JALU01, JLAGU, JSAGU]> {
let Latency = 16;
let ResourceCycles = [3,16,16];
let ReleaseAtCycles = [3,16,16];
let NumMicroOps = 5;
}

def JWriteLOCK_CMPXCHGrm : SchedWriteRes<[JALU01, JLAGU, JSAGU]> {
let Latency = 17;
let ResourceCycles = [3,17,17];
let ReleaseAtCycles = [3,17,17];
let NumMicroOps = 6;
}

def JWriteCMPXCHG8rm : SchedWriteRes<[JALU01, JLAGU, JSAGU]> {
let Latency = 11;
let ResourceCycles = [3,1,1];
let ReleaseAtCycles = [3,1,1];
let NumMicroOps = 5;
}

def JWriteCMPXCHG8B : SchedWriteRes<[JALU01, JLAGU, JSAGU]> {
let Latency = 11;
let ResourceCycles = [3,1,1];
let ReleaseAtCycles = [3,1,1];
let NumMicroOps = 18;
}

def JWriteCMPXCHG16B : SchedWriteRes<[JALU01, JLAGU, JSAGU]> {
let Latency = 32;
let ResourceCycles = [6,1,1];
let ReleaseAtCycles = [6,1,1];
let NumMicroOps = 28;
}

def JWriteLOCK_CMPXCHG8B : SchedWriteRes<[JALU01, JLAGU, JSAGU]> {
let Latency = 19;
let ResourceCycles = [3,19,19];
let ReleaseAtCycles = [3,19,19];
let NumMicroOps = 18;
}

def JWriteLOCK_CMPXCHG16B : SchedWriteRes<[JALU01, JLAGU, JSAGU]> {
let Latency = 38;
let ResourceCycles = [6,38,38];
let ReleaseAtCycles = [6,38,38];
let NumMicroOps = 28;
}

Expand Down Expand Up @@ -394,7 +394,7 @@ def : InstRW<[JWriteCMPXCHGVariant,

def JWriteLOCK_ALURMW : SchedWriteRes<[JALU01, JLAGU, JSAGU]> {
let Latency = 19;
let ResourceCycles = [1,19,19];
let ReleaseAtCycles = [1,19,19];
let NumMicroOps = 1;
}

Expand All @@ -409,7 +409,7 @@ def : InstRW<[JWriteLOCK_ALURMWVariant], (instrs INC8m, INC16m, INC32m, INC64m,

def JWriteXCHG8rr_XADDrr : SchedWriteRes<[JALU01]> {
let Latency = 2;
let ResourceCycles = [3];
let ReleaseAtCycles = [3];
let NumMicroOps = 3;
}
def : InstRW<[JWriteXCHG8rr_XADDrr], (instrs XCHG8rr, XADD8rr, XADD16rr,
Expand All @@ -434,7 +434,7 @@ def : InstRW<[JWriteXCHG8rr_XADDrr], (instrs XCHG8rr, XADD8rr, XADD16rr,
// latency is assumed to be 3cy.
def JWriteXADDrm_XCHG_Part : SchedWriteRes<[JALU01]> {
let Latency = 3; // load-to-use latency
let ResourceCycles = [3];
let ReleaseAtCycles = [3];
let NumMicroOps = 3;
}

Expand All @@ -451,7 +451,7 @@ def JWriteXADDrm_XCHG_Part : SchedWriteRes<[JALU01]> {
// execution. This write is used to specifically set that operand latency.
def JWriteLOCK_XADDrm_XCHG_Part : SchedWriteRes<[JALU01]> {
let Latency = 11;
let ResourceCycles = [3];
let ReleaseAtCycles = [3];
let NumMicroOps = 3;
}

Expand All @@ -463,19 +463,19 @@ def JWriteLOCK_XADDrm_XCHG_Part : SchedWriteRes<[JALU01]> {
// set the instruction latency to 16cy.
def JWriteXCHGrm_XCHG_Part : SchedWriteRes<[JALU01]> {
let Latency = 11;
let ResourceCycles = [2];
let ReleaseAtCycles = [2];
let NumMicroOps = 2;
}

def JWriteXADDrm_LdSt_Part : SchedWriteRes<[JLAGU, JSAGU]> {
let Latency = 11;
let ResourceCycles = [1, 1];
let ReleaseAtCycles = [1, 1];
let NumMicroOps = 1;
}

def JWriteXCHGrm_LdSt_Part : SchedWriteRes<[JLAGU, JSAGU]> {
let Latency = 16;
let ResourceCycles = [16, 16];
let ReleaseAtCycles = [16, 16];
let NumMicroOps = 1;
}

Expand Down Expand Up @@ -798,7 +798,7 @@ defm : JWriteResFpuPair<WriteCLMul, [JFPU0, JVIMUL], 2>;

def JWriteINSERTQ: SchedWriteRes<[JFPU01, JVALU]> {
let Latency = 2;
let ResourceCycles = [1, 4];
let ReleaseAtCycles = [1, 4];
}
def : InstRW<[JWriteINSERTQ], (instrs INSERTQ, INSERTQI)>;

Expand All @@ -811,7 +811,7 @@ def : InstRW<[JWriteVecExtractF128], (instrs VEXTRACTF128rr)>;

def JWriteVBROADCASTYLd: SchedWriteRes<[JLAGU, JFPU01, JFPX]> {
let Latency = 6;
let ResourceCycles = [1, 2, 4];
let ReleaseAtCycles = [1, 2, 4];
let NumMicroOps = 2;
}
def : InstRW<[JWriteVBROADCASTYLd], (instrs VBROADCASTSDYrm,
Expand All @@ -836,7 +836,7 @@ def : InstRW<[JWriteJVZEROUPPER], (instrs VZEROUPPER)>;

def JWriteMASKMOVDQU: SchedWriteRes<[JFPU0, JFPA, JFPU1, JSTC, JLAGU, JSAGU, JALU01]> {
let Latency = 34;
let ResourceCycles = [1, 1, 2, 2, 2, 16, 42];
let ReleaseAtCycles = [1, 1, 2, 2, 2, 16, 42];
let NumMicroOps = 63;
}
def : InstRW<[JWriteMASKMOVDQU], (instrs MASKMOVDQU, MASKMOVDQU64,
Expand Down Expand Up @@ -960,7 +960,7 @@ def : InstRW<[JWriteLEA], (instrs LEA32r, LEA64r, LEA64_32r)>;

def JSlowLEA16r : SchedWriteRes<[JALU01]> {
let Latency = 3;
let ResourceCycles = [4];
let ReleaseAtCycles = [4];
}

def : InstRW<[JSlowLEA16r], (instrs LEA16r)>;
Expand Down
16 changes: 8 additions & 8 deletions llvm/lib/Target/X86/X86ScheduleSLM.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -66,15 +66,15 @@ multiclass SLMWriteResPair<X86FoldableSchedWrite SchedRW,
// Register variant is using a single cycle on ExePort.
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
let ResourceCycles = Res;
let ReleaseAtCycles = Res;
let NumMicroOps = UOps;
}

// Memory variant also uses a cycle on MEC_RSV and adds LoadLat cycles to
// the latency (default = 3).
def : WriteRes<SchedRW.Folded, !listconcat([SLM_MEC_RSV], ExePorts)> {
let Latency = !add(Lat, LoadLat);
let ResourceCycles = !listconcat([1], Res);
let ReleaseAtCycles = !listconcat([1], Res);
let NumMicroOps = !add(UOps, LoadUOps);
}
}
Expand Down Expand Up @@ -139,7 +139,7 @@ defm : X86WriteRes<WriteFCMOV, [SLM_FPC_RSV1], 3, [1], 1>; // x87 conditional mo
def : WriteRes<WriteSETCC, [SLM_IEC_RSV01]>;
def : WriteRes<WriteSETCCStore, [SLM_IEC_RSV01, SLM_MEC_RSV]> {
// FIXME Latency and NumMicrOps?
let ResourceCycles = [2,1];
let ReleaseAtCycles = [2,1];
}
defm : X86WriteRes<WriteLAHFSAHF, [SLM_IEC_RSV01], 1, [1], 1>;
defm : X86WriteRes<WriteBitTest, [SLM_IEC_RSV0, SLM_IEC_RSV1], 1, [1,1], 1>;
Expand Down Expand Up @@ -413,7 +413,7 @@ def : WriteRes<WriteVecExtract, [SLM_FPC_RSV0]> {
def : WriteRes<WriteVecExtractSt, [SLM_FPC_RSV0, SLM_MEC_RSV]> {
let Latency = 4;
let NumMicroOps = 5;
let ResourceCycles = [1, 2];
let ReleaseAtCycles = [1, 2];
}

////////////////////////////////////////////////////////////////////////////////
Expand Down Expand Up @@ -465,7 +465,7 @@ def : WriteRes<WriteNop, []>;
def SLMWriteResGroup1rr : SchedWriteRes<[SLM_FPC_RSV01]> {
let Latency = 4;
let NumMicroOps = 2;
let ResourceCycles = [8];
let ReleaseAtCycles = [8];
}
def: InstRW<[SLMWriteResGroup1rr], (instrs MMX_PADDQrr, PADDQrr,
MMX_PSUBQrr, PSUBQrr,
Expand All @@ -474,14 +474,14 @@ def: InstRW<[SLMWriteResGroup1rr], (instrs MMX_PADDQrr, PADDQrr,
def SLMWriteResGroup2rr : SchedWriteRes<[SLM_FPC_RSV0]> {
let Latency = 5;
let NumMicroOps = 1;
let ResourceCycles = [2];
let ReleaseAtCycles = [2];
}
def: InstRW<[SLMWriteResGroup2rr], (instrs PCMPGTQrr)>;

def SLMWriteResGroup1rm : SchedWriteRes<[SLM_MEC_RSV,SLM_FPC_RSV01]> {
let Latency = 7;
let NumMicroOps = 3;
let ResourceCycles = [1,8];
let ReleaseAtCycles = [1,8];
}

def: InstRW<[SLMWriteResGroup1rm], (instrs MMX_PADDQrm, PADDQrm,
Expand All @@ -491,7 +491,7 @@ def: InstRW<[SLMWriteResGroup1rm], (instrs MMX_PADDQrm, PADDQrm,
def SLMWriteResGroup2rm : SchedWriteRes<[SLM_MEC_RSV,SLM_FPC_RSV0]> {
let Latency = 8;
let NumMicroOps = 2;
let ResourceCycles = [1,2];
let ReleaseAtCycles = [1,2];
}
def: InstRW<[SLMWriteResGroup2rm], (instrs PCMPGTQrm)>;

Expand Down
44 changes: 22 additions & 22 deletions llvm/lib/Target/X86/X86ScheduleZnver1.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -136,15 +136,15 @@ multiclass ZnWriteResPair<X86FoldableSchedWrite SchedRW,
// Register variant takes 1-cycle on Execution Port.
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
let ResourceCycles = Res;
let ReleaseAtCycles = Res;
let NumMicroOps = UOps;
}

// Memory variant also uses a cycle on ZnAGU
// adds LoadLat cycles to the latency (default = 4).
def : WriteRes<SchedRW.Folded, !listconcat([ZnAGU], ExePorts)> {
let Latency = !add(Lat, LoadLat);
let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
let ReleaseAtCycles = !if(!empty(Res), [], !listconcat([1], Res));
let NumMicroOps = !add(UOps, LoadUOps);
}
}
Expand All @@ -157,15 +157,15 @@ multiclass ZnWriteResFpuPair<X86FoldableSchedWrite SchedRW,
// Register variant takes 1-cycle on Execution Port.
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
let ResourceCycles = Res;
let ReleaseAtCycles = Res;
let NumMicroOps = UOps;
}

// Memory variant also uses a cycle on ZnAGU
// adds LoadLat cycles to the latency (default = 7).
def : WriteRes<SchedRW.Folded, !listconcat([ZnAGU], ExePorts)> {
let Latency = !add(Lat, LoadLat);
let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
let ReleaseAtCycles = !if(!empty(Res), [], !listconcat([1], Res));
let NumMicroOps = !add(UOps, LoadUOps);
}
}
Expand Down Expand Up @@ -455,12 +455,12 @@ defm : ZnWriteResFpuPair<WriteVecInsert, [ZnFPU], 1>;

def : WriteRes<WriteVecExtract, [ZnFPU12, ZnFPU2]> {
let Latency = 2;
let ResourceCycles = [1, 2];
let ReleaseAtCycles = [1, 2];
}
def : WriteRes<WriteVecExtractSt, [ZnAGU, ZnFPU12, ZnFPU2]> {
let Latency = 5;
let NumMicroOps = 2;
let ResourceCycles = [1, 2, 3];
let ReleaseAtCycles = [1, 2, 3];
}

// MOVMSK Instructions.
Expand All @@ -471,7 +471,7 @@ def : WriteRes<WriteVecMOVMSK, [ZnFPU2]>;
def : WriteRes<WriteVecMOVMSKY, [ZnFPU2]> {
let NumMicroOps = 2;
let Latency = 2;
let ResourceCycles = [2];
let ReleaseAtCycles = [2];
}

// AES Instructions.
Expand Down Expand Up @@ -869,7 +869,7 @@ def ZnWriteFPU03 : SchedWriteRes<[ZnAGU, ZnFPU03]>
{
let Latency = 12;
let NumMicroOps = 2;
let ResourceCycles = [1,3];
let ReleaseAtCycles = [1,3];
}

// FICOM(P).
Expand Down Expand Up @@ -910,12 +910,12 @@ def : InstRW<[ZnWriteFPU01Y], (instrs VPBLENDDYrri)>;
def ZnWriteFPU01Op2 : SchedWriteRes<[ZnAGU, ZnFPU01]> {
let NumMicroOps = 2;
let Latency = 8;
let ResourceCycles = [1, 2];
let ReleaseAtCycles = [1, 2];
}
def ZnWriteFPU01Op2Y : SchedWriteRes<[ZnAGU, ZnFPU01]> {
let NumMicroOps = 2;
let Latency = 9;
let ResourceCycles = [1, 3];
let ReleaseAtCycles = [1, 3];
}
def : InstRW<[ZnWriteFPU01Op2], (instrs VPBLENDDrmi)>;
def : InstRW<[ZnWriteFPU01Op2Y], (instrs VPBLENDDYrmi)>;
Expand All @@ -938,7 +938,7 @@ def : InstRW<[WriteMicrocoded], (instregex "VPMASKMOV(D|Q)(Y?)mr")>;
def ZnWriteVPBROADCAST128Ld : SchedWriteRes<[ZnAGU, ZnFPU12]> {
let Latency = 8;
let NumMicroOps = 2;
let ResourceCycles = [1, 2];
let ReleaseAtCycles = [1, 2];
}
def : InstRW<[ZnWriteVPBROADCAST128Ld],
(instregex "VPBROADCAST(B|W)rm")>;
Expand All @@ -947,7 +947,7 @@ def : InstRW<[ZnWriteVPBROADCAST128Ld],
def ZnWriteVPBROADCAST256Ld : SchedWriteRes<[ZnAGU, ZnFPU1]> {
let Latency = 8;
let NumMicroOps = 2;
let ResourceCycles = [1, 2];
let ReleaseAtCycles = [1, 2];
}
def : InstRW<[ZnWriteVPBROADCAST256Ld],
(instregex "VPBROADCAST(B|W)Yrm")>;
Expand Down Expand Up @@ -977,7 +977,7 @@ def ZnWritePCMPGTQm : SchedWriteRes<[ZnAGU, ZnFPU03]> {
def ZnWritePCMPGTQYm : SchedWriteRes<[ZnAGU, ZnFPU03]> {
let Latency = 8;
let NumMicroOps = 2;
let ResourceCycles = [1,2];
let ReleaseAtCycles = [1,2];
}
def : InstRW<[ZnWritePCMPGTQm], (instregex "(V?)PCMPGTQrm")>;
def : InstRW<[ZnWritePCMPGTQYm], (instrs VPCMPGTQYrm)>;
Expand All @@ -1004,14 +1004,14 @@ def : InstRW<[ZnWriteBROADCAST], (instrs VBROADCASTF128,
def ZnWriteEXTRACTPSr : SchedWriteRes<[ZnFPU12, ZnFPU2]> {
let Latency = 2;
let NumMicroOps = 2;
let ResourceCycles = [1, 2];
let ReleaseAtCycles = [1, 2];
}
def : InstRW<[ZnWriteEXTRACTPSr], (instregex "(V?)EXTRACTPSrr")>;

def ZnWriteEXTRACTPSm : SchedWriteRes<[ZnAGU,ZnFPU12, ZnFPU2]> {
let Latency = 5;
let NumMicroOps = 2;
let ResourceCycles = [5, 1, 2];
let ReleaseAtCycles = [5, 1, 2];
}
// m32,x,i.
def : InstRW<[ZnWriteEXTRACTPSm], (instregex "(V?)EXTRACTPSmr")>;
Expand All @@ -1027,12 +1027,12 @@ def : InstRW<[ZnWriteFPU013m], (instrs VEXTRACTF128mr,

def ZnWriteVINSERT128r: SchedWriteRes<[ZnFPU013]> {
let Latency = 2;
let ResourceCycles = [2];
let ReleaseAtCycles = [2];
}
def ZnWriteVINSERT128Ld: SchedWriteRes<[ZnAGU,ZnFPU013]> {
let Latency = 9;
let NumMicroOps = 2;
let ResourceCycles = [1, 2];
let ReleaseAtCycles = [1, 2];
}
// VINSERTF128 / VINSERTI128.
// y,y,x,i.
Expand All @@ -1051,7 +1051,7 @@ def ZnWriteCVTPD2PSr: SchedWriteRes<[ZnFPU3]> {
def ZnWriteCVTPD2PSYr: SchedWriteRes<[ZnFPU3]> {
let Latency = 5;
let NumMicroOps = 2;
let ResourceCycles = [2];
let ReleaseAtCycles = [2];
}

// CVTPD2PS.
Expand All @@ -1072,7 +1072,7 @@ def : SchedAlias<WriteCvtPD2PSLd, ZnWriteCVTPD2PSLd>;
def ZnWriteCVTPD2PSYLd : SchedWriteRes<[ZnAGU, ZnFPU3]> {
let Latency = 11;
let NumMicroOps = 2;
let ResourceCycles = [1,2];
let ReleaseAtCycles = [1,2];
}
def : SchedAlias<WriteCvtPD2PSYLd, ZnWriteCVTPD2PSYLd>;
// z,m512
Expand Down Expand Up @@ -1121,7 +1121,7 @@ def : SchedAlias<WriteCvtSS2SD, ZnWriteCVTSS2SDr>;
def ZnWriteCVTSS2SDLd : SchedWriteRes<[ZnAGU, ZnFPU3]> {
let Latency = 11;
let NumMicroOps = 2;
let ResourceCycles = [1, 2];
let ReleaseAtCycles = [1, 2];
}
def : SchedAlias<WriteCvtSS2SDLd, ZnWriteCVTSS2SDLd>;

Expand Down Expand Up @@ -1243,13 +1243,13 @@ def : InstRW<[WriteMicrocoded], (instregex "SHA256MSG2(Y?)r(r|m)")>;
// x,x.
def ZnWriteSHA1MSG1r : SchedWriteRes<[ZnFPU12]> {
let Latency = 2;
let ResourceCycles = [2];
let ReleaseAtCycles = [2];
}
def : InstRW<[ZnWriteSHA1MSG1r], (instregex "SHA(1|256)MSG1rr")>;
// x,m.
def ZnWriteSHA1MSG1Ld : SchedWriteRes<[ZnAGU, ZnFPU12]> {
let Latency = 9;
let ResourceCycles = [1,2];
let ReleaseAtCycles = [1,2];
}
def : InstRW<[ZnWriteSHA1MSG1Ld], (instregex "SHA(1|256)MSG1rm")>;

Expand Down
32 changes: 16 additions & 16 deletions llvm/lib/Target/X86/X86ScheduleZnver2.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -135,15 +135,15 @@ multiclass Zn2WriteResPair<X86FoldableSchedWrite SchedRW,
// Register variant takes 1-cycle on Execution Port.
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
let ResourceCycles = Res;
let ReleaseAtCycles = Res;
let NumMicroOps = UOps;
}

// Memory variant also uses a cycle on Zn2AGU
// adds LoadLat cycles to the latency (default = 4).
def : WriteRes<SchedRW.Folded, !listconcat([Zn2AGU], ExePorts)> {
let Latency = !add(Lat, LoadLat);
let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
let ReleaseAtCycles = !if(!empty(Res), [], !listconcat([1], Res));
let NumMicroOps = !add(UOps, LoadUOps);
}
}
Expand All @@ -156,15 +156,15 @@ multiclass Zn2WriteResFpuPair<X86FoldableSchedWrite SchedRW,
// Register variant takes 1-cycle on Execution Port.
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
let ResourceCycles = Res;
let ReleaseAtCycles = Res;
let NumMicroOps = UOps;
}

// Memory variant also uses a cycle on Zn2AGU
// adds LoadLat cycles to the latency (default = 7).
def : WriteRes<SchedRW.Folded, !listconcat([Zn2AGU], ExePorts)> {
let Latency = !add(Lat, LoadLat);
let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
let ReleaseAtCycles = !if(!empty(Res), [], !listconcat([1], Res));
let NumMicroOps = !add(UOps, LoadUOps);
}
}
Expand Down Expand Up @@ -454,12 +454,12 @@ defm : Zn2WriteResFpuPair<WriteVecInsert, [Zn2FPU], 1>;

def : WriteRes<WriteVecExtract, [Zn2FPU12, Zn2FPU2]> {
let Latency = 2;
let ResourceCycles = [1, 2];
let ReleaseAtCycles = [1, 2];
}
def : WriteRes<WriteVecExtractSt, [Zn2AGU, Zn2FPU12, Zn2FPU2]> {
let Latency = 5;
let NumMicroOps = 2;
let ResourceCycles = [1, 2, 3];
let ReleaseAtCycles = [1, 2, 3];
}

// MOVMSK Instructions.
Expand All @@ -470,7 +470,7 @@ def : WriteRes<WriteVecMOVMSK, [Zn2FPU2]>;
def : WriteRes<WriteVecMOVMSKY, [Zn2FPU2]> {
let NumMicroOps = 2;
let Latency = 2;
let ResourceCycles = [2];
let ReleaseAtCycles = [2];
}

// AES Instructions.
Expand Down Expand Up @@ -879,7 +879,7 @@ def Zn2WriteFPU03 : SchedWriteRes<[Zn2AGU, Zn2FPU03]>
{
let Latency = 12;
let NumMicroOps = 2;
let ResourceCycles = [1,3];
let ReleaseAtCycles = [1,3];
}

// FICOM(P).
Expand Down Expand Up @@ -920,12 +920,12 @@ def : InstRW<[Zn2WriteFPU01Y], (instrs VPBLENDDYrri)>;
def Zn2WriteFPU01Op2 : SchedWriteRes<[Zn2AGU, Zn2FPU01]> {
let NumMicroOps = 2;
let Latency = 8;
let ResourceCycles = [1, 2];
let ReleaseAtCycles = [1, 2];
}
def Zn2WriteFPU01Op2Y : SchedWriteRes<[Zn2AGU, Zn2FPU01]> {
let NumMicroOps = 2;
let Latency = 9;
let ResourceCycles = [1, 3];
let ReleaseAtCycles = [1, 3];
}
def : InstRW<[Zn2WriteFPU01Op2], (instrs VPBLENDDrmi)>;
def : InstRW<[Zn2WriteFPU01Op2Y], (instrs VPBLENDDYrmi)>;
Expand All @@ -948,7 +948,7 @@ def : InstRW<[WriteMicrocoded], (instregex "VPMASKMOV(D|Q)(Y?)mr")>;
def Zn2WriteVPBROADCAST128Ld : SchedWriteRes<[Zn2AGU, Zn2FPU12]> {
let Latency = 8;
let NumMicroOps = 2;
let ResourceCycles = [1, 2];
let ReleaseAtCycles = [1, 2];
}
def : InstRW<[Zn2WriteVPBROADCAST128Ld],
(instregex "VPBROADCAST(B|W)rm")>;
Expand All @@ -957,7 +957,7 @@ def : InstRW<[Zn2WriteVPBROADCAST128Ld],
def Zn2WriteVPBROADCAST256Ld : SchedWriteRes<[Zn2AGU, Zn2FPU1]> {
let Latency = 8;
let NumMicroOps = 2;
let ResourceCycles = [1, 2];
let ReleaseAtCycles = [1, 2];
}
def : InstRW<[Zn2WriteVPBROADCAST256Ld],
(instregex "VPBROADCAST(B|W)Yrm")>;
Expand Down Expand Up @@ -1012,14 +1012,14 @@ def : InstRW<[Zn2WriteBROADCAST], (instrs VBROADCASTF128,
def Zn2WriteEXTRACTPSr : SchedWriteRes<[Zn2FPU12, Zn2FPU2]> {
let Latency = 2;
let NumMicroOps = 2;
let ResourceCycles = [1, 2];
let ReleaseAtCycles = [1, 2];
}
def : InstRW<[Zn2WriteEXTRACTPSr], (instregex "(V?)EXTRACTPSrr")>;

def Zn2WriteEXTRACTPSm : SchedWriteRes<[Zn2AGU,Zn2FPU12, Zn2FPU2]> {
let Latency = 5;
let NumMicroOps = 2;
let ResourceCycles = [5, 1, 2];
let ReleaseAtCycles = [5, 1, 2];
}
// m32,x,i.
def : InstRW<[Zn2WriteEXTRACTPSm], (instregex "(V?)EXTRACTPSmr")>;
Expand All @@ -1035,7 +1035,7 @@ def : InstRW<[Zn2WriteFPU013m], (instrs VEXTRACTF128mr,

def Zn2WriteVINSERT128r: SchedWriteRes<[Zn2FPU013]> {
let Latency = 2;
// let ResourceCycles = [2];
// let ReleaseAtCycles = [2];
}
def Zn2WriteVINSERT128Ld: SchedWriteRes<[Zn2AGU,Zn2FPU013]> {
let Latency = 9;
Expand Down Expand Up @@ -1124,7 +1124,7 @@ def : SchedAlias<WriteCvtSS2SD, Zn2WriteCVTSS2SDr>;
def Zn2WriteCVTSS2SDLd : SchedWriteRes<[Zn2AGU, Zn2FPU3]> {
let Latency = 10;
let NumMicroOps = 2;
let ResourceCycles = [1, 2];
let ReleaseAtCycles = [1, 2];
}
def : SchedAlias<WriteCvtSS2SDLd, Zn2WriteCVTSS2SDLd>;

Expand Down
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