30 changes: 15 additions & 15 deletions llvm/test/Analysis/RegionInfo/infinite_loop_3.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -6,35 +6,35 @@
; RUN: opt -regions -print-region-style=rn -analyze < %s 2>&1 | FileCheck -check-prefix=RNIT %s

define void @normal_condition() nounwind {
0:
"0":
br label %"7"
7:
"7":
br i1 1, label %"1", label %"8"
1:
"1":
br i1 1, label %"2", label %"3"
2:
"2":
br label %"5"
5:
"5":
br i1 1, label %"11", label %"12"
11:
"11":
br label %"6"
12:
"12":
br label %"6"
6:
"6":
br label %"2"
8:
"8":
br label %"9"
9:
"9":
br i1 1, label %"13", label %"14"
13:
"13":
br label %"10"
14:
"14":
br label %"10"
10:
"10":
br label %"8"
3:
"3":
br label %"4"
4:
"4":
ret void
}
; CHECK-NOT: =>
Expand Down
32 changes: 16 additions & 16 deletions llvm/test/Analysis/RegionInfo/infinite_loop_4.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,35 +5,35 @@
; RUN: opt -regions -print-region-style=rn -analyze < %s 2>&1 | FileCheck -check-prefix=RNIT %s

define void @normal_condition() nounwind {
0:
"0":
br label %"7"
7:
"7":
br i1 1, label %"1", label %"8"
1:
"1":
br i1 1, label %"2", label %"3"
2:
"2":
br label %"5"
5:
"5":
br i1 1, label %"11", label %"12"
11:
"11":
br label %"6"
12:
"12":
br label %"6"
6:
"6":
br i1 1, label %"2", label %"10"
8:
"8":
br label %"9"
9:
"9":
br i1 1, label %"13", label %"14"
13:
"13":
br label %"10"
14:
"14":
br label %"10"
10:
"10":
br label %"8"
3:
"3":
br label %"4"
4:
"4":
ret void
}
; CHECK-NOT: =>
Expand All @@ -48,4 +48,4 @@ define void @normal_condition() nounwind {
; BBIT: 5, 11, 12,
; RNIT: 0, 7, 1, 2 => 10, 10, 8, 9, 13, 14, 3, 4,
; RNIT: 2, 5 => 6, 6,
; RNIT: 5, 11, 12,
; RNIT: 5, 11, 12,
14 changes: 7 additions & 7 deletions llvm/test/Analysis/RegionInfo/infinite_loop_5_a.ll
View file
Original file line number Diff line number Diff line change
@@ -1,19 +1,19 @@
; RUN: opt -regions -analyze < %s | FileCheck %s

define void @normal_condition() nounwind {
0:
"0":
br label %"7"
7:
"7":
br i1 1, label %"1", label %"8"
1:
"1":
br i1 1, label %"6", label %"3"
6:
"6":
br label %"8"
8:
"8":
br label %"8"
3:
"3":
br label %"4"
4:
"4":
ret void
}

Expand Down
16 changes: 8 additions & 8 deletions llvm/test/Analysis/RegionInfo/infinite_loop_5_b.ll
View file
Original file line number Diff line number Diff line change
@@ -1,21 +1,21 @@
; RUN: opt -regions -analyze < %s | FileCheck %s

define void @normal_condition() nounwind {
0:
"0":
br label %"7"
7:
"7":
br i1 1, label %"1", label %"9"
9:
"9":
br label %"8"
1:
"1":
br i1 1, label %"6", label %"3"
6:
"6":
br label %"9"
8:
"8":
br label %"8"
3:
"3":
br label %"4"
4:
"4":
ret void
}

Expand Down
14 changes: 7 additions & 7 deletions llvm/test/Analysis/RegionInfo/infinite_loop_5_c.ll
View file
Original file line number Diff line number Diff line change
@@ -1,19 +1,19 @@
; RUN: opt -regions -analyze < %s | FileCheck %s

define void @normal_condition() nounwind {
0:
"0":
br label %"7"
7:
"7":
br i1 1, label %"1", label %"8"
1:
"1":
br i1 1, label %"6", label %"3"
6:
"6":
br label %"8"
8:
"8":
br i1 1, label %"8", label %"7"
3:
"3":
br label %"4"
4:
"4":
ret void
}

Expand Down
20 changes: 10 additions & 10 deletions llvm/test/Analysis/RegionInfo/loop_with_condition.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,25 +8,25 @@
; RUN: opt < %s -passes='print<regions>' 2>&1 | FileCheck %s

define void @normal_condition() nounwind {
0:
"0":
br label %"1"
1:
"1":
br i1 1, label %"6", label %"2"
2:
"2":
br i1 1, label %"3", label %"4"
3:
"3":
br label %"5"
4:
"4":
br label %"5"
5:
"5":
br label %"8"
8:
"8":
br i1 1, label %"7", label %"9"
9:
"9":
br label %"2"
7:
"7":
br label %"6"
6:
"6":
ret void
}

Expand Down
38 changes: 19 additions & 19 deletions llvm/test/Analysis/RegionInfo/mix_1.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,45 +8,45 @@
; RUN: opt < %s -passes='print<regions>' 2>&1 | FileCheck %s

define void @a_linear_impl_fig_1() nounwind {
0:
"0":

br i1 1, label %"1", label %"15"
1:
"1":
switch i32 0, label %"2" [ i32 0, label %"3"
i32 1, label %"7"]
2:
"2":
br label %"4"
3:
"3":
br label %"5"
4:
"4":
br label %"6"
5:
"5":
br label %"6"
6:
"6":
br label %"7"
7:
"7":
br label %"15"
15:
"15":
br label %"8"
8:
"8":
br label %"16"
16:
"16":
br label %"9"
9:
"9":
br i1 1, label %"10", label %"11"
11:
"11":
br i1 1, label %"13", label %"12"
13:
"13":
br label %"14"
12:
"12":
br label %"14"
14:
"14":
br label %"8"
10:
"10":
br label %"17"
17:
"17":
br label %"18"
18:
"18":
ret void
}

Expand Down
28 changes: 14 additions & 14 deletions llvm/test/Analysis/RegionInfo/paper.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,33 +7,33 @@
; RUN: opt < %s -passes='print<regions>' 2>&1 | FileCheck %s

define void @a_linear_impl_fig_1() nounwind {
0:
"0":
br label %"1"
1:
"1":
br label %"2"
2:
"2":
br label %"3"
3:
"3":
br i1 1, label %"13", label %"4"
4:
"4":
br i1 1, label %"5", label %"1"
5:
"5":
br i1 1, label %"8", label %"6"
6:
"6":
br i1 1, label %"7", label %"4"
7:
"7":
ret void
8:
"8":
br i1 1, label %"9", label %"1"
9:
"9":
br label %"10"
10:
"10":
br i1 1, label %"12", label %"11"
11:
"11":
br i1 1, label %"9", label %"8"
13:
"13":
br i1 1, label %"2", label %"1"
12:
"12":
switch i32 0, label %"1" [ i32 0, label %"9"
i32 1, label %"8"]
}
Expand Down
48 changes: 48 additions & 0 deletions llvm/test/Assembler/block-labels.ll
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Original file line number Diff line number Diff line change
@@ -0,0 +1,48 @@
; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s --match-full-lines
; RUN: verify-uselistorder %s

define i32 @test1(i32 %X) {
; Implicit entry label. Not printed on output.
%1 = alloca i32
br label %2
; Implicit label ids still allowed.
br label %3
3: ; Explicit numeric label
br label %"2"
"2": ; string label, quoted number
br label %-3
-3: ; numeric-looking, but actually string, label
br label %-N-
-N-:
br label %$N
$N:
%4 = add i32 1, 1
ret i32 %4
}

; CHECK-LABEL: define i32 @test1(i32 %X) {
; CHECK-NEXT: %1 = alloca i32
; CHECK-NEXT: br label %2
; CHECK: 2: ; preds = %0
; CHECK-NEXT: br label %3
; CHECK: 3: ; preds = %2
; CHECK-NEXT: br label %"2"
; CHECK: "2": ; preds = %3
; CHECK-NEXT: br label %-3
; CHECK: -3: ; preds = %"2"
; CHECK-NEXT: br label %-N-
; CHECK: -N-: ; preds = %-3
; CHECK-NEXT: br label %"$N"
; CHECK: "$N": ; preds = %-N-
; CHECK-NEXT: %4 = add i32 1, 1
; CHECK-NEXT: ret i32 %4
; CHECK-NEXT: }

define void @test2(i32, i32) {
; entry label id still not printed on output
2:
ret void
}

; CHECK-LABEL: define void @test2(i32, i32) {
; CHECK-NEXT: ret void
7 changes: 7 additions & 0 deletions llvm/test/Assembler/invalid-block-label-num.ll
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,7 @@
; RUN: not llvm-as < %s 2>&1 | FileCheck %s

define void @f () {
1:
; CHECK: error: label expected to be numbered '0'
ret void
}
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/X86/atomic-pointer.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@ define i32* @test_atomic_ptr_load(i32** %a0) {
; CHECK: movl
; CHECK: movl
; CHECK: ret
0:
entry:
%0 = load atomic i32*, i32** %a0 seq_cst, align 4
ret i32* %0
}
Expand All @@ -16,7 +16,7 @@ define void @test_atomic_ptr_store(i32* %a0, i32** %a1) {
; CHECK: movl
; CHECK: xchgl
; CHECK: ret
0:
store atomic i32* %a0, i32** %a1 seq_cst, align 4
entry:
store atomic i32* %a0, i32** %a1 seq_cst, align 4
ret void
}
32 changes: 16 additions & 16 deletions llvm/test/Instrumentation/AddressSanitizer/asan-masked-load-store.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -75,39 +75,39 @@ define void @store.v4f32.variable(<4 x float> %arg, <4 x i1> %mask) sanitize_add
%p = load <4 x float>*, <4 x float>** @v4f32, align 8
; STORE: [[MASK0:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 0
; STORE: br i1 [[MASK0]], label %[[THEN0:[0-9A-Za-z]+]], label %[[AFTER0:[0-9A-Za-z]+]]
; STORE: <label>:[[THEN0]]:
; STORE: [[THEN0]]:
; STORE: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 0
; STORE: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP0]] to i64
; STORE: call void @__asan_store4(i64 [[PGEP0]])
; STORE: br label %[[AFTER0]]
; STORE: <label>:[[AFTER0]]
; STORE: [[AFTER0]]:

; STORE: [[MASK1:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 1
; STORE: br i1 [[MASK1]], label %[[THEN1:[0-9A-Za-z]+]], label %[[AFTER1:[0-9A-Za-z]+]]
; STORE: <label>:[[THEN1]]:
; STORE: [[THEN1]]:
; STORE: [[GEP1:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 1
; STORE: [[PGEP1:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP1]] to i64
; STORE: call void @__asan_store4(i64 [[PGEP1]])
; STORE: br label %[[AFTER1]]
; STORE: <label>:[[AFTER1]]
; STORE: [[AFTER1]]:

; STORE: [[MASK2:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 2
; STORE: br i1 [[MASK2]], label %[[THEN2:[0-9A-Za-z]+]], label %[[AFTER2:[0-9A-Za-z]+]]
; STORE: <label>:[[THEN2]]:
; STORE: [[THEN2]]:
; STORE: [[GEP2:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 2
; STORE: [[PGEP2:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP2]] to i64
; STORE: call void @__asan_store4(i64 [[PGEP2]])
; STORE: br label %[[AFTER2]]
; STORE: <label>:[[AFTER2]]
; STORE: [[AFTER2]]:

; STORE: [[MASK3:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 3
; STORE: br i1 [[MASK3]], label %[[THEN3:[0-9A-Za-z]+]], label %[[AFTER3:[0-9A-Za-z]+]]
; STORE: <label>:[[THEN3]]:
; STORE: [[THEN3]]:
; STORE: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 3
; STORE: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP3]] to i64
; STORE: call void @__asan_store4(i64 [[PGEP3]])
; STORE: br label %[[AFTER3]]
; STORE: <label>:[[AFTER3]]
; STORE: [[AFTER3]]:

; STORE: tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> %mask)
tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> %mask)
Expand Down Expand Up @@ -203,39 +203,39 @@ define <4 x float> @load.v4f32.variable(<4 x float> %arg, <4 x i1> %mask) saniti
%p = load <4 x float>*, <4 x float>** @v4f32, align 8
; LOAD: [[MASK0:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 0
; LOAD: br i1 [[MASK0]], label %[[THEN0:[0-9A-Za-z]+]], label %[[AFTER0:[0-9A-Za-z]+]]
; LOAD: <label>:[[THEN0]]:
; LOAD: [[THEN0]]:
; LOAD: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 0
; LOAD: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP0]] to i64
; LOAD: call void @__asan_load4(i64 [[PGEP0]])
; LOAD: br label %[[AFTER0]]
; LOAD: <label>:[[AFTER0]]
; LOAD: [[AFTER0]]:

; LOAD: [[MASK1:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 1
; LOAD: br i1 [[MASK1]], label %[[THEN1:[0-9A-Za-z]+]], label %[[AFTER1:[0-9A-Za-z]+]]
; LOAD: <label>:[[THEN1]]:
; LOAD: [[THEN1]]:
; LOAD: [[GEP1:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 1
; LOAD: [[PGEP1:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP1]] to i64
; LOAD: call void @__asan_load4(i64 [[PGEP1]])
; LOAD: br label %[[AFTER1]]
; LOAD: <label>:[[AFTER1]]
; LOAD: [[AFTER1]]:

; LOAD: [[MASK2:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 2
; LOAD: br i1 [[MASK2]], label %[[THEN2:[0-9A-Za-z]+]], label %[[AFTER2:[0-9A-Za-z]+]]
; LOAD: <label>:[[THEN2]]:
; LOAD: [[THEN2]]:
; LOAD: [[GEP2:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 2
; LOAD: [[PGEP2:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP2]] to i64
; LOAD: call void @__asan_load4(i64 [[PGEP2]])
; LOAD: br label %[[AFTER2]]
; LOAD: <label>:[[AFTER2]]
; LOAD: [[AFTER2]]:

; LOAD: [[MASK3:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 3
; LOAD: br i1 [[MASK3]], label %[[THEN3:[0-9A-Za-z]+]], label %[[AFTER3:[0-9A-Za-z]+]]
; LOAD: <label>:[[THEN3]]:
; LOAD: [[THEN3]]:
; LOAD: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 3
; LOAD: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP3]] to i64
; LOAD: call void @__asan_load4(i64 [[PGEP3]])
; LOAD: br label %[[AFTER3]]
; LOAD: <label>:[[AFTER3]]
; LOAD: [[AFTER3]]:

; LOAD: tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> %mask, <4 x float> %arg)
%res = tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> %mask, <4 x float> %arg)
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/Instrumentation/AddressSanitizer/stack-poisoning-and-lifetime-be.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -159,14 +159,14 @@ entry:

; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 40, i8* %zz)

; CHECK-LABEL: <label>
; CHECK: {{^[0-9]+}}:

; CHECK-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 0
; CHECK-NEXT: call void @__asan_set_shadow_f5(i64 [[OFFSET]], i64 128)

; CHECK-NOT: add i64 [[SHADOW_BASE]]

; CHECK-LABEL: <label>
; CHECK: {{^[0-9]+}}:

; 00000000
; EXIT-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 0
Expand Down Expand Up @@ -205,7 +205,7 @@ entry:
; CHECK-NOT: add i64 [[SHADOW_BASE]]

ret void
; CHECK-LABEL: <label>
; CHECK: {{^[0-9]+}}:
; CHECK: ret void
}

Expand Down
6 changes: 3 additions & 3 deletions llvm/test/Instrumentation/AddressSanitizer/stack-poisoning-and-lifetime.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -159,14 +159,14 @@ entry:

; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 40, i8* %zz)

; CHECK-LABEL: <label>
; CHECK: {{^[0-9]+}}:

; CHECK-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 0
; CHECK-NEXT: call void @__asan_set_shadow_f5(i64 [[OFFSET]], i64 128)

; CHECK-NOT: add i64 [[SHADOW_BASE]]

; CHECK-LABEL: <label>
; CHECK: {{^[0-9]+}}:

; 00000000
; EXIT-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 0
Expand Down Expand Up @@ -205,7 +205,7 @@ entry:
; CHECK-NOT: add i64 [[SHADOW_BASE]]

ret void
; CHECK-LABEL: <label>
; CHECK: {{^[0-9]+}}:
; CHECK: ret void
}

Expand Down
6 changes: 3 additions & 3 deletions llvm/test/Instrumentation/AddressSanitizer/stack_dynamic_alloca.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -12,14 +12,14 @@ entry:
; CHECK: entry:
; CHECK: load i32, i32* @__asan_option_detect_stack_use_after_return

; CHECK: <label>:[[UAR_ENABLED_BB:[0-9]+]]
; CHECK: [[UAR_ENABLED_BB:^[0-9]+]]:
; CHECK: [[FAKE_STACK_RT:%[0-9]+]] = call i64 @__asan_stack_malloc_

; CHECK: <label>:[[FAKE_STACK_BB:[0-9]+]]
; CHECK: [[FAKE_STACK_BB:^[0-9]+]]:
; CHECK: [[FAKE_STACK:%[0-9]+]] = phi i64 [ 0, %entry ], [ [[FAKE_STACK_RT]], %[[UAR_ENABLED_BB]] ]
; CHECK: icmp eq i64 [[FAKE_STACK]], 0

; CHECK: <label>:[[NO_FAKE_STACK_BB:[0-9]+]]
; CHECK: [[NO_FAKE_STACK_BB:^[0-9]+]]:
; CHECK: %MyAlloca = alloca i8, i64
; CHECK: [[ALLOCA:%[0-9]+]] = ptrtoint i8* %MyAlloca

Expand Down
4 changes: 2 additions & 2 deletions llvm/test/Instrumentation/MemorySanitizer/check_access_address.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -44,9 +44,9 @@ entry:
; CHECK-NOT: xor
; CHECK: icmp
; CHECK: br i1
; CHECK: <label>
; CHECK: {{^[0-9]+}}:
; CHECK: call void @__msan_warning_noreturn
; CHECK: <label>
; CHECK: {{^[0-9]+}}:
; CHECK: xor
; CHECK: store
; CHECK: store i32 %x
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -39,10 +39,10 @@ entry:
; CHECK: store
; CHECK-ORIGINS: icmp
; CHECK-ORIGINS: br i1
; CHECK-ORIGINS: <label>
; CHECK-ORIGINS: {{^[0-9]+}}:
; CHECK-ORIGINS: store
; CHECK-ORIGINS: br label
; CHECK-ORIGINS: <label>
; CHECK-ORIGINS: {{^[0-9]+}}:
; CHECK: store
; CHECK: ret void

Expand All @@ -63,10 +63,10 @@ entry:
; CHECK: store {{.*}} align 32
; CHECK-ORIGINS: icmp
; CHECK-ORIGINS: br i1
; CHECK-ORIGINS: <label>
; CHECK-ORIGINS: {{^[0-9]+}}:
; CHECK-ORIGINS: store {{.*}} align 32
; CHECK-ORIGINS: br label
; CHECK-ORIGINS: <label>
; CHECK-ORIGINS: {{^[0-9]+}}:
; CHECK: store {{.*}} align 32
; CHECK: ret void

Expand Down
86 changes: 43 additions & 43 deletions llvm/test/Instrumentation/MemorySanitizer/msan_kernel_basic.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -40,29 +40,29 @@ entry:
}

; CHECK-LABEL: @Store1
; CHECK-LABEL: entry:
; CHECK: entry:
; CHECK: @__msan_get_context_state()
; CHECK: [[PARAM_SHADOW:%[a-z0-9_]+]] = getelementptr {{.*}} i32 0, i32 0
; CHECK-LABEL: entry.split:
; CHECK: entry.split:
; CHECK: [[BASE2:%[0-9]+]] = ptrtoint {{.*}} [[PARAM_SHADOW]]
; CHECK: [[BASE:%[0-9]+]] = ptrtoint {{.*}} [[PARAM_SHADOW]]
; CHECK: [[SHADOW:%[a-z0-9_]+]] = inttoptr {{.*}} [[BASE]]
; Load the shadow of %p and check it
; CHECK: load i64, i64* [[SHADOW]]
; CHECK: icmp
; CHECK: br i1
; CHECK-LABEL: <label>
; CHECK: {{^[0-9]+}}:
; CHECK: @__msan_metadata_ptr_for_store_1(i8* %p)
; CHECK: store i8
; If the new shadow is non-zero, jump to __msan_chain_origin()
; CHECK: icmp
; CHECK: br i1
; CHECK: <label>
; CHECK: {{^[0-9]+}}:
; CHECK: @__msan_chain_origin
; Storing origin here:
; CHECK: store i32
; CHECK: br label
; CHECK: <label>
; CHECK: {{^[0-9]+}}:
; CHECK: store i8
; CHECK: ret void

Expand All @@ -73,28 +73,28 @@ entry:
}

; CHECK-LABEL: @Store2
; CHECK-LABEL: entry:
; CHECK: entry:
; CHECK: @__msan_get_context_state()
; CHECK: [[PARAM_SHADOW:%[a-z0-9_]+]] = getelementptr {{.*}} i32 0, i32 0
; CHECK-LABEL: entry.split:
; CHECK: entry.split:
; CHECK: ptrtoint {{.*}} [[PARAM_SHADOW]]
; Load the shadow of %p and check it
; CHECK: load i64
; CHECK: icmp
; CHECK: br i1
; CHECK-LABEL: <label>
; CHECK: {{^[0-9]+}}:
; CHECK: [[REG:%[0-9]+]] = bitcast i16* %p to i8*
; CHECK: @__msan_metadata_ptr_for_store_2(i8* [[REG]])
; CHECK: store i16
; If the new shadow is non-zero, jump to __msan_chain_origin()
; CHECK: icmp
; CHECK: br i1
; CHECK: <label>
; CHECK: {{^[0-9]+}}:
; CHECK: @__msan_chain_origin
; Storing origin here:
; CHECK: store i32
; CHECK: br label
; CHECK: <label>
; CHECK: {{^[0-9]+}}:
; CHECK: store i16
; CHECK: ret void

Expand All @@ -106,28 +106,28 @@ entry:
}

; CHECK-LABEL: @Store4
; CHECK-LABEL: entry:
; CHECK: entry:
; CHECK: @__msan_get_context_state()
; CHECK: [[PARAM_SHADOW:%[a-z0-9_]+]] = getelementptr {{.*}} i32 0, i32 0
; CHECK-LABEL: entry.split:
; CHECK: entry.split:
; CHECK: ptrtoint {{.*}} [[PARAM_SHADOW]]
; Load the shadow of %p and check it
; CHECK: load i32
; CHECK: icmp
; CHECK: br i1
; CHECK-LABEL: <label>
; CHECK: {{^[0-9]+}}:
; CHECK: [[REG:%[0-9]+]] = bitcast i32* %p to i8*
; CHECK: @__msan_metadata_ptr_for_store_4(i8* [[REG]])
; CHECK: store i32
; If the new shadow is non-zero, jump to __msan_chain_origin()
; CHECK: icmp
; CHECK: br i1
; CHECK: <label>
; CHECK: {{^[0-9]+}}:
; CHECK: @__msan_chain_origin
; Storing origin here:
; CHECK: store i32
; CHECK: br label
; CHECK: <label>
; CHECK: {{^[0-9]+}}:
; CHECK: store i32
; CHECK: ret void

Expand All @@ -138,28 +138,28 @@ entry:
}

; CHECK-LABEL: @Store8
; CHECK-LABEL: entry:
; CHECK: entry:
; CHECK: @__msan_get_context_state()
; CHECK: [[PARAM_SHADOW:%[a-z0-9_]+]] = getelementptr {{.*}} i32 0, i32 0
; CHECK-LABEL: entry.split:
; CHECK: entry.split:
; CHECK: ptrtoint {{.*}} [[PARAM_SHADOW]]
; Load the shadow of %p and check it
; CHECK: load i64
; CHECK: icmp
; CHECK: br i1
; CHECK-LABEL: <label>
; CHECK: {{^[0-9]+}}:
; CHECK: [[REG:%[0-9]+]] = bitcast i64* %p to i8*
; CHECK: @__msan_metadata_ptr_for_store_8(i8* [[REG]])
; CHECK: store i64
; If the new shadow is non-zero, jump to __msan_chain_origin()
; CHECK: icmp
; CHECK: br i1
; CHECK: <label>
; CHECK: {{^[0-9]+}}:
; CHECK: @__msan_chain_origin
; Storing origin here:
; CHECK: store i32
; CHECK: br label
; CHECK: <label>
; CHECK: {{^[0-9]+}}:
; CHECK: store i64
; CHECK: ret void

Expand All @@ -170,28 +170,28 @@ entry:
}

; CHECK-LABEL: @Store16
; CHECK-LABEL: entry:
; CHECK: entry:
; CHECK: @__msan_get_context_state()
; CHECK: [[PARAM_SHADOW:%[a-z0-9_]+]] = getelementptr {{.*}} i32 0, i32 0
; CHECK-LABEL: entry.split:
; CHECK: entry.split:
; CHECK: ptrtoint {{.*}} [[PARAM_SHADOW]]
; Load the shadow of %p and check it
; CHECK: load i64
; CHECK: icmp
; CHECK: br i1
; CHECK-LABEL: <label>
; CHECK: {{^[0-9]+}}:
; CHECK: [[REG:%[0-9]+]] = bitcast i128* %p to i8*
; CHECK: @__msan_metadata_ptr_for_store_n(i8* [[REG]], i64 16)
; CHECK: store i128
; If the new shadow is non-zero, jump to __msan_chain_origin()
; CHECK: icmp
; CHECK: br i1
; CHECK: <label>
; CHECK: {{^[0-9]+}}:
; CHECK: @__msan_chain_origin
; Storing origin here:
; CHECK: store i32
; CHECK: br label
; CHECK: <label>
; CHECK: {{^[0-9]+}}:
; CHECK: store i128
; CHECK: ret void

Expand All @@ -205,16 +205,16 @@ entry:
}

; CHECK-LABEL: @Load1
; CHECK-LABEL: entry:
; CHECK: entry:
; CHECK: @__msan_get_context_state()
; CHECK: [[PARAM_SHADOW:%[a-z0-9_]+]] = getelementptr {{.*}} i32 0, i32 0
; CHECK-LABEL: entry.split:
; CHECK: entry.split:
; CHECK: ptrtoint {{.*}} [[PARAM_SHADOW]]
; Load the shadow of %p and check it
; CHECK: load i64
; CHECK: icmp
; CHECK: br i1
; CHECK-LABEL: <label>
; CHECK: {{^[0-9]+}}:
; Load the value from %p. This is done before accessing the shadow
; to ease atomic handling.
; CHECK: load i8
Expand All @@ -231,16 +231,16 @@ entry:
}

; CHECK-LABEL: @Load2
; CHECK-LABEL: entry:
; CHECK: entry:
; CHECK: @__msan_get_context_state()
; CHECK: [[PARAM_SHADOW:%[a-z0-9_]+]] = getelementptr {{.*}} i32 0, i32 0
; CHECK-LABEL: entry.split:
; CHECK: entry.split:
; CHECK: ptrtoint {{.*}} [[PARAM_SHADOW]]
; Load the shadow of %p and check it
; CHECK: load i64
; CHECK: icmp
; CHECK: br i1
; CHECK-LABEL: <label>
; CHECK: {{^[0-9]+}}:
; Load the value from %p. This is done before accessing the shadow
; to ease atomic handling.
; CHECK: load i16
Expand All @@ -258,16 +258,16 @@ entry:
}

; CHECK-LABEL: @Load4
; CHECK-LABEL: entry:
; CHECK: entry:
; CHECK: @__msan_get_context_state()
; CHECK: [[PARAM_SHADOW:%[a-z0-9_]+]] = getelementptr {{.*}} i32 0, i32 0
; CHECK-LABEL: entry.split:
; CHECK: entry.split:
; CHECK: ptrtoint {{.*}} [[PARAM_SHADOW]]
; Load the shadow of %p and check it
; CHECK: load i64
; CHECK: icmp
; CHECK: br i1
; CHECK-LABEL: <label>
; CHECK: {{^[0-9]+}}:
; Load the value from %p. This is done before accessing the shadow
; to ease atomic handling.
; CHECK: load i32
Expand All @@ -284,16 +284,16 @@ entry:
}

; CHECK-LABEL: @Load8
; CHECK-LABEL: entry:
; CHECK: entry:
; CHECK: @__msan_get_context_state()
; CHECK: [[PARAM_SHADOW:%[a-z0-9_]+]] = getelementptr {{.*}} i32 0, i32 0
; CHECK-LABEL: entry.split:
; CHECK: entry.split:
; CHECK: ptrtoint {{.*}} [[PARAM_SHADOW]]
; Load the shadow of %p and check it
; CHECK: load i64
; CHECK: icmp
; CHECK: br i1
; CHECK-LABEL: <label>
; CHECK: {{^[0-9]+}}:
; Load the value from %p. This is done before accessing the shadow
; to ease atomic handling.
; CHECK: load i64
Expand All @@ -310,16 +310,16 @@ entry:
}

; CHECK-LABEL: @Load16
; CHECK-LABEL: entry:
; CHECK: entry:
; CHECK: @__msan_get_context_state()
; CHECK: [[PARAM_SHADOW:%[a-z0-9_]+]] = getelementptr {{.*}} i32 0, i32 0
; CHECK-LABEL: entry.split:
; CHECK: entry.split:
; CHECK: ptrtoint {{.*}} [[PARAM_SHADOW]]
; Load the shadow of %p and check it
; CHECK: load i64
; CHECK: icmp
; CHECK: br i1
; CHECK-LABEL: <label>
; CHECK: {{^[0-9]+}}:
; Load the value from %p. This is done before accessing the shadow
; to ease atomic handling.
; CHECK: load i128
Expand Down Expand Up @@ -359,7 +359,7 @@ attributes #0 = { "target-features"="+fxsr,+x87,-sse" }
; CHECK: [[VA_ARG_ORIGIN:%[a-z0-9_]+]] = getelementptr {{.*}} i32 0, i32 3
; CHECK: [[VA_ARG_OVERFLOW_SIZE:%[a-z0-9_]+]] = getelementptr {{.*}} i32 0, i32 4

; CHECK-LABEL: entry.split:
; CHECK: entry.split:
; CHECK: [[OSIZE:%[0-9]+]] = load i64, i64* [[VA_ARG_OVERFLOW_SIZE]]
; Register save area is 48 bytes for non-SSE builds.
; CHECK: [[SIZE:%[0-9]+]] = add i64 48, [[OSIZE]]
Expand All @@ -380,13 +380,13 @@ entry:

; CHECK-LABEL: @VarArgCaller

; CHECK-LABEL: entry:
; CHECK: entry:
; CHECK: @__msan_get_context_state()
; CHECK: [[PARAM_SHADOW:%[a-z0-9_]+]] = getelementptr {{.*}} i32 0, i32 0
; CHECK: [[VA_ARG_SHADOW:%[a-z0-9_]+]] = getelementptr {{.*}} i32 0, i32 2
; CHECK: [[VA_ARG_OVERFLOW_SIZE:%[a-z0-9_]+]] = getelementptr {{.*}} i32 0, i32 4

; CHECK-LABEL: entry.split:
; CHECK: entry.split:
; CHECK: [[PARAM_SI:%[_a-z0-9]+]] = ptrtoint {{.*}} [[PARAM_SHADOW]]
; CHECK: [[ARG1_S:%[_a-z0-9]+]] = inttoptr i64 [[PARAM_SI]] to i64*
; First argument is initialized
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/Instrumentation/MemorySanitizer/msan_x86_bts_asm.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -96,6 +96,6 @@ if.else: ; preds = %entry
; CHECK: br i1 [[MSCMP]], label %[[IFTRUE:.*]], label {{.*}}

; If yes, raise a warning.
; CHECK: <label>:[[IFTRUE]]
; CHECK: [[IFTRUE]]:
; CHECK: call void @__msan_warning

4 changes: 2 additions & 2 deletions llvm/test/Instrumentation/MemorySanitizer/store-origin.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -74,7 +74,7 @@ attributes #1 = { nounwind readnone }
; CHECK: store {{.*}}!dbg ![[DBG:[0-9]+]]
; CHECK: icmp
; CHECK: br i1
; CHECK: <label>
; CHECK: {{^[0-9]+}}:

; Origin tracking level 1: simply store the origin value
; CHECK-ORIGINS1: store i32 {{.*}}[[ORIGIN]],{{.*}}!dbg !{{.*}}[[DBG]]
Expand All @@ -84,6 +84,6 @@ attributes #1 = { nounwind readnone }
; CHECK-ORIGINS2: store i32 {{.*}}[[ORIGIN2]],{{.*}}!dbg !{{.*}}[[DBG]]

; CHECK: br label{{.*}}!dbg !{{.*}}[[DBG]]
; CHECK: <label>
; CHECK: {{^[0-9]+}}:
; CHECK: store{{.*}}!dbg !{{.*}}[[DBG]]
; CHECK: ret void
2 changes: 1 addition & 1 deletion llvm/test/Instrumentation/SanitizerCoverage/stack-depth.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -29,7 +29,7 @@ entry:
; CHECK: [[lowest:%[^ \t]+]] = load [[intType]], [[intType]]* @__sancov_lowest_stack
; CHECK: [[cmp:%[^ \t]+]] = icmp ult [[intType]] [[frameInt]], [[lowest]]
; CHECK: br i1 [[cmp]], label %[[ifLabel:[^ \t]+]], label
; CHECK: <label>:[[ifLabel]]:
; CHECK: [[ifLabel]]:
; CHECK: store [[intType]] [[frameInt]], [[intType]]* @__sancov_lowest_stack
; CHECK: %call = call i32 @foo()
; CHECK: ret i32 %call
Expand Down
26 changes: 13 additions & 13 deletions llvm/test/Transforms/GVNHoist/pr36787.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,58 +16,58 @@ define void @func() personality i8* bitcast (i32 (...)* @gxx_personality to i8*)
invoke void @f0()
to label %3 unwind label %1

; <label>:1:
1:
%2 = landingpad { i8*, i32 }
catch i8* bitcast (i8** @g to i8*)
catch i8* null
br label %16

; <label>:3:
3:
br i1 undef, label %4, label %10

;CHECK: <label>:4
;CHECK: 4:
;CHECK-NEXT: %5 = load i32*, i32** undef, align 8
;CHECK-NEXT: invoke void @f1()

; <label>:4:
4:
%5 = load i32*, i32** undef, align 8
invoke void @f1()
to label %6 unwind label %1

;CHECK: <label>:6
;CHECK: 6:
;CHECK-NEXT: %7 = load i32*, i32** undef, align 8
;CHECK-NEXT: %8 = load i32*, i32** undef, align 8

; <label>:6:
6:
%7 = load i32*, i32** undef, align 8
%8 = load i32*, i32** undef, align 8
br i1 true, label %9, label %17

; <label>:9:
9:
invoke void @f0()
to label %10 unwind label %1

; <label>:10:
10:
invoke void @f2()
to label %11 unwind label %1

; <label>:11:
11:
%12 = invoke signext i32 undef(i32* null, i32 signext undef, i1 zeroext undef)
to label %13 unwind label %14

; <label>:13:
13:
unreachable

; <label>:14:
14:
%15 = landingpad { i8*, i32 }
catch i8* bitcast (i8** @g to i8*)
catch i8* null
br label %16

; <label>:16:
16:
unreachable

; <label>:17:
17:
ret void

; uselistorder directives
Expand Down
14 changes: 7 additions & 7 deletions llvm/test/Transforms/LowerSwitch/2014-06-23-PHIlowering.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2,10 +2,10 @@

define i32 @test(i32 %arg) #0 {
; CHECK-LABEL: @test
; CHECK: ; <label>:2
; CHECK: 2:
; CHECK-NEXT: %res.0 = phi i32 [ 1, %NodeBlock ], [ 2, %1 ]
; CHECK-NEXT: br label %3
; CHECK: ; <label>:5
; CHECK: 5:
; CHECK-NEXT: %res.3 = phi i32 [ 0, %NewDefault ], [ %res.2, %4 ]
; CHECK-NEXT: %6 = add nsw i32 %res.3, 1
; CHECK-NEXT: ret i32 %6
Expand All @@ -17,23 +17,23 @@ define i32 @test(i32 %arg) #0 {
i32 4, label %4
]

; <label>:1
1:
br label %2

; <label>:2
2:
%res.0 = phi i32 [ 1, %0 ], [ 2, %1 ]
br label %3

; <label>:3
3:
%res.1 = phi i32 [ 0, %0 ], [ %res.0, %2 ]
%phitmp = add nsw i32 %res.1, 2
br label %4

; <label>:4
4:
%res.2 = phi i32 [ 1, %0 ], [ %phitmp, %3 ]
br label %5

; <label>:5
5:
%res.3 = phi i32 [ 0, %0 ], [ %res.2, %4 ]
%6 = add nsw i32 %res.3, 1
ret i32 %6
Expand Down