11 changes: 7 additions & 4 deletions clang/lib/Sema/SemaInit.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10561,7 +10561,7 @@ static bool isOrIsDerivedFromSpecializationOf(CXXRecordDecl *RD,

QualType Sema::DeduceTemplateSpecializationFromInitializer(
TypeSourceInfo *TSInfo, const InitializedEntity &Entity,
const InitializationKind &Kind, MultiExprArg Inits, ParenListExpr *PL) {
const InitializationKind &Kind, MultiExprArg Inits) {
auto *DeducedTST = dyn_cast<DeducedTemplateSpecializationType>(
TSInfo->getType()->getContainedDeducedType());
assert(DeducedTST && "not a deduced template specialization type");
Expand Down Expand Up @@ -10792,9 +10792,12 @@ QualType Sema::DeduceTemplateSpecializationFromInitializer(
if (getLangOpts().CPlusPlus20 && !HasAnyDeductionGuide) {
if (ListInit && ListInit->getNumInits()) {
SynthesizeAggrGuide(ListInit);
} else if (PL && PL->getNumExprs()) {
InitListExpr TempListInit(getASTContext(), PL->getLParenLoc(),
PL->exprs(), PL->getRParenLoc());
} else if (Inits.size()) { // parenthesized expression-list
// Inits are expressions inside the parentheses. We don't have
// the parentheses source locations, use the begin/end of Inits as the
// best heuristic.
InitListExpr TempListInit(getASTContext(), Inits.front()->getBeginLoc(),
Inits, Inits.back()->getEndLoc());
SynthesizeAggrGuide(&TempListInit);
}
}
Expand Down
19 changes: 10 additions & 9 deletions clang/lib/Sema/SemaRISCVVectorLookup.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -206,15 +206,16 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(
{"xsfvfwmaccqqq", RVV_REQ_Xsfvfwmaccqqq},
{"xsfvqmaccdod", RVV_REQ_Xsfvqmaccdod},
{"xsfvqmaccqoq", RVV_REQ_Xsfvqmaccqoq},
{"experimental-zvbb", RVV_REQ_Zvbb},
{"experimental-zvbc", RVV_REQ_Zvbc},
{"experimental-zvkb", RVV_REQ_Zvkb},
{"experimental-zvkg", RVV_REQ_Zvkg},
{"experimental-zvkned", RVV_REQ_Zvkned},
{"experimental-zvknha", RVV_REQ_Zvknha},
{"experimental-zvknhb", RVV_REQ_Zvknhb},
{"experimental-zvksed", RVV_REQ_Zvksed},
{"experimental-zvksh", RVV_REQ_Zvksh}};
{"zvbb", RVV_REQ_Zvbb},
{"zvbc", RVV_REQ_Zvbc},
{"zvkb", RVV_REQ_Zvkb},
{"zvkg", RVV_REQ_Zvkg},
{"zvkned", RVV_REQ_Zvkned},
{"zvknha", RVV_REQ_Zvknha},
{"zvknhb", RVV_REQ_Zvknhb},
{"zvksed", RVV_REQ_Zvksed},
{"zvksh", RVV_REQ_Zvksh},
{"experimental", RVV_REQ_Experimental}};

// Construction of RVVIntrinsicRecords need to sync with createRVVIntrinsics
// in RISCVVEmitter.cpp.
Expand Down
2 changes: 1 addition & 1 deletion clang/lib/Support/RISCVVIntrinsicUtils.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1217,7 +1217,7 @@ raw_ostream &operator<<(raw_ostream &OS, const RVVIntrinsicRecord &Record) {
OS << (int)Record.PrototypeLength << ",";
OS << (int)Record.SuffixLength << ",";
OS << (int)Record.OverloadedSuffixSize << ",";
OS << (int)Record.RequiredExtensions << ",";
OS << Record.RequiredExtensions << ",";
OS << (int)Record.TypeRangeMask << ",";
OS << (int)Record.Log2LMULMask << ",";
OS << (int)Record.NF << ",";
Expand Down
20 changes: 10 additions & 10 deletions clang/test/CodeGen/PowerPC/ppc-emmintrin.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -521,14 +521,14 @@ test_converts() {
// CHECK: sitofp i64 %{{[0-9a-zA-Z_.]+}} to double

// CHECK-LABEL: define available_externally <2 x i64> @_mm_cvtsi64_si128
// CHECK: %[[INS:[0-9a-zA-Z_.]+]] = insertelement <2 x i64> undef, i64 %{{[0-9a-zA-Z_.]+}}, i32 0
// CHECK: %[[INS:[0-9a-zA-Z_.]+]] = insertelement <2 x i64> poison, i64 %{{[0-9a-zA-Z_.]+}}, i32 0
// CHECK: insertelement <2 x i64> %[[INS]], i64 0, i32 1

// CHECK-LABEL: define available_externally <2 x double> @_mm_cvtsi64x_sd
// CHECK: call <2 x double> @_mm_cvtsi64_sd(<2 x double> noundef %{{[0-9a-zA-Z_.]+}}, i64 noundef %{{[0-9a-zA-Z_.]+}})

// CHECK-LABEL: define available_externally <2 x i64> @_mm_cvtsi64x_si128
// CHECK: %[[INS:[0-9a-zA-Z_.]+]] = insertelement <2 x i64> undef, i64 %{{[0-9a-zA-Z_.]+}}, i32 0
// CHECK: %[[INS:[0-9a-zA-Z_.]+]] = insertelement <2 x i64> poison, i64 %{{[0-9a-zA-Z_.]+}}, i32 0
// CHECK: insertelement <2 x i64> %[[INS]], i64 0, i32 1

// CHECK-LABEL: define available_externally <2 x double> @_mm_cvtss_sd
Expand Down Expand Up @@ -906,35 +906,35 @@ test_set() {

// CHECK-LABEL: define available_externally <2 x i64> @_mm_set_epi16
// CHECK-COUNT-8: store i16 {{[0-9a-zA-Z_%.]+}}, ptr {{[0-9a-zA-Z_%.]+}}, align 2
// CHECK: insertelement <8 x i16> undef, i16 {{[0-9a-zA-Z_%.]+}}, i32 0
// CHECK: insertelement <8 x i16> poison, i16 {{[0-9a-zA-Z_%.]+}}, i32 0
// CHECK-COUNT-7: insertelement <8 x i16> {{[0-9a-zA-Z_%.]+}}, i16 {{[0-9a-zA-Z_%.]+}}, i32 {{[1-7]}}

// CHECK-LABEL: define available_externally <2 x i64> @_mm_set_epi32
// CHECK-COUNT-4: store i32 {{[0-9a-zA-Z_%.]+}}, ptr {{[0-9a-zA-Z_%.]+}}, align 4
// CHECK: insertelement <4 x i32> undef, i32 {{[0-9a-zA-Z_%.]+}}, i32 0
// CHECK: insertelement <4 x i32> poison, i32 {{[0-9a-zA-Z_%.]+}}, i32 0
// CHECK-COUNT-3: insertelement <4 x i32> {{[0-9a-zA-Z_%.]+}}, i32 {{[0-9a-zA-Z_%.]+}}, i32 {{[1-3]}}

// CHECK-LABEL: define available_externally <2 x i64> @_mm_set_epi64
// CHECK: call <2 x i64> @_mm_set_epi64x(i64 noundef %{{[0-9a-zA-Z_.]+}}, i64 noundef %{{[0-9a-zA-Z_.]+}})

// CHECK-LABEL: define available_externally <2 x i64> @_mm_set_epi64x
// CHECK: %[[VEC:[0-9a-zA-Z_.]+]] = insertelement <2 x i64> undef, i64 %{{[0-9a-zA-Z_.]+}}, i32 0
// CHECK: %[[VEC:[0-9a-zA-Z_.]+]] = insertelement <2 x i64> poison, i64 %{{[0-9a-zA-Z_.]+}}, i32 0
// CHECK: insertelement <2 x i64> %[[VEC]], i64 %{{[0-9a-zA-Z_.]+}}, i32 1

// CHECK-LABEL: define available_externally <2 x i64> @_mm_set_epi8
// CHECK-COUNT-16: store i8 {{[0-9a-zA-Z_%.]+}}, ptr {{[0-9a-zA-Z_%.]+}}, align 1
// CHECK: insertelement <16 x i8> undef, i8 {{[0-9a-zA-Z_%.]+}}, i32 {{[0-9]+}}
// CHECK: insertelement <16 x i8> poison, i8 {{[0-9a-zA-Z_%.]+}}, i32 {{[0-9]+}}
// CHECK-COUNT-15: {{[0-9a-zA-Z_%.]+}} = insertelement <16 x i8> {{[0-9a-zA-Z_%.]+}}, i8 {{[0-9a-zA-Z_%.]+}}, i32 {{[0-9]+}}

// CHECK-LABEL: define available_externally <2 x double> @_mm_set_pd
// CHECK: %[[VEC:[0-9a-zA-Z_.]+]] = insertelement <2 x double> undef, double %{{[0-9a-zA-Z_.]+}}, i32 0
// CHECK: %[[VEC:[0-9a-zA-Z_.]+]] = insertelement <2 x double> poison, double %{{[0-9a-zA-Z_.]+}}, i32 0
// CHECK: insertelement <2 x double> %[[VEC]], double %{{[0-9a-zA-Z_.]+}}, i32 1

// CHECK-LABEL: define available_externally <2 x double> @_mm_set_pd1
// CHECK: call <2 x double> @_mm_set1_pd(double noundef %{{[0-9a-zA-Z_.]+}})

// CHECK-LABEL: define available_externally <2 x double> @_mm_set_sd
// CHECK: %[[VEC:[0-9a-zA-Z_.]+]] = insertelement <2 x double> undef, double %{{[0-9a-zA-Z_.]+}}, i32 0
// CHECK: %[[VEC:[0-9a-zA-Z_.]+]] = insertelement <2 x double> poison, double %{{[0-9a-zA-Z_.]+}}, i32 0
// CHECK: insertelement <2 x double> %[[VEC]], double 0.000000e+00, i32 1

// CHECK-LABEL: define available_externally <2 x i64> @_mm_set1_epi16
Expand All @@ -960,7 +960,7 @@ test_set() {
// CHECK: call <2 x i64> @_mm_set_epi8

// CHECK-LABEL: define available_externally <2 x double> @_mm_set1_pd
// CHECK: %[[VEC:[0-9a-zA-Z_.]+]] = insertelement <2 x double> undef, double %{{[0-9a-zA-Z_.]+}}, i32 0
// CHECK: %[[VEC:[0-9a-zA-Z_.]+]] = insertelement <2 x double> poison, double %{{[0-9a-zA-Z_.]+}}, i32 0
// CHECK: insertelement <2 x double> %[[VEC]], double %{{[0-9a-zA-Z_.]+}}, i32 1

// CHECK-LABEL: define available_externally <2 x i64> @_mm_setr_epi16
Expand All @@ -981,7 +981,7 @@ test_set() {
// CHECK: call <2 x i64> @_mm_set_epi8

// CHECK-LABEL: define available_externally <2 x double> @_mm_setr_pd
// CHECK: %[[VEC:[0-9a-zA-Z_.]+]] = insertelement <2 x double> undef, double %{{[0-9a-zA-Z_.]+}}, i32 0
// CHECK: %[[VEC:[0-9a-zA-Z_.]+]] = insertelement <2 x double> poison, double %{{[0-9a-zA-Z_.]+}}, i32 0
// CHECK: insertelement <2 x double> %[[VEC]], double %{{[0-9a-zA-Z_.]+}}, i32 1

// CHECK-LABEL: define available_externally <2 x double> @_mm_setzero_pd()
Expand Down
12 changes: 6 additions & 6 deletions clang/test/CodeGen/PowerPC/ppc-xmmintrin.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -796,8 +796,8 @@ test_sad() {

// CHECK-LABEL: define available_externally i64 @_mm_sad_pu8
// CHECK: call void @llvm.memset.p0.i64(ptr align 8 %{{[0-9a-zA-Z_.]+}}, i8 0, i64 8, i1 false)
// CHECK: insertelement <2 x i64> <i64 0, i64 undef>, i64 %{{[0-9a-zA-Z_.]+}}, i32 1
// CHECK: insertelement <2 x i64> <i64 0, i64 undef>, i64 %{{[0-9a-zA-Z_.]+}}, i32 1
// CHECK: insertelement <2 x i64> <i64 0, i64 poison>, i64 %{{[0-9a-zA-Z_.]+}}, i32 1
// CHECK: insertelement <2 x i64> <i64 0, i64 poison>, i64 %{{[0-9a-zA-Z_.]+}}, i32 1
// CHECK: call <16 x i8> @vec_min(unsigned char vector[16], unsigned char vector[16])
// CHECK: call <16 x i8> @vec_max(unsigned char vector[16], unsigned char vector[16])
// CHECK: call <16 x i8> @vec_sub(unsigned char vector[16], unsigned char vector[16])
Expand All @@ -823,7 +823,7 @@ test_set() {
// CHECK-LABEL: @test_set

// CHECK-LABEL: define available_externally <4 x float> @_mm_set_ps
// CHECK: %[[VEC:[0-9a-zA-Z_.]+]] = insertelement <4 x float> undef, float %{{[0-9a-zA-Z_.]+}}, i32 0
// CHECK: %[[VEC:[0-9a-zA-Z_.]+]] = insertelement <4 x float> poison, float %{{[0-9a-zA-Z_.]+}}, i32 0
// CHECK: %[[VEC2:[0-9a-zA-Z_.]+]] = insertelement <4 x float> %[[VEC]], float %{{[0-9a-zA-Z_.]+}}, i32 1
// CHECK: %[[VEC3:[0-9a-zA-Z_.]+]] = insertelement <4 x float> %[[VEC2]], float %{{[0-9a-zA-Z_.]+}}, i32 2
// CHECK: %[[VEC4:[0-9a-zA-Z_.]+]] = insertelement <4 x float> %[[VEC3]], float %{{[0-9a-zA-Z_.]+}}, i32 3
Expand All @@ -833,21 +833,21 @@ test_set() {
// CHECK: call <4 x float> @_mm_set1_ps

// CHECK-LABEL: define available_externally <4 x float> @_mm_set_ss
// CHECK: %[[VEC:[0-9a-zA-Z_.]+]] = insertelement <4 x float> undef, float %{{[0-9a-zA-Z_.]+}}, i32 0
// CHECK: %[[VEC:[0-9a-zA-Z_.]+]] = insertelement <4 x float> poison, float %{{[0-9a-zA-Z_.]+}}, i32 0
// CHECK: %[[VEC2:[0-9a-zA-Z_.]+]] = insertelement <4 x float> %[[VEC]], float 0.000000e+00, i32 1
// CHECK: %[[VEC3:[0-9a-zA-Z_.]+]] = insertelement <4 x float> %[[VEC2]], float 0.000000e+00, i32 2
// CHECK: %[[VEC4:[0-9a-zA-Z_.]+]] = insertelement <4 x float> %[[VEC3]], float 0.000000e+00, i32 3
// CHECK: store <4 x float> %[[VEC4]], ptr %{{[0-9a-zA-Z_.]+}}, align 16

// CHECK-LABEL: define available_externally <4 x float> @_mm_set1_ps
// CHECK: %[[VEC:[0-9a-zA-Z_.]+]] = insertelement <4 x float> undef, float %{{[0-9a-zA-Z_.]+}}, i32 0
// CHECK: %[[VEC:[0-9a-zA-Z_.]+]] = insertelement <4 x float> poison, float %{{[0-9a-zA-Z_.]+}}, i32 0
// CHECK: %[[VEC2:[0-9a-zA-Z_.]+]] = insertelement <4 x float> %[[VEC]], float %{{[0-9a-zA-Z_.]+}}, i32 1
// CHECK: %[[VEC3:[0-9a-zA-Z_.]+]] = insertelement <4 x float> %[[VEC2]], float %{{[0-9a-zA-Z_.]+}}, i32 2
// CHECK: %[[VEC4:[0-9a-zA-Z_.]+]] = insertelement <4 x float> %[[VEC3]], float %{{[0-9a-zA-Z_.]+}}, i32 3
// CHECK: store <4 x float> %[[VEC4]], ptr %{{[0-9a-zA-Z_.]+}}, align 16

// CHECK-LABEL: define available_externally <4 x float> @_mm_setr_ps
// CHECK: %[[VEC:[0-9a-zA-Z_.]+]] = insertelement <4 x float> undef, float %{{[0-9a-zA-Z_.]+}}, i32 0
// CHECK: %[[VEC:[0-9a-zA-Z_.]+]] = insertelement <4 x float> poison, float %{{[0-9a-zA-Z_.]+}}, i32 0
// CHECK: %[[VEC2:[0-9a-zA-Z_.]+]] = insertelement <4 x float> %[[VEC]], float %{{[0-9a-zA-Z_.]+}}, i32 1
// CHECK: %[[VEC3:[0-9a-zA-Z_.]+]] = insertelement <4 x float> %[[VEC2]], float %{{[0-9a-zA-Z_.]+}}, i32 2
// CHECK: %[[VEC4:[0-9a-zA-Z_.]+]] = insertelement <4 x float> %[[VEC3]], float %{{[0-9a-zA-Z_.]+}}, i32 3
Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesef.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesem.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf1.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf2.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesz.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
18 changes: 10 additions & 8 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vandn.c
View file
Original file line number Diff line number Diff line change
@@ -1,14 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkb \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
18 changes: 10 additions & 8 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev8.c
View file
Original file line number Diff line number Diff line change
@@ -1,14 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkb \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmul.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmulh.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclz.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
16 changes: 14 additions & 2 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpopv.c
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,18 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvbb -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck %s

#include <riscv_vector.h>

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vctz.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vghsh.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vgmul.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
18 changes: 10 additions & 8 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrev8.c
View file
Original file line number Diff line number Diff line change
@@ -1,14 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkb \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
18 changes: 10 additions & 8 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrol.c
View file
Original file line number Diff line number Diff line change
@@ -1,14 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkb \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
18 changes: 10 additions & 8 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vror.c
View file
Original file line number Diff line number Diff line change
@@ -1,14 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkb \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ch.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2cl.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ms.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3c.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3me.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4k.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4r.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsll.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdf.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdm.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesef.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesem.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf1.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf2.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesz.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
18 changes: 10 additions & 8 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vandn.c
View file
Original file line number Diff line number Diff line change
@@ -1,14 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkb \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
18 changes: 10 additions & 8 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev8.c
View file
Original file line number Diff line number Diff line change
@@ -1,14 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkb \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmul.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmulh.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclz.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
16 changes: 14 additions & 2 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpopv.c
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,18 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvbb -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck %s

#include <riscv_vector.h>

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vctz.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vghsh.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vgmul.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
18 changes: 10 additions & 8 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrev8.c
View file
Original file line number Diff line number Diff line change
@@ -1,14 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkb \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
18 changes: 10 additions & 8 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrol.c
View file
Original file line number Diff line number Diff line change
@@ -1,14 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkb \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
18 changes: 10 additions & 8 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vror.c
View file
Original file line number Diff line number Diff line change
@@ -1,14 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkb \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2ch.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2cl.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2ms.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm3c.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm3me.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm4k.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm4r.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vwsll.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdf.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdm.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesef.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesem.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaeskf1.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaeskf2.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesz.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
18 changes: 10 additions & 8 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vandn.c
View file
Original file line number Diff line number Diff line change
@@ -1,14 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkb \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vbrev.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
18 changes: 10 additions & 8 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vbrev8.c
View file
Original file line number Diff line number Diff line change
@@ -1,14 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkb \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclmul.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclmulh.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
16 changes: 14 additions & 2 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclz.c
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,18 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvbb -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck %s

#include <riscv_vector.h>

Expand Down
16 changes: 14 additions & 2 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcpopv.c
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,18 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvbb -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck %s

#include <riscv_vector.h>

Expand Down
16 changes: 14 additions & 2 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vctz.c
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,18 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvbb -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck %s

#include <riscv_vector.h>

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vghsh.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vgmul.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
18 changes: 10 additions & 8 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrev8.c
View file
Original file line number Diff line number Diff line change
@@ -1,14 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkb \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
18 changes: 10 additions & 8 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrol.c
View file
Original file line number Diff line number Diff line change
@@ -1,14 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkb \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
18 changes: 10 additions & 8 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vror.c
View file
Original file line number Diff line number Diff line change
@@ -1,14 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkb \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2ch.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2cl.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsha2ms.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm3c.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm3me.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm4k.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm4r.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
17 changes: 10 additions & 7 deletions clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vwsll.c
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,16 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
// RUN: -target-feature +experimental-zvbb \
// RUN: -target-feature +experimental-zvbc \
// RUN: -target-feature +experimental-zvkg \
// RUN: -target-feature +experimental-zvkned \
// RUN: -target-feature +experimental-zvknhb \
// RUN: -target-feature +experimental-zvksed \
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
// RUN: -target-feature +zvbb \
// RUN: -target-feature +zvbc \
// RUN: -target-feature +zvkb \
// RUN: -target-feature +zvkg \
// RUN: -target-feature +zvkned \
// RUN: -target-feature +zvknhb \
// RUN: -target-feature +zvksed \
// RUN: -target-feature +zvksh \
// RUN: -target-feature +experimental \
// RUN: -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s

Expand Down
Loading