35 changes: 23 additions & 12 deletions llvm/test/DebugInfo/WebAssembly/dbg-value-reg-stackify.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -8,44 +8,44 @@
declare void @use(i32)
declare void @use_2(i32, i32)

define void @sink_simple() {
define void @sink_simple() !dbg !6 {
call void @llvm.dbg.value(metadata i32 0, metadata !5, metadata !DIExpression()), !dbg !10
call void @llvm.dbg.value(metadata i32 0, metadata !11, metadata !DIExpression()), !dbg !10
call void @llvm.dbg.value(metadata i32 0, metadata !12, metadata !DIExpression()), !dbg !10
call void @llvm.dbg.value(metadata i32 0, metadata !13, metadata !DIExpression()), !dbg !10
ret void
}
define void @sink_non_consecutive() {
define void @sink_non_consecutive() !dbg !14 {
unreachable
}
define void @dont_sink_above_def() {
define void @dont_sink_above_def() !dbg !15 {
unreachable
}
define void @sink_to_same_place() {
define void @sink_to_same_place() !dbg !16 {
unreachable
}
define void @cannot_sink_across_same_variable() {
define void @cannot_sink_across_same_variable() !dbg !17 {
unreachable
}
define void @cannot_sink_across_same_variable2() {
define void @cannot_sink_across_same_variable2() !dbg !18 {
unreachable
}
define void @can_sink_across_same_variable_with_same_const() {
define void @can_sink_across_same_variable_with_same_const() !dbg !19 {
unreachable
}
define void @sink_multiple_defs() {
define void @sink_multiple_defs() !dbg !20 {
unreachable
}
define void @clone_same_bb() {
define void @clone_same_bb() !dbg !21 {
unreachable
}
define void @clone_different_bb() {
define void @clone_different_bb() !dbg !22 {
unreachable
}
define void @tee_with_two_use_insts() {
define void @tee_with_two_use_insts() !dbg !23 {
unreachable
}
define void @tee_with_one_inst_with_two_uses() {
define void @tee_with_one_inst_with_two_uses() !dbg !24 {
unreachable
}
declare void @llvm.dbg.value(metadata, metadata, metadata)
Expand Down Expand Up @@ -81,6 +81,17 @@
; CHECK: ![[VAR_C:[0-9]+]] = !DILocalVariable(name: "var_c"
!13 = !DILocalVariable(name: "var_d", scope: !6, file: !1, line: 2, type: !9)
; CHECK: ![[VAR_D:[0-9]+]] = !DILocalVariable(name: "var_d"
!14 = distinct !DISubprogram(name: "sink_non_consecutive", scope: !1, file: !1, line: 1, type: !7, scopeLine: 1, unit: !0)
!15 = distinct !DISubprogram(name: "dont_sink_above_def", scope: !1, file: !1, line: 1, type: !7, scopeLine: 1, unit: !0)
!16 = distinct !DISubprogram(name: "sink_to_same_place", scope: !1, file: !1, line: 1, type: !7, scopeLine: 1, unit: !0)
!17 = distinct !DISubprogram(name: "cannot_sink_across_same_variable", scope: !1, file: !1, line: 1, type: !7, scopeLine: 1, unit: !0)
!18 = distinct !DISubprogram(name: "cannot_sink_across_same_variable2", scope: !1, file: !1, line: 1, type: !7, scopeLine: 1, unit: !0)
!19 = distinct !DISubprogram(name: "can_sink_across_same_variable_with_same_const", scope: !1, file: !1, line: 1, type: !7, scopeLine: 1, unit: !0)
!20 = distinct !DISubprogram(name: "sink_multiple_defs", scope: !1, file: !1, line: 1, type: !7, scopeLine: 1, unit: !0)
!21 = distinct !DISubprogram(name: "clone_same_bb", scope: !1, file: !1, line: 1, type: !7, scopeLine: 1, unit: !0)
!22 = distinct !DISubprogram(name: "clone_different_bb", scope: !1, file: !1, line: 1, type: !7, scopeLine: 1, unit: !0)
!23 = distinct !DISubprogram(name: "tee_with_two_use_insts", scope: !1, file: !1, line: 1, type: !7, scopeLine: 1, unit: !0)
!24 = distinct !DISubprogram(name: "tee_with_one_inst_with_two_uses", scope: !1, file: !1, line: 1, type: !7, scopeLine: 1, unit: !0)
...

---
Expand Down
18 changes: 9 additions & 9 deletions llvm/test/TableGen/DefaultOpsGlobalISel.td
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Original file line number Diff line number Diff line change
Expand Up @@ -53,8 +53,8 @@ def clamp : OperandWithDefaultOps <i1, (ops (i1 0))>;
// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // mods1
// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
// CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: // GIR_Coverage, 3,
// CHECK-NEXT: GIR_Done,
// CHECK-NEXT: // Label 0: @79
Expand All @@ -73,8 +73,8 @@ def clamp : OperandWithDefaultOps <i1, (ops (i1 0))>;
// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // omod
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: // GIR_Coverage, 2,
// CHECK-NEXT: GIR_Done,
// CHECK-NEXT: // Label 1: @139
Expand All @@ -95,8 +95,8 @@ def clamp : OperandWithDefaultOps <i1, (ops (i1 0))>;
// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // mods
// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src
// CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: // GIR_Coverage, 8,
// CHECK-NEXT: GIR_Done,
// CHECK-NEXT: // Label 2: @207
Expand All @@ -115,8 +115,8 @@ def clamp : OperandWithDefaultOps <i1, (ops (i1 0))>;
// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // omod
// CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: // GIR_Coverage, 5,
// CHECK-NEXT: GIR_Done,
// CHECK-NEXT: // Label 3: @265
Expand All @@ -141,8 +141,8 @@ def clamp : OperandWithDefaultOps <i1, (ops (i1 0))>;
// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // clamp
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: // GIR_Coverage, 7,
// CHECK-NEXT: GIR_Done,
// CHECK-NEXT: // Label 4: @345
Expand All @@ -160,8 +160,8 @@ def clamp : OperandWithDefaultOps <i1, (ops (i1 0))>;
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // clamp
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: // GIR_Coverage, 0,
// CHECK-NEXT: GIR_Done,
// CHECK-NEXT: // Label 5: @400
Expand All @@ -180,8 +180,8 @@ def clamp : OperandWithDefaultOps <i1, (ops (i1 0))>;
// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
// CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/93,
// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // clamp
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: // GIR_Coverage, 6,
// CHECK-NEXT: GIR_Done,
// CHECK-NEXT: // Label 6: @458
Expand All @@ -198,8 +198,8 @@ def clamp : OperandWithDefaultOps <i1, (ops (i1 0))>;
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
// CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: // GIR_Coverage, 1,
// CHECK-NEXT: GIR_Done,
// CHECK-NEXT: // Label 7: @503
Expand All @@ -216,8 +216,8 @@ def clamp : OperandWithDefaultOps <i1, (ops (i1 0))>;
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
// CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: // GIR_Coverage, 4,
// CHECK-NEXT: GIR_Done,
// CHECK-NEXT: // Label 8: @548
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td
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Original file line number Diff line number Diff line change
Expand Up @@ -54,8 +54,8 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // a
// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // y
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_ReplaceRegWithTempReg, /*OldInsnID*/0, /*OldOpIdx*/1, /*TempRegID*/0,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_Done,
// CHECK-NEXT: // Label 3: @525
// CHECK-NEXT: GIM_Reject,
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-operand-types.td
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Original file line number Diff line number Diff line change
Expand Up @@ -39,11 +39,11 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // b
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // c
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::G_ADD),
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, // a
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // b
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_Done,
// CHECK-NEXT: // Label 0: @81
// CHECK-NEXT: GIM_Reject,
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-permutations.td
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Original file line number Diff line number Diff line change
Expand Up @@ -196,8 +196,8 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_CustomAction, GIMT_Encode2(GICXXCustomAction_CombineApplyGICombiner0),
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_Done,
// CHECK-NEXT: // Label 1: @99
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 2*/ GIMT_Encode4(199), // Rule ID 6 //
Expand Down Expand Up @@ -239,8 +239,8 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_CustomAction, GIMT_Encode2(GICXXCustomAction_CombineApplyGICombiner0),
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_Done,
// CHECK-NEXT: // Label 2: @199
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 3*/ GIMT_Encode4(299), // Rule ID 5 //
Expand Down Expand Up @@ -282,8 +282,8 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_CustomAction, GIMT_Encode2(GICXXCustomAction_CombineApplyGICombiner0),
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_Done,
// CHECK-NEXT: // Label 3: @299
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4(409), // Rule ID 4 //
Expand Down Expand Up @@ -329,8 +329,8 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_CustomAction, GIMT_Encode2(GICXXCustomAction_CombineApplyGICombiner0),
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_Done,
// CHECK-NEXT: // Label 4: @409
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 5*/ GIMT_Encode4(509), // Rule ID 3 //
Expand Down Expand Up @@ -372,8 +372,8 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_CustomAction, GIMT_Encode2(GICXXCustomAction_CombineApplyGICombiner0),
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_Done,
// CHECK-NEXT: // Label 5: @509
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 6*/ GIMT_Encode4(619), // Rule ID 2 //
Expand Down Expand Up @@ -419,8 +419,8 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_CustomAction, GIMT_Encode2(GICXXCustomAction_CombineApplyGICombiner0),
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_Done,
// CHECK-NEXT: // Label 6: @619
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 7*/ GIMT_Encode4(729), // Rule ID 1 //
Expand Down Expand Up @@ -466,8 +466,8 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_CustomAction, GIMT_Encode2(GICXXCustomAction_CombineApplyGICombiner0),
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_Done,
// CHECK-NEXT: // Label 7: @729
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 8*/ GIMT_Encode4(849), // Rule ID 0 //
Expand Down Expand Up @@ -517,8 +517,8 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_CustomAction, GIMT_Encode2(GICXXCustomAction_CombineApplyGICombiner0),
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_Done,
// CHECK-NEXT: // Label 8: @849
// CHECK-NEXT: GIM_Reject,
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-typeof.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -32,11 +32,11 @@ def Test0 : GICombineRule<
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::G_CONSTANT),
// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
// CHECK-NEXT: GIR_AddCImm, /*InsnID*/0, /*Type*/uint8_t(-2), /*Imm*/GIMT_Encode8(42),
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::G_SUB),
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, // dst
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_Done,
// CHECK-NEXT: // Label 0: @77
// CHECK-NEXT: GIM_Reject,
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td
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Original file line number Diff line number Diff line change
Expand Up @@ -204,8 +204,8 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ext
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ptr
// CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_CustomAction, GIMT_Encode2(GICXXCustomAction_CombineApplyGICombiner2),
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_Done,
// CHECK-NEXT: // Label 10: @578
// CHECK-NEXT: GIM_Reject,
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/TableGen/GlobalISelEmitter-input-discard.td
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Original file line number Diff line number Diff line change
Expand Up @@ -24,8 +24,8 @@ def FOO : I<(outs GPR32:$dst), (ins GPR32Op:$src0, GPR32Op:$src1), []>;
// GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
// GISEL-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
// GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
// GISEL-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// GISEL-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GISEL-NEXT: GIR_EraseFromParent, /*InsnID*/0,
def : Pat <
(int_tgt_foo (i32 srcvalue), i32:$src1),
(FOO (IMPLICIT_DEF), GPR32:$src1)
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/TableGen/GlobalISelEmitter-multiple-output-discard.td
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Original file line number Diff line number Diff line change
Expand Up @@ -38,5 +38,5 @@ def : Pat<(two_out GPR32:$val), (THREE_OUTS GPR32:$val)>;
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // DstI[out2]
// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // val
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
2 changes: 1 addition & 1 deletion llvm/test/TableGen/GlobalISelEmitter-multiple-output.td
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Original file line number Diff line number Diff line change
Expand Up @@ -82,5 +82,5 @@ def : Pat<(two_in GPR32:$i1, GPR32:$i2), (TWO_INS GPR32:$i2, GPR32:$i1)>;
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // DstI[out2]
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // i2
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // i1
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
2 changes: 1 addition & 1 deletion llvm/test/TableGen/GlobalISelEmitter-nested-subregs.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -54,9 +54,9 @@ def A0 : RegisterClass<"MyTarget", [i32], 32, (add a0)>;
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
// CHECK-NEXT: GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(MyTarget::lo16),
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(MyTarget::A0wRegClassID),
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(MyTarget::A0RegClassID),
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
def : Pat<(i16 (anyext i8:$src)),
(i16 (EXTRACT_SUBREG
(i32 (INSERT_SUBREG
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/TableGen/GlobalISelEmitter-output-discard.td
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Original file line number Diff line number Diff line change
Expand Up @@ -19,8 +19,8 @@ def ADD_CO : I<(outs GPR32:$dst, GPR8:$flag),
// GISEL-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
// GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
// GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
// GISEL-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// GISEL-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GISEL-NEXT: GIR_EraseFromParent, /*InsnID*/0,
def : Pat <
(add i32:$src0, i32:$src1),
(ADD_CO GPR32:$src0, GPR32:$src1)
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/TableGen/GlobalISelEmitter-zero-reg.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -36,7 +36,7 @@ def INST : PredI<(outs GPR32:$dst), (ins GPR32:$src), []>;
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
// CHECK-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
// CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
def : Pat<(i32 (load GPR32:$src)),
(INST GPR32:$src)>;
42 changes: 21 additions & 21 deletions llvm/test/TableGen/GlobalISelEmitter.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -296,8 +296,8 @@ def HasC : Predicate<"Subtarget->hasC()"> { let RecomputePerFunction = 1; }
// R19C-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2b
// R19C-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2a
// R19C-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
// R19C-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// R19C-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// R19C-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// R19C-NEXT: // GIR_Coverage, 20,
// R19C-NEXT: GIR_Done,
// R19C-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]]
Expand Down Expand Up @@ -365,8 +365,8 @@ def : Pat<(select GPR32:$src1, (complex_rr GPR32:$src2a, GPR32:$src2b),
// R21C-NEXT: GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1),
// R21C-NEXT: GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0),
// R21C-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0
// R21C-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// R21C-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// R21C-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// R21C-NEXT: // GIR_Coverage, 22,
// R21C-NEXT: GIR_Done,
// R21C-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]]
Expand Down Expand Up @@ -414,8 +414,8 @@ def : Pat<(select GPR32:$src1, (complex_rr GPR32:$src2a, GPR32:$src2b),
// R20C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
// R20C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
// R20C-NEXT: GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0),
// R20C-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// R20C-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// R20C-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// R20C-NEXT: // GIR_Coverage, 21,
// R20C-NEXT: GIR_Done,
// R20C-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]]
Expand Down Expand Up @@ -507,8 +507,8 @@ def : Pat<(frag GPR32:$src1, complex:$src2, complex:$src3),
// R00C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
// R00C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src3
// R00C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src4
// R00C-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// R00C-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// R00C-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// R00C-NEXT: // GIR_Coverage, 0,
// R00C-NEXT: GIR_Done,
// R00C-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]]
Expand Down Expand Up @@ -558,8 +558,8 @@ def INSNBOB : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2, GPR32:$src3, G
// R01C-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MOV),
// R01C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
// R01C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
// R01C-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// R01C-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// R01C-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// R01C-NEXT: // GIR_Coverage, 1,
// R01C-NEXT: GIR_Done,
// R01C-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]]
Expand Down Expand Up @@ -607,8 +607,8 @@ def MOV : I<(outs GPR32:$dst), (ins GPR32:$src1),
// R02C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
// R02C-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1),
// R02C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
// R02C-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// R02C-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// R02C-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// R02C-NEXT: // GIR_Coverage, 2,
// R02C-NEXT: GIR_Done,
// R02C-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]]
Expand Down Expand Up @@ -639,8 +639,8 @@ def XORI : I<(outs GPR32:$dst), (ins m1:$src2, GPR32:$src1),
// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
// NOOPT-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::R0),
// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
// NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// NOOPT-NEXT: // GIR_Coverage, 3,
// NOOPT-NEXT: GIR_Done,
// NOOPT-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]]
Expand Down Expand Up @@ -669,8 +669,8 @@ def XOR : I<(outs GPR32:$dst), (ins Z:$src2, GPR32:$src1),
// NOOPT-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1),
// NOOPT-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::R0),
// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
// NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// NOOPT-NEXT: // GIR_Coverage, 4,
// NOOPT-NEXT: GIR_Done,
// NOOPT-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]]
Expand Down Expand Up @@ -700,8 +700,8 @@ def XORlike : I<(outs GPR32:$dst), (ins m1Z:$src2, GPR32:$src1),
// NOOPT-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::R0),
// NOOPT-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::R0),
// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
// NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// NOOPT-NEXT: // GIR_Coverage, 5,
// NOOPT-NEXT: GIR_Done,
// NOOPT-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]]
Expand Down Expand Up @@ -729,8 +729,8 @@ def XORManyDefaults : I<(outs GPR32:$dst), (ins m1Z:$src3, Z:$src2, GPR32:$src1)
// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
// NOOPT-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/13,
// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
// NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// NOOPT-NEXT: // GIR_Coverage, 6,
// NOOPT-NEXT: GIR_Done,
// NOOPT-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]]
Expand Down Expand Up @@ -761,8 +761,8 @@ def XORIb : I<(outs GPR32:$dst), (ins mb:$src2, GPR32:$src1),
// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
// NOOPT-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::R0),
// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Wm
// NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// NOOPT-NEXT: // GIR_Coverage, 23,
// NOOPT-NEXT: GIR_Done,
// NOOPT-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]]
Expand Down Expand Up @@ -802,8 +802,8 @@ def : Pat<(not GPR32:$Wm), (ORN R0, GPR32:$Wm)>;
// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src3
// NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// NOOPT-NEXT: // GIR_Coverage, 7,
// NOOPT-NEXT: GIR_Done,
// NOOPT-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]]
Expand Down Expand Up @@ -840,8 +840,8 @@ def : Pat<(not GPR32:$Wm), (ORN R0, GPR32:$Wm)>;
// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src3
// NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// NOOPT-NEXT: // GIR_Coverage, 28,
// NOOPT-NEXT: GIR_Done,
// NOOPT-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]]
Expand All @@ -864,8 +864,8 @@ def MULADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2, GPR32:$src3),
// NOOPT-NEXT: // 1:{ *:[i32] } => (MOV1:{ *:[i32] })
// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MOV1),
// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
// NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// NOOPT-NEXT: // GIR_Coverage, 8,
// NOOPT-NEXT: GIR_Done,
// NOOPT-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]]
Expand All @@ -887,8 +887,8 @@ def MOV1 : I<(outs GPR32:$dst), (ins), [(set GPR32:$dst, 1)]>;
// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MOVimm8),
// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
// NOOPT-NEXT: GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
// NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// NOOPT-NEXT: // GIR_Coverage, 9,
// NOOPT-NEXT: GIR_Done,
// NOOPT-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]]
Expand All @@ -911,8 +911,8 @@ def MOVimm8 : I<(outs GPR32:$dst), (ins i32imm:$imm), [(set GPR32:$dst, simm8:$i
// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MOVimm9),
// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
// NOOPT-NEXT: GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
// NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// NOOPT-NEXT: // GIR_Coverage, 10,
// NOOPT-NEXT: GIR_Done,
// NOOPT-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]]
Expand All @@ -935,8 +935,8 @@ def MOVimm9 : I<(outs GPR32:$dst), (ins i32imm:$imm), [(set GPR32:$dst, simm9:$i
// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MOVcimm8),
// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
// NOOPT-NEXT: GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderImm), // imm
// NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// NOOPT-NEXT: // GIR_Coverage, 11,
// NOOPT-NEXT: GIR_Done,
// NOOPT-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]]
Expand All @@ -958,8 +958,8 @@ def MOVcimm8 : I<(outs GPR32:$dst), (ins i32imm:$imm), [(set GPR32:$dst, cimm8:$
// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MOVfpimmz),
// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
// NOOPT-NEXT: GIR_CopyFConstantAsFPImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
// NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// NOOPT-NEXT: // GIR_Coverage, 18,
// NOOPT-NEXT: GIR_Done,
// NOOPT-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]]
Expand Down Expand Up @@ -1074,8 +1074,8 @@ def ADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2),
// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::DOUBLE),
// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
// NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// NOOPT-NEXT: // GIR_Coverage, 15,
// NOOPT-NEXT: GIR_Done,
// NOOPT-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]]
Expand Down Expand Up @@ -1153,8 +1153,8 @@ def : Pat<(add i32:$src1, i32:$src2),
// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2
// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
// NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// NOOPT-NEXT: // GIR_Coverage, 16,
// NOOPT-NEXT: GIR_Done,
// NOOPT-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]]
Expand Down Expand Up @@ -1199,8 +1199,8 @@ def : Pat<(i32 (bitconvert FPR32:$src1)),
// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MOVimm),
// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
// NOOPT-NEXT: GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
// NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// NOOPT-NEXT: // GIR_Coverage, 17,
// NOOPT-NEXT: GIR_Done,
// NOOPT-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]]
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizer.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -64,8 +64,8 @@ def LOAD16Imm : I<(outs GPR16:$dst), (ins GPR16:$src), []>;
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
// CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: // GIR_Coverage, 3,
// CHECK-NEXT: GIR_Done,
// CHECK-NEXT: // Label [[L2_ID]]: @[[L2_AT]]
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand-invalid.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -37,8 +37,8 @@ def InstThreeOperands : I<(outs GPR32:$dst), (ins GPR32:$cond, GPR32:$src,GPR32:
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // cond
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: // GIR_Coverage, 1,
// CHECK-NEXT: GIR_Done,
// CHECK-NEXT: // Label 2: @126
Expand All @@ -65,8 +65,8 @@ def InstThreeOperands : I<(outs GPR32:$dst), (ins GPR32:$cond, GPR32:$src,GPR32:
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // cond
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: // GIR_Coverage, 2,
// CHECK-NEXT: GIR_Done,
// CHECK-NEXT: // Label 3: @216
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/TableGen/GlobalISelEmitterRegSequence.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -55,10 +55,10 @@ def SUBSOME_INSN : I<(outs SRegs:$dst), (ins SOP:$src), []>;
// CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1,
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
// CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Test::DRegsRegClassID),
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Test::SRegsRegClassID),
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(Test::SRegsRegClassID),
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
def : Pat<(i32 (sext SOP:$src)),
(REG_SEQUENCE DRegs, (SUBSOME_INSN SOP:$src), sub0,
(SUBSOME_INSN SOP:$src), sub1)>;
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/TableGen/GlobalISelEmitterSubreg.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -75,8 +75,8 @@ def : Pat<(sub (complex DOP:$src1, DOP:$src2), 77),
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,

// Test that we import INSERT_SUBREG when its subregister source has a given
// class.
Expand All @@ -91,10 +91,10 @@ def : Pat<(i32 (anyext i16:$src)), (INSERT_SUBREG (i32 (IMPLICIT_DEF)), SOP:$src
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
// CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Test::DRegsRegClassID),
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Test::DRegsRegClassID),
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Test::SRegsRegClassID),
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,


// Test that we can import INSERT_SUBREG when it is a subinstruction of another
Expand All @@ -117,8 +117,8 @@ def : Pat<(i32 (anyext i16:$src)), (SOME_INSN (INSERT_SUBREG (i32 (IMPLICIT_DEF)
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::SOME_INSN),
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,


// Test that we correctly infer the super register class for INSERT_SUBREG when
Expand Down Expand Up @@ -149,10 +149,10 @@ def : Pat<(i32 (anyext i16:$src)), (INSERT_SUBREG (i32 (IMPLICIT_DEF)), (SUBSOME
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
// CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Test::DRegsRegClassID),
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Test::DRegsRegClassID),
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Test::SRegsRegClassID),
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,

// Test an EXTRACT_SUBREG that is a sub instruction. The individual
// operands should be constrained to specific register classes, and
Expand Down Expand Up @@ -184,9 +184,9 @@ def : Pat<(i16 (trunc (bitreverse DOP:$src))),
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
// CHECK-NEXT: GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(sub0),
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Test::SRegsRegClassID),
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Test::DRegsRegClassID),
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,

// EXTRACT_SUBREG is subinstruction, but also doesn't have a leaf input

Expand All @@ -209,8 +209,8 @@ def : Pat<(i16 (trunc (bitreverse DOP:$src))),
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::SUBSOME_INSN2),
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
def : Pat<(i16 (trunc (ctpop DOP:$src))),
(SUBSOME_INSN2 (EXTRACT_SUBREG (SOME_INSN DOP:$src), sub0))>;

Expand All @@ -221,9 +221,9 @@ def : Pat<(i16 (trunc DOP:$src)),
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
// CHECK-NEXT: GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // src
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Test::SRegsRegClassID),
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Test::DRegsRegClassID),
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,


// Test that we can import SUBREG_TO_REG
Expand All @@ -240,6 +240,6 @@ def : Pat<(i32 (zext SOP:$src)),
// CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
// CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Test::DRegsRegClassID),
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Test::SRegsRegClassID),
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
2 changes: 1 addition & 1 deletion llvm/test/TableGen/HasNoUse.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -28,8 +28,8 @@ def NO_RET_ATOMIC_ADD : I<(outs), (ins GPR32Op:$src0, GPR32Op:$src1), []>;
// GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
// GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
// GISEL-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
// GISEL-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// GISEL-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GISEL-NEXT: GIR_EraseFromParent, /*InsnID*/0,
let HasNoUse = true in
defm atomic_load_add_no_ret : binary_atomic_op<atomic_load_add>;

Expand Down
4 changes: 2 additions & 2 deletions llvm/test/TableGen/gisel-physreg-input.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -43,8 +43,8 @@ class I<dag OOps, dag IOps, list<dag> Pat>
// GISEL-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::ADD_PHYS),
// GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
// GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
// GISEL-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// GISEL-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GISEL-NEXT: GIR_EraseFromParent, /*InsnID*/0,
def ADD_PHYS : I<(outs GPR32:$dst), (ins GPR32:$src0),
[(set GPR32:$dst, (add GPR32:$src0, SPECIAL))]> {
let Uses = [SPECIAL];
Expand All @@ -71,8 +71,8 @@ def ADD_PHYS : I<(outs GPR32:$dst), (ins GPR32:$src0),
// GISEL-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MUL_PHYS),
// GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
// GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // SPECIAL
// GISEL-NEXT: GIR_EraseFromParent, /*InsnID*/0,
// GISEL-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GISEL-NEXT: GIR_EraseFromParent, /*InsnID*/0,
def MUL_PHYS : I<(outs GPR32:$dst), (ins GPR32:$SPECIAL),
[(set GPR32:$dst, (mul GPR32:$SPECIAL, SPECIAL))]> {
let Uses = [SPECIAL];
Expand Down
45 changes: 0 additions & 45 deletions llvm/test/Transforms/InstCombine/cast_ptr.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -113,51 +113,6 @@ define i1 @test4(i32 %A) {
ret i1 %C
}

define i1 @test4_icmp_with_var(i32 %A1, i32 %A2) {
; CHECK-LABEL: @test4_icmp_with_var(
; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[A1:%.*]], [[A2:%.*]]
; CHECK-NEXT: ret i1 [[C]]
;
%B1 = inttoptr i32 %A1 to ptr
%B2 = inttoptr i32 %A2 to ptr
%C = icmp ugt ptr %B1, %B2
ret i1 %C
}

define i1 @test4_cmp_with_nonnull_constant(i32 %A) {
; CHECK-LABEL: @test4_cmp_with_nonnull_constant(
; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[A:%.*]], 1
; CHECK-NEXT: ret i1 [[C]]
;
%B = inttoptr i32 %A to ptr
%C = icmp eq ptr %B, inttoptr (i32 1 to ptr)
ret i1 %C
}

define i1 @test4_cmp_eq_0_or_1(i32 %x) {
; CHECK-LABEL: @test4_cmp_eq_0_or_1(
; CHECK-NEXT: [[OR:%.*]] = icmp ult i32 [[X:%.*]], 2
; CHECK-NEXT: ret i1 [[OR]]
;
%cast = inttoptr i32 %x to ptr
%tobool = icmp eq i32 %x, 0
%cmp = icmp eq ptr %cast, inttoptr (i32 1 to ptr)
%or = or i1 %tobool, %cmp
ret i1 %or
}

define i1 @test4_icmp_with_var_mismatched_type(i32 %A1, i64 %A2) {
; CHECK-LABEL: @test4_icmp_with_var_mismatched_type(
; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[A2:%.*]] to i32
; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[TMP1]], [[A1:%.*]]
; CHECK-NEXT: ret i1 [[C]]
;
%B1 = inttoptr i32 %A1 to ptr
%B2 = inttoptr i64 %A2 to ptr
%C = icmp ugt ptr %B1, %B2
ret i1 %C
}

define i1 @test4_as2(i16 %A) {
; CHECK-LABEL: @test4_as2(
; CHECK-NEXT: [[C:%.*]] = icmp eq i16 [[A:%.*]], 0
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/tools/llvm-dwarfdump/dump_dwo.test
View file
Original file line number Diff line number Diff line change
Expand Up @@ -36,7 +36,7 @@
# CHECK: 0x0000001a: DW_TAG_subprogram
# CHECK: DW_AT_low_pc (0x0000000000000000)
# CHECK: DW_AT_high_pc (0x0000000000000008)
# CHECK: DW_AT_frame_base (DW_OP_reg6 RBP)
# CHECK: DW_AT_frame_base (DW_OP_reg6
# CHECK: DW_AT_linkage_name ("_Z3foov")
# CHECK: DW_AT_name ("foo")
# CHECK: DW_AT_decl_file (0x00)
Expand All @@ -47,7 +47,7 @@
# CHECK: 0x0000002a: DW_TAG_subprogram
# CHECK: DW_AT_low_pc (0x0000000000000010)
# CHECK: DW_AT_high_pc (0x0000000000000033)
# CHECK: DW_AT_frame_base (DW_OP_reg6 RBP)
# CHECK: DW_AT_frame_base (DW_OP_reg6
# CHECK: DW_AT_name ("main")
# CHECK: DW_AT_decl_file (0x00)
# CHECK: DW_AT_decl_line (6)
Expand Down Expand Up @@ -125,7 +125,7 @@
# LOOKUP: 0x0000002a: DW_TAG_subprogram
# LOOKUP: DW_AT_low_pc (0x0000000000000010)
# LOOKUP: DW_AT_high_pc (0x0000000000000033)
# LOOKUP: DW_AT_frame_base (DW_OP_reg6)
# LOOKUP: DW_AT_frame_base (DW_OP_reg6
# LOOKUP: DW_AT_name ("main")
# LOOKUP: DW_AT_decl_file (0x00)
# LOOKUP: DW_AT_decl_line (6)
Expand Down
2 changes: 2 additions & 0 deletions llvm/unittests/MIR/CMakeLists.txt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,13 +6,15 @@ set(LLVM_LINK_COMPONENTS
FileCheck
MC
MIRParser
Passes
Support
Target
TargetParser
)

add_llvm_unittest(MIRTests
MachineMetadata.cpp
PassBuilderCallbacksTest.cpp
)

target_link_libraries(MIRTests PRIVATE LLVMTestingSupport)
500 changes: 500 additions & 0 deletions llvm/unittests/MIR/PassBuilderCallbacksTest.cpp
View file

Large diffs are not rendered by default.

11 changes: 5 additions & 6 deletions llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2185,6 +2185,11 @@ bool CombineRuleBuilder::emitApplyPatterns(CodeExpansions &CE, RuleMatcher &M) {
}
}

// Erase the root.
unsigned RootInsnID =
M.getInsnVarID(M.getInstructionMatcher(MatchRoot->getName()));
M.addAction<EraseInstAction>(RootInsnID);

return true;
}

Expand Down Expand Up @@ -2418,12 +2423,6 @@ bool CombineRuleBuilder::emitBuiltinApplyPattern(
// checkSemantics should have ensured that we can only rewrite the root.
// Ensure we're deleting it.
assert(MatchOpTable.getDef(Old) == MatchRoot);
// TODO: We could avoid adding the action again if it's already in. The
// MatchTable is smart enough to only emit one opcode even if
// EraseInstAction is present multiple times. I think searching for a copy
// is more expensive than just blindly adding it though.
M.addAction<EraseInstAction>(/*InsnID*/ 0);

return true;
}
}
Expand Down
43 changes: 13 additions & 30 deletions llvm/utils/TableGen/GlobalISelEmitter.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1972,6 +1972,10 @@ Expected<RuleMatcher> GlobalISelEmitter::runOnPattern(const PatternToMatch &P) {
DstMIBuilder.addRenderer<CopyRenderer>(Dst->getName());
M.addAction<ConstrainOperandToRegClassAction>(0, 0, RC);

// Erase the root.
unsigned RootInsnID = M.getInsnVarID(InsnMatcher);
M.addAction<EraseInstAction>(RootInsnID);

// We're done with this pattern! It's eligible for GISel emission; return
// it.
++NumPatternImported;
Expand Down Expand Up @@ -2099,14 +2103,7 @@ Expected<RuleMatcher> GlobalISelEmitter::runOnPattern(const PatternToMatch &P) {

M.addAction<ConstrainOperandToRegClassAction>(
0, 0, Target.getRegisterClass(DstIOpRec));

// We're done with this pattern! It's eligible for GISel emission; return
// it.
++NumPatternImported;
return std::move(M);
}

if (DstIName == "EXTRACT_SUBREG") {
} else if (DstIName == "EXTRACT_SUBREG") {
auto SuperClass = inferRegClassFromPattern(Dst->getChild(0));
if (!SuperClass)
return failedImport(
Expand Down Expand Up @@ -2136,14 +2133,7 @@ Expected<RuleMatcher> GlobalISelEmitter::runOnPattern(const PatternToMatch &P) {
M.addAction<ConstrainOperandToRegClassAction>(0, 0,
*SrcRCDstRCPair->second);
M.addAction<ConstrainOperandToRegClassAction>(0, 1, *SrcRCDstRCPair->first);

// We're done with this pattern! It's eligible for GISel emission; return
// it.
++NumPatternImported;
return std::move(M);
}

if (DstIName == "INSERT_SUBREG") {
} else if (DstIName == "INSERT_SUBREG") {
assert(Src->getExtTypes().size() == 1 &&
"Expected Src of INSERT_SUBREG to have one result type");
// We need to constrain the destination, a super regsister source, and a
Expand All @@ -2160,11 +2150,7 @@ Expected<RuleMatcher> GlobalISelEmitter::runOnPattern(const PatternToMatch &P) {
M.addAction<ConstrainOperandToRegClassAction>(0, 0, **SuperClass);
M.addAction<ConstrainOperandToRegClassAction>(0, 1, **SuperClass);
M.addAction<ConstrainOperandToRegClassAction>(0, 2, **SubClass);
++NumPatternImported;
return std::move(M);
}

if (DstIName == "SUBREG_TO_REG") {
} else if (DstIName == "SUBREG_TO_REG") {
// We need to constrain the destination and subregister source.
assert(Src->getExtTypes().size() == 1 &&
"Expected Src of SUBREG_TO_REG to have one result type");
Expand All @@ -2184,11 +2170,7 @@ Expected<RuleMatcher> GlobalISelEmitter::runOnPattern(const PatternToMatch &P) {
"Cannot infer register class for SUBREG_TO_REG operand #0");
M.addAction<ConstrainOperandToRegClassAction>(0, 0, **SuperClass);
M.addAction<ConstrainOperandToRegClassAction>(0, 2, **SubClass);
++NumPatternImported;
return std::move(M);
}

if (DstIName == "REG_SEQUENCE") {
} else if (DstIName == "REG_SEQUENCE") {
auto SuperClass = inferRegClassFromPattern(Dst->getChild(0));

M.addAction<ConstrainOperandToRegClassAction>(0, 0, **SuperClass);
Expand All @@ -2207,12 +2189,13 @@ Expected<RuleMatcher> GlobalISelEmitter::runOnPattern(const PatternToMatch &P) {
M.addAction<ConstrainOperandToRegClassAction>(0, I,
*SrcRCDstRCPair->second);
}

++NumPatternImported;
return std::move(M);
} else {
M.addAction<ConstrainOperandsToDefinitionAction>(0);
}

M.addAction<ConstrainOperandsToDefinitionAction>(0);
// Erase the root.
unsigned RootInsnID = M.getInsnVarID(InsnMatcher);
M.addAction<EraseInstAction>(RootInsnID);

// We're done with this pattern! It's eligible for GISel emission; return it.
++NumPatternImported;
Expand Down
9 changes: 3 additions & 6 deletions llvm/utils/TableGen/GlobalISelMatchTable.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2172,6 +2172,9 @@ void BuildMIAction::emitActionOpcodes(MatchTable &Table,
}

AddMIFlags();

// Mark the mutated instruction as erased.
Rule.tryEraseInsnID(RecycleInsnID);
return;
}

Expand Down Expand Up @@ -2223,12 +2226,6 @@ void BuildMIAction::emitActionOpcodes(MatchTable &Table,
}

AddMIFlags();

// FIXME: This is a hack but it's sufficient for ISel. We'll need to do
// better for combines. Particularly when there are multiple match
// roots.
if (InsnID == 0)
EraseInstAction::emitActionOpcodes(Table, Rule, /*InsnID*/ 0);
}

//===- BuildConstantAction ------------------------------------------------===//
Expand Down
5 changes: 4 additions & 1 deletion llvm/utils/gn/secondary/llvm/unittests/MIR/BUILD.gn
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,5 +13,8 @@ unittest("MIRTests") {
"//llvm/lib/TargetParser",
"//llvm/lib/Testing/Support",
]
sources = [ "MachineMetadata.cpp" ]
sources = [
"MachineMetadata.cpp",
"PassBuilderCallbacksTest.cpp",
]
}
16 changes: 16 additions & 0 deletions mlir/include/mlir/Analysis/Presburger/Barvinok.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -27,6 +27,7 @@
#include "mlir/Analysis/Presburger/GeneratingFunction.h"
#include "mlir/Analysis/Presburger/IntegerRelation.h"
#include "mlir/Analysis/Presburger/Matrix.h"
#include "mlir/Analysis/Presburger/QuasiPolynomial.h"
#include <optional>

namespace mlir {
Expand Down Expand Up @@ -83,6 +84,21 @@ ConeH getDual(ConeV cone);
GeneratingFunction unimodularConeGeneratingFunction(ParamPoint vertex, int sign,
ConeH cone);

/// Find a vector that is not orthogonal to any of the given vectors,
/// i.e., has nonzero dot product with those of the given vectors
/// that are not null.
/// If any of the vectors is null, it is ignored.
Point getNonOrthogonalVector(ArrayRef<Point> vectors);

/// Find the coefficient of a given power of s in a rational function
/// given by P(s)/Q(s), where
/// P is a polynomial, in which the coefficients are QuasiPolynomials
/// over d parameters (distinct from s), and
/// and Q is a polynomial with Fraction coefficients.
QuasiPolynomial getCoefficientInRationalFunction(unsigned power,
ArrayRef<QuasiPolynomial> num,
ArrayRef<Fraction> den);

} // namespace detail
} // namespace presburger
} // namespace mlir
Expand Down
18 changes: 18 additions & 0 deletions mlir/include/mlir/Analysis/Presburger/Matrix.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -192,6 +192,24 @@ class Matrix {
/// invariants satisfied.
bool hasConsistentState() const;

/// Move the columns in the source range [srcPos, srcPos + num) to the
/// specified destination [dstPos, dstPos + num), while moving the columns
/// adjacent to the source range to the left/right of the shifted columns.
///
/// When moving the source columns right (i.e. dstPos > srcPos), columns that
/// were at positions [0, srcPos) and [dstPos + num, nCols) will stay where
/// they are; columns that were at positions [srcPos, srcPos + num) will be
/// moved to [dstPos, dstPos + num); and columns that were at positions
/// [srcPos + num, dstPos + num) will be moved to [srcPos, dstPos).
/// Equivalently, the columns [srcPos + num, dstPos + num) are interchanged
/// with [srcPos, srcPos + num).
/// For example, if m = |0 1 2 3 4 5| then:
/// m.moveColumns(1, 3, 2) will result in m = |0 4 1 2 3 5|; or
/// m.moveColumns(1, 2, 4) will result in m = |0 3 4 5 1 2|.
///
/// The left shift operation (i.e. dstPos < srcPos) works in a similar way.
void moveColumns(unsigned srcPos, unsigned num, unsigned dstPos);

protected:
/// The current number of rows, columns, and reserved columns. The underlying
/// data vector is viewed as an nRows x nReservedColumns matrix, of which the
Expand Down
4 changes: 4 additions & 0 deletions mlir/include/mlir/Analysis/Presburger/QuasiPolynomial.h
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Original file line number Diff line number Diff line change
Expand Up @@ -39,6 +39,8 @@ class QuasiPolynomial : public PresburgerSpace {
QuasiPolynomial(unsigned numVars, SmallVector<Fraction> coeffs = {},
std::vector<std::vector<SmallVector<Fraction>>> aff = {});

QuasiPolynomial(unsigned numVars, Fraction constant);

// Find the number of inputs (numDomain) to the polynomial.
// numSymbols is set to zero.
unsigned getNumInputs() const {
Expand All @@ -60,6 +62,8 @@ class QuasiPolynomial : public PresburgerSpace {
// Removes terms which evaluate to zero from the expression.
QuasiPolynomial simplify();

Fraction getConstantTerm();

private:
SmallVector<Fraction> coefficients;
std::vector<std::vector<SmallVector<Fraction>>> affine;
Expand Down
101 changes: 101 additions & 0 deletions mlir/lib/Analysis/Presburger/Barvinok.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -8,6 +8,7 @@

#include "mlir/Analysis/Presburger/Barvinok.h"
#include "llvm/ADT/Sequence.h"
#include <algorithm>

using namespace mlir;
using namespace presburger;
Expand Down Expand Up @@ -144,3 +145,103 @@ GeneratingFunction mlir::presburger::detail::unimodularConeGeneratingFunction(
std::vector({numerator}),
std::vector({denominator}));
}

/// We use an iterative procedure to find a vector not orthogonal
/// to a given set, ignoring the null vectors.
/// Let the inputs be {x_1, ..., x_k}, all vectors of length n.
///
/// In the following,
/// vs[:i] means the elements of vs up to and including the i'th one,
/// <vs, us> means the dot product of vs and us,
/// vs ++ [v] means the vector vs with the new element v appended to it.
///
/// We proceed iteratively; for steps d = 0, ... n-1, we construct a vector
/// which is not orthogonal to any of {x_1[:d], ..., x_n[:d]}, ignoring
/// the null vectors.
/// At step d = 0, we let vs = [1]. Clearly this is not orthogonal to
/// any vector in the set {x_1[0], ..., x_n[0]}, except the null ones,
/// which we ignore.
/// At step d > 0 , we need a number v
/// s.t. <x_i[:d], vs++[v]> != 0 for all i.
/// => <x_i[:d-1], vs> + x_i[d]*v != 0
/// => v != - <x_i[:d-1], vs> / x_i[d]
/// We compute this value for all x_i, and then
/// set v to be the maximum element of this set plus one. Thus
/// v is outside the set as desired, and we append it to vs
/// to obtain the result of the d'th step.
Point mlir::presburger::detail::getNonOrthogonalVector(
ArrayRef<Point> vectors) {
unsigned dim = vectors[0].size();
assert(
llvm::all_of(vectors,
[&](const Point &vector) { return vector.size() == dim; }) &&
"all vectors need to be the same size!");

SmallVector<Fraction> newPoint = {Fraction(1, 1)};
Fraction maxDisallowedValue = -Fraction(1, 0),
disallowedValue = Fraction(0, 1);

for (unsigned d = 1; d < dim; ++d) {
// Compute the disallowed values - <x_i[:d-1], vs> / x_i[d] for each i.
maxDisallowedValue = -Fraction(1, 0);
for (const Point &vector : vectors) {
if (vector[d] == 0)
continue;
disallowedValue =
-dotProduct(ArrayRef(vector).slice(0, d), newPoint) / vector[d];

// Find the biggest such value
maxDisallowedValue = std::max(maxDisallowedValue, disallowedValue);
}
newPoint.push_back(maxDisallowedValue + 1);
}
return newPoint;
}

/// We use the following recursive formula to find the coefficient of
/// s^power in the rational function given by P(s)/Q(s).
///
/// Let P[i] denote the coefficient of s^i in the polynomial P(s).
/// (P/Q)[r] =
/// if (r == 0) then
/// P[0]/Q[0]
/// else
/// (P[r] - {Σ_{i=1}^r (P/Q)[r-i] * Q[i])}/(Q[0])
/// We therefore recursively call `getCoefficientInRationalFunction` on
/// all i \in [0, power).
///
/// https://math.ucdavis.edu/~deloera/researchsummary/
/// barvinokalgorithm-latte1.pdf, p. 1285
QuasiPolynomial mlir::presburger::detail::getCoefficientInRationalFunction(
unsigned power, ArrayRef<QuasiPolynomial> num, ArrayRef<Fraction> den) {
assert(den.size() != 0 &&
"division by empty denominator in rational function!");

unsigned numParam = num[0].getNumInputs();
// We use the `isEqual` method of PresburgerSpace, which QuasiPolynomial
// inherits from.
assert(
llvm::all_of(
num, [&](const QuasiPolynomial &qp) { return num[0].isEqual(qp); }) &&
"the quasipolynomials should all belong to the same space!");

std::vector<QuasiPolynomial> coefficients;
coefficients.reserve(power + 1);

coefficients.push_back(num[0] / den[0]);
for (unsigned i = 1; i <= power; ++i) {
// If the power is not there in the numerator, the coefficient is zero.
coefficients.push_back(i < num.size() ? num[i]
: QuasiPolynomial(numParam, 0));

// After den.size(), the coefficients are zero, so we stop
// subtracting at that point (if it is less than i).
unsigned limit = std::min<unsigned long>(i, den.size() - 1);
for (unsigned j = 1; j <= limit; ++j)
coefficients[i] = coefficients[i] -
coefficients[i - j] * QuasiPolynomial(numParam, den[j]);

coefficients[i] = coefficients[i] / den[0];
}
return coefficients[power].simplify();
}
41 changes: 41 additions & 0 deletions mlir/lib/Analysis/Presburger/Matrix.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -240,6 +240,47 @@ void Matrix<T>::fillRow(unsigned row, const T &value) {
at(row, col) = value;
}

// moveColumns is implemented by moving the columns adjacent to the source range
// to their final position. When moving right (i.e. dstPos > srcPos), the range
// of the adjacent columns is [srcPos + num, dstPos + num). When moving left
// (i.e. dstPos < srcPos) the range of the adjacent columns is [dstPos, srcPos).
// First, zeroed out columns are inserted in the final positions of the adjacent
// columns. Then, the adjacent columns are moved to their final positions by
// swapping them with the zeroed columns. Finally, the now zeroed adjacent
// columns are deleted.
template <typename T>
void Matrix<T>::moveColumns(unsigned srcPos, unsigned num, unsigned dstPos) {
if (num == 0)
return;

int offset = dstPos - srcPos;
if (offset == 0)
return;

assert(srcPos + num <= getNumColumns() &&
"move source range exceeds matrix columns");
assert(dstPos + num <= getNumColumns() &&
"move destination range exceeds matrix columns");

unsigned insertCount = offset > 0 ? offset : -offset;
unsigned finalAdjStart = offset > 0 ? srcPos : srcPos + num;
unsigned curAdjStart = offset > 0 ? srcPos + num : dstPos;
// TODO: This can be done using std::rotate.
// Insert new zero columns in the positions where the adjacent columns are to
// be moved.
insertColumns(finalAdjStart, insertCount);
// Update curAdjStart if insertion of new columns invalidates it.
if (finalAdjStart < curAdjStart)
curAdjStart += insertCount;

// Swap the adjacent columns with inserted zero columns.
for (unsigned i = 0; i < insertCount; ++i)
swapColumns(finalAdjStart + i, curAdjStart + i);

// Delete the now redundant zero columns.
removeColumns(curAdjStart, insertCount);
}

template <typename T>
void Matrix<T>::addToRow(unsigned sourceRow, unsigned targetRow,
const T &scale) {
Expand Down
14 changes: 14 additions & 0 deletions mlir/lib/Analysis/Presburger/QuasiPolynomial.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -36,6 +36,12 @@ QuasiPolynomial::QuasiPolynomial(
#endif // NDEBUG
}

/// Define a quasipolynomial which is a single constant.
QuasiPolynomial::QuasiPolynomial(unsigned numVars, Fraction constant)
: PresburgerSpace(/*numDomain=*/numVars, /*numRange=*/1, /*numSymbols=*/0,
/*numLocals=*/0),
coefficients({constant}), affine({{}}) {}

QuasiPolynomial QuasiPolynomial::operator+(const QuasiPolynomial &x) const {
assert(getNumInputs() == x.getNumInputs() &&
"two quasi-polynomials with different numbers of symbols cannot "
Expand Down Expand Up @@ -113,3 +119,11 @@ QuasiPolynomial QuasiPolynomial::simplify() {
}
return QuasiPolynomial(getNumInputs(), newCoeffs, newAffine);
}

Fraction QuasiPolynomial::getConstantTerm() {
Fraction constTerm = 0;
for (unsigned i = 0, e = coefficients.size(); i < e; ++i)
if (affine[i].size() == 0)
constTerm += coefficients[i];
return constTerm;
}
2 changes: 1 addition & 1 deletion mlir/lib/Dialect/Bufferization/Transforms/OneShotAnalysis.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -279,7 +279,7 @@ static bool isReachable(Block *from, Block *to, ArrayRef<Block *> except) {
worklist.push_back(succ);
while (!worklist.empty()) {
Block *next = worklist.pop_back_val();
if (llvm::find(except, next) != except.end())
if (llvm::is_contained(except, next))
continue;
if (next == to)
return true;
Expand Down
2 changes: 1 addition & 1 deletion mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1759,7 +1759,7 @@ transform::PadOp::apply(transform::TransformRewriter &rewriter,
if (options.copyBackOp != LinalgPaddingOptions::CopyBackOp::None) {
for (Value v : replacements) {
Operation *copyBackOp = v.getDefiningOp();
if (llvm::find(copyBackOps, copyBackOp) == copyBackOps.end())
if (!llvm::is_contained(copyBackOps, copyBackOp))
copyBackOps.push_back(copyBackOp);
}
}
Expand Down
2 changes: 1 addition & 1 deletion mlir/lib/Dialect/Linalg/Transforms/BufferizableOpInterfaceImpl.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -125,7 +125,7 @@ struct LinalgOpInterface
if (!isa<RankedTensorType, MemRefType>(operand.get().getType()))
continue;
// Only consider operands in `opOperands`.
if (llvm::find(opOperands, &operand) == opOperands.end())
if (!llvm::is_contained(opOperands, &operand))
continue;
// TODO: This could be generalized to other indexing maps. (All indexing
// must be the same.)
Expand Down
2 changes: 1 addition & 1 deletion mlir/lib/Dialect/Linalg/Transforms/ConvertToDestinationStyle.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -523,7 +523,7 @@ Value linalg::bufferizeToAllocation(
// bufferize out-of-place.
SmallVector<OpOperand *> outOfPlaceOperands, resultUses;
auto addOutOfPlaceOperand = [&](OpOperand *operand) {
if (llvm::find(outOfPlaceOperands, operand) == outOfPlaceOperands.end())
if (!llvm::is_contained(outOfPlaceOperands, operand))
outOfPlaceOperands.push_back(operand);
};
for (OpResult result : tensorResults) {
Expand Down
3 changes: 1 addition & 2 deletions mlir/lib/Dialect/Vector/Transforms/BufferizableOpInterfaceImpl.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -217,8 +217,7 @@ struct MaskOpInterface
SmallVector<Value> newReturnValues(maskOp->getNumResults(), Value());
SmallVector<Value> newYieldedValues;
for (const auto &it : llvm::enumerate(yieldOp.getOperands())) {
if (llvm::find(maskedOp->getOpResults(), it.value()) !=
maskedOp->getOpResults().end()) {
if (llvm::is_contained(maskedOp->getOpResults(), it.value())) {
newYieldedValues.push_back(it.value());
} else {
// This used to be a tensor result of the masked op, but is now a memref
Expand Down
42 changes: 42 additions & 0 deletions mlir/unittests/Analysis/Presburger/BarvinokTest.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -82,3 +82,45 @@ TEST(BarvinokTest, unimodularConeGeneratingFunction) {
1, {1}, {makeFracMatrix(2, 3, {{-83, -100, -41}, {-22, -27, -15}})},
{{{8, 47, -17}, {-7, -41, 15}, {1, 5, -2}}}));
}

// The following vectors are randomly generated.
// We then check that the output of the function has non-zero
// dot product with all non-null vectors.
TEST(BarvinokTest, getNonOrthogonalVector) {
std::vector<Point> vectors = {Point({1, 2, 3, 4}), Point({-1, 0, 1, 1}),
Point({2, 7, 0, 0}), Point({0, 0, 0, 0})};
Point nonOrth = getNonOrthogonalVector(vectors);

for (unsigned i = 0; i < 3; i++)
EXPECT_NE(dotProduct(nonOrth, vectors[i]), 0);

vectors = {Point({0, 1, 3}), Point({-2, -1, 1}), Point({6, 3, 0}),
Point({0, 0, -3}), Point({5, 0, -1})};
nonOrth = getNonOrthogonalVector(vectors);

for (const Point &vector : vectors)
EXPECT_NE(dotProduct(nonOrth, vector), 0);
}

// The following polynomials are randomly generated and the
// coefficients are computed by hand.
// Although the function allows the coefficients of the numerator
// to be arbitrary quasipolynomials, we stick to constants for simplicity,
// as the relevant arithmetic operations on quasipolynomials
// are tested separately.
TEST(BarvinokTest, getCoefficientInRationalFunction) {
std::vector<QuasiPolynomial> numerator = {
QuasiPolynomial(0, 2), QuasiPolynomial(0, 3), QuasiPolynomial(0, 5)};
std::vector<Fraction> denominator = {Fraction(1), Fraction(0), Fraction(4),
Fraction(3)};
QuasiPolynomial coeff =
getCoefficientInRationalFunction(1, numerator, denominator);
EXPECT_EQ(coeff.getConstantTerm(), 3);

numerator = {QuasiPolynomial(0, -1), QuasiPolynomial(0, 4),
QuasiPolynomial(0, -2), QuasiPolynomial(0, 5),
QuasiPolynomial(0, 6)};
denominator = {Fraction(8), Fraction(4), Fraction(0), Fraction(-2)};
coeff = getCoefficientInRationalFunction(3, numerator, denominator);
EXPECT_EQ(coeff.getConstantTerm(), Fraction(55, 64));
}
53 changes: 49 additions & 4 deletions mlir/unittests/Analysis/Presburger/MatrixTest.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -194,13 +194,21 @@ TEST(MatrixTest, resize) {
EXPECT_EQ(mat(row, col), row >= 3 || col >= 3 ? 0 : int(10 * row + col));
}

template <typename T>
static void checkMatEqual(const Matrix<T> m1, const Matrix<T> m2) {
EXPECT_EQ(m1.getNumRows(), m2.getNumRows());
EXPECT_EQ(m1.getNumColumns(), m2.getNumColumns());

for (unsigned row = 0, rows = m1.getNumRows(); row < rows; ++row)
for (unsigned col = 0, cols = m1.getNumColumns(); col < cols; ++col)
EXPECT_EQ(m1(row, col), m2(row, col));
}

static void checkHermiteNormalForm(const IntMatrix &mat,
const IntMatrix &hermiteForm) {
auto [h, u] = mat.computeHermiteNormalForm();

for (unsigned row = 0; row < mat.getNumRows(); row++)
for (unsigned col = 0; col < mat.getNumColumns(); col++)
EXPECT_EQ(h(row, col), hermiteForm(row, col));
checkMatEqual(h, hermiteForm);
}

TEST(MatrixTest, computeHermiteNormalForm) {
Expand Down Expand Up @@ -428,4 +436,41 @@ TEST(MatrixTest, LLL) {
mat.LLL(Fraction(3, 4));

checkReducedBasis(mat, Fraction(3, 4));
}
}

TEST(MatrixTest, moveColumns) {
IntMatrix mat =
makeIntMatrix(3, 4, {{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 4, 2}});

{
IntMatrix movedMat =
makeIntMatrix(3, 4, {{0, 3, 1, 2}, {4, 7, 5, 6}, {8, 2, 9, 4}});

movedMat.moveColumns(2, 2, 1);
checkMatEqual(mat, movedMat);
}

{
IntMatrix movedMat =
makeIntMatrix(3, 4, {{0, 3, 1, 2}, {4, 7, 5, 6}, {8, 2, 9, 4}});

movedMat.moveColumns(1, 1, 3);
checkMatEqual(mat, movedMat);
}

{
IntMatrix movedMat =
makeIntMatrix(3, 4, {{1, 2, 0, 3}, {5, 6, 4, 7}, {9, 4, 8, 2}});

movedMat.moveColumns(0, 2, 1);
checkMatEqual(mat, movedMat);
}

{
IntMatrix movedMat =
makeIntMatrix(3, 4, {{1, 0, 2, 3}, {5, 4, 6, 7}, {9, 8, 4, 2}});

movedMat.moveColumns(0, 1, 1);
checkMatEqual(mat, movedMat);
}
}