40 changes: 20 additions & 20 deletions llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3449,7 +3449,7 @@ static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
}

/// parseITCondCode - Try to parse a condition code for an IT instruction.
ARMAsmParser::OperandMatchResultTy
OperandMatchResultTy
ARMAsmParser::parseITCondCode(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
SMLoc S = Parser.getTok().getLoc();
Expand Down Expand Up @@ -3487,7 +3487,7 @@ ARMAsmParser::parseITCondCode(OperandVector &Operands) {
/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
/// token must be an Identifier when called, and if it is a coprocessor
/// number, the token is eaten and the operand is added to the operand list.
ARMAsmParser::OperandMatchResultTy
OperandMatchResultTy
ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
SMLoc S = Parser.getTok().getLoc();
Expand All @@ -3510,7 +3510,7 @@ ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) {
/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
/// token must be an Identifier when called, and if it is a coprocessor
/// number, the token is eaten and the operand is added to the operand list.
ARMAsmParser::OperandMatchResultTy
OperandMatchResultTy
ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
SMLoc S = Parser.getTok().getLoc();
Expand All @@ -3529,7 +3529,7 @@ ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) {

/// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
/// coproc_option : '{' imm0_255 '}'
ARMAsmParser::OperandMatchResultTy
OperandMatchResultTy
ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
SMLoc S = Parser.getTok().getLoc();
Expand Down Expand Up @@ -3739,7 +3739,7 @@ bool ARMAsmParser::parseRegisterList(OperandVector &Operands) {
}

// Helper function to parse the lane index for vector lists.
ARMAsmParser::OperandMatchResultTy ARMAsmParser::
OperandMatchResultTy ARMAsmParser::
parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
MCAsmParser &Parser = getParser();
Index = 0; // Always return a defined index value.
Expand Down Expand Up @@ -3791,7 +3791,7 @@ parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
}

// parse a vector register list
ARMAsmParser::OperandMatchResultTy
OperandMatchResultTy
ARMAsmParser::parseVectorList(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
VectorLaneTy LaneKind;
Expand Down Expand Up @@ -4043,7 +4043,7 @@ ARMAsmParser::parseVectorList(OperandVector &Operands) {
}

/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
ARMAsmParser::OperandMatchResultTy
OperandMatchResultTy
ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
SMLoc S = Parser.getTok().getLoc();
Expand Down Expand Up @@ -4115,7 +4115,7 @@ ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) {
}

/// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
ARMAsmParser::OperandMatchResultTy
OperandMatchResultTy
ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
SMLoc S = Parser.getTok().getLoc();
Expand Down Expand Up @@ -4167,7 +4167,7 @@ ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) {


/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
ARMAsmParser::OperandMatchResultTy
OperandMatchResultTy
ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
SMLoc S = Parser.getTok().getLoc();
Expand Down Expand Up @@ -4202,7 +4202,7 @@ ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) {
}

/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
ARMAsmParser::OperandMatchResultTy
OperandMatchResultTy
ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
SMLoc S = Parser.getTok().getLoc();
Expand Down Expand Up @@ -4355,7 +4355,7 @@ ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {

/// parseBankedRegOperand - Try to parse a banked register (e.g. "lr_irq") for
/// use in the MRS/MSR instructions added to support virtualization.
ARMAsmParser::OperandMatchResultTy
OperandMatchResultTy
ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
SMLoc S = Parser.getTok().getLoc();
Expand Down Expand Up @@ -4410,7 +4410,7 @@ ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) {
return MatchOperand_Success;
}

ARMAsmParser::OperandMatchResultTy
OperandMatchResultTy
ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low,
int High) {
MCAsmParser &Parser = getParser();
Expand Down Expand Up @@ -4459,7 +4459,7 @@ ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low,
return MatchOperand_Success;
}

ARMAsmParser::OperandMatchResultTy
OperandMatchResultTy
ARMAsmParser::parseSetEndImm(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
const AsmToken &Tok = Parser.getTok();
Expand Down Expand Up @@ -4489,7 +4489,7 @@ ARMAsmParser::parseSetEndImm(OperandVector &Operands) {
/// lsl #n 'n' in [0,31]
/// asr #n 'n' in [1,32]
/// n == 32 encoded as n == 0.
ARMAsmParser::OperandMatchResultTy
OperandMatchResultTy
ARMAsmParser::parseShifterImm(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
const AsmToken &Tok = Parser.getTok();
Expand Down Expand Up @@ -4560,7 +4560,7 @@ ARMAsmParser::parseShifterImm(OperandVector &Operands) {
/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
/// of instructions. Legal values are:
/// ror #n 'n' in {0, 8, 16, 24}
ARMAsmParser::OperandMatchResultTy
OperandMatchResultTy
ARMAsmParser::parseRotImm(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
const AsmToken &Tok = Parser.getTok();
Expand Down Expand Up @@ -4607,7 +4607,7 @@ ARMAsmParser::parseRotImm(OperandVector &Operands) {
return MatchOperand_Success;
}

ARMAsmParser::OperandMatchResultTy
OperandMatchResultTy
ARMAsmParser::parseModImm(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
MCAsmLexer &Lexer = getLexer();
Expand Down Expand Up @@ -4724,7 +4724,7 @@ ARMAsmParser::parseModImm(OperandVector &Operands) {
}
}

ARMAsmParser::OperandMatchResultTy
OperandMatchResultTy
ARMAsmParser::parseBitfield(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
SMLoc S = Parser.getTok().getLoc();
Expand Down Expand Up @@ -4793,7 +4793,7 @@ ARMAsmParser::parseBitfield(OperandVector &Operands) {
return MatchOperand_Success;
}

ARMAsmParser::OperandMatchResultTy
OperandMatchResultTy
ARMAsmParser::parsePostIdxReg(OperandVector &Operands) {
// Check for a post-index addressing register operand. Specifically:
// postidx_reg := '+' register {, shift}
Expand Down Expand Up @@ -4843,7 +4843,7 @@ ARMAsmParser::parsePostIdxReg(OperandVector &Operands) {
return MatchOperand_Success;
}

ARMAsmParser::OperandMatchResultTy
OperandMatchResultTy
ARMAsmParser::parseAM3Offset(OperandVector &Operands) {
// Check for a post-index addressing register operand. Specifically:
// am3offset := '+' register
Expand Down Expand Up @@ -5245,7 +5245,7 @@ bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
}

/// parseFPImm - A floating point immediate expression operand.
ARMAsmParser::OperandMatchResultTy
OperandMatchResultTy
ARMAsmParser::parseFPImm(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
// Anything that can accept a floating point constant as an operand
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -496,7 +496,7 @@ bool AVRAsmParser::parseOperand(OperandVector &Operands) {
return true;
}

AVRAsmParser::OperandMatchResultTy
OperandMatchResultTy
AVRAsmParser::parseMemriOperand(OperandVector &Operands) {
DEBUG(dbgs() << "parseMemriOperand()\n");

Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -844,7 +844,7 @@ bool shouldBeSls(const LanaiOperand &Op) {
}

// Matches memory operand. Returns true if error encountered.
LanaiAsmParser::OperandMatchResultTy
OperandMatchResultTy
LanaiAsmParser::parseMemoryOperand(OperandVector &Operands) {
// Try to match a memory operand.
// The memory operands are of the form:
Expand Down Expand Up @@ -978,7 +978,7 @@ LanaiAsmParser::parseMemoryOperand(OperandVector &Operands) {
// Looks at a token type and creates the relevant operand from this
// information, adding to operands.
// If operand was parsed, returns false, else true.
LanaiAsmParser::OperandMatchResultTy
OperandMatchResultTy
LanaiAsmParser::parseOperand(OperandVector *Operands, StringRef Mnemonic) {
// Check if the current operand has a custom associated parser, if so, try to
// custom parse the operand, or fallback to the general approach.
Expand Down
20 changes: 10 additions & 10 deletions llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4512,14 +4512,14 @@ bool MipsAsmParser::parseMemOffset(const MCExpr *&Res, bool isParenExpr) {
return getParser().parseExpression(Res);
}

MipsAsmParser::OperandMatchResultTy
OperandMatchResultTy
MipsAsmParser::parseMemOperand(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
DEBUG(dbgs() << "parseMemOperand\n");
const MCExpr *IdVal = nullptr;
SMLoc S;
bool isParenExpr = false;
MipsAsmParser::OperandMatchResultTy Res = MatchOperand_NoMatch;
OperandMatchResultTy Res = MatchOperand_NoMatch;
// First operand is the offset.
S = Parser.getTok().getLoc();

Expand Down Expand Up @@ -4676,7 +4676,7 @@ bool MipsAsmParser::searchSymbolAlias(OperandVector &Operands) {
return false;
}

MipsAsmParser::OperandMatchResultTy
OperandMatchResultTy
MipsAsmParser::matchAnyRegisterNameWithoutDollar(OperandVector &Operands,
StringRef Identifier,
SMLoc S) {
Expand Down Expand Up @@ -4739,7 +4739,7 @@ MipsAsmParser::matchAnyRegisterNameWithoutDollar(OperandVector &Operands,
return MatchOperand_NoMatch;
}

MipsAsmParser::OperandMatchResultTy
OperandMatchResultTy
MipsAsmParser::matchAnyRegisterWithoutDollar(OperandVector &Operands, SMLoc S) {
MCAsmParser &Parser = getParser();
auto Token = Parser.getLexer().peekTok(false);
Expand All @@ -4763,7 +4763,7 @@ MipsAsmParser::matchAnyRegisterWithoutDollar(OperandVector &Operands, SMLoc S) {
return MatchOperand_NoMatch;
}

MipsAsmParser::OperandMatchResultTy
OperandMatchResultTy
MipsAsmParser::parseAnyRegister(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
DEBUG(dbgs() << "parseAnyRegister\n");
Expand Down Expand Up @@ -4791,7 +4791,7 @@ MipsAsmParser::parseAnyRegister(OperandVector &Operands) {
return ResTy;
}

MipsAsmParser::OperandMatchResultTy
OperandMatchResultTy
MipsAsmParser::parseJumpTarget(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
DEBUG(dbgs() << "parseJumpTarget\n");
Expand All @@ -4814,7 +4814,7 @@ MipsAsmParser::parseJumpTarget(OperandVector &Operands) {
return MatchOperand_Success;
}

MipsAsmParser::OperandMatchResultTy
OperandMatchResultTy
MipsAsmParser::parseInvNum(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
const MCExpr *IdVal;
Expand All @@ -4833,7 +4833,7 @@ MipsAsmParser::parseInvNum(OperandVector &Operands) {
return MatchOperand_Success;
}

MipsAsmParser::OperandMatchResultTy
OperandMatchResultTy
MipsAsmParser::parseRegisterList(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
SmallVector<unsigned, 10> Regs;
Expand Down Expand Up @@ -4919,7 +4919,7 @@ MipsAsmParser::parseRegisterList(OperandVector &Operands) {
return MatchOperand_Success;
}

MipsAsmParser::OperandMatchResultTy
OperandMatchResultTy
MipsAsmParser::parseRegisterPair(OperandVector &Operands) {
MCAsmParser &Parser = getParser();

Expand All @@ -4935,7 +4935,7 @@ MipsAsmParser::parseRegisterPair(OperandVector &Operands) {
return MatchOperand_Success;
}

MipsAsmParser::OperandMatchResultTy
OperandMatchResultTy
MipsAsmParser::parseMovePRegPair(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
SmallVector<std::unique_ptr<MCParsedAsmOperand>, 8> TmpOperands;
Expand Down
8 changes: 4 additions & 4 deletions llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -715,7 +715,7 @@ bool SparcAsmParser:: parseDirectiveWord(unsigned Size, SMLoc L) {
return false;
}

SparcAsmParser::OperandMatchResultTy
OperandMatchResultTy
SparcAsmParser::parseMEMOperand(OperandVector &Operands) {

SMLoc S, E;
Expand Down Expand Up @@ -753,7 +753,7 @@ SparcAsmParser::parseMEMOperand(OperandVector &Operands) {
return MatchOperand_Success;
}

SparcAsmParser::OperandMatchResultTy
OperandMatchResultTy
SparcAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {

OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
Expand Down Expand Up @@ -821,7 +821,7 @@ SparcAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
return MatchOperand_Success;
}

SparcAsmParser::OperandMatchResultTy
OperandMatchResultTy
SparcAsmParser::parseSparcAsmOperand(std::unique_ptr<SparcOperand> &Op,
bool isCall) {

Expand Down Expand Up @@ -908,7 +908,7 @@ SparcAsmParser::parseSparcAsmOperand(std::unique_ptr<SparcOperand> &Op,
return (Op) ? MatchOperand_Success : MatchOperand_ParseFail;
}

SparcAsmParser::OperandMatchResultTy
OperandMatchResultTy
SparcAsmParser::parseBranchModifiers(OperandVector &Operands) {

// parse (,a|,pn|,pt)+
Expand Down
10 changes: 5 additions & 5 deletions llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -662,7 +662,7 @@ bool SystemZAsmParser::parseRegister(Register &Reg, RegisterGroup Group,
}

// Parse a register and add it to Operands. The other arguments are as above.
SystemZAsmParser::OperandMatchResultTy
OperandMatchResultTy
SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterGroup Group,
const unsigned *Regs, RegisterKind Kind) {
if (Parser.getTok().isNot(AsmToken::Percent))
Expand All @@ -679,7 +679,7 @@ SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterGroup Group,
}

// Parse any type of register (including integers) and add it to Operands.
SystemZAsmParser::OperandMatchResultTy
OperandMatchResultTy
SystemZAsmParser::parseAnyRegister(OperandVector &Operands) {
// Handle integer values.
if (Parser.getTok().is(AsmToken::Integer)) {
Expand Down Expand Up @@ -792,7 +792,7 @@ SystemZAsmParser::parseAddressRegister(Register &Reg) {

// Parse a memory operand and add it to Operands. The other arguments
// are as above.
SystemZAsmParser::OperandMatchResultTy
OperandMatchResultTy
SystemZAsmParser::parseAddress(OperandVector &Operands, MemoryKind MemKind,
const unsigned *Regs, RegisterKind RegKind) {
SMLoc StartLoc = Parser.getTok().getLoc();
Expand Down Expand Up @@ -1183,7 +1183,7 @@ bool SystemZAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
llvm_unreachable("Unexpected match type");
}

SystemZAsmParser::OperandMatchResultTy
OperandMatchResultTy
SystemZAsmParser::parseAccessReg(OperandVector &Operands) {
if (Parser.getTok().isNot(AsmToken::Percent))
return MatchOperand_NoMatch;
Expand All @@ -1198,7 +1198,7 @@ SystemZAsmParser::parseAccessReg(OperandVector &Operands) {
return MatchOperand_Success;
}

SystemZAsmParser::OperandMatchResultTy
OperandMatchResultTy
SystemZAsmParser::parsePCRel(OperandVector &Operands, int64_t MinVal,
int64_t MaxVal, bool AllowTLS) {
MCContext &Ctx = getContext();
Expand Down
11 changes: 2 additions & 9 deletions llvm/utils/TableGen/AsmMatcherEmitter.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2728,8 +2728,7 @@ static void emitCustomOperandParsing(raw_ostream &OS, CodeGenTarget &Target,

// Emit the operand class switch to call the correct custom parser for
// the found operand class.
OS << Target.getName() << ClassName << "::OperandMatchResultTy "
<< Target.getName() << ClassName << "::\n"
OS << "OperandMatchResultTy " << Target.getName() << ClassName << "::\n"
<< "tryCustomParseOperand(OperandVector"
<< " &Operands,\n unsigned MCK) {\n\n"
<< " switch(MCK) {\n";
Expand All @@ -2750,8 +2749,7 @@ static void emitCustomOperandParsing(raw_ostream &OS, CodeGenTarget &Target,
// Emit the static custom operand parser. This code is very similar with
// the other matcher. Also use MatchResultTy here just in case we go for
// a better error handling.
OS << Target.getName() << ClassName << "::OperandMatchResultTy "
<< Target.getName() << ClassName << "::\n"
OS << "OperandMatchResultTy " << Target.getName() << ClassName << "::\n"
<< "MatchOperandParserImpl(OperandVector"
<< " &Operands,\n StringRef Mnemonic) {\n";

Expand Down Expand Up @@ -2905,11 +2903,6 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
<< " unsigned VariantID = 0);\n";

if (!Info.OperandMatchInfo.empty()) {
OS << "\n enum OperandMatchResultTy {\n";
OS << " MatchOperand_Success, // operand matched successfully\n";
OS << " MatchOperand_NoMatch, // operand did not match\n";
OS << " MatchOperand_ParseFail // operand matched but had errors\n";
OS << " };\n";
OS << " OperandMatchResultTy MatchOperandParserImpl(\n";
OS << " OperandVector &Operands,\n";
OS << " StringRef Mnemonic);\n";
Expand Down