diff --git a/llvm/lib/Target/Mips/MipsRegisterInfo.td b/llvm/lib/Target/Mips/MipsRegisterInfo.td
@@ -209,7 +209,8 @@ let Namespace = "Mips" in {
   def PC : Register<"pc">;
 
   // Hardware register $29
-  def HWR29 : MipsReg<29, "29">;
+  foreach I = 0-31 in
+  def HWR#I : MipsReg<#I, ""#I>;
 
   // Accum registers
   foreach I = 0-3 in
@@ -364,7 +365,8 @@ def LO64 : RegisterClass<"Mips", [i64], 64, (add LO0_64)>;
 def HI64 : RegisterClass<"Mips", [i64], 64, (add HI0_64)>;
 
 // Hardware registers
-def HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>, Unallocatable;
+def HWRegs : RegisterClass<"Mips", [i32], 32, (sequence "HWR%u", 0, 31)>,
+             Unallocatable;
 
 // Accumulator Registers
 def ACC64 : RegisterClass<"Mips", [untyped], 64, (add AC0)> {
@@ -394,86 +396,68 @@ def OCTEON_P : RegisterClass<"Mips", [i64], 64, (add P0, P1, P2)>,
 // Register Operands.
 
 class MipsAsmRegOperand : AsmOperandClass {
-  let RenderMethod = "addRegAsmOperands";
-}
-def GPR32AsmOperand : MipsAsmRegOperand {
-  let Name = "GPR32Asm";
-  let ParserMethod = "parseGPR32";
+  let ParserMethod = "ParseAnyRegister";
 }
 
 def GPR64AsmOperand : MipsAsmRegOperand {
-  let Name = "GPR64Asm";
-  let ParserMethod = "parseGPR64";
+  let Name = "GPR64AsmReg";
+  let PredicateMethod = "isGPRAsmReg";
 }
 
-def ACC64DSPAsmOperand : MipsAsmRegOperand {
-  let Name = "ACC64DSPAsm";
-  let ParserMethod = "parseACC64DSP";
+def GPR32AsmOperand : MipsAsmRegOperand {
+  let Name = "GPR32AsmReg";
+  let PredicateMethod = "isGPRAsmReg";
 }
 
-def LO32DSPAsmOperand : MipsAsmRegOperand {
-  let Name = "LO32DSPAsm";
-  let ParserMethod = "parseLO32DSP";
+def ACC64DSPAsmOperand : MipsAsmRegOperand {
+  let Name = "ACC64DSPAsmReg";
+  let PredicateMethod = "isACCAsmReg";
 }
 
 def HI32DSPAsmOperand : MipsAsmRegOperand {
-  let Name = "HI32DSPAsm";
-  let ParserMethod = "parseHI32DSP";
+  let Name = "HI32DSPAsmReg";
+  let PredicateMethod = "isACCAsmReg";
+}
+
+def LO32DSPAsmOperand : MipsAsmRegOperand {
+  let Name = "LO32DSPAsmReg";
+  let PredicateMethod = "isACCAsmReg";
 }
 
 def CCRAsmOperand : MipsAsmRegOperand {
-  let Name = "CCRAsm";
-  let ParserMethod = "parseCCRRegs";
+  let Name = "CCRAsmReg";
 }
 
 def AFGR64AsmOperand : MipsAsmRegOperand {
-  let Name = "AFGR64Asm";
-  let ParserMethod = "parseAFGR64Regs";
+  let Name = "AFGR64AsmReg";
+  let PredicateMethod = "isFGRAsmReg";
 }
 
 def FGR64AsmOperand : MipsAsmRegOperand {
-  let Name = "FGR64Asm";
-  let ParserMethod = "parseFGR64Regs";
+  let Name = "FGR64AsmReg";
+  let PredicateMethod = "isFGRAsmReg";
 }
 
 def FGR32AsmOperand : MipsAsmRegOperand {
-  let Name = "FGR32Asm";
-  let ParserMethod = "parseFGR32Regs";
+  let Name = "FGR32AsmReg";
+  let PredicateMethod = "isFGRAsmReg";
 }
 
 def FGRH32AsmOperand : MipsAsmRegOperand {
-  let Name = "FGRH32Asm";
-  let ParserMethod = "parseFGRH32Regs";
+  let Name = "FGRH32AsmReg";
+  let PredicateMethod = "isFGRAsmReg";
 }
 
 def FCCRegsAsmOperand : MipsAsmRegOperand {
-  let Name = "FCCRegsAsm";
-  let ParserMethod = "parseFCCRegs";
-}
-
-def MSA128BAsmOperand : MipsAsmRegOperand {
-  let Name = "MSA128BAsm";
-  let ParserMethod = "parseMSA128BRegs";
-}
-
-def MSA128HAsmOperand : MipsAsmRegOperand {
-  let Name = "MSA128HAsm";
-  let ParserMethod = "parseMSA128HRegs";
-}
-
-def MSA128WAsmOperand : MipsAsmRegOperand {
-  let Name = "MSA128WAsm";
-  let ParserMethod = "parseMSA128WRegs";
+  let Name = "FCCAsmReg";
 }
 
-def MSA128DAsmOperand : MipsAsmRegOperand {
-  let Name = "MSA128DAsm";
-  let ParserMethod = "parseMSA128DRegs";
+def MSA128AsmOperand : MipsAsmRegOperand {
+  let Name = "MSA128AsmReg";
 }
 
-def MSA128CRAsmOperand : MipsAsmRegOperand {
-  let Name = "MSA128CRAsm";
-  let ParserMethod = "parseMSA128CtrlRegs";
+def MSACtrlAsmOperand : MipsAsmRegOperand {
+  let Name = "MSACtrlAsmReg";
 }
 
 def GPR32Opnd : RegisterOperand<GPR32> {
@@ -493,13 +477,11 @@ def CCROpnd : RegisterOperand<CCR> {
 }
 
 def HWRegsAsmOperand : MipsAsmRegOperand {
-  let Name = "HWRegsAsm";
-  let ParserMethod = "parseHWRegs";
+  let Name = "HWRegsAsmReg";
 }
 
 def COP2AsmOperand : MipsAsmRegOperand {
-  let Name = "COP2Asm";
-  let ParserMethod = "parseCOP2";
+  let Name = "COP2AsmReg";
 }
 
 def HWRegsOpnd : RegisterOperand<HWRegs> {
@@ -543,22 +525,22 @@ def COP2Opnd : RegisterOperand<COP2> {
 }
 
 def MSA128BOpnd : RegisterOperand<MSA128B> {
-  let ParserMatchClass = MSA128BAsmOperand;
+  let ParserMatchClass = MSA128AsmOperand;
 }
 
 def MSA128HOpnd : RegisterOperand<MSA128H> {
-  let ParserMatchClass = MSA128HAsmOperand;
+  let ParserMatchClass = MSA128AsmOperand;
 }
 
 def MSA128WOpnd : RegisterOperand<MSA128W> {
-  let ParserMatchClass = MSA128WAsmOperand;
+  let ParserMatchClass = MSA128AsmOperand;
 }
 
 def MSA128DOpnd : RegisterOperand<MSA128D> {
-  let ParserMatchClass = MSA128DAsmOperand;
+  let ParserMatchClass = MSA128AsmOperand;
 }
 
 def MSA128CROpnd : RegisterOperand<MSACtrl> {
-  let ParserMatchClass = MSA128CRAsmOperand;
+  let ParserMatchClass = MSACtrlAsmOperand;
 }
 
diff --git a/llvm/lib/Target/Mips/MipsSEISelLowering.cpp b/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
@@ -1810,6 +1810,13 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
   case Intrinsic::mips_insert_d:
     return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
                        Op->getOperand(1), Op->getOperand(3), Op->getOperand(2));
+  case Intrinsic::mips_insve_b:
+  case Intrinsic::mips_insve_h:
+  case Intrinsic::mips_insve_w:
+  case Intrinsic::mips_insve_d:
+    return DAG.getNode(MipsISD::INSVE, DL, Op->getValueType(0),
+                       Op->getOperand(1), Op->getOperand(2), Op->getOperand(3),
+                       DAG.getConstant(0, MVT::i32));
   case Intrinsic::mips_ldi_b:
   case Intrinsic::mips_ldi_h:
   case Intrinsic::mips_ldi_w:
@@ -2837,7 +2844,8 @@ MipsSETargetLowering::emitINSERT_FW(MachineInstr *MI,
   BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_W), Wd)
       .addReg(Wd_in)
       .addImm(Lane)
-      .addReg(Wt);
+      .addReg(Wt)
+      .addImm(0);
 
   MI->eraseFromParent(); // The pseudo instruction is gone now.
   return BB;
@@ -2870,7 +2878,8 @@ MipsSETargetLowering::emitINSERT_FD(MachineInstr *MI,
   BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_D), Wd)
       .addReg(Wd_in)
       .addImm(Lane)
-      .addReg(Wt);
+      .addReg(Wt)
+      .addImm(0);
 
   MI->eraseFromParent(); // The pseudo instruction is gone now.
   return BB;

diff --git a/llvm/test/MC/Mips/cfi.s b/llvm/test/MC/Mips/cfi.s
@@ -0,0 +1,13 @@
+# RUN: llvm-mc %s -triple=mips-unknown-unknown -show-encoding -mcpu=mips32 | \
+# RUN:     FileCheck %s
+# RUN: llvm-mc %s -triple=mips64-unknown-unknown -show-encoding -mcpu=mips64 | \
+# RUN:     FileCheck %s
+
+# Check that we can accept register names in CFI directives and that they are
+# canonicalised to their DWARF register numbers.
+
+        .cfi_startproc         # CHECK: .cfi_startproc
+        .cfi_register   $6, $5 # CHECK: .cfi_register 6, 5
+        .cfi_def_cfa    $fp, 8 # CHECK: .cfi_def_cfa 30, 8
+        .cfi_def_cfa    $2, 16 # CHECK: .cfi_def_cfa 2, 16
+        .cfi_endproc           # CHECK: .cfi_endproc
diff --git a/llvm/test/MC/Mips/mips-register-names-invalid.s b/llvm/test/MC/Mips/mips-register-names-invalid.s
@@ -4,5 +4,5 @@
 # $32 used to trigger an assertion instead of the usual error message due to
 # an off-by-one bug.
 
-# CHECK: :[[@LINE+1]]:18: error: invalid operand for instruction
+# CHECK: :[[@LINE+1]]:17: error: invalid operand for instruction
         add     $32, $0, $0
diff --git a/llvm/test/MC/Mips/mips3/valid-xfail.s b/llvm/test/MC/Mips/mips3/valid-xfail.s
@@ -8,10 +8,6 @@
 # XFAIL: *
 
 	.set noat
-	ddiv	$zero,$k0,$s3
-	ddivu	$zero,$s0,$s1
-	div	$zero,$t9,$t3
-	divu	$zero,$t9,$t7
 	ehb
 	lwc3	$10,-32265($k0)
 	ssnop

diff --git a/llvm/test/MC/Mips/mips3/valid.s b/llvm/test/MC/Mips/mips3/valid.s
@@ -35,8 +35,12 @@
 	dadd	$s3,$at,$ra
 	daddi	$sp,$s4,-27705
 	daddiu	$k0,$s6,-4586
+	ddiv	$zero,$k0,$s3
+	ddivu	$zero,$s0,$s1
+	div	$zero,$t9,$t3
 	div.d	$f29,$f20,$f27
 	div.s	$f4,$f5,$f15
+	divu	$zero,$t9,$t7
 	dmfc1	$t4,$f13
 	dmtc1	$s0,$f14
 	dmult	$s7,$t1

diff --git a/llvm/test/MC/Mips/mips32r2/valid-xfail.s b/llvm/test/MC/Mips/mips32r2/valid-xfail.s
@@ -2,7 +2,7 @@
 # they aren't implemented yet).
 # This test is set up to XPASS if any instruction generates an encoding.
 #
-# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r2 | FileCheck %s
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r2 | not FileCheck %s
 # CHECK-NOT: encoding
 # XFAIL: *
 
@@ -48,7 +48,6 @@
 	c.nge.d	$fcc5,$f21,$f16
 	c.nge.ps	$f1,$f26
 	c.nge.s	$fcc3,$f11,$f8
-	c.ngl.d	$f29,$f29
 	c.ngl.ps	$f21,$f30
 	c.ngl.s	$fcc2,$f31,$f23
 	c.ngle.ps	$fcc7,$f12,$f20
@@ -66,7 +65,6 @@
 	c.seq.ps	$fcc6,$f31,$f14
 	c.seq.s	$fcc7,$f1,$f25
 	c.sf.ps	$fcc6,$f4,$f6
-	c.sf.s	$f14,$f22
 	c.ueq.d	$fcc4,$f13,$f25
 	c.ueq.ps	$fcc1,$f5,$f29
 	c.ueq.s	$fcc6,$f3,$f30
@@ -96,14 +94,10 @@
 	cmpu.lt.qb	$at,$a3
 	ctcmsa	$31,$s7
 	cvt.d.l	$f4,$f16
-	cvt.l.d	$f24,$f15
-	cvt.l.s	$f11,$f29
 	cvt.ps.s	$f3,$f18,$f19
 	cvt.s.l	$f15,$f30
 	cvt.s.pl	$f30,$f1
 	cvt.s.pu	$f14,$f25
-	div	$zero,$t9,$t3
-	divu	$zero,$t9,$t7
 	dmt	$k0
 	dpa.w.ph	$ac1,$s7,$k0
 	dpaq_s.w.ph	$ac2,$a0,$t5
@@ -152,8 +146,6 @@
 	flog2.w	$w19,$w23
 	floor.l.d	$f26,$f7
 	floor.l.s	$f12,$f5
-	floor.w.d	$f14,$f11
-	floor.w.s	$f8,$f9
 	fork	$s2,$t0,$a0
 	frcp.d	$w12,$w4
 	frcp.w	$w30,$w8
@@ -228,12 +220,8 @@
 	nlzc.d	$w14,$w14
 	nlzc.h	$w24,$w24
 	nlzc.w	$w10,$w4
-	nmadd.d	$f18,$f9,$f14,$f19
 	nmadd.ps	$f27,$f4,$f9,$f25
-	nmadd.s	$f0,$f5,$f25,$f12
-	nmsub.d	$f30,$f8,$f16,$f30
 	nmsub.ps	$f6,$f12,$f14,$f17
-	nmsub.s	$f1,$f24,$f19,$f4
 	nor.v	$w20,$w20,$w15
 	or.v	$w13,$w23,$w12
 	packrl.ph	$ra,$t8,$t6
@@ -264,7 +252,6 @@
 	pul.ps	$f9,$f30,$f26
 	puu.ps	$f24,$f9,$f2
 	raddu.w.qb	$t9,$s3
-	rdhwr	$sp,$11
 	rdpgpr	$s3,$t1
 	recip.d	$f19,$f6
 	recip.s	$f3,$f30
@@ -311,7 +298,6 @@
 	swe	$t8,94($k0)
 	swle	$v1,-209($gp)
 	swre	$k0,-202($s2)
-	swxc1	$f19,$t4($k0)
 	synci	20023($s0)
 	tlbginv
 	tlbginvf

diff --git a/llvm/test/MC/Mips/mips32r2/valid.s b/llvm/test/MC/Mips/mips32r2/valid.s
@@ -11,8 +11,10 @@
 	addi	$t5,$t1,26322
 	addu	$t1,$a0,$a2
 	and	$s7,$v0,$t4
+	c.ngl.d	$f29,$f29
 	c.ngle.d	$f0,$f16
 	c.sf.d	$f30,$f0
+	c.sf.s	$f14,$f22
 	ceil.w.d	$f11,$f25
 	ceil.w.s	$f6,$f20
 	cfc1	$s1,$21
@@ -21,16 +23,22 @@
 	ctc1	$a2,$26
 	cvt.d.s	$f22,$f28
 	cvt.d.w	$f26,$f11
+	cvt.l.d	$f24,$f15
+	cvt.l.s	$f11,$f29
 	cvt.s.d	$f26,$f8
 	cvt.s.w	$f22,$f15
 	cvt.w.d	$f20,$f14
 	cvt.w.s	$f20,$f24
 	deret
 	di	$s8
+	div	$zero,$t9,$t3
 	div.d	$f29,$f20,$f27
 	div.s	$f4,$f5,$f15
+	divu	$zero,$t9,$t7
 	ei	$t6
 	eret
+	floor.w.d	$f14,$f11
+	floor.w.s	$f8,$f9
 	lb	$t8,-14515($t2)
 	lbu	$t0,30195($v1)
 	ldc1	$f11,16391($s0)
@@ -94,9 +102,14 @@
 	multu	$t1,$s2
 	neg.d	$f27,$f18
 	neg.s	$f1,$f15
+	nmadd.d	$f18,$f9,$f14,$f19
+	nmadd.s	$f0,$f5,$f25,$f12
+	nmsub.d	$f30,$f8,$f16,$f30
+	nmsub.s	$f1,$f24,$f19,$f4
 	nop
 	nor	$a3,$zero,$a3
 	or	$t4,$s0,$sp
+	rdhwr	$sp,$11
 	round.w.d	$f6,$f4
 	round.w.s	$f27,$f28
 	sb	$s6,-19857($t6)
@@ -126,6 +139,7 @@
 	swc2	$25,24880($s0)
 	swl	$t7,13694($s3)
 	swr	$s1,-26590($t6)
+	swxc1	$f19,$t4($k0)
 	teqi	$s5,-17504
 	tgei	$s1,5025
 	tgeiu	$sp,-28621

diff --git a/llvm/test/MC/Mips/mips4/valid-xfail.s b/llvm/test/MC/Mips/mips4/valid-xfail.s
@@ -36,10 +36,6 @@
 	c.ult.s	$fcc7,$f24,$f10
 	c.un.d	$fcc6,$f23,$f24
 	c.un.s	$fcc1,$f30,$f4
-	ddiv	$zero,$k0,$s3
-	ddivu	$zero,$s0,$s1
-	div	$zero,$t9,$t3
-	divu	$zero,$t9,$t7
 	ehb
 	madd.d	$f18,$f19,$f26,$f20
 	madd.s	$f1,$f31,$f19,$f25

diff --git a/llvm/test/MC/Mips/mips4/valid.s b/llvm/test/MC/Mips/mips4/valid.s
@@ -35,8 +35,12 @@
 	dadd	$s3,$at,$ra
 	daddi	$sp,$s4,-27705
 	daddiu	$k0,$s6,-4586
+	ddiv	$zero,$k0,$s3
+	ddivu	$zero,$s0,$s1
+	div	$zero,$t9,$t3
 	div.d	$f29,$f20,$f27
 	div.s	$f4,$f5,$f15
+	divu	$zero,$t9,$t7
 	dmfc1	$t4,$f13
 	dmtc1	$s0,$f14
 	dmult	$s7,$t1

diff --git a/llvm/test/MC/Mips/mips5/valid-xfail.s b/llvm/test/MC/Mips/mips5/valid-xfail.s
@@ -58,10 +58,6 @@
 	cvt.ps.s	$f3,$f18,$f19
 	cvt.s.pl	$f30,$f1
 	cvt.s.pu	$f14,$f25
-	ddiv	$zero,$k0,$s3
-	ddivu	$zero,$s0,$s1
-	div	$zero,$t9,$t3
-	divu	$zero,$t9,$t7
 	ehb
 	madd.d	$f18,$f19,$f26,$f20
 	madd.ps	$f22,$f3,$f14,$f3

diff --git a/llvm/test/MC/Mips/mips5/valid.s b/llvm/test/MC/Mips/mips5/valid.s
@@ -35,8 +35,12 @@
 	dadd	$s3,$at,$ra
 	daddi	$sp,$s4,-27705
 	daddiu	$k0,$s6,-4586
+	ddiv	$zero,$k0,$s3
+	ddivu	$zero,$s0,$s1
+	div	$zero,$t9,$t3
 	div.d	$f29,$f20,$f27
 	div.s	$f4,$f5,$f15
+	divu	$zero,$t9,$t7
 	dmfc1	$t4,$f13
 	dmtc1	$s0,$f14
 	dmult	$s7,$t1

diff --git a/llvm/test/MC/Mips/mips64/valid-xfail.s b/llvm/test/MC/Mips/mips64/valid-xfail.s
@@ -60,10 +60,6 @@
 	cvt.ps.s	$f3,$f18,$f19
 	cvt.s.pl	$f30,$f1
 	cvt.s.pu	$f14,$f25
-	ddiv	$zero,$k0,$s3
-	ddivu	$zero,$s0,$s1
-	div	$zero,$t9,$t3
-	divu	$zero,$t9,$t7
 	dmfc0	$t2,c0_watchhi,2
 	dmtc0	$t7,c0_datalo
 	ehb

diff --git a/llvm/test/MC/Mips/mips64/valid.s b/llvm/test/MC/Mips/mips64/valid.s
@@ -39,8 +39,12 @@
 	dclo	$s2,$a2
 	dclz	$s0,$t9
 	deret
+	ddiv	$zero,$k0,$s3
+	ddivu	$zero,$s0,$s1
+	div	$zero,$t9,$t3
 	div.d	$f29,$f20,$f27
 	div.s	$f4,$f5,$f15
+	divu	$zero,$t9,$t7
 	dmfc1	$t4,$f13
 	dmtc1	$s0,$f14
 	dmult	$s7,$t1

diff --git a/llvm/test/MC/Mips/mips64r2/valid-xfail.s b/llvm/test/MC/Mips/mips64r2/valid-xfail.s
@@ -52,7 +52,6 @@
 	c.nge.d	$fcc5,$f21,$f16
 	c.nge.ps	$f1,$f26
 	c.nge.s	$fcc3,$f11,$f8
-	c.ngl.d	$f29,$f29
 	c.ngl.ps	$f21,$f30
 	c.ngl.s	$fcc2,$f31,$f23
 	c.ngle.ps	$fcc7,$f12,$f20
@@ -70,7 +69,6 @@
 	c.seq.ps	$fcc6,$f31,$f14
 	c.seq.s	$fcc7,$f1,$f25
 	c.sf.ps	$fcc6,$f4,$f6
-	c.sf.s	$f14,$f22
 	c.ueq.d	$fcc4,$f13,$f25
 	c.ueq.ps	$fcc1,$f5,$f29
 	c.ueq.s	$fcc6,$f3,$f30
@@ -98,10 +96,6 @@
 	cmpu.lt.qb	$at,$a3
 	cvt.s.pl	$f30,$f1
 	cvt.s.pu	$f14,$f25
-	ddiv	$zero,$k0,$s3
-	ddivu	$zero,$s0,$s1
-	div	$zero,$t9,$t3
-	divu	$zero,$t9,$t7
 	dmfc0	$t2,c0_watchhi,2
 	dmfgc0	$gp,c0_perfcnt,6
 	dmt	$k0
@@ -124,8 +118,6 @@
 	dpsu.h.qbr	$ac2,$a1,$s6
 	dpsx.w.ph	$ac0,$s7,$gp
 	drorv	$at,$a1,$s7
-	dsbh	$v1,$t6
-	dshd	$v0,$sp
 	dvpe	$s6
 	ehb
 	emt	$t0
@@ -188,7 +180,6 @@
 	lwx	$t4,$t4($s4)
 	madd.d	$f18,$f19,$f26,$f20
 	madd.ps	$f22,$f3,$f14,$f3
-	madd.s	$f1,$f31,$f19,$f25
 	maq_s.w.phl	$ac2,$t9,$t3
 	maq_s.w.phr	$ac0,$t2,$t9
 	maq_sa.w.phl	$ac3,$a1,$v1
@@ -206,7 +197,6 @@
 	msub	$ac2,$sp,$t6
 	msub.d	$f10,$f1,$f31,$f18
 	msub.ps	$f12,$f14,$f29,$f17
-	msub.s	$f12,$f19,$f10,$f16
 	msubu	$ac2,$a1,$t8
 	mtc0	$t1,c0_datahi1
 	mtgc0	$s4,$21,7
@@ -236,10 +226,8 @@
 	nlzc.w	$w10,$w4
 	nmadd.d	$f18,$f9,$f14,$f19
 	nmadd.ps	$f27,$f4,$f9,$f25
-	nmadd.s	$f0,$f5,$f25,$f12
 	nmsub.d	$f30,$f8,$f16,$f30
 	nmsub.ps	$f6,$f12,$f14,$f17
-	nmsub.s	$f1,$f24,$f19,$f4
 	nor.v	$w20,$w20,$w15
 	or.v	$w13,$w23,$w12
 	packrl.ph	$ra,$t8,$t6
@@ -270,7 +258,6 @@
 	pul.ps	$f9,$f30,$f26
 	puu.ps	$f24,$f9,$f2
 	raddu.w.qb	$t9,$s3
-	rdhwr	$sp,$11
 	rdpgpr	$s3,$t1
 	recip.d	$f19,$f6
 	recip.s	$f3,$f30
@@ -282,8 +269,6 @@
 	rsqrt.s	$f4,$f8
 	sbe	$s7,33($s1)
 	sce	$sp,189($t2)
-	seb	$t9,$t7
-	seh	$v1,$t4
 	she	$t8,105($v0)
 	shilo	$ac1,26
 	shilov	$ac2,$t2
@@ -330,6 +315,5 @@
 	tlbwi
 	tlbwr
 	wrpgpr	$zero,$t5
-	wsbh	$k1,$t1
 	xor.v	$w20,$w21,$w30
 	yield	$v1,$s0
diff --git a/llvm/test/MC/Mips/mips64r2/valid.s b/llvm/test/MC/Mips/mips64r2/valid.s
@@ -11,8 +11,10 @@
 	addi	$t5,$t1,26322
 	addu	$t1,$a0,$a2
 	and	$s7,$v0,$t4
+	c.ngl.d	$f29,$f29
 	c.ngle.d	$f0,$f16
 	c.sf.d	$f30,$f0
+	c.sf.s	$f14,$f22
 	ceil.l.d	$f1,$f3
 	ceil.l.s	$f18,$f13
 	ceil.w.d	$f11,$f25
@@ -38,12 +40,18 @@
 	dclz	$s0,$t9
 	deret
 	di	$s8
+	ddiv	$zero,$k0,$s3
+	ddivu	$zero,$s0,$s1
+	div	$zero,$t9,$t3
 	div.d	$f29,$f20,$f27
 	div.s	$f4,$f5,$f15
+	divu	$zero,$t9,$t7
 	dmfc1	$t4,$f13
 	dmtc1	$s0,$f14
 	dmult	$s7,$t1
 	dmultu	$a1,$a2
+	dsbh	$v1,$t6
+	dshd	$v0,$sp
 	dsllv	$zero,$s4,$t4
 	dsrav	$gp,$s2,$s3
 	dsrlv	$s3,$t6,$s4
@@ -79,6 +87,7 @@
 	lwxc1	$f12,$s1($s8)
 	madd	$s6,$t5
 	madd	$zero,$t1
+	madd.s	$f1,$f31,$f19,$f25
 	maddu	$s3,$gp
 	maddu	$t8,$s2
 	mfc0	$a2,$14,1
@@ -106,6 +115,7 @@
 	movz.d	$f12,$f29,$t1
 	movz.s	$f25,$f7,$v1
 	msub	$s7,$k1
+	msub.s	$f12,$f19,$f10,$f16
 	msubu	$t7,$a1
 	mtc1	$s8,$f9
 	mthc1	$zero,$f16
@@ -121,9 +131,12 @@
 	multu	$t1,$s2
 	neg.d	$f27,$f18
 	neg.s	$f1,$f15
+	nmadd.s	$f0,$f5,$f25,$f12
+	nmsub.s	$f1,$f24,$f19,$f4
 	nop
 	nor	$a3,$zero,$a3
 	or	$t4,$s0,$sp
+	rdhwr	$sp,$11
 	round.l.d	$f12,$f1
 	round.l.s	$f25,$f5
 	round.w.d	$f6,$f4
@@ -137,6 +150,8 @@
 	sdl	$a3,-20961($s8)
 	sdr	$t3,-20423($t4)
 	sdxc1	$f11,$t2($t6)
+	seb	$t9,$t7
+	seh	$v1,$t4
 	sh	$t6,-6704($t7)
 	sllv	$a3,$zero,$t1
 	slt	$s7,$t3,$k1
@@ -169,3 +184,4 @@
 	trunc.w.d	$f22,$f15
 	trunc.w.s	$f28,$f30
 	xor	$s2,$a0,$s8
+	wsbh	$k1,$t1
diff --git a/llvm/test/MC/Mips/set-at-directive-explicit-at.s b/llvm/test/MC/Mips/set-at-directive-explicit-at.s
@@ -7,12 +7,12 @@
     .text
 foo:
 # CHECK:   jr    $1                      # encoding: [0x08,0x00,0x20,0x00]
-# WARNINGS: :[[@LINE+2]]:12: warning: Used $at without ".set noat"
+# WARNINGS: :[[@LINE+2]]:11: warning: Used $at without ".set noat"
     .set    at=$1
     jr    $at
 
 # CHECK:   jr    $1                      # encoding: [0x08,0x00,0x20,0x00]
-# WARNINGS: :[[@LINE+2]]:12: warning: Used $at without ".set noat"
+# WARNINGS: :[[@LINE+2]]:11: warning: Used $at without ".set noat"
     .set    at=$1
     jr    $1
 # WARNINGS-NOT: warning: Used $at without ".set noat"
@@ -31,12 +31,12 @@ foo:
     jr    $at
 
 # CHECK:   jr    $16                     # encoding: [0x08,0x00,0x00,0x02]
-# WARNINGS: :[[@LINE+2]]:12: warning: Used $16 with ".set at=$16"
+# WARNINGS: :[[@LINE+2]]:11: warning: Used $16 with ".set at=$16"
     .set    at=$16
     jr    $s0
 
 # CHECK:   jr    $16                     # encoding: [0x08,0x00,0x00,0x02]
-# WARNINGS: :[[@LINE+2]]:12: warning: Used $16 with ".set at=$16"
+# WARNINGS: :[[@LINE+2]]:11: warning: Used $16 with ".set at=$16"
     .set    at=$16
     jr    $16
 # WARNINGS-NOT: warning