6 changes: 3 additions & 3 deletions llvm/test/CodeGen/AArch64/early-ifcvt-regclass-mismatch.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@
br i1 undef, label %if.then139.i, label %if.else142.i

if.then139.i: ; preds = %entry
%0 = load double, double* undef, align 8
%0 = load double, ptr undef, align 8
br label %if.end161.i

if.else142.i: ; preds = %entry
Expand Down Expand Up @@ -35,7 +35,7 @@
ret void
}
declare double @llvm.fabs.f64(double) #1
declare void @llvm.stackprotector(i8*, i8**) #2
declare void @llvm.stackprotector(ptr, ptr) #2

attributes #0 = { "target-cpu"="apple-a7" }
attributes #1 = { nounwind readnone speculatable willreturn }
Expand Down Expand Up @@ -128,7 +128,7 @@ body: |
bb.2.if.then139.i:
successors: %bb.5(0x80000000)
%7:gpr64 = LDRXui %8, 0 :: (load (s64) from `double* undef`)
%7:gpr64 = LDRXui %8, 0 :: (load (s64) from `ptr undef`)
B %bb.5
bb.3.if.else142.i:
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AArch64/elim-dead-mi.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
@d = common dso_local local_unnamed_addr global i32 0, align 4

define dso_local i32 @main() local_unnamed_addr {
%scevgep = getelementptr i8, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @c, i64 0, i64 1), i64 0
%scevgep = getelementptr i8, ptr getelementptr inbounds ([3 x i8], ptr @c, i64 0, i64 1), i64 0
ret i32 0
}
...
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AArch64/expand-blr-rvmarker-pseudo.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -29,7 +29,7 @@
ret void
}

declare i8* @attachedcall()
declare ptr @attachedcall()

declare ptr @objc_retainAutoreleasedReturnValue()
...
Expand Down
18 changes: 9 additions & 9 deletions llvm/test/CodeGen/AArch64/fmov-imm-licm.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,28 +6,28 @@
; and also by checking that we're not spilling any FP callee-saved
; registers.

%struct.Node = type { %struct.Node*, i8* }
%struct.Node = type { ptr, ptr }

define void @process_nodes(%struct.Node* %0) {
define void @process_nodes(ptr %0) {
; CHECK-LABEL: process_nodes:
; CHECK-NOT: stp {{d[0-9]+}}
; CHECK-LABEL: .LBB0_2:
; CHECK: fmov s0, #1.00000000
; CHECK: bl do_it
entry:
%1 = icmp eq %struct.Node* %0, null
%1 = icmp eq ptr %0, null
br i1 %1, label %exit, label %loop

loop:
%2 = phi %struct.Node* [ %4, %loop ], [ %0, %entry ]
tail call void @do_it(float 1.000000e+00, %struct.Node* nonnull %2)
%3 = getelementptr inbounds %struct.Node, %struct.Node* %2, i64 0, i32 0
%4 = load %struct.Node*, %struct.Node** %3, align 8
%5 = icmp eq %struct.Node* %4, null
%2 = phi ptr [ %4, %loop ], [ %0, %entry ]
tail call void @do_it(float 1.000000e+00, ptr nonnull %2)
%3 = getelementptr inbounds %struct.Node, ptr %2, i64 0, i32 0
%4 = load ptr, ptr %3, align 8
%5 = icmp eq ptr %4, null
br i1 %5, label %exit, label %loop

exit:
ret void
}

declare void @do_it(float, %struct.Node*)
declare void @do_it(float, ptr)
14 changes: 7 additions & 7 deletions llvm/test/CodeGen/AArch64/inline-asm-constraints-bad-sve.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,24 +15,24 @@ entry:
ret <vscale x 16 x i1> %1
}

define <vscale x 4 x float> @foo2(<vscale x 4 x i32> *%in) {
define <vscale x 4 x float> @foo2(ptr %in) {
entry:
%0 = load <vscale x 4 x i32>, <vscale x 4 x i32>* %in, align 16
%0 = load <vscale x 4 x i32>, ptr %in, align 16
%1 = call <vscale x 4 x float> asm sideeffect "ptrue p0.s, #1 \0Afabs $0.s, p0/m, $1.s \0A", "=w,r"(<vscale x 4 x i32> %0)
ret <vscale x 4 x float> %1
}

define <vscale x 16 x i1> @foo3(<vscale x 16 x i1> *%in) {
define <vscale x 16 x i1> @foo3(ptr %in) {
entry:
%0 = load <vscale x 16 x i1>, <vscale x 16 x i1>* %in, align 2
%0 = load <vscale x 16 x i1>, ptr %in, align 2
%1 = call <vscale x 16 x i1> asm sideeffect "mov $0.b, $1.b \0A", "=&w,w"(<vscale x 16 x i1> %0)
ret <vscale x 16 x i1> %1
}

define half @foo4(<vscale x 16 x i1> *%inp, <vscale x 8 x half> *%inv) {
define half @foo4(ptr %inp, ptr %inv) {
entry:
%0 = load <vscale x 16 x i1>, <vscale x 16 x i1>* %inp, align 2
%1 = load <vscale x 8 x half>, <vscale x 8 x half>* %inv, align 16
%0 = load <vscale x 16 x i1>, ptr %inp, align 2
%1 = load <vscale x 8 x half>, ptr %inv, align 16
%2 = call half asm "fminv ${0:h}, $1, $2.h", "=r,@3Upl,w"(<vscale x 16 x i1> %0, <vscale x 8 x half> %1)
ret half %2
}
66 changes: 33 additions & 33 deletions llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@ target triple = "aarch64-unknown-linux-gnu"

; SCALABLE INSERTED INTO SCALABLE TESTS

define <vscale x 8 x i8> @vec_scalable_subvec_scalable_idx_zero_i8(<vscale x 8 x i8>* %a, <vscale x 4 x i8>* %b) #0 {
define <vscale x 8 x i8> @vec_scalable_subvec_scalable_idx_zero_i8(ptr %a, ptr %b) #0 {
; CHECK-LABEL: vec_scalable_subvec_scalable_idx_zero_i8:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.h
Expand All @@ -15,13 +15,13 @@ define <vscale x 8 x i8> @vec_scalable_subvec_scalable_idx_zero_i8(<vscale x 8 x
; CHECK-NEXT: uunpkhi z0.s, z0.h
; CHECK-NEXT: uzp1 z0.h, z1.h, z0.h
; CHECK-NEXT: ret
%vec = load <vscale x 8 x i8>, <vscale x 8 x i8>* %a
%subvec = load <vscale x 4 x i8>, <vscale x 4 x i8>* %b
%vec = load <vscale x 8 x i8>, ptr %a
%subvec = load <vscale x 4 x i8>, ptr %b
%ins = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.nxv4i8(<vscale x 8 x i8> %vec, <vscale x 4 x i8> %subvec, i64 0)
ret <vscale x 8 x i8> %ins
}

define <vscale x 8 x i8> @vec_scalable_subvec_scalable_idx_nonzero_i8(<vscale x 8 x i8>* %a, <vscale x 4 x i8>* %b) #0 {
define <vscale x 8 x i8> @vec_scalable_subvec_scalable_idx_nonzero_i8(ptr %a, ptr %b) #0 {
; CHECK-LABEL: vec_scalable_subvec_scalable_idx_nonzero_i8:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.h
Expand All @@ -31,13 +31,13 @@ define <vscale x 8 x i8> @vec_scalable_subvec_scalable_idx_nonzero_i8(<vscale x
; CHECK-NEXT: uunpklo z0.s, z0.h
; CHECK-NEXT: uzp1 z0.h, z0.h, z1.h
; CHECK-NEXT: ret
%vec = load <vscale x 8 x i8>, <vscale x 8 x i8>* %a
%subvec = load <vscale x 4 x i8>, <vscale x 4 x i8>* %b
%vec = load <vscale x 8 x i8>, ptr %a
%subvec = load <vscale x 4 x i8>, ptr %b
%ins = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.nxv4i8(<vscale x 8 x i8> %vec, <vscale x 4 x i8> %subvec, i64 4)
ret <vscale x 8 x i8> %ins
}

define <vscale x 4 x i16> @vec_scalable_subvec_scalable_idx_zero_i16(<vscale x 4 x i16>* %a, <vscale x 2 x i16>* %b) #0 {
define <vscale x 4 x i16> @vec_scalable_subvec_scalable_idx_zero_i16(ptr %a, ptr %b) #0 {
; CHECK-LABEL: vec_scalable_subvec_scalable_idx_zero_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s
Expand All @@ -47,13 +47,13 @@ define <vscale x 4 x i16> @vec_scalable_subvec_scalable_idx_zero_i16(<vscale x 4
; CHECK-NEXT: uunpkhi z0.d, z0.s
; CHECK-NEXT: uzp1 z0.s, z1.s, z0.s
; CHECK-NEXT: ret
%vec = load <vscale x 4 x i16>, <vscale x 4 x i16>* %a
%subvec = load <vscale x 2 x i16>, <vscale x 2 x i16>* %b
%vec = load <vscale x 4 x i16>, ptr %a
%subvec = load <vscale x 2 x i16>, ptr %b
%ins = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.nxv2i16(<vscale x 4 x i16> %vec, <vscale x 2 x i16> %subvec, i64 0)
ret <vscale x 4 x i16> %ins
}

define <vscale x 4 x i16> @vec_scalable_subvec_scalable_idx_nonzero_i16(<vscale x 4 x i16>* %a, <vscale x 2 x i16>* %b) #0 {
define <vscale x 4 x i16> @vec_scalable_subvec_scalable_idx_nonzero_i16(ptr %a, ptr %b) #0 {
; CHECK-LABEL: vec_scalable_subvec_scalable_idx_nonzero_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s
Expand All @@ -63,15 +63,15 @@ define <vscale x 4 x i16> @vec_scalable_subvec_scalable_idx_nonzero_i16(<vscale
; CHECK-NEXT: uunpklo z0.d, z0.s
; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s
; CHECK-NEXT: ret
%vec = load <vscale x 4 x i16>, <vscale x 4 x i16>* %a
%subvec = load <vscale x 2 x i16>, <vscale x 2 x i16>* %b
%vec = load <vscale x 4 x i16>, ptr %a
%subvec = load <vscale x 2 x i16>, ptr %b
%ins = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.nxv2i16(<vscale x 4 x i16> %vec, <vscale x 2 x i16> %subvec, i64 2)
ret <vscale x 4 x i16> %ins
}

; FIXED INSERTED INTO SCALABLE TESTS

define <vscale x 8 x i8> @vec_scalable_subvec_fixed_idx_zero_i8(<vscale x 8 x i8>* %a, <8 x i8>* %b) #0 {
define <vscale x 8 x i8> @vec_scalable_subvec_fixed_idx_zero_i8(ptr %a, ptr %b) #0 {
; CHECK-LABEL: vec_scalable_subvec_fixed_idx_zero_i8:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.h
Expand All @@ -81,13 +81,13 @@ define <vscale x 8 x i8> @vec_scalable_subvec_fixed_idx_zero_i8(<vscale x 8 x i8
; CHECK-NEXT: ld1b { z1.h }, p0/z, [x0]
; CHECK-NEXT: sel z0.h, p1, z0.h, z1.h
; CHECK-NEXT: ret
%vec = load <vscale x 8 x i8>, <vscale x 8 x i8>* %a
%subvec = load <8 x i8>, <8 x i8>* %b
%vec = load <vscale x 8 x i8>, ptr %a
%subvec = load <8 x i8>, ptr %b
%ins = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v8i8(<vscale x 8 x i8> %vec, <8 x i8> %subvec, i64 0)
ret <vscale x 8 x i8> %ins
}

define <vscale x 8 x i8> @vec_scalable_subvec_fixed_idx_nonzero_i8(<vscale x 8 x i8>* %a, <8 x i8>* %b) #0 {
define <vscale x 8 x i8> @vec_scalable_subvec_fixed_idx_nonzero_i8(ptr %a, ptr %b) #0 {
; CHECK-LABEL: vec_scalable_subvec_fixed_idx_nonzero_i8:
; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
Expand All @@ -109,13 +109,13 @@ define <vscale x 8 x i8> @vec_scalable_subvec_fixed_idx_nonzero_i8(<vscale x 8 x
; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
%vec = load <vscale x 8 x i8>, <vscale x 8 x i8>* %a
%subvec = load <8 x i8>, <8 x i8>* %b
%vec = load <vscale x 8 x i8>, ptr %a
%subvec = load <8 x i8>, ptr %b
%ins = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v8i8(<vscale x 8 x i8> %vec, <8 x i8> %subvec, i64 8)
ret <vscale x 8 x i8> %ins
}

define <vscale x 4 x i16> @vec_scalable_subvec_fixed_idx_zero_i16(<vscale x 4 x i16>* %a, <4 x i16>* %b) #0 {
define <vscale x 4 x i16> @vec_scalable_subvec_fixed_idx_zero_i16(ptr %a, ptr %b) #0 {
; CHECK-LABEL: vec_scalable_subvec_fixed_idx_zero_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s
Expand All @@ -125,13 +125,13 @@ define <vscale x 4 x i16> @vec_scalable_subvec_fixed_idx_zero_i16(<vscale x 4 x
; CHECK-NEXT: ld1h { z1.s }, p0/z, [x0]
; CHECK-NEXT: sel z0.s, p1, z0.s, z1.s
; CHECK-NEXT: ret
%vec = load <vscale x 4 x i16>, <vscale x 4 x i16>* %a
%subvec = load <4 x i16>, <4 x i16>* %b
%vec = load <vscale x 4 x i16>, ptr %a
%subvec = load <4 x i16>, ptr %b
%ins = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v4i16(<vscale x 4 x i16> %vec, <4 x i16> %subvec, i64 0)
ret <vscale x 4 x i16> %ins
}

define <vscale x 4 x i16> @vec_scalable_subvec_fixed_idx_nonzero_i16(<vscale x 4 x i16>* %a, <4 x i16>* %b) #0 {
define <vscale x 4 x i16> @vec_scalable_subvec_fixed_idx_nonzero_i16(ptr %a, ptr %b) #0 {
; CHECK-LABEL: vec_scalable_subvec_fixed_idx_nonzero_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
Expand All @@ -153,13 +153,13 @@ define <vscale x 4 x i16> @vec_scalable_subvec_fixed_idx_nonzero_i16(<vscale x 4
; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
%vec = load <vscale x 4 x i16>, <vscale x 4 x i16>* %a
%subvec = load <4 x i16>, <4 x i16>* %b
%vec = load <vscale x 4 x i16>, ptr %a
%subvec = load <4 x i16>, ptr %b
%ins = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v4i16(<vscale x 4 x i16> %vec, <4 x i16> %subvec, i64 4)
ret <vscale x 4 x i16> %ins
}

define <vscale x 2 x i32> @vec_scalable_subvec_fixed_idx_zero_i32(<vscale x 2 x i32>* %a, <2 x i32>* %b) #0 {
define <vscale x 2 x i32> @vec_scalable_subvec_fixed_idx_zero_i32(ptr %a, ptr %b) #0 {
; CHECK-LABEL: vec_scalable_subvec_fixed_idx_zero_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
Expand All @@ -169,13 +169,13 @@ define <vscale x 2 x i32> @vec_scalable_subvec_fixed_idx_zero_i32(<vscale x 2 x
; CHECK-NEXT: ld1w { z1.d }, p0/z, [x0]
; CHECK-NEXT: sel z0.d, p1, z0.d, z1.d
; CHECK-NEXT: ret
%vec = load <vscale x 2 x i32>, <vscale x 2 x i32>* %a
%subvec = load <2 x i32>, <2 x i32>* %b
%vec = load <vscale x 2 x i32>, ptr %a
%subvec = load <2 x i32>, ptr %b
%ins = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v2i32(<vscale x 2 x i32> %vec, <2 x i32> %subvec, i64 0)
ret <vscale x 2 x i32> %ins
}

define <vscale x 2 x i32> @vec_scalable_subvec_fixed_idx_nonzero_i32(<vscale x 2 x i32>* %a, <2 x i32>* %b) #0 {
define <vscale x 2 x i32> @vec_scalable_subvec_fixed_idx_nonzero_i32(ptr %a, ptr %b) #0 {
; CHECK-LABEL: vec_scalable_subvec_fixed_idx_nonzero_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
Expand All @@ -197,13 +197,13 @@ define <vscale x 2 x i32> @vec_scalable_subvec_fixed_idx_nonzero_i32(<vscale x 2
; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
%vec = load <vscale x 2 x i32>, <vscale x 2 x i32>* %a
%subvec = load <2 x i32>, <2 x i32>* %b
%vec = load <vscale x 2 x i32>, ptr %a
%subvec = load <2 x i32>, ptr %b
%ins = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v2i32(<vscale x 2 x i32> %vec, <2 x i32> %subvec, i64 2)
ret <vscale x 2 x i32> %ins
}

define <vscale x 2 x i32> @vec_scalable_subvec_fixed_idx_nonzero_large_i32(<vscale x 2 x i32>* %a, <8 x i32>* %b) #1 {
define <vscale x 2 x i32> @vec_scalable_subvec_fixed_idx_nonzero_large_i32(ptr %a, ptr %b) #1 {
; CHECK-LABEL: vec_scalable_subvec_fixed_idx_nonzero_large_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
Expand All @@ -218,8 +218,8 @@ define <vscale x 2 x i32> @vec_scalable_subvec_fixed_idx_nonzero_large_i32(<vsca
; CHECK-NEXT: addvl sp, sp, #1
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
%vec = load <vscale x 2 x i32>, <vscale x 2 x i32>* %a
%subvec = load <8 x i32>, <8 x i32>* %b
%vec = load <vscale x 2 x i32>, ptr %a
%subvec = load <8 x i32>, ptr %b
%ins = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> %vec, <8 x i32> %subvec, i64 8)
ret <vscale x 2 x i32> %ins
}
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/AArch64/irg-nomem.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,18 +4,18 @@
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-unknown-linux-android"

define void @f(i64* nocapture %x) "target-features"="+mte" {
define void @f(ptr nocapture %x) "target-features"="+mte" {
entry:
store i64 1, i64* %x, align 8
%0 = tail call i8* @llvm.aarch64.irg(i8* null, i64 0)
%1 = tail call i8* @llvm.aarch64.irg.sp(i64 0)
%arrayidx1 = getelementptr inbounds i64, i64* %x, i64 1
store i64 1, i64* %arrayidx1, align 8
store i64 1, ptr %x, align 8
%0 = tail call ptr @llvm.aarch64.irg(ptr null, i64 0)
%1 = tail call ptr @llvm.aarch64.irg.sp(i64 0)
%arrayidx1 = getelementptr inbounds i64, ptr %x, i64 1
store i64 1, ptr %arrayidx1, align 8
ret void
}

declare i8* @llvm.aarch64.irg(i8*, i64) nounwind
declare i8* @llvm.aarch64.irg.sp(i64) nounwind
declare ptr @llvm.aarch64.irg(ptr, i64) nounwind
declare ptr @llvm.aarch64.irg.sp(i64) nounwind
...
---
name: f
Expand Down
26 changes: 13 additions & 13 deletions llvm/test/CodeGen/AArch64/ldradr.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@

%struct.T = type <{ i32, i64, i8, i32 }>

@ptr = external dso_local local_unnamed_addr global i32*, align 8
@ptr = external dso_local local_unnamed_addr global ptr, align 8
@ch = external dso_local local_unnamed_addr global i32, align 4
@ch8 = external dso_local local_unnamed_addr global i8, align 4
@t = external dso_local local_unnamed_addr global %struct.T, align 4
Expand All @@ -17,8 +17,8 @@ define i32 @barp() {
; CHECK-NEXT: ldr w0, [x8]
; CHECK-NEXT: ret
entry:
%0 = load i32*, i32** @ptr, align 8
%1 = load i32, i32* %0, align 4
%0 = load ptr, ptr @ptr, align 8
%1 = load i32, ptr %0, align 4
ret i32 %1
}

Expand All @@ -28,7 +28,7 @@ define i32 @barch() {
; CHECK-NEXT: ldr w0, ch
; CHECK-NEXT: ret
entry:
%0 = load i32, i32* @ch, align 4
%0 = load i32, ptr @ch, align 4
ret i32 %0
}

Expand All @@ -38,7 +38,7 @@ define i32 @barta() {
; CHECK-NEXT: ldr w0, t
; CHECK-NEXT: ret
entry:
%0 = load i32, i32* getelementptr inbounds (%struct.T, %struct.T* @t, i64 0, i32 0), align 4
%0 = load i32, ptr @t, align 4
ret i32 %0
}

Expand All @@ -48,7 +48,7 @@ define i64 @bartb() {
; CHECK-NEXT: ldr x0, t+4
; CHECK-NEXT: ret
entry:
%0 = load i64, i64* getelementptr inbounds (%struct.T, %struct.T* @t, i64 0, i32 1), align 8
%0 = load i64, ptr getelementptr inbounds (%struct.T, ptr @t, i64 0, i32 1), align 8
ret i64 %0
}

Expand All @@ -59,7 +59,7 @@ define i32 @bartc() {
; CHECK-NEXT: ldr w0, [x8]
; CHECK-NEXT: ret
entry:
%0 = load i32, i32* getelementptr inbounds (%struct.T, %struct.T* @t, i64 0, i32 3), align 1
%0 = load i32, ptr getelementptr inbounds (%struct.T, ptr @t, i64 0, i32 3), align 1
ret i32 %0
}

Expand All @@ -70,7 +70,7 @@ define i32 @bart2a() {
; CHECK-NEXT: ldr w0, [x8]
; CHECK-NEXT: ret
entry:
%0 = load i32, i32* getelementptr inbounds (%struct.T, %struct.T* @t2, i64 0, i32 0), align 2
%0 = load i32, ptr @t2, align 2
ret i32 %0
}

Expand All @@ -80,7 +80,7 @@ define i64 @zextload() {
; CHECK-NEXT: ldr w0, ch
; CHECK-NEXT: ret
entry:
%0 = load i32, i32* @ch, align 4
%0 = load i32, ptr @ch, align 4
%1 = zext i32 %0 to i64
ret i64 %1
}
Expand All @@ -92,7 +92,7 @@ define i64 @zextload8() {
; CHECK-NEXT: ldrb w0, [x8]
; CHECK-NEXT: ret
entry:
%0 = load i8, i8* @ch8, align 4
%0 = load i8, ptr @ch8, align 4
%1 = zext i8 %0 to i64
ret i64 %1
}
Expand All @@ -103,7 +103,7 @@ define i64 @sextload() {
; CHECK-NEXT: ldrsw x0, ch
; CHECK-NEXT: ret
entry:
%0 = load i32, i32* @ch, align 4
%0 = load i32, ptr @ch, align 4
%1 = sext i32 %0 to i64
ret i64 %1
}
Expand All @@ -115,7 +115,7 @@ define i64 @sextload8() {
; CHECK-NEXT: ldrsb x0, [x8]
; CHECK-NEXT: ret
entry:
%0 = load i8, i8* @ch8, align 4
%0 = load i8, ptr @ch8, align 4
%1 = sext i8 %0 to i64
ret i64 %1
}
Expand All @@ -126,7 +126,7 @@ define float @floatload() {
; CHECK-NEXT: ldr s0, f
; CHECK-NEXT: ret
entry:
%0 = load float, float* @f, align 4
%0 = load float, ptr @f, align 4
ret float %0
}

62 changes: 31 additions & 31 deletions llvm/test/CodeGen/AArch64/ldst-nopreidx-sp-redzone.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,67 +4,67 @@
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "arm64e-apple-ios13.0"

%struct.widget = type { i64, i64, i32, i32, i64, i64, i64, i64, i64, i32, i32, i32, i16, i32, %struct.snork*, %struct.zot, %struct.zot, %struct.zot, %struct.zot, %struct.zot, i64, i64, i64, i32, i64, i32, i32, i32, i8*, %struct.baz, %struct.baz, i64, i64, %struct.snork*, %struct.zot, i32, i32, i32, i32, i32, i32, i32, [32 x i8], i64, i64, %struct.wombat, i32, i64, i64, i64, i64 }
%struct.widget = type { i64, i64, i32, i32, i64, i64, i64, i64, i64, i32, i32, i32, i16, i32, ptr, %struct.zot, %struct.zot, %struct.zot, %struct.zot, %struct.zot, i64, i64, i64, i32, i64, i32, i32, i32, ptr, %struct.baz, %struct.baz, i64, i64, ptr, %struct.zot, i32, i32, i32, i32, i32, i32, i32, [32 x i8], i64, i64, %struct.wombat, i32, i64, i64, i64, i64 }
%struct.baz = type { [4 x i32] }
%struct.snork = type { i32, i32, [1 x %struct.spam] }
%struct.spam = type { %struct.baz, i32, i32 }
%struct.zot = type { i64, i64 }
%struct.wombat = type { [2 x i32] }
%struct.wombat.0 = type { [200 x i32] }

@__stack_chk_guard = external global i8*
@__stack_chk_guard = external global ptr

; Function Attrs: noredzone ssp
define hidden void @with_noredzone_80bytes() #0 {
bb:
%StackGuardSlot = alloca i8*, align 8
%0 = call i8* @llvm.stackguard()
call void @llvm.stackprotector(i8* %0, i8** %StackGuardSlot)
%StackGuardSlot = alloca ptr, align 8
%0 = call ptr @llvm.stackguard()
call void @llvm.stackprotector(ptr %0, ptr %StackGuardSlot)
%tmp = alloca %struct.widget, align 16
%tmp1 = alloca %struct.wombat.0*, align 8
%tmp2 = alloca %struct.wombat.0*, align 8
%tmp3 = alloca %struct.wombat.0*, align 8
%tmp4 = alloca %struct.wombat.0*, align 8
store %struct.wombat.0* null, %struct.wombat.0** %tmp3, align 8
store %struct.wombat.0* null, %struct.wombat.0** %tmp4, align 8
%tmp1 = alloca ptr, align 8
%tmp2 = alloca ptr, align 8
%tmp3 = alloca ptr, align 8
%tmp4 = alloca ptr, align 8
store ptr null, ptr %tmp3, align 8
store ptr null, ptr %tmp4, align 8
ret void
}

define hidden void @with_redzone_480bytes() #2 {
bb:
%StackGuardSlot = alloca i8*, align 8
%0 = call i8* @llvm.stackguard()
call void @llvm.stackprotector(i8* %0, i8** %StackGuardSlot)
%StackGuardSlot = alloca ptr, align 8
%0 = call ptr @llvm.stackguard()
call void @llvm.stackprotector(ptr %0, ptr %StackGuardSlot)
%tmp = alloca %struct.widget, align 16
%tmp1 = alloca %struct.wombat.0*, align 8
%tmp2 = alloca %struct.wombat.0*, align 8
%tmp3 = alloca %struct.wombat.0*, align 8
%tmp4 = alloca %struct.wombat.0*, align 8
store %struct.wombat.0* null, %struct.wombat.0** %tmp3, align 8
store %struct.wombat.0* null, %struct.wombat.0** %tmp4, align 8
%tmp1 = alloca ptr, align 8
%tmp2 = alloca ptr, align 8
%tmp3 = alloca ptr, align 8
%tmp4 = alloca ptr, align 8
store ptr null, ptr %tmp3, align 8
store ptr null, ptr %tmp4, align 8
ret void
}

define hidden void @with_noredzone_no_mem_between() #0 {
bb:
%StackGuardSlot = alloca i8*, align 8
%0 = call i8* @llvm.stackguard()
call void @llvm.stackprotector(i8* %0, i8** %StackGuardSlot)
%StackGuardSlot = alloca ptr, align 8
%0 = call ptr @llvm.stackguard()
call void @llvm.stackprotector(ptr %0, ptr %StackGuardSlot)
%tmp = alloca %struct.widget, align 16
%tmp1 = alloca %struct.wombat.0*, align 8
%tmp2 = alloca %struct.wombat.0*, align 8
%tmp3 = alloca %struct.wombat.0*, align 8
%tmp4 = alloca %struct.wombat.0*, align 8
store %struct.wombat.0* null, %struct.wombat.0** %tmp3, align 8
store %struct.wombat.0* null, %struct.wombat.0** %tmp4, align 8
%tmp1 = alloca ptr, align 8
%tmp2 = alloca ptr, align 8
%tmp3 = alloca ptr, align 8
%tmp4 = alloca ptr, align 8
store ptr null, ptr %tmp3, align 8
store ptr null, ptr %tmp4, align 8
ret void
}

; Function Attrs: nofree nosync nounwind willreturn
declare i8* @llvm.stackguard() #1
declare ptr @llvm.stackguard() #1

; Function Attrs: nofree nosync nounwind willreturn
declare void @llvm.stackprotector(i8*, i8**) #1
declare void @llvm.stackprotector(ptr, ptr) #1

attributes #0 = { noredzone ssp "frame-pointer"="non-leaf" }
attributes #1 = { nofree nosync nounwind willreturn }
Expand Down
14 changes: 7 additions & 7 deletions llvm/test/CodeGen/AArch64/ldst-opt-aa.mir
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,13 @@
# RUN: llc -mtriple=aarch64--linux-gnu -run-pass=aarch64-ldst-opt %s -verify-machineinstrs -o - | FileCheck %s
--- |
define void @ldr_str_aa(i32* noalias nocapture %x, i32* noalias nocapture readonly %y) {
define void @ldr_str_aa(ptr noalias nocapture %x, ptr noalias nocapture readonly %y) {
entry:
%0 = load i32, i32* %y, align 4
store i32 %0, i32* %x, align 4
%arrayidx2 = getelementptr inbounds i32, i32* %y, i32 1
%1 = load i32, i32* %arrayidx2, align 4
%arrayidx3 = getelementptr inbounds i32, i32* %x, i32 1
store i32 %1, i32* %arrayidx3, align 4
%0 = load i32, ptr %y, align 4
store i32 %0, ptr %x, align 4
%arrayidx2 = getelementptr inbounds i32, ptr %y, i32 1
%1 = load i32, ptr %arrayidx2, align 4
%arrayidx3 = getelementptr inbounds i32, ptr %x, i32 1
store i32 %1, ptr %arrayidx3, align 4
ret void
}

Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/AArch64/ldst-opt-non-imm-offset.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,8 +4,8 @@

define i32 @test() {
entry:
store i32 0, i32* @g, align 4
%0 = load i32, i32* undef, align 4
store i32 0, ptr @g, align 4
%0 = load i32, ptr undef, align 4
ret i32 %0
}

Expand All @@ -21,7 +21,7 @@ body: |
bb.0.entry:
renamable $x8 = ADRP target-flags(aarch64-page) @g
STRWui $wzr, killed renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @g :: (store (s32) into @g)
renamable $w0 = LDRWui undef renamable $x8, 0 :: (load (s32) from `i32* undef`)
renamable $w0 = LDRWui undef renamable $x8, 0 :: (load (s32) from `ptr undef`)
RET_ReallyLR implicit $w0
...
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AArch64/ldst-opt-zr-clobber.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@
# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass aarch64-ldst-opt -verify-machineinstrs -o - %s | FileCheck %s

--- |
define i1 @no-clobber-zr(i64* %p, i64 %x) { ret i1 0 }
define i1 @no-clobber-zr(ptr %p, i64 %x) { ret i1 0 }
...
---
# Check that write of xzr doesn't inhibit pairing of xzr stores since
Expand Down
32 changes: 16 additions & 16 deletions llvm/test/CodeGen/AArch64/machine-combiner-fmul-dup.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,96 +6,96 @@
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-unknown-linux-gnu"

define void @indexed_2s(<2 x float> %shuf, <2 x float> %mu, <2 x float> %ad, <2 x float>* %ret) #0 {
define void @indexed_2s(<2 x float> %shuf, <2 x float> %mu, <2 x float> %ad, ptr %ret) #0 {
entry:
%shuffle = shufflevector <2 x float> %shuf, <2 x float> undef, <2 x i32> zeroinitializer
br label %for.cond

for.cond: ; preds = %for.cond, %entry
%mul = fmul <2 x float> %mu, %shuffle
%add = fadd <2 x float> %mul, %ad
store <2 x float> %add, <2 x float>* %ret, align 16
store <2 x float> %add, ptr %ret, align 16
br label %for.cond
}

define void @indexed_2s_rev(<2 x float> %shuf, <2 x float> %mu, <2 x float> %ad, <2 x float>* %ret) #0 {
define void @indexed_2s_rev(<2 x float> %shuf, <2 x float> %mu, <2 x float> %ad, ptr %ret) #0 {
entry:
%shuffle = shufflevector <2 x float> %shuf, <2 x float> undef, <2 x i32> zeroinitializer
br label %for.cond

for.cond: ; preds = %for.cond, %entry
%mul = fmul <2 x float> %shuffle, %mu
%add = fadd <2 x float> %mul, %ad
store <2 x float> %add, <2 x float>* %ret, align 16
store <2 x float> %add, ptr %ret, align 16
br label %for.cond
}

define void @indexed_2d(<2 x double> %shuf, <2 x double> %mu, <2 x double> %ad, <2 x double>* %ret) #0 {
define void @indexed_2d(<2 x double> %shuf, <2 x double> %mu, <2 x double> %ad, ptr %ret) #0 {
entry:
%shuffle = shufflevector <2 x double> %shuf, <2 x double> undef, <2 x i32> zeroinitializer
br label %for.cond

for.cond: ; preds = %for.cond, %entry
%mul = fmul <2 x double> %mu, %shuffle
%add = fadd <2 x double> %mul, %ad
store <2 x double> %add, <2 x double>* %ret, align 16
store <2 x double> %add, ptr %ret, align 16
br label %for.cond
}

define void @indexed_4s(<4 x float> %shuf, <4 x float> %mu, <4 x float> %ad, <4 x float>* %ret) #0 {
define void @indexed_4s(<4 x float> %shuf, <4 x float> %mu, <4 x float> %ad, ptr %ret) #0 {
entry:
%shuffle = shufflevector <4 x float> %shuf, <4 x float> undef, <4 x i32> zeroinitializer
br label %for.cond

for.cond: ; preds = %for.cond, %entry
%mul = fmul <4 x float> %mu, %shuffle
%add = fadd <4 x float> %mul, %ad
store <4 x float> %add, <4 x float>* %ret, align 16
store <4 x float> %add, ptr %ret, align 16
br label %for.cond
}

define void @indexed_4h(<4 x half> %shuf, <4 x half> %mu, <4 x half> %ad, <4 x half>* %ret) #0 {
define void @indexed_4h(<4 x half> %shuf, <4 x half> %mu, <4 x half> %ad, ptr %ret) #0 {
entry:
%shuffle = shufflevector <4 x half> %shuf, <4 x half> undef, <4 x i32> zeroinitializer
br label %for.cond

for.cond:
%mul = fmul <4 x half> %mu, %shuffle
%add = fadd <4 x half> %mul, %ad
store <4 x half> %add, <4 x half>* %ret, align 16
store <4 x half> %add, ptr %ret, align 16
br label %for.cond
}

define void @indexed_8h(<8 x half> %shuf, <8 x half> %mu, <8 x half> %ad, <8 x half>* %ret) #0 {
define void @indexed_8h(<8 x half> %shuf, <8 x half> %mu, <8 x half> %ad, ptr %ret) #0 {
entry:
%shuffle = shufflevector <8 x half> %shuf, <8 x half> undef, <8 x i32> zeroinitializer
br label %for.cond

for.cond:
%mul = fmul <8 x half> %mu, %shuffle
%add = fadd <8 x half> %mul, %ad
store <8 x half> %add, <8 x half>* %ret, align 16
store <8 x half> %add, ptr %ret, align 16
br label %for.cond
}

define void @kill_state(<2 x float> %shuf, <2 x float> %mu, <2 x float> %ad,
<2 x float>* %ret, <2 x float>* %ret2, float %f) #0 {
ptr %ret, ptr %ret2, float %f) #0 {
entry:
%zero_elem = extractelement <2 x float> %shuf, i32 0
%ins = insertelement <2 x float> undef, float %zero_elem, i32 0
%shuffle = shufflevector <2 x float> %ins, <2 x float> undef, <2 x i32> zeroinitializer
%ins2 = insertelement <2 x float> %ins, float %f, i32 1
store <2 x float> %ins2, <2 x float>* %ret2, align 8
store <2 x float> %ins2, ptr %ret2, align 8
br label %for.cond

for.cond: ; preds = %for.cond, %entry
%mul = fmul <2 x float> %mu, %shuffle
%add = fadd <2 x float> %mul, %ad
store <2 x float> %add, <2 x float>* %ret, align 16
store <2 x float> %add, ptr %ret, align 16
br label %for.cond
}

define void @extracopy(<2 x float> %shuf, <2 x float> %mu, <2 x float> %ad, <2 x float>* %ret) #0 {
define void @extracopy(<2 x float> %shuf, <2 x float> %mu, <2 x float> %ad, ptr %ret) #0 {
unreachable
}

Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AArch64/machine-outliner-bti.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,7 @@
--- |
@g = hidden local_unnamed_addr global i32 0, align 4

define hidden void @bar(void ()* nocapture %f) "branch-target-enforcement"="true" {
define hidden void @bar(ptr nocapture %f) "branch-target-enforcement"="true" {
entry:
ret void
}
Expand Down
58 changes: 29 additions & 29 deletions llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-sp-mod.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,57 +4,57 @@
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-arm-linux-gnu"

@v = common dso_local global i32* null, align 8
@v = common dso_local global ptr null, align 8

; Function Attrs: nounwind
define dso_local void @legal0() #0 {
%1 = alloca i32, align 4
store volatile i32* %1, i32** @v, align 8
store volatile i32* %1, i32** @v, align 8
store volatile i32* %1, i32** @v, align 8
store volatile i32* %1, i32** @v, align 8
store volatile i32* %1, i32** @v, align 8
store volatile i32* %1, i32** @v, align 8
store volatile i32* %1, i32** @v, align 8
store volatile ptr %1, ptr @v, align 8
store volatile ptr %1, ptr @v, align 8
store volatile ptr %1, ptr @v, align 8
store volatile ptr %1, ptr @v, align 8
store volatile ptr %1, ptr @v, align 8
store volatile ptr %1, ptr @v, align 8
store volatile ptr %1, ptr @v, align 8
ret void
}

; Function Attrs: nounwind
define dso_local void @legal1() #0 {
%1 = alloca i32, align 4
store volatile i32* %1, i32** @v, align 8
store volatile i32* %1, i32** @v, align 8
store volatile i32* %1, i32** @v, align 8
store volatile i32* %1, i32** @v, align 8
store volatile i32* %1, i32** @v, align 8
store volatile i32* %1, i32** @v, align 8
store volatile i32* %1, i32** @v, align 8
store volatile ptr %1, ptr @v, align 8
store volatile ptr %1, ptr @v, align 8
store volatile ptr %1, ptr @v, align 8
store volatile ptr %1, ptr @v, align 8
store volatile ptr %1, ptr @v, align 8
store volatile ptr %1, ptr @v, align 8
store volatile ptr %1, ptr @v, align 8
ret void
}

; Function Attrs: nounwind
define dso_local void @illegal0() #0 {
%1 = alloca i32, align 4
store volatile i32* %1, i32** @v, align 8
store volatile i32* %1, i32** @v, align 8
store volatile i32* %1, i32** @v, align 8
store volatile i32* %1, i32** @v, align 8
store volatile i32* %1, i32** @v, align 8
store volatile i32* %1, i32** @v, align 8
store volatile i32* %1, i32** @v, align 8
store volatile ptr %1, ptr @v, align 8
store volatile ptr %1, ptr @v, align 8
store volatile ptr %1, ptr @v, align 8
store volatile ptr %1, ptr @v, align 8
store volatile ptr %1, ptr @v, align 8
store volatile ptr %1, ptr @v, align 8
store volatile ptr %1, ptr @v, align 8
ret void
}

; Function Attrs: nounwind
define dso_local void @illegal1() #0 {
%1 = alloca i32, align 4
store volatile i32* %1, i32** @v, align 8
store volatile i32* %1, i32** @v, align 8
store volatile i32* %1, i32** @v, align 8
store volatile i32* %1, i32** @v, align 8
store volatile i32* %1, i32** @v, align 8
store volatile i32* %1, i32** @v, align 8
store volatile i32* %1, i32** @v, align 8
store volatile ptr %1, ptr @v, align 8
store volatile ptr %1, ptr @v, align 8
store volatile ptr %1, ptr @v, align 8
store volatile ptr %1, ptr @v, align 8
store volatile ptr %1, ptr @v, align 8
store volatile ptr %1, ptr @v, align 8
store volatile ptr %1, ptr @v, align 8
ret void
}

Expand Down
14 changes: 7 additions & 7 deletions llvm/test/CodeGen/AArch64/machine-scheduler.mir
View file
Original file line number Diff line number Diff line change
@@ -1,15 +1,15 @@
# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass machine-scheduler -verify-machineinstrs -o - %s | FileCheck %s

--- |
define i64 @load_imp-def(i64* nocapture %P, i32 %v) {
define i64 @load_imp-def(ptr nocapture %P, i32 %v) {
entry:
%0 = bitcast i64* %P to i32*
%1 = load i32, i32* %0
%0 = bitcast ptr %P to ptr
%1 = load i32, ptr %0
%conv = zext i32 %1 to i64
%arrayidx19 = getelementptr inbounds i64, i64* %P, i64 1
%arrayidx1 = bitcast i64* %arrayidx19 to i32*
store i32 %v, i32* %arrayidx1
%2 = load i64, i64* %arrayidx19
%arrayidx19 = getelementptr inbounds i64, ptr %P, i64 1
%arrayidx1 = bitcast ptr %arrayidx19 to ptr
store i32 %v, ptr %arrayidx1
%2 = load i64, ptr %arrayidx19
%and = and i64 %2, 4294967295
%add = add nuw nsw i64 %and, %conv
ret i64 %add
Expand Down
86 changes: 43 additions & 43 deletions llvm/test/CodeGen/AArch64/memcpy-scoped-aa.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@
; MIR-LABEL: name: test_memcpy
; MIR: %2:fpr128 = LDRQui %0, 1 :: (load (s128) from %ir.p1, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]])
; MIR-NEXT: STRQui killed %2, %0, 0 :: (store (s128) into %ir.p0, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]])
define i32 @test_memcpy(i32* nocapture %p, i32* nocapture readonly %q) {
define i32 @test_memcpy(ptr nocapture %p, ptr nocapture readonly %q) {
; CHECK-LABEL: test_memcpy:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp w9, w10, [x1]
Expand All @@ -20,21 +20,21 @@ define i32 @test_memcpy(i32* nocapture %p, i32* nocapture readonly %q) {
; CHECK-NEXT: add w0, w9, w10
; CHECK-NEXT: str q0, [x8]
; CHECK-NEXT: ret
%p0 = bitcast i32* %p to i8*
%add.ptr = getelementptr inbounds i32, i32* %p, i64 4
%p1 = bitcast i32* %add.ptr to i8*
tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* noundef nonnull align 4 dereferenceable(16) %p0, i8* noundef nonnull align 4 dereferenceable(16) %p1, i64 16, i1 false), !alias.scope !2, !noalias !4
%v0 = load i32, i32* %q, align 4, !alias.scope !4, !noalias !2
%q1 = getelementptr inbounds i32, i32* %q, i64 1
%v1 = load i32, i32* %q1, align 4, !alias.scope !4, !noalias !2
%p0 = bitcast ptr %p to ptr
%add.ptr = getelementptr inbounds i32, ptr %p, i64 4
%p1 = bitcast ptr %add.ptr to ptr
tail call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 4 dereferenceable(16) %p0, ptr noundef nonnull align 4 dereferenceable(16) %p1, i64 16, i1 false), !alias.scope !2, !noalias !4
%v0 = load i32, ptr %q, align 4, !alias.scope !4, !noalias !2
%q1 = getelementptr inbounds i32, ptr %q, i64 1
%v1 = load i32, ptr %q1, align 4, !alias.scope !4, !noalias !2
%add = add i32 %v0, %v1
ret i32 %add
}

; MIR-LABEL: name: test_memcpy_inline
; MIR: %2:fpr128 = LDRQui %0, 1 :: (load (s128) from %ir.p1, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]])
; MIR-NEXT: STRQui killed %2, %0, 0 :: (store (s128) into %ir.p0, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]])
define i32 @test_memcpy_inline(i32* nocapture %p, i32* nocapture readonly %q) {
define i32 @test_memcpy_inline(ptr nocapture %p, ptr nocapture readonly %q) {
; CHECK-LABEL: test_memcpy_inline:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp w9, w10, [x1]
Expand All @@ -43,21 +43,21 @@ define i32 @test_memcpy_inline(i32* nocapture %p, i32* nocapture readonly %q) {
; CHECK-NEXT: add w0, w9, w10
; CHECK-NEXT: str q0, [x8]
; CHECK-NEXT: ret
%p0 = bitcast i32* %p to i8*
%add.ptr = getelementptr inbounds i32, i32* %p, i64 4
%p1 = bitcast i32* %add.ptr to i8*
tail call void @llvm.memcpy.inline.p0i8.p0i8.i64(i8* noundef nonnull align 4 dereferenceable(16) %p0, i8* noundef nonnull align 4 dereferenceable(16) %p1, i64 16, i1 false), !alias.scope !2, !noalias !4
%v0 = load i32, i32* %q, align 4, !alias.scope !4, !noalias !2
%q1 = getelementptr inbounds i32, i32* %q, i64 1
%v1 = load i32, i32* %q1, align 4, !alias.scope !4, !noalias !2
%p0 = bitcast ptr %p to ptr
%add.ptr = getelementptr inbounds i32, ptr %p, i64 4
%p1 = bitcast ptr %add.ptr to ptr
tail call void @llvm.memcpy.inline.p0.p0.i64(ptr noundef nonnull align 4 dereferenceable(16) %p0, ptr noundef nonnull align 4 dereferenceable(16) %p1, i64 16, i1 false), !alias.scope !2, !noalias !4
%v0 = load i32, ptr %q, align 4, !alias.scope !4, !noalias !2
%q1 = getelementptr inbounds i32, ptr %q, i64 1
%v1 = load i32, ptr %q1, align 4, !alias.scope !4, !noalias !2
%add = add i32 %v0, %v1
ret i32 %add
}

; MIR-LABEL: name: test_memmove
; MIR: %2:fpr128 = LDRQui %0, 1 :: (load (s128) from %ir.p1, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]])
; MIR-NEXT: STRQui killed %2, %0, 0 :: (store (s128) into %ir.p0, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]])
define i32 @test_memmove(i32* nocapture %p, i32* nocapture readonly %q) {
define i32 @test_memmove(ptr nocapture %p, ptr nocapture readonly %q) {
; CHECK-LABEL: test_memmove:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp w9, w10, [x1]
Expand All @@ -66,13 +66,13 @@ define i32 @test_memmove(i32* nocapture %p, i32* nocapture readonly %q) {
; CHECK-NEXT: add w0, w9, w10
; CHECK-NEXT: str q0, [x8]
; CHECK-NEXT: ret
%p0 = bitcast i32* %p to i8*
%add.ptr = getelementptr inbounds i32, i32* %p, i64 4
%p1 = bitcast i32* %add.ptr to i8*
tail call void @llvm.memmove.p0i8.p0i8.i64(i8* noundef nonnull align 4 dereferenceable(16) %p0, i8* noundef nonnull align 4 dereferenceable(16) %p1, i64 16, i1 false), !alias.scope !2, !noalias !4
%v0 = load i32, i32* %q, align 4, !alias.scope !4, !noalias !2
%q1 = getelementptr inbounds i32, i32* %q, i64 1
%v1 = load i32, i32* %q1, align 4, !alias.scope !4, !noalias !2
%p0 = bitcast ptr %p to ptr
%add.ptr = getelementptr inbounds i32, ptr %p, i64 4
%p1 = bitcast ptr %add.ptr to ptr
tail call void @llvm.memmove.p0.p0.i64(ptr noundef nonnull align 4 dereferenceable(16) %p0, ptr noundef nonnull align 4 dereferenceable(16) %p1, i64 16, i1 false), !alias.scope !2, !noalias !4
%v0 = load i32, ptr %q, align 4, !alias.scope !4, !noalias !2
%q1 = getelementptr inbounds i32, ptr %q, i64 1
%v1 = load i32, ptr %q1, align 4, !alias.scope !4, !noalias !2
%add = add i32 %v0, %v1
ret i32 %add
}
Expand All @@ -81,7 +81,7 @@ define i32 @test_memmove(i32* nocapture %p, i32* nocapture readonly %q) {
; MIR: %2:gpr64 = MOVi64imm -6148914691236517206
; MIR-NEXT: STRXui %2, %0, 1 :: (store (s64) into %ir.p0 + 8, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]])
; MIR-NEXT: STRXui %2, %0, 0 :: (store (s64) into %ir.p0, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]])
define i32 @test_memset(i32* nocapture %p, i32* nocapture readonly %q) {
define i32 @test_memset(ptr nocapture %p, ptr nocapture readonly %q) {
; CHECK-LABEL: test_memset:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp w10, w11, [x1]
Expand All @@ -90,19 +90,19 @@ define i32 @test_memset(i32* nocapture %p, i32* nocapture readonly %q) {
; CHECK-NEXT: stp x9, x9, [x8]
; CHECK-NEXT: add w0, w10, w11
; CHECK-NEXT: ret
%p0 = bitcast i32* %p to i8*
tail call void @llvm.memset.p0i8.i64(i8* noundef nonnull align 4 dereferenceable(16) %p0, i8 170, i64 16, i1 false), !alias.scope !2, !noalias !4
%v0 = load i32, i32* %q, align 4, !alias.scope !4, !noalias !2
%q1 = getelementptr inbounds i32, i32* %q, i64 1
%v1 = load i32, i32* %q1, align 4, !alias.scope !4, !noalias !2
%p0 = bitcast ptr %p to ptr
tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 4 dereferenceable(16) %p0, i8 170, i64 16, i1 false), !alias.scope !2, !noalias !4
%v0 = load i32, ptr %q, align 4, !alias.scope !4, !noalias !2
%q1 = getelementptr inbounds i32, ptr %q, i64 1
%v1 = load i32, ptr %q1, align 4, !alias.scope !4, !noalias !2
%add = add i32 %v0, %v1
ret i32 %add
}

; MIR-LABEL: name: test_mempcpy
; MIR: %2:fpr128 = LDRQui %0, 1 :: (load (s128) from %ir.p1, align 1, !alias.scope ![[SET0]], !noalias ![[SET1]])
; MIR-NEXT: STRQui killed %2, %0, 0 :: (store (s128) into %ir.p0, align 1, !alias.scope ![[SET0]], !noalias ![[SET1]])
define i32 @test_mempcpy(i32* nocapture %p, i32* nocapture readonly %q) {
define i32 @test_mempcpy(ptr nocapture %p, ptr nocapture readonly %q) {
; CHECK-LABEL: test_mempcpy:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp w9, w10, [x1]
Expand All @@ -111,23 +111,23 @@ define i32 @test_mempcpy(i32* nocapture %p, i32* nocapture readonly %q) {
; CHECK-NEXT: add w0, w9, w10
; CHECK-NEXT: str q0, [x8]
; CHECK-NEXT: ret
%p0 = bitcast i32* %p to i8*
%add.ptr = getelementptr inbounds i32, i32* %p, i64 4
%p1 = bitcast i32* %add.ptr to i8*
%call = tail call i8* @mempcpy(i8* noundef nonnull align 4 dereferenceable(16) %p0, i8* noundef nonnull align 4 dereferenceable(16) %p1, i64 16), !alias.scope !2, !noalias !4
%v0 = load i32, i32* %q, align 4, !alias.scope !4, !noalias !2
%q1 = getelementptr inbounds i32, i32* %q, i64 1
%v1 = load i32, i32* %q1, align 4, !alias.scope !4, !noalias !2
%p0 = bitcast ptr %p to ptr
%add.ptr = getelementptr inbounds i32, ptr %p, i64 4
%p1 = bitcast ptr %add.ptr to ptr
%call = tail call ptr @mempcpy(ptr noundef nonnull align 4 dereferenceable(16) %p0, ptr noundef nonnull align 4 dereferenceable(16) %p1, i64 16), !alias.scope !2, !noalias !4
%v0 = load i32, ptr %q, align 4, !alias.scope !4, !noalias !2
%q1 = getelementptr inbounds i32, ptr %q, i64 1
%v1 = load i32, ptr %q1, align 4, !alias.scope !4, !noalias !2
%add = add i32 %v0, %v1
ret i32 %add
}

declare void @llvm.memcpy.p0i8.p0i8.i64(i8* noalias nocapture writeonly, i8* noalias nocapture readonly, i64, i1 immarg)
declare void @llvm.memcpy.inline.p0i8.p0i8.i64(i8* noalias nocapture writeonly, i8* noalias nocapture readonly, i64, i1 immarg)
declare void @llvm.memmove.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i1 immarg)
declare void @llvm.memset.p0i8.i64(i8* nocapture writeonly, i8, i64, i1 immarg)
declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg)
declare void @llvm.memcpy.inline.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg)
declare void @llvm.memmove.p0.p0.i64(ptr nocapture writeonly, ptr nocapture readonly, i64, i1 immarg)
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg)

declare i8* @mempcpy(i8*, i8*, i64)
declare ptr @mempcpy(ptr, ptr, i64)

!0 = distinct !{!0, !"bax"}
!1 = distinct !{!1, !0, !"bax: %p"}
Expand Down
28 changes: 14 additions & 14 deletions llvm/test/CodeGen/AArch64/merge-scoped-aa-store.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -12,38 +12,38 @@
; MIR-DAG: ![[SET2:[0-9]+]] = !{![[SCOPE2]]}
; MIR-DAG: ![[SET3:[0-9]+]] = !{![[SCOPE3]]}

define void @blam0(<3 x float>* %g0, <3 x float>* %g1) {
define void @blam0(ptr %g0, ptr %g1) {
; MIR-LABEL: name: blam0
; MIR: LDRDui %0, 0 :: (load (s64) from %ir.g0, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]])
; MIR: STRDui killed %5, %1, 0 :: (store (s64) into %ir.tmp41, align 4, !alias.scope ![[SET1]], !noalias ![[SET0]])
%tmp4 = getelementptr inbounds <3 x float>, <3 x float>* %g1, i64 0, i64 0
%tmp5 = load <3 x float>, <3 x float>* %g0, align 4, !alias.scope !0, !noalias !1
%tmp4 = getelementptr inbounds <3 x float>, ptr %g1, i64 0, i64 0
%tmp5 = load <3 x float>, ptr %g0, align 4, !alias.scope !0, !noalias !1
%tmp6 = extractelement <3 x float> %tmp5, i64 0
store float %tmp6, float* %tmp4, align 4, !alias.scope !1, !noalias !0
%tmp7 = getelementptr inbounds float, float* %tmp4, i64 1
%tmp8 = load <3 x float>, <3 x float>* %g0, align 4, !alias.scope !0, !noalias !1
store float %tmp6, ptr %tmp4, align 4, !alias.scope !1, !noalias !0
%tmp7 = getelementptr inbounds float, ptr %tmp4, i64 1
%tmp8 = load <3 x float>, ptr %g0, align 4, !alias.scope !0, !noalias !1
%tmp9 = extractelement <3 x float> %tmp8, i64 1
store float %tmp9, float* %tmp7, align 4, !alias.scope !1, !noalias !0
store float %tmp9, ptr %tmp7, align 4, !alias.scope !1, !noalias !0
ret void;
}

; Ensure new scoped AA metadata are calculated after merging stores.
define void @blam1(<3 x float>* %g0, <3 x float>* %g1) {
define void @blam1(ptr %g0, ptr %g1) {
; MIR-LABEL: name: blam1
; MIR: machineMetadataNodes:
; MIR-DAG: ![[MMSET0:[0-9]+]] = !{![[SCOPE2]], ![[SCOPE1]]}
; MIR-DAG: ![[MMSET1:[0-9]+]] = !{}
; MIR: body:
; MIR: LDRDui %0, 0 :: (load (s64) from %ir.g0, align 4, !alias.scope ![[SET0]], !noalias ![[SET1]])
; MIR: STRDui killed %5, %1, 0 :: (store (s64) into %ir.tmp41, align 4, !alias.scope ![[MMSET0]], !noalias ![[MMSET1]])
%tmp4 = getelementptr inbounds <3 x float>, <3 x float>* %g1, i64 0, i64 0
%tmp5 = load <3 x float>, <3 x float>* %g0, align 4, !alias.scope !0, !noalias !1
%tmp4 = getelementptr inbounds <3 x float>, ptr %g1, i64 0, i64 0
%tmp5 = load <3 x float>, ptr %g0, align 4, !alias.scope !0, !noalias !1
%tmp6 = extractelement <3 x float> %tmp5, i64 0
store float %tmp6, float* %tmp4, align 4, !alias.scope !1, !noalias !0
%tmp7 = getelementptr inbounds float, float* %tmp4, i64 1
%tmp8 = load <3 x float>, <3 x float>* %g0, align 4, !alias.scope !0, !noalias !1
store float %tmp6, ptr %tmp4, align 4, !alias.scope !1, !noalias !0
%tmp7 = getelementptr inbounds float, ptr %tmp4, i64 1
%tmp8 = load <3 x float>, ptr %g0, align 4, !alias.scope !0, !noalias !1
%tmp9 = extractelement <3 x float> %tmp8, i64 1
store float %tmp9, float* %tmp7, align 4, !alias.scope !5, !noalias !6
store float %tmp9, ptr %tmp7, align 4, !alias.scope !5, !noalias !6
ret void;
}

Expand Down
22 changes: 11 additions & 11 deletions llvm/test/CodeGen/AArch64/merge-store.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -23,14 +23,14 @@ define void @blam() {
; MISALIGNED-NEXT: add x8, x8, :lo12:g1
; MISALIGNED-NEXT: str d0, [x8]
; MISALIGNED-NEXT: ret
%tmp4 = getelementptr inbounds <3 x float>, <3 x float>* @g1, i64 0, i64 0
%tmp5 = load <3 x float>, <3 x float>* @g0, align 16
%tmp4 = getelementptr inbounds <3 x float>, ptr @g1, i64 0, i64 0
%tmp5 = load <3 x float>, ptr @g0, align 16
%tmp6 = extractelement <3 x float> %tmp5, i64 0
store float %tmp6, float* %tmp4
%tmp7 = getelementptr inbounds float, float* %tmp4, i64 1
%tmp8 = load <3 x float>, <3 x float>* @g0, align 16
store float %tmp6, ptr %tmp4
%tmp7 = getelementptr inbounds float, ptr %tmp4, i64 1
%tmp8 = load <3 x float>, ptr @g0, align 16
%tmp9 = extractelement <3 x float> %tmp8, i64 1
store float %tmp9, float* %tmp7
store float %tmp9, ptr %tmp7
ret void;
}

Expand All @@ -41,7 +41,7 @@ define void @blam() {
; unaligned 16-byte stores are slow. This test would infinite loop when
; the fastness of unaligned accesses was not specified correctly.

define void @merge_vec_extract_stores(<4 x float> %v1, <2 x float>* %ptr) {
define void @merge_vec_extract_stores(<4 x float> %v1, ptr %ptr) {
; SPLITTING-LABEL: merge_vec_extract_stores:
; SPLITTING: // %bb.0:
; SPLITTING-NEXT: ext v1.16b, v0.16b, v0.16b, #8
Expand All @@ -53,14 +53,14 @@ define void @merge_vec_extract_stores(<4 x float> %v1, <2 x float>* %ptr) {
; MISALIGNED: // %bb.0:
; MISALIGNED-NEXT: stur q0, [x0, #24]
; MISALIGNED-NEXT: ret
%idx0 = getelementptr inbounds <2 x float>, <2 x float>* %ptr, i64 3
%idx1 = getelementptr inbounds <2 x float>, <2 x float>* %ptr, i64 4
%idx0 = getelementptr inbounds <2 x float>, ptr %ptr, i64 3
%idx1 = getelementptr inbounds <2 x float>, ptr %ptr, i64 4

%shuffle0 = shufflevector <4 x float> %v1, <4 x float> undef, <2 x i32> <i32 0, i32 1>
%shuffle1 = shufflevector <4 x float> %v1, <4 x float> undef, <2 x i32> <i32 2, i32 3>

store <2 x float> %shuffle0, <2 x float>* %idx0, align 8
store <2 x float> %shuffle1, <2 x float>* %idx1, align 8
store <2 x float> %shuffle0, ptr %idx0, align 8
store <2 x float> %shuffle1, ptr %idx1, align 8
ret void
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
Expand Down
72 changes: 36 additions & 36 deletions llvm/test/CodeGen/AArch64/multi-vector-load-size.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,103 +4,103 @@
%struct.__neon_float32x2x3_t = type { <2 x float>, <2 x float>, <2 x float> }
%struct.__neon_float32x2x4_t = type { <2 x float>, <2 x float>, <2 x float>, <2 x float> }

declare %struct.__neon_float32x2x2_t @llvm.aarch64.neon.ld2.v2f32.p0f32(float*)
declare %struct.__neon_float32x2x3_t @llvm.aarch64.neon.ld3.v2f32.p0f32(float*)
declare %struct.__neon_float32x2x4_t @llvm.aarch64.neon.ld4.v2f32.p0f32(float*)
declare %struct.__neon_float32x2x2_t @llvm.aarch64.neon.ld2.v2f32.p0(ptr)
declare %struct.__neon_float32x2x3_t @llvm.aarch64.neon.ld3.v2f32.p0(ptr)
declare %struct.__neon_float32x2x4_t @llvm.aarch64.neon.ld4.v2f32.p0(ptr)

declare %struct.__neon_float32x2x2_t @llvm.aarch64.neon.ld1x2.v2f32.p0f32(float*)
declare %struct.__neon_float32x2x3_t @llvm.aarch64.neon.ld1x3.v2f32.p0f32(float*)
declare %struct.__neon_float32x2x4_t @llvm.aarch64.neon.ld1x4.v2f32.p0f32(float*)
declare %struct.__neon_float32x2x2_t @llvm.aarch64.neon.ld1x2.v2f32.p0(ptr)
declare %struct.__neon_float32x2x3_t @llvm.aarch64.neon.ld1x3.v2f32.p0(ptr)
declare %struct.__neon_float32x2x4_t @llvm.aarch64.neon.ld1x4.v2f32.p0(ptr)

declare %struct.__neon_float32x2x2_t @llvm.aarch64.neon.ld2r.v2f32.p0f32(float*)
declare %struct.__neon_float32x2x3_t @llvm.aarch64.neon.ld3r.v2f32.p0f32(float*)
declare %struct.__neon_float32x2x4_t @llvm.aarch64.neon.ld4r.v2f32.p0f32(float*)
declare %struct.__neon_float32x2x2_t @llvm.aarch64.neon.ld2r.v2f32.p0(ptr)
declare %struct.__neon_float32x2x3_t @llvm.aarch64.neon.ld3r.v2f32.p0(ptr)
declare %struct.__neon_float32x2x4_t @llvm.aarch64.neon.ld4r.v2f32.p0(ptr)

declare %struct.__neon_float32x2x2_t @llvm.aarch64.neon.ld2lane.v2f32.p0f32(<2 x float>, <2 x float>, i64, float*)
declare %struct.__neon_float32x2x3_t @llvm.aarch64.neon.ld3lane.v2f32.p0f32(<2 x float>, <2 x float>, <2 x float>, i64, float*)
declare %struct.__neon_float32x2x4_t @llvm.aarch64.neon.ld4lane.v2f32.p0f32(<2 x float>, <2 x float>, <2 x float>, <2 x float>, i64, float*)
declare %struct.__neon_float32x2x2_t @llvm.aarch64.neon.ld2lane.v2f32.p0(<2 x float>, <2 x float>, i64, ptr)
declare %struct.__neon_float32x2x3_t @llvm.aarch64.neon.ld3lane.v2f32.p0(<2 x float>, <2 x float>, <2 x float>, i64, ptr)
declare %struct.__neon_float32x2x4_t @llvm.aarch64.neon.ld4lane.v2f32.p0(<2 x float>, <2 x float>, <2 x float>, <2 x float>, i64, ptr)


define %struct.__neon_float32x2x2_t @test_ld2(float* %addr) {
define %struct.__neon_float32x2x2_t @test_ld2(ptr %addr) {
; CHECK-LABEL: name: test_ld2
; CHECK: LD2Twov2s {{.*}} :: (load (s128) {{.*}})
%val = call %struct.__neon_float32x2x2_t @llvm.aarch64.neon.ld2.v2f32.p0f32(float* %addr)
%val = call %struct.__neon_float32x2x2_t @llvm.aarch64.neon.ld2.v2f32.p0(ptr %addr)
ret %struct.__neon_float32x2x2_t %val
}

define %struct.__neon_float32x2x3_t @test_ld3(float* %addr) {
define %struct.__neon_float32x2x3_t @test_ld3(ptr %addr) {
; CHECK-LABEL: name: test_ld3
; CHECK: LD3Threev2s {{.*}} :: (load (s192) {{.*}})
%val = call %struct.__neon_float32x2x3_t @llvm.aarch64.neon.ld3.v2f32.p0f32(float* %addr)
%val = call %struct.__neon_float32x2x3_t @llvm.aarch64.neon.ld3.v2f32.p0(ptr %addr)
ret %struct.__neon_float32x2x3_t %val
}

define %struct.__neon_float32x2x4_t @test_ld4(float* %addr) {
define %struct.__neon_float32x2x4_t @test_ld4(ptr %addr) {
; CHECK-LABEL: name: test_ld4
; CHECK: LD4Fourv2s {{.*}} :: (load (s256) {{.*}})
%val = call %struct.__neon_float32x2x4_t @llvm.aarch64.neon.ld4.v2f32.p0f32(float* %addr)
%val = call %struct.__neon_float32x2x4_t @llvm.aarch64.neon.ld4.v2f32.p0(ptr %addr)
ret %struct.__neon_float32x2x4_t %val
}

define %struct.__neon_float32x2x2_t @test_ld1x2(float* %addr) {
define %struct.__neon_float32x2x2_t @test_ld1x2(ptr %addr) {
; CHECK-LABEL: name: test_ld1x2
; CHECK: LD1Twov2s {{.*}} :: (load (s128) {{.*}})
%val = call %struct.__neon_float32x2x2_t @llvm.aarch64.neon.ld1x2.v2f32.p0f32(float* %addr)
%val = call %struct.__neon_float32x2x2_t @llvm.aarch64.neon.ld1x2.v2f32.p0(ptr %addr)
ret %struct.__neon_float32x2x2_t %val
}

define %struct.__neon_float32x2x3_t @test_ld1x3(float* %addr) {
define %struct.__neon_float32x2x3_t @test_ld1x3(ptr %addr) {
; CHECK-LABEL: name: test_ld1x3
; CHECK: LD1Threev2s {{.*}} :: (load (s192) {{.*}})
%val = call %struct.__neon_float32x2x3_t @llvm.aarch64.neon.ld1x3.v2f32.p0f32(float* %addr)
%val = call %struct.__neon_float32x2x3_t @llvm.aarch64.neon.ld1x3.v2f32.p0(ptr %addr)
ret %struct.__neon_float32x2x3_t %val
}

define %struct.__neon_float32x2x4_t @test_ld1x4(float* %addr) {
define %struct.__neon_float32x2x4_t @test_ld1x4(ptr %addr) {
; CHECK-LABEL: name: test_ld1x4
; CHECK: LD1Fourv2s {{.*}} :: (load (s256) {{.*}})
%val = call %struct.__neon_float32x2x4_t @llvm.aarch64.neon.ld1x4.v2f32.p0f32(float* %addr)
%val = call %struct.__neon_float32x2x4_t @llvm.aarch64.neon.ld1x4.v2f32.p0(ptr %addr)
ret %struct.__neon_float32x2x4_t %val
}

define %struct.__neon_float32x2x2_t @test_ld2r(float* %addr) {
define %struct.__neon_float32x2x2_t @test_ld2r(ptr %addr) {
; CHECK-LABEL: name: test_ld2r
; CHECK: LD2Rv2s {{.*}} :: (load (s64) {{.*}})
%val = call %struct.__neon_float32x2x2_t @llvm.aarch64.neon.ld2r.v2f32.p0f32(float* %addr)
%val = call %struct.__neon_float32x2x2_t @llvm.aarch64.neon.ld2r.v2f32.p0(ptr %addr)
ret %struct.__neon_float32x2x2_t %val
}

define %struct.__neon_float32x2x3_t @test_ld3r(float* %addr) {
define %struct.__neon_float32x2x3_t @test_ld3r(ptr %addr) {
; CHECK-LABEL: name: test_ld3r
; CHECK: LD3Rv2s {{.*}} :: (load (s96) {{.*}})
%val = call %struct.__neon_float32x2x3_t @llvm.aarch64.neon.ld3r.v2f32.p0f32(float* %addr)
%val = call %struct.__neon_float32x2x3_t @llvm.aarch64.neon.ld3r.v2f32.p0(ptr %addr)
ret %struct.__neon_float32x2x3_t %val
}

define %struct.__neon_float32x2x4_t @test_ld4r(float* %addr) {
define %struct.__neon_float32x2x4_t @test_ld4r(ptr %addr) {
; CHECK-LABEL: name: test_ld4r
; CHECK: LD4Rv2s {{.*}} :: (load (s128) {{.*}})
%val = call %struct.__neon_float32x2x4_t @llvm.aarch64.neon.ld4r.v2f32.p0f32(float* %addr)
%val = call %struct.__neon_float32x2x4_t @llvm.aarch64.neon.ld4r.v2f32.p0(ptr %addr)
ret %struct.__neon_float32x2x4_t %val
}

define %struct.__neon_float32x2x2_t @test_ld2lane(<2 x float> %a, <2 x float> %b, float* %addr) {
define %struct.__neon_float32x2x2_t @test_ld2lane(<2 x float> %a, <2 x float> %b, ptr %addr) {
; CHECK-LABEL: name: test_ld2lane
; CHECK: {{.*}} LD2i32 {{.*}}
%val = call %struct.__neon_float32x2x2_t @llvm.aarch64.neon.ld2lane.v2f32.p0f32(<2 x float> %a, <2 x float> %b, i64 1, float* %addr)
%val = call %struct.__neon_float32x2x2_t @llvm.aarch64.neon.ld2lane.v2f32.p0(<2 x float> %a, <2 x float> %b, i64 1, ptr %addr)
ret %struct.__neon_float32x2x2_t %val
}

define %struct.__neon_float32x2x3_t @test_ld3lane(<2 x float> %a, <2 x float> %b, <2 x float> %c, float* %addr) {
define %struct.__neon_float32x2x3_t @test_ld3lane(<2 x float> %a, <2 x float> %b, <2 x float> %c, ptr %addr) {
; CHECK-LABEL: name: test_ld3lane
; CHECK: {{.*}} LD3i32 {{.*}}
%val = call %struct.__neon_float32x2x3_t @llvm.aarch64.neon.ld3lane.v2f32.p0f32(<2 x float> %a, <2 x float> %b, <2 x float> %c, i64 1, float* %addr)
%val = call %struct.__neon_float32x2x3_t @llvm.aarch64.neon.ld3lane.v2f32.p0(<2 x float> %a, <2 x float> %b, <2 x float> %c, i64 1, ptr %addr)
ret %struct.__neon_float32x2x3_t %val
}

define %struct.__neon_float32x2x4_t @test_ld4lane(<2 x float> %a, <2 x float> %b, <2 x float> %c, <2 x float> %d, float* %addr) {
define %struct.__neon_float32x2x4_t @test_ld4lane(<2 x float> %a, <2 x float> %b, <2 x float> %c, <2 x float> %d, ptr %addr) {
; CHECK-LABEL: name: test_ld4lane
; CHECK: {{.*}} LD4i32 {{.*}}
%val = call %struct.__neon_float32x2x4_t @llvm.aarch64.neon.ld4lane.v2f32.p0f32(<2 x float> %a, <2 x float> %b, <2 x float> %c, <2 x float> %d, i64 1, float* %addr)
%val = call %struct.__neon_float32x2x4_t @llvm.aarch64.neon.ld4lane.v2f32.p0(<2 x float> %a, <2 x float> %b, <2 x float> %c, <2 x float> %d, i64 1, ptr %addr)
ret %struct.__neon_float32x2x4_t %val
}
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AArch64/nontemporal-load.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -624,7 +624,7 @@ define <16 x double> @test_ldnp_v16f64(ptr %A) {
ret <16 x double> %lv
}

define <vscale x 20 x float> @test_ldnp_v20f32_vscale(<vscale x 20 x float>* %A) {
define <vscale x 20 x float> @test_ldnp_v20f32_vscale(ptr %A) {
; CHECK-LABEL: test_ldnp_v20f32_vscale:
; CHECK: ; %bb.0:
; CHECK-NEXT: ptrue p0.s
Expand All @@ -644,7 +644,7 @@ define <vscale x 20 x float> @test_ldnp_v20f32_vscale(<vscale x 20 x float>* %A)
; CHECK-BE-NEXT: ld1w { z3.s }, p0/z, [x0, #3, mul vl]
; CHECK-BE-NEXT: ld1w { z4.s }, p0/z, [x0, #4, mul vl]
; CHECK-BE-NEXT: ret
%lv = load<vscale x 20 x float>, <vscale x 20 x float>* %A, align 8, !nontemporal !0
%lv = load<vscale x 20 x float>, ptr %A, align 8, !nontemporal !0
ret <vscale x 20 x float> %lv
}

Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/AArch64/pre-indexed-addrmode-with-constant-offset.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@
; Reduced test from https://github.com/llvm/llvm-project/issues/60645.
; To check that we are generating -32 as offset for the first store.

define i8* @pr60645(i8* %ptr, i64 %t0) {
define ptr @pr60645(ptr %ptr, i64 %t0) {
; CHECK-LABEL: pr60645:
; CHECK: // %bb.0:
; CHECK-NEXT: sub x8, x0, x1, lsl #2
Expand All @@ -12,13 +12,13 @@ define i8* @pr60645(i8* %ptr, i64 %t0) {
; CHECK-NEXT: ret
%t1 = add nuw nsw i64 %t0, 8
%t2 = mul i64 %t1, -4
%t3 = getelementptr i8, i8* %ptr, i64 %t2
%t4 = bitcast i8* %t3 to i32*
store i32 0, i32* %t4, align 4
%t3 = getelementptr i8, ptr %ptr, i64 %t2
%t4 = bitcast ptr %t3 to ptr
store i32 0, ptr %t4, align 4
%t5 = shl i64 %t1, 2
%t6 = sub nuw nsw i64 -8, %t5
%t7 = getelementptr i8, i8* %ptr, i64 %t6
%t8 = bitcast i8* %t7 to i32*
store i32 0, i32* %t8, align 4
ret i8* %ptr
%t7 = getelementptr i8, ptr %ptr, i64 %t6
%t8 = bitcast ptr %t7 to ptr
store i32 0, ptr %t8, align 4
ret ptr %ptr
}
92 changes: 46 additions & 46 deletions llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -273,14 +273,14 @@ for.cond1.preheader: ; preds = %for.cond1.preheader
%28 = phi <2 x i64> [ undef, %entry ], [ %41, %for.cond1.preheader ]
%29 = phi <2 x i64> [ undef, %entry ], [ %39, %for.cond1.preheader ]
%indvars.iv40 = phi i64 [ 0, %entry ], [ %indvars.iv.next41, %for.cond1.preheader ]
%30 = load <2 x i64>, <2 x i64>* null, align 8
%31 = load <2 x i64>, <2 x i64>* undef, align 8
%arrayidx14.4.phi.trans.insert = getelementptr inbounds [8 x [8 x i64]], [8 x [8 x i64]]* @B, i64 0, i64 %indvars.iv40, i64 4
%32 = load <2 x i64>, <2 x i64>* null, align 8
%arrayidx14.6.phi.trans.insert = getelementptr inbounds [8 x [8 x i64]], [8 x [8 x i64]]* @B, i64 0, i64 %indvars.iv40, i64 6
%33 = bitcast i64* %arrayidx14.6.phi.trans.insert to <2 x i64>*
%34 = load <2 x i64>, <2 x i64>* %33, align 8
%35 = load i64, i64* null, align 8
%30 = load <2 x i64>, ptr null, align 8
%31 = load <2 x i64>, ptr undef, align 8
%arrayidx14.4.phi.trans.insert = getelementptr inbounds [8 x [8 x i64]], ptr @B, i64 0, i64 %indvars.iv40, i64 4
%32 = load <2 x i64>, ptr null, align 8
%arrayidx14.6.phi.trans.insert = getelementptr inbounds [8 x [8 x i64]], ptr @B, i64 0, i64 %indvars.iv40, i64 6
%33 = bitcast ptr %arrayidx14.6.phi.trans.insert to ptr
%34 = load <2 x i64>, ptr %33, align 8
%35 = load i64, ptr null, align 8
%36 = insertelement <2 x i64> undef, i64 %35, i32 0
%37 = shufflevector <2 x i64> %36, <2 x i64> undef, <2 x i32> zeroinitializer
%38 = mul nsw <2 x i64> %30, %37
Expand All @@ -291,7 +291,7 @@ for.cond1.preheader: ; preds = %for.cond1.preheader
%43 = add nsw <2 x i64> %27, %42
%44 = mul nsw <2 x i64> %34, %37
%45 = add nsw <2 x i64> %26, %44
%46 = load i64, i64* undef, align 8
%46 = load i64, ptr undef, align 8
%47 = insertelement <2 x i64> undef, i64 %46, i32 0
%48 = shufflevector <2 x i64> %47, <2 x i64> undef, <2 x i32> zeroinitializer
%49 = mul nsw <2 x i64> %30, %48
Expand All @@ -302,8 +302,8 @@ for.cond1.preheader: ; preds = %for.cond1.preheader
%54 = add nsw <2 x i64> %23, %53
%55 = mul nsw <2 x i64> %34, %48
%56 = add nsw <2 x i64> %22, %55
%arrayidx10.2 = getelementptr inbounds [8 x [8 x i64]], [8 x [8 x i64]]* @A, i64 0, i64 2, i64 %indvars.iv40
%57 = load i64, i64* %arrayidx10.2, align 8
%arrayidx10.2 = getelementptr inbounds [8 x [8 x i64]], ptr @A, i64 0, i64 2, i64 %indvars.iv40
%57 = load i64, ptr %arrayidx10.2, align 8
%58 = insertelement <2 x i64> undef, i64 %57, i32 0
%59 = shufflevector <2 x i64> %58, <2 x i64> undef, <2 x i32> zeroinitializer
%60 = mul nsw <2 x i64> %31, %59
Expand All @@ -312,7 +312,7 @@ for.cond1.preheader: ; preds = %for.cond1.preheader
%63 = add nsw <2 x i64> %20, %62
%64 = mul nsw <2 x i64> %34, %59
%65 = add nsw <2 x i64> %19, %64
%66 = load i64, i64* undef, align 8
%66 = load i64, ptr undef, align 8
%67 = insertelement <2 x i64> undef, i64 %66, i32 0
%68 = shufflevector <2 x i64> %67, <2 x i64> undef, <2 x i32> zeroinitializer
%69 = mul nsw <2 x i64> %30, %68
Expand All @@ -321,7 +321,7 @@ for.cond1.preheader: ; preds = %for.cond1.preheader
%72 = add nsw <2 x i64> %17, %71
%73 = mul nsw <2 x i64> %34, %68
%74 = add nsw <2 x i64> %16, %73
%75 = load i64, i64* undef, align 8
%75 = load i64, ptr undef, align 8
%76 = insertelement <2 x i64> undef, i64 %75, i32 0
%77 = shufflevector <2 x i64> %76, <2 x i64> undef, <2 x i32> zeroinitializer
%78 = mul nsw <2 x i64> %30, %77
Expand All @@ -332,7 +332,7 @@ for.cond1.preheader: ; preds = %for.cond1.preheader
%83 = add nsw <2 x i64> %13, %82
%84 = mul nsw <2 x i64> %34, %77
%85 = add nsw <2 x i64> %12, %84
%86 = load i64, i64* undef, align 8
%86 = load i64, ptr undef, align 8
%87 = insertelement <2 x i64> undef, i64 %86, i32 0
%88 = shufflevector <2 x i64> %87, <2 x i64> undef, <2 x i32> zeroinitializer
%89 = mul nsw <2 x i64> %30, %88
Expand All @@ -343,7 +343,7 @@ for.cond1.preheader: ; preds = %for.cond1.preheader
%94 = add nsw <2 x i64> %9, %93
%95 = mul nsw <2 x i64> %34, %88
%96 = add nsw <2 x i64> %8, %95
%97 = load i64, i64* undef, align 8
%97 = load i64, ptr undef, align 8
%98 = insertelement <2 x i64> undef, i64 %97, i32 0
%99 = shufflevector <2 x i64> %98, <2 x i64> undef, <2 x i32> zeroinitializer
%100 = mul nsw <2 x i64> %30, %99
Expand All @@ -354,7 +354,7 @@ for.cond1.preheader: ; preds = %for.cond1.preheader
%105 = add nsw <2 x i64> %5, %104
%106 = mul nsw <2 x i64> %34, %99
%107 = add nsw <2 x i64> %4, %106
%108 = load i64, i64* undef, align 8
%108 = load i64, ptr undef, align 8
%109 = insertelement <2 x i64> undef, i64 %108, i32 0
%110 = shufflevector <2 x i64> %109, <2 x i64> undef, <2 x i32> zeroinitializer
%111 = mul nsw <2 x i64> %30, %110
Expand All @@ -370,35 +370,35 @@ for.cond1.preheader: ; preds = %for.cond1.preheader
br i1 %exitcond42, label %for.cond.cleanup, label %for.cond1.preheader

for.cond.cleanup: ; preds = %for.cond1.preheader
store <2 x i64> %39, <2 x i64>* bitcast ([8 x [8 x i64]]* @C to <2 x i64>*), align 8
store <2 x i64> %41, <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x [8 x i64]], [8 x [8 x i64]]* @C, i64 0, i64 0, i64 2) to <2 x i64>*), align 8
store <2 x i64> %43, <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x [8 x i64]], [8 x [8 x i64]]* @C, i64 0, i64 0, i64 4) to <2 x i64>*), align 8
store <2 x i64> %45, <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x [8 x i64]], [8 x [8 x i64]]* @C, i64 0, i64 0, i64 6) to <2 x i64>*), align 8
store <2 x i64> %50, <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x [8 x i64]], [8 x [8 x i64]]* @C, i64 0, i64 1, i64 0) to <2 x i64>*), align 8
store <2 x i64> %52, <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x [8 x i64]], [8 x [8 x i64]]* @C, i64 0, i64 1, i64 2) to <2 x i64>*), align 8
store <2 x i64> %54, <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x [8 x i64]], [8 x [8 x i64]]* @C, i64 0, i64 1, i64 4) to <2 x i64>*), align 8
store <2 x i64> %56, <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x [8 x i64]], [8 x [8 x i64]]* @C, i64 0, i64 1, i64 6) to <2 x i64>*), align 8
store <2 x i64> %61, <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x [8 x i64]], [8 x [8 x i64]]* @C, i64 0, i64 2, i64 2) to <2 x i64>*), align 8
store <2 x i64> %63, <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x [8 x i64]], [8 x [8 x i64]]* @C, i64 0, i64 2, i64 4) to <2 x i64>*), align 8
store <2 x i64> %65, <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x [8 x i64]], [8 x [8 x i64]]* @C, i64 0, i64 2, i64 6) to <2 x i64>*), align 8
store <2 x i64> %70, <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x [8 x i64]], [8 x [8 x i64]]* @C, i64 0, i64 3, i64 0) to <2 x i64>*), align 8
store <2 x i64> %72, <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x [8 x i64]], [8 x [8 x i64]]* @C, i64 0, i64 3, i64 2) to <2 x i64>*), align 8
store <2 x i64> %74, <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x [8 x i64]], [8 x [8 x i64]]* @C, i64 0, i64 3, i64 6) to <2 x i64>*), align 8
store <2 x i64> %79, <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x [8 x i64]], [8 x [8 x i64]]* @C, i64 0, i64 4, i64 0) to <2 x i64>*), align 8
store <2 x i64> %81, <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x [8 x i64]], [8 x [8 x i64]]* @C, i64 0, i64 4, i64 2) to <2 x i64>*), align 8
store <2 x i64> %83, <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x [8 x i64]], [8 x [8 x i64]]* @C, i64 0, i64 4, i64 4) to <2 x i64>*), align 8
store <2 x i64> %85, <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x [8 x i64]], [8 x [8 x i64]]* @C, i64 0, i64 4, i64 6) to <2 x i64>*), align 8
store <2 x i64> %90, <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x [8 x i64]], [8 x [8 x i64]]* @C, i64 0, i64 5, i64 0) to <2 x i64>*), align 8
store <2 x i64> %92, <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x [8 x i64]], [8 x [8 x i64]]* @C, i64 0, i64 5, i64 2) to <2 x i64>*), align 8
store <2 x i64> %94, <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x [8 x i64]], [8 x [8 x i64]]* @C, i64 0, i64 5, i64 4) to <2 x i64>*), align 8
store <2 x i64> %96, <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x [8 x i64]], [8 x [8 x i64]]* @C, i64 0, i64 5, i64 6) to <2 x i64>*), align 8
store <2 x i64> %101, <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x [8 x i64]], [8 x [8 x i64]]* @C, i64 0, i64 6, i64 0) to <2 x i64>*), align 8
store <2 x i64> %103, <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x [8 x i64]], [8 x [8 x i64]]* @C, i64 0, i64 6, i64 2) to <2 x i64>*), align 8
store <2 x i64> %105, <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x [8 x i64]], [8 x [8 x i64]]* @C, i64 0, i64 6, i64 4) to <2 x i64>*), align 8
store <2 x i64> %107, <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x [8 x i64]], [8 x [8 x i64]]* @C, i64 0, i64 6, i64 6) to <2 x i64>*), align 8
store <2 x i64> %112, <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x [8 x i64]], [8 x [8 x i64]]* @C, i64 0, i64 7, i64 0) to <2 x i64>*), align 8
store <2 x i64> %114, <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x [8 x i64]], [8 x [8 x i64]]* @C, i64 0, i64 7, i64 2) to <2 x i64>*), align 8
store <2 x i64> %116, <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x [8 x i64]], [8 x [8 x i64]]* @C, i64 0, i64 7, i64 4) to <2 x i64>*), align 8
store <2 x i64> %118, <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x [8 x i64]], [8 x [8 x i64]]* @C, i64 0, i64 7, i64 6) to <2 x i64>*), align 8
store <2 x i64> %39, ptr @C, align 8
store <2 x i64> %41, ptr getelementptr inbounds ([8 x [8 x i64]], ptr @C, i64 0, i64 0, i64 2), align 8
store <2 x i64> %43, ptr getelementptr inbounds ([8 x [8 x i64]], ptr @C, i64 0, i64 0, i64 4), align 8
store <2 x i64> %45, ptr getelementptr inbounds ([8 x [8 x i64]], ptr @C, i64 0, i64 0, i64 6), align 8
store <2 x i64> %50, ptr getelementptr inbounds ([8 x [8 x i64]], ptr @C, i64 0, i64 1, i64 0), align 8
store <2 x i64> %52, ptr getelementptr inbounds ([8 x [8 x i64]], ptr @C, i64 0, i64 1, i64 2), align 8
store <2 x i64> %54, ptr getelementptr inbounds ([8 x [8 x i64]], ptr @C, i64 0, i64 1, i64 4), align 8
store <2 x i64> %56, ptr getelementptr inbounds ([8 x [8 x i64]], ptr @C, i64 0, i64 1, i64 6), align 8
store <2 x i64> %61, ptr getelementptr inbounds ([8 x [8 x i64]], ptr @C, i64 0, i64 2, i64 2), align 8
store <2 x i64> %63, ptr getelementptr inbounds ([8 x [8 x i64]], ptr @C, i64 0, i64 2, i64 4), align 8
store <2 x i64> %65, ptr getelementptr inbounds ([8 x [8 x i64]], ptr @C, i64 0, i64 2, i64 6), align 8
store <2 x i64> %70, ptr getelementptr inbounds ([8 x [8 x i64]], ptr @C, i64 0, i64 3, i64 0), align 8
store <2 x i64> %72, ptr getelementptr inbounds ([8 x [8 x i64]], ptr @C, i64 0, i64 3, i64 2), align 8
store <2 x i64> %74, ptr getelementptr inbounds ([8 x [8 x i64]], ptr @C, i64 0, i64 3, i64 6), align 8
store <2 x i64> %79, ptr getelementptr inbounds ([8 x [8 x i64]], ptr @C, i64 0, i64 4, i64 0), align 8
store <2 x i64> %81, ptr getelementptr inbounds ([8 x [8 x i64]], ptr @C, i64 0, i64 4, i64 2), align 8
store <2 x i64> %83, ptr getelementptr inbounds ([8 x [8 x i64]], ptr @C, i64 0, i64 4, i64 4), align 8
store <2 x i64> %85, ptr getelementptr inbounds ([8 x [8 x i64]], ptr @C, i64 0, i64 4, i64 6), align 8
store <2 x i64> %90, ptr getelementptr inbounds ([8 x [8 x i64]], ptr @C, i64 0, i64 5, i64 0), align 8
store <2 x i64> %92, ptr getelementptr inbounds ([8 x [8 x i64]], ptr @C, i64 0, i64 5, i64 2), align 8
store <2 x i64> %94, ptr getelementptr inbounds ([8 x [8 x i64]], ptr @C, i64 0, i64 5, i64 4), align 8
store <2 x i64> %96, ptr getelementptr inbounds ([8 x [8 x i64]], ptr @C, i64 0, i64 5, i64 6), align 8
store <2 x i64> %101, ptr getelementptr inbounds ([8 x [8 x i64]], ptr @C, i64 0, i64 6, i64 0), align 8
store <2 x i64> %103, ptr getelementptr inbounds ([8 x [8 x i64]], ptr @C, i64 0, i64 6, i64 2), align 8
store <2 x i64> %105, ptr getelementptr inbounds ([8 x [8 x i64]], ptr @C, i64 0, i64 6, i64 4), align 8
store <2 x i64> %107, ptr getelementptr inbounds ([8 x [8 x i64]], ptr @C, i64 0, i64 6, i64 6), align 8
store <2 x i64> %112, ptr getelementptr inbounds ([8 x [8 x i64]], ptr @C, i64 0, i64 7, i64 0), align 8
store <2 x i64> %114, ptr getelementptr inbounds ([8 x [8 x i64]], ptr @C, i64 0, i64 7, i64 2), align 8
store <2 x i64> %116, ptr getelementptr inbounds ([8 x [8 x i64]], ptr @C, i64 0, i64 7, i64 4), align 8
store <2 x i64> %118, ptr getelementptr inbounds ([8 x [8 x i64]], ptr @C, i64 0, i64 7, i64 6), align 8
ret void
}
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AArch64/rvmarker-pseudo-expansion-and-outlining.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -41,7 +41,7 @@

declare void @cb2()

declare i8* @attachedcall()
declare ptr @attachedcall()
...
---
name: fn1
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/AArch64/sched-movprfx.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@


; NOTE: The unused paramter ensures z0/z1 is free, avoiding the antidependence for schedule.
define <vscale x 2 x i64> @and_i64_zero(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, <vscale x 2 x i64>* %base) {
define <vscale x 2 x i64> @and_i64_zero(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, ptr %base) {
; CHECK-LABEL: and_i64_zero:
; CHECK: // %bb.0:
; CHECK-NEXT: ld1d { z1.d }, p0/z, [x0]
Expand All @@ -17,7 +17,7 @@ define <vscale x 2 x i64> @and_i64_zero(<vscale x 2 x i1> %pg, <vscale x 2 x i64
; CHECK-NEXT: add z0.d, z0.d, z1.d
; CHECK-NEXT: ret
%data0 = tail call <vscale x 2 x i64> @llvm.abs.nxv2i64(<vscale x 2 x i64> %c, i1 0)
%data1 = call <vscale x 2 x i64> @llvm.masked.load.nxv2i64(<vscale x 2 x i64>* %base,
%data1 = call <vscale x 2 x i64> @llvm.masked.load.nxv2i64(ptr %base,
i32 1,
<vscale x 2 x i1> %pg,
<vscale x 2 x i64> undef)
Expand All @@ -26,4 +26,4 @@ define <vscale x 2 x i64> @and_i64_zero(<vscale x 2 x i1> %pg, <vscale x 2 x i64
}

declare <vscale x 2 x i64> @llvm.abs.nxv2i64(<vscale x 2 x i64>, i1)
declare <vscale x 2 x i64> @llvm.masked.load.nxv2i64(<vscale x 2 x i64>*, i32, <vscale x 2 x i1>, <vscale x 2 x i64>)
declare <vscale x 2 x i64> @llvm.masked.load.nxv2i64(ptr, i32, <vscale x 2 x i1>, <vscale x 2 x i64>)
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/AArch64/settag-merge.mir
View file
Original file line number Diff line number Diff line change
@@ -1,27 +1,27 @@
# RUN: llc -mtriple=aarch64 -mattr=+mte -run-pass=prologepilog %s -o - | FileCheck %s

--- |
declare void @llvm.aarch64.settag(i8* nocapture writeonly, i64) argmemonly nounwind writeonly "target-features"="+mte"
declare void @llvm.aarch64.settag(ptr nocapture writeonly, i64) argmemonly nounwind writeonly "target-features"="+mte"
define i32 @stg16_16_16_16_ret() "target-features"="+mte" {
entry:
%a = alloca i8, i32 16, align 16
%b = alloca i8, i32 16, align 16
%c = alloca i8, i32 16, align 16
%d = alloca i8, i32 16, align 16
call void @llvm.aarch64.settag(i8* %a, i64 16)
call void @llvm.aarch64.settag(i8* %b, i64 16)
call void @llvm.aarch64.settag(i8* %c, i64 16)
call void @llvm.aarch64.settag(i8* %d, i64 16)
call void @llvm.aarch64.settag(ptr %a, i64 16)
call void @llvm.aarch64.settag(ptr %b, i64 16)
call void @llvm.aarch64.settag(ptr %c, i64 16)
call void @llvm.aarch64.settag(ptr %d, i64 16)
ret i32 0
}

define void @stg16_store_128() "target-features"="+mte" {
entry:
%a = alloca i8, i32 16, align 16
%b = alloca i8, i32 128, align 16
call void @llvm.aarch64.settag(i8* %a, i64 16)
store i8 42, i8* %a
call void @llvm.aarch64.settag(i8* %b, i64 128)
call void @llvm.aarch64.settag(ptr %a, i64 16)
store i8 42, ptr %a
call void @llvm.aarch64.settag(ptr %b, i64 128)
ret void
}

Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AArch64/sme-intrinsics-mova-extract.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -166,7 +166,7 @@ define <vscale x 8 x half> @extract_f16(<vscale x 8 x half> %zd, <vscale x 8 x i
ret <vscale x 8 x half> %z0
}

define <vscale x 8 x bfloat> @extract_bf16(<vscale x 8 x bfloat> %zd, <vscale x 8 x i1> %pg, i32 %tileslice, <vscale x 8 x bfloat> *%ptr) {
define <vscale x 8 x bfloat> @extract_bf16(<vscale x 8 x bfloat> %zd, <vscale x 8 x i1> %pg, i32 %tileslice, ptr %ptr) {
; CHECK-LABEL: extract_bf16:
; CHECK: // %bb.0:
; CHECK-NEXT: mov z1.d, z0.d
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/AArch64/speculation-hardening-sls.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10,10 +10,10 @@
# Check that the SLS hardening pass also protects BRA* indirect branches that
# llvm currently does not generate.
--- |
@ptr_aa = private unnamed_addr constant [2 x i8*] [i8* blockaddress(@br_aa, %return), i8* blockaddress(@br_aa, %l2)], align 8
@ptr_aaz = private unnamed_addr constant [2 x i8*] [i8* blockaddress(@br_aaz, %return), i8* blockaddress(@br_aaz, %l2)], align 8
@ptr_ab = private unnamed_addr constant [2 x i8*] [i8* blockaddress(@br_ab, %return), i8* blockaddress(@br_ab, %l2)], align 8
@ptr_abz = private unnamed_addr constant [2 x i8*] [i8* blockaddress(@br_abz, %return), i8* blockaddress(@br_abz, %l2)], align 8
@ptr_aa = private unnamed_addr constant [2 x ptr] [ptr blockaddress(@br_aa, %return), ptr blockaddress(@br_aa, %l2)], align 8
@ptr_aaz = private unnamed_addr constant [2 x ptr] [ptr blockaddress(@br_aaz, %return), ptr blockaddress(@br_aaz, %l2)], align 8
@ptr_ab = private unnamed_addr constant [2 x ptr] [ptr blockaddress(@br_ab, %return), ptr blockaddress(@br_ab, %l2)], align 8
@ptr_abz = private unnamed_addr constant [2 x ptr] [ptr blockaddress(@br_abz, %return), ptr blockaddress(@br_abz, %l2)], align 8

define dso_local i32 @br_aa(i32 %a, i32 %b, i32 %i) {
entry:
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AArch64/speculation-hardening.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -31,7 +31,7 @@
define void @indirect_call_x17(i32 %a, i32 %b) speculative_load_hardening {
ret void
}
@g = common dso_local local_unnamed_addr global i64 (...)* null, align 8
@g = common dso_local local_unnamed_addr global ptr null, align 8
define void @indirect_tailcall_x17(i32 %a, i32 %b) speculative_load_hardening {
ret void
}
Expand Down
144 changes: 72 additions & 72 deletions llvm/test/CodeGen/AArch64/spillfill-sve.ll
View file

Large diffs are not rendered by default.

6 changes: 3 additions & 3 deletions llvm/test/CodeGen/AArch64/stack-guard-reassign-sve.mir
View file
Original file line number Diff line number Diff line change
@@ -1,9 +1,9 @@
# RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve -start-before=localstackalloc -stop-after=prologepilog -o - %s | FileCheck %s

--- |
@__stack_chk_guard = external global i8*
define i32 @main(i32, i8**) {
%StackGuardSlot = alloca i8*
@__stack_chk_guard = external global ptr
define i32 @main(i32, ptr) {
%StackGuardSlot = alloca ptr
unreachable
}
...
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/AArch64/stack-guard-reassign.mir
View file
Original file line number Diff line number Diff line change
@@ -1,9 +1,9 @@
# RUN: llc -mtriple=arm64-apple-ios -start-before=localstackalloc -stop-after=prologepilog -o - %s | FileCheck %s

--- |
@__stack_chk_guard = external global i8*
define i32 @main(i32, i8**) {
%StackGuardSlot = alloca i8*
@__stack_chk_guard = external global ptr
define i32 @main(i32, ptr) {
%StackGuardSlot = alloca ptr
unreachable
}
...
Expand Down
122 changes: 61 additions & 61 deletions llvm/test/CodeGen/AArch64/stack-guard-sve.ll
View file
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve < %s | FileCheck %s

declare dso_local void @val_fn(<vscale x 4 x float>)
declare dso_local void @ptr_fn(<vscale x 4 x float>*)
declare dso_local void @ptr_fn(ptr)

; An alloca of a scalable vector shouldn't trigger stack protection.

Expand All @@ -13,8 +13,8 @@ declare dso_local void @ptr_fn(<vscale x 4 x float>*)
define void @call_value() #0 {
entry:
%x = alloca <vscale x 4 x float>, align 16
store <vscale x 4 x float> zeroinitializer, <vscale x 4 x float>* %x, align 16
%0 = load <vscale x 4 x float>, <vscale x 4 x float>* %x, align 16
store <vscale x 4 x float> zeroinitializer, ptr %x, align 16
%0 = load <vscale x 4 x float>, ptr %x, align 16
call void @val_fn(<vscale x 4 x float> %0)
ret void
}
Expand All @@ -27,8 +27,8 @@ entry:
define void @call_value_strong() #1 {
entry:
%x = alloca <vscale x 4 x float>, align 16
store <vscale x 4 x float> zeroinitializer, <vscale x 4 x float>* %x, align 16
%0 = load <vscale x 4 x float>, <vscale x 4 x float>* %x, align 16
store <vscale x 4 x float> zeroinitializer, ptr %x, align 16
%0 = load <vscale x 4 x float>, ptr %x, align 16
call void @val_fn(<vscale x 4 x float> %0)
ret void
}
Expand All @@ -45,7 +45,7 @@ entry:
define void @call_ptr() #0 {
entry:
%x = alloca <vscale x 4 x float>, align 16
call void @ptr_fn(<vscale x 4 x float>* %x)
call void @ptr_fn(ptr %x)
ret void
}

Expand All @@ -60,7 +60,7 @@ entry:
define void @call_ptr_strong() #1 {
entry:
%x = alloca <vscale x 4 x float>, align 16
call void @ptr_fn(<vscale x 4 x float>* %x)
call void @ptr_fn(ptr %x)
ret void
}

Expand All @@ -78,10 +78,10 @@ define void @call_both() #0 {
entry:
%x = alloca <vscale x 4 x float>, align 16
%y = alloca <vscale x 4 x float>, align 16
store <vscale x 4 x float> zeroinitializer, <vscale x 4 x float>* %x, align 16
%0 = load <vscale x 4 x float>, <vscale x 4 x float>* %x, align 16
store <vscale x 4 x float> zeroinitializer, ptr %x, align 16
%0 = load <vscale x 4 x float>, ptr %x, align 16
call void @val_fn(<vscale x 4 x float> %0)
call void @ptr_fn(<vscale x 4 x float>* %y)
call void @ptr_fn(ptr %y)
ret void
}

Expand All @@ -99,10 +99,10 @@ define void @call_both_strong() #1 {
entry:
%x = alloca <vscale x 4 x float>, align 16
%y = alloca <vscale x 4 x float>, align 16
store <vscale x 4 x float> zeroinitializer, <vscale x 4 x float>* %x, align 16
%0 = load <vscale x 4 x float>, <vscale x 4 x float>* %x, align 16
store <vscale x 4 x float> zeroinitializer, ptr %x, align 16
%0 = load <vscale x 4 x float>, ptr %x, align 16
call void @val_fn(<vscale x 4 x float> %0)
call void @ptr_fn(<vscale x 4 x float>* %y)
call void @ptr_fn(ptr %y)
ret void
}

Expand All @@ -120,8 +120,8 @@ entry:
define void @callee_save(<vscale x 4 x float> %x) #0 {
entry:
%x.addr = alloca <vscale x 4 x float>, align 16
store <vscale x 4 x float> %x, <vscale x 4 x float>* %x.addr, align 16
call void @ptr_fn(<vscale x 4 x float>* %x.addr)
store <vscale x 4 x float> %x, ptr %x.addr, align 16
call void @ptr_fn(ptr %x.addr)
ret void
}

Expand All @@ -138,8 +138,8 @@ entry:
define void @callee_save_strong(<vscale x 4 x float> %x) #1 {
entry:
%x.addr = alloca <vscale x 4 x float>, align 16
store <vscale x 4 x float> %x, <vscale x 4 x float>* %x.addr, align 16
call void @ptr_fn(<vscale x 4 x float>* %x.addr)
store <vscale x 4 x float> %x, ptr %x.addr, align 16
call void @ptr_fn(ptr %x.addr)
ret void
}

Expand Down Expand Up @@ -177,22 +177,22 @@ entry:
define void @local_stack_alloc(i64 %val) #0 {
entry:
%char_arr = alloca [8 x i8], align 4
%gep0 = getelementptr [8 x i8], [8 x i8]* %char_arr, i64 0, i64 0
store i8 0, i8* %gep0, align 8
%gep0 = getelementptr [8 x i8], ptr %char_arr, i64 0, i64 0
store i8 0, ptr %gep0, align 8
%large1 = alloca [4096 x i64], align 8
%large2 = alloca [4096 x i64], align 8
%vec_1 = alloca <vscale x 4 x float>, align 16
%vec_2 = alloca <vscale x 4 x float>, align 16
%gep1 = getelementptr [4096 x i64], [4096 x i64]* %large1, i64 0, i64 0
%gep2 = getelementptr [4096 x i64], [4096 x i64]* %large1, i64 0, i64 1
store i64 %val, i64* %gep1, align 8
store i64 %val, i64* %gep2, align 8
%gep3 = getelementptr [4096 x i64], [4096 x i64]* %large2, i64 0, i64 0
%gep4 = getelementptr [4096 x i64], [4096 x i64]* %large2, i64 0, i64 1
store i64 %val, i64* %gep3, align 8
store i64 %val, i64* %gep4, align 8
call void @ptr_fn(<vscale x 4 x float>* %vec_1)
call void @ptr_fn(<vscale x 4 x float>* %vec_2)
%gep1 = getelementptr [4096 x i64], ptr %large1, i64 0, i64 0
%gep2 = getelementptr [4096 x i64], ptr %large1, i64 0, i64 1
store i64 %val, ptr %gep1, align 8
store i64 %val, ptr %gep2, align 8
%gep3 = getelementptr [4096 x i64], ptr %large2, i64 0, i64 0
%gep4 = getelementptr [4096 x i64], ptr %large2, i64 0, i64 1
store i64 %val, ptr %gep3, align 8
store i64 %val, ptr %gep4, align 8
call void @ptr_fn(ptr %vec_1)
call void @ptr_fn(ptr %vec_2)
ret void
}

Expand Down Expand Up @@ -227,22 +227,22 @@ entry:
define void @local_stack_alloc_strong(i64 %val) #1 {
entry:
%char_arr = alloca [8 x i8], align 4
%gep0 = getelementptr [8 x i8], [8 x i8]* %char_arr, i64 0, i64 0
store i8 0, i8* %gep0, align 8
%gep0 = getelementptr [8 x i8], ptr %char_arr, i64 0, i64 0
store i8 0, ptr %gep0, align 8
%large1 = alloca [4096 x i64], align 8
%large2 = alloca [4096 x i64], align 8
%vec_1 = alloca <vscale x 4 x float>, align 16
%vec_2 = alloca <vscale x 4 x float>, align 16
%gep1 = getelementptr [4096 x i64], [4096 x i64]* %large1, i64 0, i64 0
%gep2 = getelementptr [4096 x i64], [4096 x i64]* %large1, i64 0, i64 1
store i64 %val, i64* %gep1, align 8
store i64 %val, i64* %gep2, align 8
%gep3 = getelementptr [4096 x i64], [4096 x i64]* %large2, i64 0, i64 0
%gep4 = getelementptr [4096 x i64], [4096 x i64]* %large2, i64 0, i64 1
store i64 %val, i64* %gep3, align 8
store i64 %val, i64* %gep4, align 8
call void @ptr_fn(<vscale x 4 x float>* %vec_1)
call void @ptr_fn(<vscale x 4 x float>* %vec_2)
%gep1 = getelementptr [4096 x i64], ptr %large1, i64 0, i64 0
%gep2 = getelementptr [4096 x i64], ptr %large1, i64 0, i64 1
store i64 %val, ptr %gep1, align 8
store i64 %val, ptr %gep2, align 8
%gep3 = getelementptr [4096 x i64], ptr %large2, i64 0, i64 0
%gep4 = getelementptr [4096 x i64], ptr %large2, i64 0, i64 1
store i64 %val, ptr %gep3, align 8
store i64 %val, ptr %gep4, align 8
call void @ptr_fn(ptr %vec_1)
call void @ptr_fn(ptr %vec_2)
ret void
}

Expand All @@ -255,8 +255,8 @@ entry:
define void @vector_gep_3() #0 {
entry:
%vec = alloca <vscale x 4 x float>, align 16
%gep = getelementptr <vscale x 4 x float>, <vscale x 4 x float>* %vec, i64 0, i64 3
store float 0.0, float* %gep, align 4
%gep = getelementptr <vscale x 4 x float>, ptr %vec, i64 0, i64 3
store float 0.0, ptr %gep, align 4
ret void
}

Expand All @@ -265,8 +265,8 @@ entry:
define void @vector_gep_4() #0 {
entry:
%vec = alloca <vscale x 4 x float>, align 16
%gep = getelementptr <vscale x 4 x float>, <vscale x 4 x float>* %vec, i64 0, i64 4
store float 0.0, float* %gep, align 4
%gep = getelementptr <vscale x 4 x float>, ptr %vec, i64 0, i64 4
store float 0.0, ptr %gep, align 4
ret void
}

Expand All @@ -275,10 +275,10 @@ entry:
define void @vector_gep_twice() #0 {
entry:
%vec = alloca <vscale x 4 x float>, align 16
%gep1 = getelementptr <vscale x 4 x float>, <vscale x 4 x float>* %vec, i64 0, i64 3
store float 0.0, float* %gep1, align 4
%gep2 = getelementptr float, float* %gep1, i64 1
store float 0.0, float* %gep2, align 4
%gep1 = getelementptr <vscale x 4 x float>, ptr %vec, i64 0, i64 3
store float 0.0, ptr %gep1, align 4
%gep2 = getelementptr float, ptr %gep1, i64 1
store float 0.0, ptr %gep2, align 4
ret void
}

Expand All @@ -287,8 +287,8 @@ entry:
define void @vector_gep_n(i64 %n) #0 {
entry:
%vec = alloca <vscale x 4 x float>, align 16
%gep = getelementptr <vscale x 4 x float>, <vscale x 4 x float>* %vec, i64 0, i64 %n
store float 0.0, float* %gep, align 4
%gep = getelementptr <vscale x 4 x float>, ptr %vec, i64 0, i64 %n
store float 0.0, ptr %gep, align 4
ret void
}

Expand All @@ -297,8 +297,8 @@ entry:
define void @vector_gep_3_strong() #1 {
entry:
%vec = alloca <vscale x 4 x float>, align 16
%gep = getelementptr <vscale x 4 x float>, <vscale x 4 x float>* %vec, i64 0, i64 3
store float 0.0, float* %gep, align 4
%gep = getelementptr <vscale x 4 x float>, ptr %vec, i64 0, i64 3
store float 0.0, ptr %gep, align 4
ret void
}

Expand All @@ -307,8 +307,8 @@ entry:
define void @vector_gep_4_strong(i64 %val) #1 {
entry:
%vec = alloca <vscale x 4 x float>, align 16
%gep = getelementptr <vscale x 4 x float>, <vscale x 4 x float>* %vec, i64 0, i64 4
store float 0.0, float* %gep, align 4
%gep = getelementptr <vscale x 4 x float>, ptr %vec, i64 0, i64 4
store float 0.0, ptr %gep, align 4
ret void
}

Expand All @@ -318,10 +318,10 @@ entry:
define void @vector_gep_twice_strong() #1 {
entry:
%vec = alloca <vscale x 4 x float>, align 16
%gep1 = getelementptr <vscale x 4 x float>, <vscale x 4 x float>* %vec, i64 0, i64 3
store float 0.0, float* %gep1, align 4
%gep2 = getelementptr float, float* %gep1, i64 1
store float 0.0, float* %gep2, align 4
%gep1 = getelementptr <vscale x 4 x float>, ptr %vec, i64 0, i64 3
store float 0.0, ptr %gep1, align 4
%gep2 = getelementptr float, ptr %gep1, i64 1
store float 0.0, ptr %gep2, align 4
ret void
}

Expand All @@ -330,8 +330,8 @@ entry:
define void @vector_gep_n_strong(i64 %n) #1 {
entry:
%vec = alloca <vscale x 4 x float>, align 16
%gep = getelementptr <vscale x 4 x float>, <vscale x 4 x float>* %vec, i64 0, i64 %n
store float 0.0, float* %gep, align 4
%gep = getelementptr <vscale x 4 x float>, ptr %vec, i64 0, i64 %n
store float 0.0, ptr %gep, align 4
ret void
}

Expand Down
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/AArch64/stack-probing-64k.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,7 @@ define void @static_65536(ptr %out) #0 {
; CHECK-NEXT: ret
entry:
%v = alloca i8, i64 65536, align 1
store i8* %v, ptr %out, align 8
store ptr %v, ptr %out, align 8
ret void
}

Expand All @@ -51,7 +51,7 @@ define void @static_65552(ptr %out) #0 {
; CHECK-NEXT: ret
entry:
%v = alloca i8, i64 65552, align 1
store i8* %v, ptr %out, align 8
store ptr %v, ptr %out, align 8
ret void
}

Expand Down Expand Up @@ -79,7 +79,7 @@ define void @static_66560(ptr %out) #0 {
; CHECK-NEXT: ret
entry:
%v = alloca i8, i64 66560, align 1
store i8* %v, ptr %out, align 8
store ptr %v, ptr %out, align 8
ret void
}

Expand Down Expand Up @@ -108,7 +108,7 @@ define void @static_66576(ptr %out) #0 {
; CHECK-NEXT: ret
entry:
%v = alloca i8, i64 66576, align 1
store i8* %v, ptr %out, align 8
store ptr %v, ptr %out, align 8
ret void
}

Expand Down Expand Up @@ -139,7 +139,7 @@ define void @static_132096(ptr %out) #0 {
; CHECK-NEXT: ret
entry:
%v = alloca i8, i64 132096, align 1
store i8* %v, ptr %out, align 8
store ptr %v, ptr %out, align 8
ret void
}

Expand Down Expand Up @@ -179,7 +179,7 @@ define void @static_327664(ptr %out) #0 {
; CHECK-NEXT: ret
entry:
%v = alloca i8, i64 327664, align 1
store i8* %v, ptr %out, align 8
store ptr %v, ptr %out, align 8
ret void
}

Expand Down Expand Up @@ -210,7 +210,7 @@ define void @static_327680(ptr %out) #0 {
; CHECK-NEXT: ret
entry:
%v = alloca i8, i64 327680, align 1
store i8* %v, ptr %out, align 8
store ptr %v, ptr %out, align 8
ret void
}

Expand Down Expand Up @@ -246,7 +246,7 @@ define void @static_328704(ptr %out) #0 {
; CHECK-NEXT: ret
entry:
%v = alloca i8, i64 328704, align 1
store i8* %v, ptr %out, align 8
store ptr %v, ptr %out, align 8
ret void
}

Expand Down Expand Up @@ -283,7 +283,7 @@ define void @static_328720(ptr %out) #0 {
; CHECK-NEXT: ret
entry:
%v = alloca i8, i64 328720, align 1
store i8* %v, ptr %out, align 8
store ptr %v, ptr %out, align 8
ret void
}

Expand Down Expand Up @@ -325,7 +325,7 @@ define void @static_16_align_131072(ptr %out) #0 {
; CHECK-NEXT: ret
entry:
%v = alloca i8, i64 16, align 131072
store i8* %v, ptr %out, align 8
store ptr %v, ptr %out, align 8
ret void
}

Expand Down Expand Up @@ -355,7 +355,7 @@ define void @static_16_align_8192(ptr %out) #0 {
; CHECK-NEXT: ret
entry:
%v = alloca i8, i64 16, align 8192
store i8* %v, ptr %out, align 8
store ptr %v, ptr %out, align 8
ret void
}

Expand Down Expand Up @@ -385,7 +385,7 @@ define void @static_32752_align_32k(ptr %out) #0 {
; CHECK-NEXT: ret
entry:
%v = alloca i8, i64 32752, align 32768
store i8* %v, ptr %out, align 8
store ptr %v, ptr %out, align 8
ret void
}

Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/AArch64/stack-tagging-cfi.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@ entry:
; CHECK: .cfi_mte_tagged_frame
; CHECK: stg
%x = alloca i32, align 4
call void @use32(i32* %x)
call void @use32(ptr %x)
ret void
}

Expand All @@ -18,7 +18,7 @@ entry:
; CHECK-NOT: .cfi_mte_tagged_frame
; CHECK: stg
%x = alloca i32, align 4
call void @use32(i32* %x)
call void @use32(ptr %x)
ret void
}

Expand All @@ -28,7 +28,7 @@ entry:
; CHECK: .cfi_mte_tagged_frame
; CHECK: stg
%x = alloca i32, align 4
call void @use32(i32* %x)
call void @use32(ptr %x)
ret void
}

Expand All @@ -38,6 +38,6 @@ entry:
; CHECK-NOT: .cfi_mte_tagged_frame
; CHECK-NOT: stg
%x = alloca i32, align 4
call void @use32(i32* %x)
call void @use32(ptr %x)
ret void
}
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AArch64/stp-opt-with-renaming-ld3.mir
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
# RUN: llc -run-pass=aarch64-ldst-opt -mtriple=arm64-apple-iphoneos -aarch64-load-store-renaming=true -o - -verify-machineinstrs %s | FileCheck %s
--- |
define void @test_ld3(<8 x i8>* %a1) {
define void @test_ld3(ptr %a1) {
entry:
%s1 = alloca i64
ret void
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AArch64/stp-opt-with-renaming-undef-assert.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -40,8 +40,8 @@ machineFunctionInfo: {}
body: |
bb.0:
liveins: $x0, $x17, $x18
renamable $q13_q14_q15 = LD3Threev16b undef renamable $x17 :: (load (s384) from `<16 x i8>* undef`, align 64)
renamable $q23_q24_q25 = LD3Threev16b undef renamable $x18 :: (load (s384) from `<16 x i8>* undef`, align 64)
renamable $q13_q14_q15 = LD3Threev16b undef renamable $x17 :: (load (s384) from `ptr undef`, align 64)
renamable $q23_q24_q25 = LD3Threev16b undef renamable $x18 :: (load (s384) from `ptr undef`, align 64)
renamable $q20 = EXTv16i8 renamable $q23, renamable $q23, 8
STRQui killed renamable $q20, $sp, 7 :: (store (s128))
renamable $q20 = EXTv16i8 renamable $q14, renamable $q14, 8
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AArch64/sub-of-bias.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -45,15 +45,15 @@ define i32 @t2_commutative(i32 %ptr, i32 %mask) nounwind {

; Extra use tests

define i32 @n3_extrause1(i32 %ptr, i32 %mask, i32* %bias_storage) nounwind {
define i32 @n3_extrause1(i32 %ptr, i32 %mask, ptr %bias_storage) nounwind {
; CHECK-LABEL: n3_extrause1:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, w1
; CHECK-NEXT: sub w0, w0, w8
; CHECK-NEXT: str w8, [x2]
; CHECK-NEXT: ret
%bias = and i32 %ptr, %mask ; has extra uses, can't fold
store i32 %bias, i32* %bias_storage
store i32 %bias, ptr %bias_storage
%r = sub i32 %ptr, %bias
ret i32 %r
}
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/AArch64/sve-alloca-stackid.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10,11 +10,11 @@
; CHECKISEL-NEXT: stack-id: scalable-vector
define i32 @foo(<vscale x 16 x i8> %val) {
%ptr = alloca <vscale x 16 x i8>
%res = call i32 @bar(<vscale x 16 x i8>* %ptr)
%res = call i32 @bar(ptr %ptr)
ret i32 %res
}

declare i32 @bar(<vscale x 16 x i8>* %ptr);
declare i32 @bar(ptr %ptr);

; CHECKCG-LABEL: foo2:
; CHECKCG: addvl sp, sp, #-2
Expand All @@ -26,7 +26,7 @@ declare i32 @bar(<vscale x 16 x i8>* %ptr);

define i32 @foo2(<vscale x 32 x i8> %val) {
%ptr = alloca <vscale x 32 x i8>, align 16
%res = call i32 @bar2(<vscale x 32 x i8>* %ptr)
%res = call i32 @bar2(ptr %ptr)
ret i32 %res
}
declare i32 @bar2(<vscale x 32 x i8>* %ptr);
declare i32 @bar2(ptr %ptr);
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/AArch64/sve-alloca.ll
View file
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64 -mattr=+sve < %s | FileCheck %s

declare void @bar(<vscale x 4 x i64>*)
declare void @bar(ptr)

define void @foo(<vscale x 4 x i64> %dst, i1 %cond) {
; CHECK-LABEL: foo:
Expand Down Expand Up @@ -104,8 +104,8 @@ entry:

if.then:
%ptr = alloca <vscale x 4 x i64>
store <vscale x 4 x i64> %dst, <vscale x 4 x i64>* %ptr
call void @bar(<vscale x 4 x i64>* %ptr)
store <vscale x 4 x i64> %dst, ptr %ptr
call void @bar(ptr %ptr)
br label %if.end

if.end:
Expand Down
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