159 changes: 159 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/sf_vqmacc_2x8x2.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+xsfvqmaccdod \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+xsfvqmaccdod \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK

declare <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8(
<vscale x 2 x i32>,
<vscale x 8 x i8>,
<vscale x 8 x i8>,
iXLen, iXLen);

define <vscale x 2 x i32> @intrinsic_vqmacc_2x8x2_tu_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmacc_2x8x2_tu_i32m1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
; CHECK-NEXT: sf.vqmacc.2x8x2 v8, v9, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8(
<vscale x 2 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
iXLen %3, iXLen 2)

ret <vscale x 2 x i32> %a
}

define <vscale x 2 x i32> @intrinsic_vqmacc_2x8x2_ta_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmacc_2x8x2_ta_i32m1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: sf.vqmacc.2x8x2 v8, v9, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8(
<vscale x 2 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
iXLen %3, iXLen 3)

ret <vscale x 2 x i32> %a
}

declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8(
<vscale x 4 x i32>,
<vscale x 8 x i8>,
<vscale x 16 x i8>,
iXLen, iXLen);

define <vscale x 4 x i32> @intrinsic_vqmacc_2x8x2_tu_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmacc_2x8x2_tu_i32m2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
; CHECK-NEXT: sf.vqmacc.2x8x2 v8, v10, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8(
<vscale x 4 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 16 x i8> %2,
iXLen %3, iXLen 2)

ret <vscale x 4 x i32> %a
}

define <vscale x 4 x i32> @intrinsic_vqmacc_2x8x2_ta_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmacc_2x8x2_ta_i32m2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: sf.vqmacc.2x8x2 v8, v10, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8(
<vscale x 4 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 16 x i8> %2,
iXLen %3, iXLen 3)

ret <vscale x 4 x i32> %a
}

declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8(
<vscale x 8 x i32>,
<vscale x 8 x i8>,
<vscale x 32 x i8>,
iXLen, iXLen);

define <vscale x 8 x i32> @intrinsic_vqmacc_2x8x2_tu_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmacc_2x8x2_tu_i32m4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
; CHECK-NEXT: sf.vqmacc.2x8x2 v8, v12, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8(
<vscale x 8 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 32 x i8> %2,
iXLen %3, iXLen 2)

ret <vscale x 8 x i32> %a
}

define <vscale x 8 x i32> @intrinsic_vqmacc_2x8x2_ta_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmacc_2x8x2_ta_i32m4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: sf.vqmacc.2x8x2 v8, v12, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8(
<vscale x 8 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 32 x i8> %2,
iXLen %3, iXLen 3)

ret <vscale x 8 x i32> %a
}

declare <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8(
<vscale x 16 x i32>,
<vscale x 8 x i8>,
<vscale x 64 x i8>,
iXLen, iXLen);

define <vscale x 16 x i32> @intrinsic_vqmacc_2x8x2_tu_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmacc_2x8x2_tu_i32m8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8r.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, ma
; CHECK-NEXT: sf.vqmacc.2x8x2 v8, v16, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8(
<vscale x 16 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 64 x i8> %2,
iXLen %3, iXLen 2)

ret <vscale x 16 x i32> %a
}

define <vscale x 16 x i32> @intrinsic_vqmacc_2x8x2_ta_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmacc_2x8x2_ta_i32m8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8r.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; CHECK-NEXT: sf.vqmacc.2x8x2 v8, v16, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8(
<vscale x 16 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 64 x i8> %2,
iXLen %3, iXLen 3)

ret <vscale x 16 x i32> %a
}
159 changes: 159 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/sf_vqmacc_4x8x4.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+xsfvqmaccqoq \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+xsfvqmaccqoq \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK

declare <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv8i8(
<vscale x 2 x i32>,
<vscale x 8 x i8>,
<vscale x 8 x i8>,
iXLen, iXLen);

define <vscale x 2 x i32> @intrinsic_vqmacc_4x8x4_tu_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmacc_4x8x4_tu_i32m1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
; CHECK-NEXT: sf.vqmacc.4x8x4 v8, v9, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv8i8(
<vscale x 2 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
iXLen %3, iXLen 2)

ret <vscale x 2 x i32> %a
}

define <vscale x 2 x i32> @intrinsic_vqmacc_4x8x4_ta_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmacc_4x8x4_ta_i32m1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: sf.vqmacc.4x8x4 v8, v9, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv8i8(
<vscale x 2 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
iXLen %3, iXLen 3)

ret <vscale x 2 x i32> %a
}

declare <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv16i8(
<vscale x 4 x i32>,
<vscale x 8 x i8>,
<vscale x 16 x i8>,
iXLen, iXLen);

define <vscale x 4 x i32> @intrinsic_vqmacc_4x8x4_tu_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmacc_4x8x4_tu_i32m2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
; CHECK-NEXT: sf.vqmacc.4x8x4 v8, v10, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv16i8(
<vscale x 4 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 16 x i8> %2,
iXLen %3, iXLen 2)

ret <vscale x 4 x i32> %a
}

define <vscale x 4 x i32> @intrinsic_vqmacc_4x8x4_ta_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmacc_4x8x4_ta_i32m2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: sf.vqmacc.4x8x4 v8, v10, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv16i8(
<vscale x 4 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 16 x i8> %2,
iXLen %3, iXLen 3)

ret <vscale x 4 x i32> %a
}

declare <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv32i8(
<vscale x 8 x i32>,
<vscale x 8 x i8>,
<vscale x 32 x i8>,
iXLen, iXLen);

define <vscale x 8 x i32> @intrinsic_vqmacc_4x8x4_tu_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmacc_4x8x4_tu_i32m4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
; CHECK-NEXT: sf.vqmacc.4x8x4 v8, v12, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv32i8(
<vscale x 8 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 32 x i8> %2,
iXLen %3, iXLen 2)

ret <vscale x 8 x i32> %a
}

define <vscale x 8 x i32> @intrinsic_vqmacc_4x8x4_ta_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmacc_4x8x4_ta_i32m4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: sf.vqmacc.4x8x4 v8, v12, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv32i8(
<vscale x 8 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 32 x i8> %2,
iXLen %3, iXLen 3)

ret <vscale x 8 x i32> %a
}

declare <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv64i8(
<vscale x 16 x i32>,
<vscale x 8 x i8>,
<vscale x 64 x i8>,
iXLen, iXLen);

define <vscale x 16 x i32> @intrinsic_vqmacc_4x8x4_tu_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmacc_4x8x4_tu_i32m8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8r.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, ma
; CHECK-NEXT: sf.vqmacc.4x8x4 v8, v16, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv64i8(
<vscale x 16 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 64 x i8> %2,
iXLen %3, iXLen 2)

ret <vscale x 16 x i32> %a
}

define <vscale x 16 x i32> @intrinsic_vqmacc_4x8x4_ta_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmacc_4x8x4_ta_i32m8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8r.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; CHECK-NEXT: sf.vqmacc.4x8x4 v8, v16, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv64i8(
<vscale x 16 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 64 x i8> %2,
iXLen %3, iXLen 3)

ret <vscale x 16 x i32> %a
}
159 changes: 159 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/sf_vqmaccsu_2x8x2.ll
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Original file line number Diff line number Diff line change
@@ -0,0 +1,159 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+xsfvqmaccdod \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+xsfvqmaccdod \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK

declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8(
<vscale x 2 x i32>,
<vscale x 8 x i8>,
<vscale x 8 x i8>,
iXLen, iXLen);

define <vscale x 2 x i32> @intrinsic_vqmaccsu_2x8x2_tu_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccsu_2x8x2_tu_i32m1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
; CHECK-NEXT: sf.vqmaccsu.2x8x2 v8, v9, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8(
<vscale x 2 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
iXLen %3, iXLen 2)

ret <vscale x 2 x i32> %a
}

define <vscale x 2 x i32> @intrinsic_vqmaccsu_2x8x2_ta_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccsu_2x8x2_ta_i32m1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: sf.vqmaccsu.2x8x2 v8, v9, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8(
<vscale x 2 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
iXLen %3, iXLen 3)

ret <vscale x 2 x i32> %a
}

declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8(
<vscale x 4 x i32>,
<vscale x 8 x i8>,
<vscale x 16 x i8>,
iXLen, iXLen);

define <vscale x 4 x i32> @intrinsic_vqmaccsu_2x8x2_tu_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccsu_2x8x2_tu_i32m2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
; CHECK-NEXT: sf.vqmaccsu.2x8x2 v8, v10, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8(
<vscale x 4 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 16 x i8> %2,
iXLen %3, iXLen 2)

ret <vscale x 4 x i32> %a
}

define <vscale x 4 x i32> @intrinsic_vqmaccsu_2x8x2_ta_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccsu_2x8x2_ta_i32m2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: sf.vqmaccsu.2x8x2 v8, v10, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8(
<vscale x 4 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 16 x i8> %2,
iXLen %3, iXLen 3)

ret <vscale x 4 x i32> %a
}

declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8(
<vscale x 8 x i32>,
<vscale x 8 x i8>,
<vscale x 32 x i8>,
iXLen, iXLen);

define <vscale x 8 x i32> @intrinsic_vqmaccsu_2x8x2_tu_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccsu_2x8x2_tu_i32m4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
; CHECK-NEXT: sf.vqmaccsu.2x8x2 v8, v12, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8(
<vscale x 8 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 32 x i8> %2,
iXLen %3, iXLen 2)

ret <vscale x 8 x i32> %a
}

define <vscale x 8 x i32> @intrinsic_vqmaccsu_2x8x2_ta_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccsu_2x8x2_ta_i32m4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: sf.vqmaccsu.2x8x2 v8, v12, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8(
<vscale x 8 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 32 x i8> %2,
iXLen %3, iXLen 3)

ret <vscale x 8 x i32> %a
}

declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8(
<vscale x 16 x i32>,
<vscale x 8 x i8>,
<vscale x 64 x i8>,
iXLen, iXLen);

define <vscale x 16 x i32> @intrinsic_vqmaccsu_2x8x2_tu_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccsu_2x8x2_tu_i32m8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8r.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, ma
; CHECK-NEXT: sf.vqmaccsu.2x8x2 v8, v16, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8(
<vscale x 16 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 64 x i8> %2,
iXLen %3, iXLen 2)

ret <vscale x 16 x i32> %a
}

define <vscale x 16 x i32> @intrinsic_vqmaccsu_2x8x2_ta_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccsu_2x8x2_ta_i32m8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8r.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; CHECK-NEXT: sf.vqmaccsu.2x8x2 v8, v16, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8(
<vscale x 16 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 64 x i8> %2,
iXLen %3, iXLen 3)

ret <vscale x 16 x i32> %a
}
159 changes: 159 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/sf_vqmaccsu_4x8x4.ll
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,159 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+xsfvqmaccqoq \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+xsfvqmaccqoq \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK

declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv8i8(
<vscale x 2 x i32>,
<vscale x 8 x i8>,
<vscale x 8 x i8>,
iXLen, iXLen);

define <vscale x 2 x i32> @intrinsic_vqmaccsu_4x8x4_tu_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccsu_4x8x4_tu_i32m1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
; CHECK-NEXT: sf.vqmaccsu.4x8x4 v8, v9, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv8i8(
<vscale x 2 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
iXLen %3, iXLen 2)

ret <vscale x 2 x i32> %a
}

define <vscale x 2 x i32> @intrinsic_vqmaccsu_4x8x4_ta_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccsu_4x8x4_ta_i32m1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: sf.vqmaccsu.4x8x4 v8, v9, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv8i8(
<vscale x 2 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
iXLen %3, iXLen 3)

ret <vscale x 2 x i32> %a
}

declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv16i8(
<vscale x 4 x i32>,
<vscale x 8 x i8>,
<vscale x 16 x i8>,
iXLen, iXLen);

define <vscale x 4 x i32> @intrinsic_vqmaccsu_4x8x4_tu_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccsu_4x8x4_tu_i32m2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
; CHECK-NEXT: sf.vqmaccsu.4x8x4 v8, v10, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv16i8(
<vscale x 4 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 16 x i8> %2,
iXLen %3, iXLen 2)

ret <vscale x 4 x i32> %a
}

define <vscale x 4 x i32> @intrinsic_vqmaccsu_4x8x4_ta_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccsu_4x8x4_ta_i32m2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: sf.vqmaccsu.4x8x4 v8, v10, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv16i8(
<vscale x 4 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 16 x i8> %2,
iXLen %3, iXLen 3)

ret <vscale x 4 x i32> %a
}

declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv32i8(
<vscale x 8 x i32>,
<vscale x 8 x i8>,
<vscale x 32 x i8>,
iXLen, iXLen);

define <vscale x 8 x i32> @intrinsic_vqmaccsu_4x8x4_tu_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccsu_4x8x4_tu_i32m4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
; CHECK-NEXT: sf.vqmaccsu.4x8x4 v8, v12, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv32i8(
<vscale x 8 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 32 x i8> %2,
iXLen %3, iXLen 2)

ret <vscale x 8 x i32> %a
}

define <vscale x 8 x i32> @intrinsic_vqmaccsu_4x8x4_ta_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccsu_4x8x4_ta_i32m4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: sf.vqmaccsu.4x8x4 v8, v12, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv32i8(
<vscale x 8 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 32 x i8> %2,
iXLen %3, iXLen 3)

ret <vscale x 8 x i32> %a
}

declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv64i8(
<vscale x 16 x i32>,
<vscale x 8 x i8>,
<vscale x 64 x i8>,
iXLen, iXLen);

define <vscale x 16 x i32> @intrinsic_vqmaccsu_4x8x4_tu_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccsu_4x8x4_tu_i32m8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8r.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, ma
; CHECK-NEXT: sf.vqmaccsu.4x8x4 v8, v16, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv64i8(
<vscale x 16 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 64 x i8> %2,
iXLen %3, iXLen 2)

ret <vscale x 16 x i32> %a
}

define <vscale x 16 x i32> @intrinsic_vqmaccsu_4x8x4_ta_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccsu_4x8x4_ta_i32m8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8r.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; CHECK-NEXT: sf.vqmaccsu.4x8x4 v8, v16, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv64i8(
<vscale x 16 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 64 x i8> %2,
iXLen %3, iXLen 3)

ret <vscale x 16 x i32> %a
}
159 changes: 159 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/sf_vqmaccu_2x8x2.ll
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,159 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+xsfvqmaccdod \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+xsfvqmaccdod \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK

declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8(
<vscale x 2 x i32>,
<vscale x 8 x i8>,
<vscale x 8 x i8>,
iXLen, iXLen);

define <vscale x 2 x i32> @intrinsic_vqmaccu_2x8x2_tu_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccu_2x8x2_tu_i32m1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
; CHECK-NEXT: sf.vqmaccu.2x8x2 v8, v9, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8(
<vscale x 2 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
iXLen %3, iXLen 2)

ret <vscale x 2 x i32> %a
}

define <vscale x 2 x i32> @intrinsic_vqmaccu_2x8x2_ta_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccu_2x8x2_ta_i32m1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: sf.vqmaccu.2x8x2 v8, v9, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8(
<vscale x 2 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
iXLen %3, iXLen 3)

ret <vscale x 2 x i32> %a
}

declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8(
<vscale x 4 x i32>,
<vscale x 8 x i8>,
<vscale x 16 x i8>,
iXLen, iXLen);

define <vscale x 4 x i32> @intrinsic_vqmaccu_2x8x2_tu_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccu_2x8x2_tu_i32m2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
; CHECK-NEXT: sf.vqmaccu.2x8x2 v8, v10, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8(
<vscale x 4 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 16 x i8> %2,
iXLen %3, iXLen 2)

ret <vscale x 4 x i32> %a
}

define <vscale x 4 x i32> @intrinsic_vqmaccu_2x8x2_ta_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccu_2x8x2_ta_i32m2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: sf.vqmaccu.2x8x2 v8, v10, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8(
<vscale x 4 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 16 x i8> %2,
iXLen %3, iXLen 3)

ret <vscale x 4 x i32> %a
}

declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8(
<vscale x 8 x i32>,
<vscale x 8 x i8>,
<vscale x 32 x i8>,
iXLen, iXLen);

define <vscale x 8 x i32> @intrinsic_vqmaccu_2x8x2_tu_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccu_2x8x2_tu_i32m4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
; CHECK-NEXT: sf.vqmaccu.2x8x2 v8, v12, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8(
<vscale x 8 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 32 x i8> %2,
iXLen %3, iXLen 2)

ret <vscale x 8 x i32> %a
}

define <vscale x 8 x i32> @intrinsic_vqmaccu_2x8x2_ta_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccu_2x8x2_ta_i32m4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: sf.vqmaccu.2x8x2 v8, v12, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8(
<vscale x 8 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 32 x i8> %2,
iXLen %3, iXLen 3)

ret <vscale x 8 x i32> %a
}

declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8(
<vscale x 16 x i32>,
<vscale x 8 x i8>,
<vscale x 64 x i8>,
iXLen, iXLen);

define <vscale x 16 x i32> @intrinsic_vqmaccu_2x8x2_tu_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccu_2x8x2_tu_i32m8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8r.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, ma
; CHECK-NEXT: sf.vqmaccu.2x8x2 v8, v16, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8(
<vscale x 16 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 64 x i8> %2,
iXLen %3, iXLen 2)

ret <vscale x 16 x i32> %a
}

define <vscale x 16 x i32> @intrinsic_vqmaccu_2x8x2_ta_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccu_2x8x2_ta_i32m8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8r.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; CHECK-NEXT: sf.vqmaccu.2x8x2 v8, v16, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8(
<vscale x 16 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 64 x i8> %2,
iXLen %3, iXLen 3)

ret <vscale x 16 x i32> %a
}
159 changes: 159 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/sf_vqmaccu_4x8x4.ll
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,159 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+xsfvqmaccqoq \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+xsfvqmaccqoq \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK

declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv8i8(
<vscale x 2 x i32>,
<vscale x 8 x i8>,
<vscale x 8 x i8>,
iXLen, iXLen);

define <vscale x 2 x i32> @intrinsic_vqmaccu_4x8x4_tu_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccu_4x8x4_tu_i32m1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
; CHECK-NEXT: sf.vqmaccu.4x8x4 v8, v9, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv8i8(
<vscale x 2 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
iXLen %3, iXLen 2)

ret <vscale x 2 x i32> %a
}

define <vscale x 2 x i32> @intrinsic_vqmaccu_4x8x4_ta_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccu_4x8x4_ta_i32m1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: sf.vqmaccu.4x8x4 v8, v9, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv2i32.nxv8i8.nxv8i8(
<vscale x 2 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
iXLen %3, iXLen 3)

ret <vscale x 2 x i32> %a
}

declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv16i8(
<vscale x 4 x i32>,
<vscale x 8 x i8>,
<vscale x 16 x i8>,
iXLen, iXLen);

define <vscale x 4 x i32> @intrinsic_vqmaccu_4x8x4_tu_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccu_4x8x4_tu_i32m2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
; CHECK-NEXT: sf.vqmaccu.4x8x4 v8, v10, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv16i8(
<vscale x 4 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 16 x i8> %2,
iXLen %3, iXLen 2)

ret <vscale x 4 x i32> %a
}

define <vscale x 4 x i32> @intrinsic_vqmaccu_4x8x4_ta_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccu_4x8x4_ta_i32m2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: sf.vqmaccu.4x8x4 v8, v10, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv4i32.nxv8i8.nxv16i8(
<vscale x 4 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 16 x i8> %2,
iXLen %3, iXLen 3)

ret <vscale x 4 x i32> %a
}

declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv32i8(
<vscale x 8 x i32>,
<vscale x 8 x i8>,
<vscale x 32 x i8>,
iXLen, iXLen);

define <vscale x 8 x i32> @intrinsic_vqmaccu_4x8x4_tu_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccu_4x8x4_tu_i32m4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
; CHECK-NEXT: sf.vqmaccu.4x8x4 v8, v12, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv32i8(
<vscale x 8 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 32 x i8> %2,
iXLen %3, iXLen 2)

ret <vscale x 8 x i32> %a
}

define <vscale x 8 x i32> @intrinsic_vqmaccu_4x8x4_ta_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccu_4x8x4_ta_i32m4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: sf.vqmaccu.4x8x4 v8, v12, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv8i32.nxv8i8.nxv32i8(
<vscale x 8 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 32 x i8> %2,
iXLen %3, iXLen 3)

ret <vscale x 8 x i32> %a
}

declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv64i8(
<vscale x 16 x i32>,
<vscale x 8 x i8>,
<vscale x 64 x i8>,
iXLen, iXLen);

define <vscale x 16 x i32> @intrinsic_vqmaccu_4x8x4_tu_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccu_4x8x4_tu_i32m8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8r.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, ma
; CHECK-NEXT: sf.vqmaccu.4x8x4 v8, v16, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv64i8(
<vscale x 16 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 64 x i8> %2,
iXLen %3, iXLen 2)

ret <vscale x 16 x i32> %a
}

define <vscale x 16 x i32> @intrinsic_vqmaccu_4x8x4_ta_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccu_4x8x4_ta_i32m8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8r.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; CHECK-NEXT: sf.vqmaccu.4x8x4 v8, v16, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.4x8x4.nxv16i32.nxv8i8.nxv64i8(
<vscale x 16 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 64 x i8> %2,
iXLen %3, iXLen 3)

ret <vscale x 16 x i32> %a
}
159 changes: 159 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/sf_vqmaccus_2x8x2.ll
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,159 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+xsfvqmaccdod \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+xsfvqmaccdod \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK

declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8(
<vscale x 2 x i32>,
<vscale x 8 x i8>,
<vscale x 8 x i8>,
iXLen, iXLen);

define <vscale x 2 x i32> @intrinsic_vqmaccus_2x8x2_tu_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccus_2x8x2_tu_i32m1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
; CHECK-NEXT: sf.vqmaccus.2x8x2 v8, v9, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8(
<vscale x 2 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
iXLen %3, iXLen 2)

ret <vscale x 2 x i32> %a
}

define <vscale x 2 x i32> @intrinsic_vqmaccus_2x8x2_ta_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccus_2x8x2_ta_i32m1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: sf.vqmaccus.2x8x2 v8, v9, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv2i32.nxv8i8.nxv8i8(
<vscale x 2 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
iXLen %3, iXLen 3)

ret <vscale x 2 x i32> %a
}

declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8(
<vscale x 4 x i32>,
<vscale x 8 x i8>,
<vscale x 16 x i8>,
iXLen, iXLen);

define <vscale x 4 x i32> @intrinsic_vqmaccus_2x8x2_tu_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccus_2x8x2_tu_i32m2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
; CHECK-NEXT: sf.vqmaccus.2x8x2 v8, v10, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8(
<vscale x 4 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 16 x i8> %2,
iXLen %3, iXLen 2)

ret <vscale x 4 x i32> %a
}

define <vscale x 4 x i32> @intrinsic_vqmaccus_2x8x2_ta_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccus_2x8x2_ta_i32m2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: sf.vqmaccus.2x8x2 v8, v10, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv4i32.nxv8i8.nxv16i8(
<vscale x 4 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 16 x i8> %2,
iXLen %3, iXLen 3)

ret <vscale x 4 x i32> %a
}

declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8(
<vscale x 8 x i32>,
<vscale x 8 x i8>,
<vscale x 32 x i8>,
iXLen, iXLen);

define <vscale x 8 x i32> @intrinsic_vqmaccus_2x8x2_tu_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccus_2x8x2_tu_i32m4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
; CHECK-NEXT: sf.vqmaccus.2x8x2 v8, v12, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8(
<vscale x 8 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 32 x i8> %2,
iXLen %3, iXLen 2)

ret <vscale x 8 x i32> %a
}

define <vscale x 8 x i32> @intrinsic_vqmaccus_2x8x2_ta_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccus_2x8x2_ta_i32m4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: sf.vqmaccus.2x8x2 v8, v12, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv8i32.nxv8i8.nxv32i8(
<vscale x 8 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 32 x i8> %2,
iXLen %3, iXLen 3)

ret <vscale x 8 x i32> %a
}

declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8(
<vscale x 16 x i32>,
<vscale x 8 x i8>,
<vscale x 64 x i8>,
iXLen, iXLen);

define <vscale x 16 x i32> @intrinsic_vqmaccus_2x8x2_tu_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccus_2x8x2_tu_i32m8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8r.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, ma
; CHECK-NEXT: sf.vqmaccus.2x8x2 v8, v16, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8(
<vscale x 16 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 64 x i8> %2,
iXLen %3, iXLen 2)

ret <vscale x 16 x i32> %a
}

define <vscale x 16 x i32> @intrinsic_vqmaccus_2x8x2_ta_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccus_2x8x2_ta_i32m8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8r.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; CHECK-NEXT: sf.vqmaccus.2x8x2 v8, v16, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.2x8x2.nxv16i32.nxv8i8.nxv64i8(
<vscale x 16 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 64 x i8> %2,
iXLen %3, iXLen 3)

ret <vscale x 16 x i32> %a
}
159 changes: 159 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/sf_vqmaccus_4x8x4.ll
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,159 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+xsfvqmaccqoq \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+xsfvqmaccqoq \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK

declare <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv8i8(
<vscale x 2 x i32>,
<vscale x 8 x i8>,
<vscale x 8 x i8>,
iXLen, iXLen);

define <vscale x 2 x i32> @intrinsic_vqmaccus_4x8x4_tu_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccus_4x8x4_tu_i32m1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
; CHECK-NEXT: sf.vqmaccus.4x8x4 v8, v9, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv8i8(
<vscale x 2 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
iXLen %3, iXLen 2)

ret <vscale x 2 x i32> %a
}

define <vscale x 2 x i32> @intrinsic_vqmaccus_4x8x4_ta_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccus_4x8x4_ta_i32m1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: sf.vqmaccus.4x8x4 v8, v9, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv2i32.nxv8i8.nxv8i8(
<vscale x 2 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 8 x i8> %2,
iXLen %3, iXLen 3)

ret <vscale x 2 x i32> %a
}

declare <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv16i8(
<vscale x 4 x i32>,
<vscale x 8 x i8>,
<vscale x 16 x i8>,
iXLen, iXLen);

define <vscale x 4 x i32> @intrinsic_vqmaccus_4x8x4_tu_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccus_4x8x4_tu_i32m2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
; CHECK-NEXT: sf.vqmaccus.4x8x4 v8, v10, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv16i8(
<vscale x 4 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 16 x i8> %2,
iXLen %3, iXLen 2)

ret <vscale x 4 x i32> %a
}

define <vscale x 4 x i32> @intrinsic_vqmaccus_4x8x4_ta_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccus_4x8x4_ta_i32m2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: sf.vqmaccus.4x8x4 v8, v10, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv4i32.nxv8i8.nxv16i8(
<vscale x 4 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 16 x i8> %2,
iXLen %3, iXLen 3)

ret <vscale x 4 x i32> %a
}

declare <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv32i8(
<vscale x 8 x i32>,
<vscale x 8 x i8>,
<vscale x 32 x i8>,
iXLen, iXLen);

define <vscale x 8 x i32> @intrinsic_vqmaccus_4x8x4_tu_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccus_4x8x4_tu_i32m4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
; CHECK-NEXT: sf.vqmaccus.4x8x4 v8, v12, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv32i8(
<vscale x 8 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 32 x i8> %2,
iXLen %3, iXLen 2)

ret <vscale x 8 x i32> %a
}

define <vscale x 8 x i32> @intrinsic_vqmaccus_4x8x4_ta_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccus_4x8x4_ta_i32m4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: sf.vqmaccus.4x8x4 v8, v12, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv8i32.nxv8i8.nxv32i8(
<vscale x 8 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 32 x i8> %2,
iXLen %3, iXLen 3)

ret <vscale x 8 x i32> %a
}

declare <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv64i8(
<vscale x 16 x i32>,
<vscale x 8 x i8>,
<vscale x 64 x i8>,
iXLen, iXLen);

define <vscale x 16 x i32> @intrinsic_vqmaccus_4x8x4_tu_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccus_4x8x4_tu_i32m8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8r.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, ma
; CHECK-NEXT: sf.vqmaccus.4x8x4 v8, v16, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv64i8(
<vscale x 16 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 64 x i8> %2,
iXLen %3, iXLen 2)

ret <vscale x 16 x i32> %a
}

define <vscale x 16 x i32> @intrinsic_vqmaccus_4x8x4_ta_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 64 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vqmaccus_4x8x4_ta_i32m8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl8r.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; CHECK-NEXT: sf.vqmaccus.4x8x4 v8, v16, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv64i8(
<vscale x 16 x i32> %0,
<vscale x 8 x i8> %1,
<vscale x 64 x i8> %2,
iXLen %3, iXLen 3)

ret <vscale x 16 x i32> %a
}
57 changes: 57 additions & 0 deletions llvm/test/MC/RISCV/rvv/xsfvqmacc.s
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,57 @@
# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+v,+xsfvqmaccqoq,+xsfvqmaccdod %s \
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+v,+xsfvqmaccqoq,+xsfvqmaccdod %s \
# RUN: | llvm-objdump -d --mattr=+v,+xsfvqmaccqoq,+xsfvqmaccdod - \
# RUN: | FileCheck %s --check-prefix=CHECK-INST
# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+v,+xsfvqmaccqoq,+xsfvqmaccdod %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN

sf.vqmaccu.2x8x2 v8, v4, v20
# CHECK-INST: sf.vqmaccu.2x8x2 v8, v4, v20
# CHECK-ENCODING: [0x5b,0x24,0x42,0xb3]
# CHECK-ERROR: instruction requires the following: 'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2))
# CHECK-UNKNOWN: 5b 24 42 b3 <unknown>

sf.vqmacc.2x8x2 v8, v4, v20
# CHECK-INST: sf.vqmacc.2x8x2 v8, v4, v20
# CHECK-ENCODING: [0x5b,0x24,0x42,0xb7]
# CHECK-ERROR: instruction requires the following: 'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2))
# CHECK-UNKNOWN: 5b 24 42 b7 <unknown>

sf.vqmaccus.2x8x2 v8, v4, v20
# CHECK-INST: sf.vqmaccus.2x8x2 v8, v4, v20
# CHECK-ENCODING: [0x5b,0x24,0x42,0xbb]
# CHECK-ERROR: instruction requires the following: 'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2))
# CHECK-UNKNOWN: 5b 24 42 bb <unknown>

sf.vqmaccsu.2x8x2 v8, v4, v20
# CHECK-INST: sf.vqmaccsu.2x8x2 v8, v4, v20
# CHECK-ENCODING: [0x5b,0x24,0x42,0xbf]
# CHECK-ERROR: instruction requires the following: 'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2))
# CHECK-UNKNOWN: 5b 24 42 bf <unknown>

sf.vqmaccu.4x8x4 v8, v4, v20
# CHECK-INST: sf.vqmaccu.4x8x4 v8, v4, v20
# CHECK-ENCODING: [0x5b,0x24,0x42,0xf3]
# CHECK-ERROR: instruction requires the following: 'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4))
# CHECK-UNKNOWN: 5b 24 42 f3 <unknown>

sf.vqmacc.4x8x4 v8, v4, v20
# CHECK-INST: sf.vqmacc.4x8x4 v8, v4, v20
# CHECK-ENCODING: [0x5b,0x24,0x42,0xf7]
# CHECK-ERROR: instruction requires the following: 'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4))
# CHECK-UNKNOWN: 5b 24 42 f7 <unknown>

sf.vqmaccus.4x8x4 v8, v4, v20
# CHECK-INST: sf.vqmaccus.4x8x4 v8, v4, v20
# CHECK-ENCODING: [0x5b,0x24,0x42,0xfb]
# CHECK-ERROR: instruction requires the following: 'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4))
# CHECK-UNKNOWN: 5b 24 42 fb <unknown>

sf.vqmaccsu.4x8x4 v8, v4, v20
# CHECK-INST: sf.vqmaccsu.4x8x4 v8, v4, v20
# CHECK-ENCODING: [0x5b,0x24,0x42,0xff]
# CHECK-ERROR: instruction requires the following: 'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4))
# CHECK-UNKNOWN: 5b 24 42 ff <unknown>
4 changes: 4 additions & 0 deletions llvm/unittests/Support/RISCVISAInfoTest.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -629,6 +629,7 @@ TEST(getTargetFeatureForExtension, RetrieveTargetFeatureFromOneExt) {
}

TEST(RiscvExtensionsHelp, CheckExtensions) {
// clang-format off
std::string ExpectedOutput =
R"(All available -march extensions for RISC-V
Expand Down Expand Up @@ -713,6 +714,8 @@ R"(All available -march extensions for RISC-V
xcvsimd 1.0
xsfcie 1.0
xsfvcp 1.0
xsfvqmaccdod 1.0
xsfvqmaccqoq 1.0
xtheadba 1.0
xtheadbb 1.0
xtheadbs 1.0
Expand Down Expand Up @@ -755,6 +758,7 @@ Experimental extensions
Use -march to specify the target's extension.
For example, clang -march=rv32i_v1p0)";
// clang-format on

StringMap<StringRef> DummyMap;
DummyMap["i"] = "This is a long dummy description";
Expand Down