714 changes: 714 additions & 0 deletions llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-logical.ll
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,714 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -O2 -S < %s | FileCheck %s

target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64--"

define float @test_merge_allof_v4sf(<4 x float> %t) {
; CHECK-LABEL: @test_merge_allof_v4sf(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[VECEXT:%.*]] = extractelement <4 x float> [[T:%.*]], i32 0
; CHECK-NEXT: [[CMP:%.*]] = fcmp olt float [[VECEXT]], 0.000000e+00
; CHECK-NEXT: [[VECEXT2:%.*]] = extractelement <4 x float> [[T]], i32 1
; CHECK-NEXT: [[CMP4:%.*]] = fcmp olt float [[VECEXT2]], 0.000000e+00
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[CMP]], i1 [[CMP4]], i1 false
; CHECK-NEXT: [[VECEXT7:%.*]] = extractelement <4 x float> [[T]], i32 2
; CHECK-NEXT: [[CMP9:%.*]] = fcmp olt float [[VECEXT7]], 0.000000e+00
; CHECK-NEXT: [[OR_COND1:%.*]] = select i1 [[OR_COND]], i1 [[CMP9]], i1 false
; CHECK-NEXT: [[VECEXT12:%.*]] = extractelement <4 x float> [[T]], i32 3
; CHECK-NEXT: [[CMP14:%.*]] = fcmp olt float [[VECEXT12]], 0.000000e+00
; CHECK-NEXT: [[OR_COND2:%.*]] = select i1 [[OR_COND1]], i1 [[CMP14]], i1 false
; CHECK-NEXT: br i1 [[OR_COND2]], label [[COMMON_RET:%.*]], label [[LOR_LHS_FALSE:%.*]]
; CHECK: common.ret:
; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi float [ [[SPEC_SELECT:%.*]], [[LOR_LHS_FALSE]] ], [ 0.000000e+00, [[ENTRY:%.*]] ]
; CHECK-NEXT: ret float [[COMMON_RET_OP]]
; CHECK: lor.lhs.false:
; CHECK-NEXT: [[CMP18:%.*]] = fcmp ogt float [[VECEXT]], 1.000000e+00
; CHECK-NEXT: [[CMP23:%.*]] = fcmp ogt float [[VECEXT2]], 1.000000e+00
; CHECK-NEXT: [[OR_COND3:%.*]] = select i1 [[CMP18]], i1 [[CMP23]], i1 false
; CHECK-NEXT: [[CMP28:%.*]] = fcmp ogt float [[VECEXT7]], 1.000000e+00
; CHECK-NEXT: [[OR_COND4:%.*]] = select i1 [[OR_COND3]], i1 [[CMP28]], i1 false
; CHECK-NEXT: [[CMP33:%.*]] = fcmp ogt float [[VECEXT12]], 1.000000e+00
; CHECK-NEXT: [[OR_COND5:%.*]] = select i1 [[OR_COND4]], i1 [[CMP33]], i1 false
; CHECK-NEXT: [[ADD:%.*]] = fadd float [[VECEXT]], [[VECEXT2]]
; CHECK-NEXT: [[SPEC_SELECT]] = select i1 [[OR_COND5]], float 0.000000e+00, float [[ADD]]
; CHECK-NEXT: br label [[COMMON_RET]]
;
entry:
%vecext = extractelement <4 x float> %t, i32 0
%conv = fpext float %vecext to double
%cmp = fcmp olt double %conv, 0.000000e+00
br i1 %cmp, label %land.lhs.true, label %lor.lhs.false

land.lhs.true:
%vecext2 = extractelement <4 x float> %t, i32 1
%conv3 = fpext float %vecext2 to double
%cmp4 = fcmp olt double %conv3, 0.000000e+00
br i1 %cmp4, label %land.lhs.true6, label %lor.lhs.false

land.lhs.true6:
%vecext7 = extractelement <4 x float> %t, i32 2
%conv8 = fpext float %vecext7 to double
%cmp9 = fcmp olt double %conv8, 0.000000e+00
br i1 %cmp9, label %land.lhs.true11, label %lor.lhs.false

land.lhs.true11:
%vecext12 = extractelement <4 x float> %t, i32 3
%conv13 = fpext float %vecext12 to double
%cmp14 = fcmp olt double %conv13, 0.000000e+00
br i1 %cmp14, label %if.then, label %lor.lhs.false

lor.lhs.false:
%vecext16 = extractelement <4 x float> %t, i32 0
%conv17 = fpext float %vecext16 to double
%cmp18 = fcmp ogt double %conv17, 1.000000e+00
br i1 %cmp18, label %land.lhs.true20, label %if.end

land.lhs.true20:
%vecext21 = extractelement <4 x float> %t, i32 1
%conv22 = fpext float %vecext21 to double
%cmp23 = fcmp ogt double %conv22, 1.000000e+00
br i1 %cmp23, label %land.lhs.true25, label %if.end

land.lhs.true25:
%vecext26 = extractelement <4 x float> %t, i32 2
%conv27 = fpext float %vecext26 to double
%cmp28 = fcmp ogt double %conv27, 1.000000e+00
br i1 %cmp28, label %land.lhs.true30, label %if.end

land.lhs.true30:
%vecext31 = extractelement <4 x float> %t, i32 3
%conv32 = fpext float %vecext31 to double
%cmp33 = fcmp ogt double %conv32, 1.000000e+00
br i1 %cmp33, label %if.then, label %if.end

if.then:
br label %return

if.end:
%vecext35 = extractelement <4 x float> %t, i32 0
%vecext36 = extractelement <4 x float> %t, i32 1
%add = fadd float %vecext35, %vecext36
br label %return

return:
%retval.0 = phi float [ 0.000000e+00, %if.then ], [ %add, %if.end ]
ret float %retval.0
}

define float @test_merge_anyof_v4sf(<4 x float> %t) {
; CHECK-LABEL: @test_merge_anyof_v4sf(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[VECEXT:%.*]] = extractelement <4 x float> [[T:%.*]], i32 0
; CHECK-NEXT: [[CMP:%.*]] = fcmp olt float [[VECEXT]], 0.000000e+00
; CHECK-NEXT: [[VECEXT2:%.*]] = extractelement <4 x float> [[T]], i32 1
; CHECK-NEXT: [[CMP4:%.*]] = fcmp olt float [[VECEXT2]], 0.000000e+00
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[CMP]], i1 true, i1 [[CMP4]]
; CHECK-NEXT: [[VECEXT7:%.*]] = extractelement <4 x float> [[T]], i32 2
; CHECK-NEXT: [[CMP9:%.*]] = fcmp olt float [[VECEXT7]], 0.000000e+00
; CHECK-NEXT: [[OR_COND1:%.*]] = select i1 [[OR_COND]], i1 true, i1 [[CMP9]]
; CHECK-NEXT: [[VECEXT12:%.*]] = extractelement <4 x float> [[T]], i32 3
; CHECK-NEXT: [[CMP14:%.*]] = fcmp olt float [[VECEXT12]], 0.000000e+00
; CHECK-NEXT: [[OR_COND2:%.*]] = select i1 [[OR_COND1]], i1 true, i1 [[CMP14]]
; CHECK-NEXT: [[CMP19:%.*]] = fcmp ogt float [[VECEXT]], 1.000000e+00
; CHECK-NEXT: [[OR_COND3:%.*]] = select i1 [[OR_COND2]], i1 true, i1 [[CMP19]]
; CHECK-NEXT: [[CMP24:%.*]] = fcmp ogt float [[VECEXT2]], 1.000000e+00
; CHECK-NEXT: [[OR_COND4:%.*]] = select i1 [[OR_COND3]], i1 true, i1 [[CMP24]]
; CHECK-NEXT: [[CMP29:%.*]] = fcmp ogt float [[VECEXT7]], 1.000000e+00
; CHECK-NEXT: [[OR_COND5:%.*]] = select i1 [[OR_COND4]], i1 true, i1 [[CMP29]]
; CHECK-NEXT: [[CMP34:%.*]] = fcmp ogt float [[VECEXT12]], 1.000000e+00
; CHECK-NEXT: [[OR_COND6:%.*]] = select i1 [[OR_COND5]], i1 true, i1 [[CMP34]]
; CHECK-NEXT: [[ADD:%.*]] = fadd float [[VECEXT]], [[VECEXT2]]
; CHECK-NEXT: [[RETVAL_0:%.*]] = select i1 [[OR_COND6]], float 0.000000e+00, float [[ADD]]
; CHECK-NEXT: ret float [[RETVAL_0]]
;
entry:
%vecext = extractelement <4 x float> %t, i32 0
%conv = fpext float %vecext to double
%cmp = fcmp olt double %conv, 0.000000e+00
br i1 %cmp, label %if.then, label %lor.lhs.false

lor.lhs.false:
%vecext2 = extractelement <4 x float> %t, i32 1
%conv3 = fpext float %vecext2 to double
%cmp4 = fcmp olt double %conv3, 0.000000e+00
br i1 %cmp4, label %if.then, label %lor.lhs.false6

lor.lhs.false6:
%vecext7 = extractelement <4 x float> %t, i32 2
%conv8 = fpext float %vecext7 to double
%cmp9 = fcmp olt double %conv8, 0.000000e+00
br i1 %cmp9, label %if.then, label %lor.lhs.false11

lor.lhs.false11:
%vecext12 = extractelement <4 x float> %t, i32 3
%conv13 = fpext float %vecext12 to double
%cmp14 = fcmp olt double %conv13, 0.000000e+00
br i1 %cmp14, label %if.then, label %lor.lhs.false16

lor.lhs.false16:
%vecext17 = extractelement <4 x float> %t, i32 0
%conv18 = fpext float %vecext17 to double
%cmp19 = fcmp ogt double %conv18, 1.000000e+00
br i1 %cmp19, label %if.then, label %lor.lhs.false21

lor.lhs.false21:
%vecext22 = extractelement <4 x float> %t, i32 1
%conv23 = fpext float %vecext22 to double
%cmp24 = fcmp ogt double %conv23, 1.000000e+00
br i1 %cmp24, label %if.then, label %lor.lhs.false26

lor.lhs.false26:
%vecext27 = extractelement <4 x float> %t, i32 2
%conv28 = fpext float %vecext27 to double
%cmp29 = fcmp ogt double %conv28, 1.000000e+00
br i1 %cmp29, label %if.then, label %lor.lhs.false31

lor.lhs.false31:
%vecext32 = extractelement <4 x float> %t, i32 3
%conv33 = fpext float %vecext32 to double
%cmp34 = fcmp ogt double %conv33, 1.000000e+00
br i1 %cmp34, label %if.then, label %if.end

if.then:
br label %return

if.end:
%vecext36 = extractelement <4 x float> %t, i32 0
%vecext37 = extractelement <4 x float> %t, i32 1
%add = fadd float %vecext36, %vecext37
br label %return

return:
%retval.0 = phi float [ 0.000000e+00, %if.then ], [ %add, %if.end ]
ret float %retval.0
}

define float @test_separate_allof_v4sf(<4 x float> %t) {
; CHECK-LABEL: @test_separate_allof_v4sf(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[VECEXT:%.*]] = extractelement <4 x float> [[T:%.*]], i32 0
; CHECK-NEXT: [[CMP:%.*]] = fcmp olt float [[VECEXT]], 0.000000e+00
; CHECK-NEXT: [[VECEXT2:%.*]] = extractelement <4 x float> [[T]], i32 1
; CHECK-NEXT: [[CMP4:%.*]] = fcmp olt float [[VECEXT2]], 0.000000e+00
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[CMP]], i1 [[CMP4]], i1 false
; CHECK-NEXT: [[VECEXT7:%.*]] = extractelement <4 x float> [[T]], i32 2
; CHECK-NEXT: [[CMP9:%.*]] = fcmp olt float [[VECEXT7]], 0.000000e+00
; CHECK-NEXT: [[OR_COND1:%.*]] = select i1 [[OR_COND]], i1 [[CMP9]], i1 false
; CHECK-NEXT: [[VECEXT12:%.*]] = extractelement <4 x float> [[T]], i32 3
; CHECK-NEXT: [[CMP14:%.*]] = fcmp olt float [[VECEXT12]], 0.000000e+00
; CHECK-NEXT: [[OR_COND2:%.*]] = select i1 [[OR_COND1]], i1 [[CMP14]], i1 false
; CHECK-NEXT: br i1 [[OR_COND2]], label [[COMMON_RET:%.*]], label [[IF_END:%.*]]
; CHECK: common.ret:
; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi float [ [[SPEC_SELECT:%.*]], [[IF_END]] ], [ 0.000000e+00, [[ENTRY:%.*]] ]
; CHECK-NEXT: ret float [[COMMON_RET_OP]]
; CHECK: if.end:
; CHECK-NEXT: [[CMP18:%.*]] = fcmp ogt float [[VECEXT]], 1.000000e+00
; CHECK-NEXT: [[CMP23:%.*]] = fcmp ogt float [[VECEXT2]], 1.000000e+00
; CHECK-NEXT: [[OR_COND3:%.*]] = select i1 [[CMP18]], i1 [[CMP23]], i1 false
; CHECK-NEXT: [[CMP28:%.*]] = fcmp ogt float [[VECEXT7]], 1.000000e+00
; CHECK-NEXT: [[OR_COND4:%.*]] = select i1 [[OR_COND3]], i1 [[CMP28]], i1 false
; CHECK-NEXT: [[CMP33:%.*]] = fcmp ogt float [[VECEXT12]], 1.000000e+00
; CHECK-NEXT: [[OR_COND5:%.*]] = select i1 [[OR_COND4]], i1 [[CMP33]], i1 false
; CHECK-NEXT: [[ADD:%.*]] = fadd float [[VECEXT]], [[VECEXT2]]
; CHECK-NEXT: [[SPEC_SELECT]] = select i1 [[OR_COND5]], float 0.000000e+00, float [[ADD]]
; CHECK-NEXT: br label [[COMMON_RET]]
;
entry:
%vecext = extractelement <4 x float> %t, i32 0
%conv = fpext float %vecext to double
%cmp = fcmp olt double %conv, 0.000000e+00
br i1 %cmp, label %land.lhs.true, label %if.end

land.lhs.true:
%vecext2 = extractelement <4 x float> %t, i32 1
%conv3 = fpext float %vecext2 to double
%cmp4 = fcmp olt double %conv3, 0.000000e+00
br i1 %cmp4, label %land.lhs.true6, label %if.end

land.lhs.true6:
%vecext7 = extractelement <4 x float> %t, i32 2
%conv8 = fpext float %vecext7 to double
%cmp9 = fcmp olt double %conv8, 0.000000e+00
br i1 %cmp9, label %land.lhs.true11, label %if.end

land.lhs.true11:
%vecext12 = extractelement <4 x float> %t, i32 3
%conv13 = fpext float %vecext12 to double
%cmp14 = fcmp olt double %conv13, 0.000000e+00
br i1 %cmp14, label %if.then, label %if.end

if.then:
br label %return

if.end:
%vecext16 = extractelement <4 x float> %t, i32 0
%conv17 = fpext float %vecext16 to double
%cmp18 = fcmp ogt double %conv17, 1.000000e+00
br i1 %cmp18, label %land.lhs.true20, label %if.end36

land.lhs.true20:
%vecext21 = extractelement <4 x float> %t, i32 1
%conv22 = fpext float %vecext21 to double
%cmp23 = fcmp ogt double %conv22, 1.000000e+00
br i1 %cmp23, label %land.lhs.true25, label %if.end36

land.lhs.true25:
%vecext26 = extractelement <4 x float> %t, i32 2
%conv27 = fpext float %vecext26 to double
%cmp28 = fcmp ogt double %conv27, 1.000000e+00
br i1 %cmp28, label %land.lhs.true30, label %if.end36

land.lhs.true30:
%vecext31 = extractelement <4 x float> %t, i32 3
%conv32 = fpext float %vecext31 to double
%cmp33 = fcmp ogt double %conv32, 1.000000e+00
br i1 %cmp33, label %if.then35, label %if.end36

if.then35:
br label %return

if.end36:
%vecext37 = extractelement <4 x float> %t, i32 0
%vecext38 = extractelement <4 x float> %t, i32 1
%add = fadd float %vecext37, %vecext38
br label %return

return:
%retval.0 = phi float [ 0.000000e+00, %if.then ], [ 0.000000e+00, %if.then35 ], [ %add, %if.end36 ]
ret float %retval.0
}

define float @test_separate_anyof_v4sf(<4 x float> %t) {
; CHECK-LABEL: @test_separate_anyof_v4sf(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[VECEXT:%.*]] = extractelement <4 x float> [[T:%.*]], i32 0
; CHECK-NEXT: [[CMP:%.*]] = fcmp olt float [[VECEXT]], 0.000000e+00
; CHECK-NEXT: [[VECEXT2:%.*]] = extractelement <4 x float> [[T]], i32 1
; CHECK-NEXT: [[CMP4:%.*]] = fcmp olt float [[VECEXT2]], 0.000000e+00
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[CMP]], i1 true, i1 [[CMP4]]
; CHECK-NEXT: [[VECEXT7:%.*]] = extractelement <4 x float> [[T]], i32 2
; CHECK-NEXT: [[CMP9:%.*]] = fcmp olt float [[VECEXT7]], 0.000000e+00
; CHECK-NEXT: [[OR_COND1:%.*]] = select i1 [[OR_COND]], i1 true, i1 [[CMP9]]
; CHECK-NEXT: [[VECEXT12:%.*]] = extractelement <4 x float> [[T]], i32 3
; CHECK-NEXT: [[CMP14:%.*]] = fcmp olt float [[VECEXT12]], 0.000000e+00
; CHECK-NEXT: [[OR_COND2:%.*]] = select i1 [[OR_COND1]], i1 true, i1 [[CMP14]]
; CHECK-NEXT: [[CMP18:%.*]] = fcmp ogt float [[VECEXT]], 1.000000e+00
; CHECK-NEXT: [[OR_COND3:%.*]] = select i1 [[OR_COND2]], i1 true, i1 [[CMP18]]
; CHECK-NEXT: [[CMP23:%.*]] = fcmp ogt float [[VECEXT2]], 1.000000e+00
; CHECK-NEXT: [[OR_COND4:%.*]] = select i1 [[OR_COND3]], i1 true, i1 [[CMP23]]
; CHECK-NEXT: [[CMP28:%.*]] = fcmp ogt float [[VECEXT7]], 1.000000e+00
; CHECK-NEXT: [[OR_COND5:%.*]] = select i1 [[OR_COND4]], i1 true, i1 [[CMP28]]
; CHECK-NEXT: [[CMP33:%.*]] = fcmp ogt float [[VECEXT12]], 1.000000e+00
; CHECK-NEXT: [[OR_COND6:%.*]] = select i1 [[OR_COND5]], i1 true, i1 [[CMP33]]
; CHECK-NEXT: [[ADD:%.*]] = fadd float [[VECEXT]], [[VECEXT2]]
; CHECK-NEXT: [[RETVAL_0:%.*]] = select i1 [[OR_COND6]], float 0.000000e+00, float [[ADD]]
; CHECK-NEXT: ret float [[RETVAL_0]]
;
entry:
%vecext = extractelement <4 x float> %t, i32 0
%conv = fpext float %vecext to double
%cmp = fcmp olt double %conv, 0.000000e+00
br i1 %cmp, label %if.then, label %lor.lhs.false

lor.lhs.false:
%vecext2 = extractelement <4 x float> %t, i32 1
%conv3 = fpext float %vecext2 to double
%cmp4 = fcmp olt double %conv3, 0.000000e+00
br i1 %cmp4, label %if.then, label %lor.lhs.false6

lor.lhs.false6:
%vecext7 = extractelement <4 x float> %t, i32 2
%conv8 = fpext float %vecext7 to double
%cmp9 = fcmp olt double %conv8, 0.000000e+00
br i1 %cmp9, label %if.then, label %lor.lhs.false11

lor.lhs.false11:
%vecext12 = extractelement <4 x float> %t, i32 3
%conv13 = fpext float %vecext12 to double
%cmp14 = fcmp olt double %conv13, 0.000000e+00
br i1 %cmp14, label %if.then, label %if.end

if.then:
br label %return

if.end:
%vecext16 = extractelement <4 x float> %t, i32 0
%conv17 = fpext float %vecext16 to double
%cmp18 = fcmp ogt double %conv17, 1.000000e+00
br i1 %cmp18, label %if.then35, label %lor.lhs.false20

lor.lhs.false20:
%vecext21 = extractelement <4 x float> %t, i32 1
%conv22 = fpext float %vecext21 to double
%cmp23 = fcmp ogt double %conv22, 1.000000e+00
br i1 %cmp23, label %if.then35, label %lor.lhs.false25

lor.lhs.false25:
%vecext26 = extractelement <4 x float> %t, i32 2
%conv27 = fpext float %vecext26 to double
%cmp28 = fcmp ogt double %conv27, 1.000000e+00
br i1 %cmp28, label %if.then35, label %lor.lhs.false30

lor.lhs.false30:
%vecext31 = extractelement <4 x float> %t, i32 3
%conv32 = fpext float %vecext31 to double
%cmp33 = fcmp ogt double %conv32, 1.000000e+00
br i1 %cmp33, label %if.then35, label %if.end36

if.then35:
br label %return

if.end36:
%vecext37 = extractelement <4 x float> %t, i32 0
%vecext38 = extractelement <4 x float> %t, i32 1
%add = fadd float %vecext37, %vecext38
br label %return

return:
%retval.0 = phi float [ 0.000000e+00, %if.then ], [ 0.000000e+00, %if.then35 ], [ %add, %if.end36 ]
ret float %retval.0
}

define float @test_merge_allof_v4si(<4 x i32> %t) {
; CHECK-LABEL: @test_merge_allof_v4si(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[VECEXT:%.*]] = extractelement <4 x i32> [[T:%.*]], i32 0
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[VECEXT]], 1
; CHECK-NEXT: [[VECEXT1:%.*]] = extractelement <4 x i32> [[T]], i32 1
; CHECK-NEXT: [[CMP2:%.*]] = icmp slt i32 [[VECEXT1]], 1
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[CMP]], i1 [[CMP2]], i1 false
; CHECK-NEXT: [[VECEXT4:%.*]] = extractelement <4 x i32> [[T]], i32 2
; CHECK-NEXT: [[CMP5:%.*]] = icmp slt i32 [[VECEXT4]], 1
; CHECK-NEXT: [[OR_COND1:%.*]] = select i1 [[OR_COND]], i1 [[CMP5]], i1 false
; CHECK-NEXT: [[VECEXT7:%.*]] = extractelement <4 x i32> [[T]], i32 3
; CHECK-NEXT: [[CMP8:%.*]] = icmp slt i32 [[VECEXT7]], 1
; CHECK-NEXT: [[OR_COND2:%.*]] = select i1 [[OR_COND1]], i1 [[CMP8]], i1 false
; CHECK-NEXT: br i1 [[OR_COND2]], label [[RETURN:%.*]], label [[LOR_LHS_FALSE:%.*]]
; CHECK: lor.lhs.false:
; CHECK-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[VECEXT]], 255
; CHECK-NEXT: [[CMP13:%.*]] = icmp sgt i32 [[VECEXT1]], 255
; CHECK-NEXT: [[OR_COND3:%.*]] = select i1 [[CMP10]], i1 [[CMP13]], i1 false
; CHECK-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[VECEXT4]], 255
; CHECK-NEXT: [[OR_COND4:%.*]] = select i1 [[OR_COND3]], i1 [[CMP16]], i1 false
; CHECK-NEXT: [[CMP19:%.*]] = icmp sgt i32 [[VECEXT7]], 255
; CHECK-NEXT: [[OR_COND5:%.*]] = select i1 [[OR_COND4]], i1 [[CMP19]], i1 false
; CHECK-NEXT: br i1 [[OR_COND5]], label [[RETURN]], label [[IF_END:%.*]]
; CHECK: if.end:
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[VECEXT]], [[VECEXT1]]
; CHECK-NEXT: [[CONV:%.*]] = sitofp i32 [[ADD]] to float
; CHECK-NEXT: br label [[RETURN]]
; CHECK: return:
; CHECK-NEXT: [[RETVAL_0:%.*]] = phi float [ [[CONV]], [[IF_END]] ], [ 0.000000e+00, [[LOR_LHS_FALSE]] ], [ 0.000000e+00, [[ENTRY:%.*]] ]
; CHECK-NEXT: ret float [[RETVAL_0]]
;
entry:
%vecext = extractelement <4 x i32> %t, i32 0
%cmp = icmp slt i32 %vecext, 1
br i1 %cmp, label %land.lhs.true, label %lor.lhs.false

land.lhs.true:
%vecext1 = extractelement <4 x i32> %t, i32 1
%cmp2 = icmp slt i32 %vecext1, 1
br i1 %cmp2, label %land.lhs.true3, label %lor.lhs.false

land.lhs.true3:
%vecext4 = extractelement <4 x i32> %t, i32 2
%cmp5 = icmp slt i32 %vecext4, 1
br i1 %cmp5, label %land.lhs.true6, label %lor.lhs.false

land.lhs.true6:
%vecext7 = extractelement <4 x i32> %t, i32 3
%cmp8 = icmp slt i32 %vecext7, 1
br i1 %cmp8, label %if.then, label %lor.lhs.false

lor.lhs.false:
%vecext9 = extractelement <4 x i32> %t, i32 0
%cmp10 = icmp sgt i32 %vecext9, 255
br i1 %cmp10, label %land.lhs.true11, label %if.end

land.lhs.true11:
%vecext12 = extractelement <4 x i32> %t, i32 1
%cmp13 = icmp sgt i32 %vecext12, 255
br i1 %cmp13, label %land.lhs.true14, label %if.end

land.lhs.true14:
%vecext15 = extractelement <4 x i32> %t, i32 2
%cmp16 = icmp sgt i32 %vecext15, 255
br i1 %cmp16, label %land.lhs.true17, label %if.end

land.lhs.true17:
%vecext18 = extractelement <4 x i32> %t, i32 3
%cmp19 = icmp sgt i32 %vecext18, 255
br i1 %cmp19, label %if.then, label %if.end

if.then:
br label %return

if.end:
%vecext20 = extractelement <4 x i32> %t, i32 0
%vecext21 = extractelement <4 x i32> %t, i32 1
%add = add nsw i32 %vecext20, %vecext21
%conv = sitofp i32 %add to float
br label %return

return:
%retval.0 = phi float [ 0.000000e+00, %if.then ], [ %conv, %if.end ]
ret float %retval.0
}

define float @test_merge_anyof_v4si(<4 x i32> %t) {
; CHECK-LABEL: @test_merge_anyof_v4si(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[VECEXT:%.*]] = extractelement <4 x i32> [[T:%.*]], i32 0
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[VECEXT]], 1
; CHECK-NEXT: [[VECEXT1:%.*]] = extractelement <4 x i32> [[T]], i32 1
; CHECK-NEXT: [[CMP2:%.*]] = icmp slt i32 [[VECEXT1]], 1
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[CMP]], i1 true, i1 [[CMP2]]
; CHECK-NEXT: [[VECEXT4:%.*]] = extractelement <4 x i32> [[T]], i32 2
; CHECK-NEXT: [[CMP5:%.*]] = icmp slt i32 [[VECEXT4]], 1
; CHECK-NEXT: [[OR_COND1:%.*]] = select i1 [[OR_COND]], i1 true, i1 [[CMP5]]
; CHECK-NEXT: [[VECEXT7:%.*]] = extractelement <4 x i32> [[T]], i32 3
; CHECK-NEXT: [[CMP8:%.*]] = icmp slt i32 [[VECEXT7]], 1
; CHECK-NEXT: [[OR_COND2:%.*]] = select i1 [[OR_COND1]], i1 true, i1 [[CMP8]]
; CHECK-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[VECEXT]], 255
; CHECK-NEXT: [[OR_COND3:%.*]] = select i1 [[OR_COND2]], i1 true, i1 [[CMP11]]
; CHECK-NEXT: [[CMP14:%.*]] = icmp sgt i32 [[VECEXT1]], 255
; CHECK-NEXT: [[OR_COND4:%.*]] = select i1 [[OR_COND3]], i1 true, i1 [[CMP14]]
; CHECK-NEXT: [[CMP17:%.*]] = icmp sgt i32 [[VECEXT4]], 255
; CHECK-NEXT: [[OR_COND5:%.*]] = select i1 [[OR_COND4]], i1 true, i1 [[CMP17]]
; CHECK-NEXT: [[CMP20:%.*]] = icmp sgt i32 [[VECEXT7]], 255
; CHECK-NEXT: [[OR_COND6:%.*]] = select i1 [[OR_COND5]], i1 true, i1 [[CMP20]]
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[VECEXT]], [[VECEXT1]]
; CHECK-NEXT: [[CONV:%.*]] = sitofp i32 [[ADD]] to float
; CHECK-NEXT: [[RETVAL_0:%.*]] = select i1 [[OR_COND6]], float 0.000000e+00, float [[CONV]]
; CHECK-NEXT: ret float [[RETVAL_0]]
;
entry:
%vecext = extractelement <4 x i32> %t, i32 0
%cmp = icmp slt i32 %vecext, 1
br i1 %cmp, label %if.then, label %lor.lhs.false

lor.lhs.false:
%vecext1 = extractelement <4 x i32> %t, i32 1
%cmp2 = icmp slt i32 %vecext1, 1
br i1 %cmp2, label %if.then, label %lor.lhs.false3

lor.lhs.false3:
%vecext4 = extractelement <4 x i32> %t, i32 2
%cmp5 = icmp slt i32 %vecext4, 1
br i1 %cmp5, label %if.then, label %lor.lhs.false6

lor.lhs.false6:
%vecext7 = extractelement <4 x i32> %t, i32 3
%cmp8 = icmp slt i32 %vecext7, 1
br i1 %cmp8, label %if.then, label %lor.lhs.false9

lor.lhs.false9:
%vecext10 = extractelement <4 x i32> %t, i32 0
%cmp11 = icmp sgt i32 %vecext10, 255
br i1 %cmp11, label %if.then, label %lor.lhs.false12

lor.lhs.false12:
%vecext13 = extractelement <4 x i32> %t, i32 1
%cmp14 = icmp sgt i32 %vecext13, 255
br i1 %cmp14, label %if.then, label %lor.lhs.false15

lor.lhs.false15:
%vecext16 = extractelement <4 x i32> %t, i32 2
%cmp17 = icmp sgt i32 %vecext16, 255
br i1 %cmp17, label %if.then, label %lor.lhs.false18

lor.lhs.false18:
%vecext19 = extractelement <4 x i32> %t, i32 3
%cmp20 = icmp sgt i32 %vecext19, 255
br i1 %cmp20, label %if.then, label %if.end

if.then:
br label %return

if.end:
%vecext21 = extractelement <4 x i32> %t, i32 0
%vecext22 = extractelement <4 x i32> %t, i32 1
%add = add nsw i32 %vecext21, %vecext22
%conv = sitofp i32 %add to float
br label %return

return:
%retval.0 = phi float [ 0.000000e+00, %if.then ], [ %conv, %if.end ]
ret float %retval.0
}

define i32 @test_separate_allof_v4si(<4 x i32> %t) {
; CHECK-LABEL: @test_separate_allof_v4si(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[VECEXT:%.*]] = extractelement <4 x i32> [[T:%.*]], i32 0
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[VECEXT]], 1
; CHECK-NEXT: [[VECEXT1:%.*]] = extractelement <4 x i32> [[T]], i32 1
; CHECK-NEXT: [[CMP2:%.*]] = icmp slt i32 [[VECEXT1]], 1
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[CMP]], i1 [[CMP2]], i1 false
; CHECK-NEXT: [[VECEXT4:%.*]] = extractelement <4 x i32> [[T]], i32 2
; CHECK-NEXT: [[CMP5:%.*]] = icmp slt i32 [[VECEXT4]], 1
; CHECK-NEXT: [[OR_COND1:%.*]] = select i1 [[OR_COND]], i1 [[CMP5]], i1 false
; CHECK-NEXT: [[VECEXT7:%.*]] = extractelement <4 x i32> [[T]], i32 3
; CHECK-NEXT: [[CMP8:%.*]] = icmp slt i32 [[VECEXT7]], 1
; CHECK-NEXT: [[OR_COND2:%.*]] = select i1 [[OR_COND1]], i1 [[CMP8]], i1 false
; CHECK-NEXT: br i1 [[OR_COND2]], label [[COMMON_RET:%.*]], label [[IF_END:%.*]]
; CHECK: common.ret:
; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i32 [ [[SPEC_SELECT:%.*]], [[IF_END]] ], [ 0, [[ENTRY:%.*]] ]
; CHECK-NEXT: ret i32 [[COMMON_RET_OP]]
; CHECK: if.end:
; CHECK-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[VECEXT]], 255
; CHECK-NEXT: [[CMP13:%.*]] = icmp sgt i32 [[VECEXT1]], 255
; CHECK-NEXT: [[OR_COND3:%.*]] = select i1 [[CMP10]], i1 [[CMP13]], i1 false
; CHECK-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[VECEXT4]], 255
; CHECK-NEXT: [[OR_COND4:%.*]] = select i1 [[OR_COND3]], i1 [[CMP16]], i1 false
; CHECK-NEXT: [[CMP19:%.*]] = icmp sgt i32 [[VECEXT7]], 255
; CHECK-NEXT: [[OR_COND5:%.*]] = select i1 [[OR_COND4]], i1 [[CMP19]], i1 false
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[VECEXT]], [[VECEXT1]]
; CHECK-NEXT: [[SPEC_SELECT]] = select i1 [[OR_COND5]], i32 0, i32 [[ADD]]
; CHECK-NEXT: br label [[COMMON_RET]]
;
entry:
%vecext = extractelement <4 x i32> %t, i32 0
%cmp = icmp slt i32 %vecext, 1
br i1 %cmp, label %land.lhs.true, label %if.end

land.lhs.true:
%vecext1 = extractelement <4 x i32> %t, i32 1
%cmp2 = icmp slt i32 %vecext1, 1
br i1 %cmp2, label %land.lhs.true3, label %if.end

land.lhs.true3:
%vecext4 = extractelement <4 x i32> %t, i32 2
%cmp5 = icmp slt i32 %vecext4, 1
br i1 %cmp5, label %land.lhs.true6, label %if.end

land.lhs.true6:
%vecext7 = extractelement <4 x i32> %t, i32 3
%cmp8 = icmp slt i32 %vecext7, 1
br i1 %cmp8, label %if.then, label %if.end

if.then:
br label %return

if.end:
%vecext9 = extractelement <4 x i32> %t, i32 0
%cmp10 = icmp sgt i32 %vecext9, 255
br i1 %cmp10, label %land.lhs.true11, label %if.end21

land.lhs.true11:
%vecext12 = extractelement <4 x i32> %t, i32 1
%cmp13 = icmp sgt i32 %vecext12, 255
br i1 %cmp13, label %land.lhs.true14, label %if.end21

land.lhs.true14:
%vecext15 = extractelement <4 x i32> %t, i32 2
%cmp16 = icmp sgt i32 %vecext15, 255
br i1 %cmp16, label %land.lhs.true17, label %if.end21

land.lhs.true17:
%vecext18 = extractelement <4 x i32> %t, i32 3
%cmp19 = icmp sgt i32 %vecext18, 255
br i1 %cmp19, label %if.then20, label %if.end21

if.then20:
br label %return

if.end21:
%vecext22 = extractelement <4 x i32> %t, i32 0
%vecext23 = extractelement <4 x i32> %t, i32 1
%add = add nsw i32 %vecext22, %vecext23
br label %return

return:
%retval.0 = phi i32 [ 0, %if.then ], [ 0, %if.then20 ], [ %add, %if.end21 ]
ret i32 %retval.0
}

define i32 @test_separate_anyof_v4si(<4 x i32> %t) {
; CHECK-LABEL: @test_separate_anyof_v4si(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[VECEXT:%.*]] = extractelement <4 x i32> [[T:%.*]], i32 0
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[VECEXT]], 1
; CHECK-NEXT: [[VECEXT1:%.*]] = extractelement <4 x i32> [[T]], i32 1
; CHECK-NEXT: [[CMP2:%.*]] = icmp slt i32 [[VECEXT1]], 1
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[CMP]], i1 true, i1 [[CMP2]]
; CHECK-NEXT: [[VECEXT4:%.*]] = extractelement <4 x i32> [[T]], i32 2
; CHECK-NEXT: [[CMP5:%.*]] = icmp slt i32 [[VECEXT4]], 1
; CHECK-NEXT: [[OR_COND1:%.*]] = select i1 [[OR_COND]], i1 true, i1 [[CMP5]]
; CHECK-NEXT: [[VECEXT7:%.*]] = extractelement <4 x i32> [[T]], i32 3
; CHECK-NEXT: [[CMP8:%.*]] = icmp slt i32 [[VECEXT7]], 1
; CHECK-NEXT: [[OR_COND2:%.*]] = select i1 [[OR_COND1]], i1 true, i1 [[CMP8]]
; CHECK-NEXT: br i1 [[OR_COND2]], label [[COMMON_RET:%.*]], label [[IF_END:%.*]]
; CHECK: common.ret:
; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i32 [ [[SPEC_SELECT:%.*]], [[IF_END]] ], [ 0, [[ENTRY:%.*]] ]
; CHECK-NEXT: ret i32 [[COMMON_RET_OP]]
; CHECK: if.end:
; CHECK-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[VECEXT]], 255
; CHECK-NEXT: [[CMP13:%.*]] = icmp sgt i32 [[VECEXT1]], 255
; CHECK-NEXT: [[OR_COND3:%.*]] = select i1 [[CMP10]], i1 true, i1 [[CMP13]]
; CHECK-NEXT: [[CMP16:%.*]] = icmp sgt i32 [[VECEXT4]], 255
; CHECK-NEXT: [[OR_COND4:%.*]] = select i1 [[OR_COND3]], i1 true, i1 [[CMP16]]
; CHECK-NEXT: [[CMP19:%.*]] = icmp sgt i32 [[VECEXT7]], 255
; CHECK-NEXT: [[OR_COND5:%.*]] = select i1 [[OR_COND4]], i1 true, i1 [[CMP19]]
; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[VECEXT]], [[VECEXT1]]
; CHECK-NEXT: [[SPEC_SELECT]] = select i1 [[OR_COND5]], i32 0, i32 [[ADD]]
; CHECK-NEXT: br label [[COMMON_RET]]
;
entry:
%vecext = extractelement <4 x i32> %t, i32 0
%cmp = icmp slt i32 %vecext, 1
br i1 %cmp, label %if.then, label %lor.lhs.false

lor.lhs.false:
%vecext1 = extractelement <4 x i32> %t, i32 1
%cmp2 = icmp slt i32 %vecext1, 1
br i1 %cmp2, label %if.then, label %lor.lhs.false3

lor.lhs.false3:
%vecext4 = extractelement <4 x i32> %t, i32 2
%cmp5 = icmp slt i32 %vecext4, 1
br i1 %cmp5, label %if.then, label %lor.lhs.false6

lor.lhs.false6:
%vecext7 = extractelement <4 x i32> %t, i32 3
%cmp8 = icmp slt i32 %vecext7, 1
br i1 %cmp8, label %if.then, label %if.end

if.then:
br label %return

if.end:
%vecext9 = extractelement <4 x i32> %t, i32 0
%cmp10 = icmp sgt i32 %vecext9, 255
br i1 %cmp10, label %if.then20, label %lor.lhs.false11

lor.lhs.false11:
%vecext12 = extractelement <4 x i32> %t, i32 1
%cmp13 = icmp sgt i32 %vecext12, 255
br i1 %cmp13, label %if.then20, label %lor.lhs.false14

lor.lhs.false14:
%vecext15 = extractelement <4 x i32> %t, i32 2
%cmp16 = icmp sgt i32 %vecext15, 255
br i1 %cmp16, label %if.then20, label %lor.lhs.false17

lor.lhs.false17:
%vecext18 = extractelement <4 x i32> %t, i32 3
%cmp19 = icmp sgt i32 %vecext18, 255
br i1 %cmp19, label %if.then20, label %if.end21

if.then20:
br label %return

if.end21:
%vecext22 = extractelement <4 x i32> %t, i32 0
%vecext23 = extractelement <4 x i32> %t, i32 1
%add = add nsw i32 %vecext22, %vecext23
br label %return

return:
%retval.0 = phi i32 [ 0, %if.then ], [ 0, %if.then20 ], [ %add, %if.end21 ]
ret i32 %retval.0
}
213 changes: 213 additions & 0 deletions llvm/test/Transforms/SLPVectorizer/X86/reduction-logical.ll
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,213 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -slp-vectorizer -mtriple=x86_64-- -S | FileCheck %s

define i1 @logical_and_icmp(<4 x i32> %x) {
; CHECK-LABEL: @logical_and_icmp(
; CHECK-NEXT: [[X0:%.*]] = extractelement <4 x i32> [[X:%.*]], i32 0
; CHECK-NEXT: [[X1:%.*]] = extractelement <4 x i32> [[X]], i32 1
; CHECK-NEXT: [[X2:%.*]] = extractelement <4 x i32> [[X]], i32 2
; CHECK-NEXT: [[X3:%.*]] = extractelement <4 x i32> [[X]], i32 3
; CHECK-NEXT: [[C0:%.*]] = icmp slt i32 [[X0]], 0
; CHECK-NEXT: [[C1:%.*]] = icmp slt i32 [[X1]], 0
; CHECK-NEXT: [[C2:%.*]] = icmp slt i32 [[X2]], 0
; CHECK-NEXT: [[C3:%.*]] = icmp slt i32 [[X3]], 0
; CHECK-NEXT: [[S1:%.*]] = select i1 [[C0]], i1 [[C1]], i1 false
; CHECK-NEXT: [[S2:%.*]] = select i1 [[S1]], i1 [[C2]], i1 false
; CHECK-NEXT: [[S3:%.*]] = select i1 [[S2]], i1 [[C3]], i1 false
; CHECK-NEXT: ret i1 [[S3]]
;
%x0 = extractelement <4 x i32> %x, i32 0
%x1 = extractelement <4 x i32> %x, i32 1
%x2 = extractelement <4 x i32> %x, i32 2
%x3 = extractelement <4 x i32> %x, i32 3
%c0 = icmp slt i32 %x0, 0
%c1 = icmp slt i32 %x1, 0
%c2 = icmp slt i32 %x2, 0
%c3 = icmp slt i32 %x3, 0
%s1 = select i1 %c0, i1 %c1, i1 false
%s2 = select i1 %s1, i1 %c2, i1 false
%s3 = select i1 %s2, i1 %c3, i1 false
ret i1 %s3
}

define i1 @logical_or_icmp(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: @logical_or_icmp(
; CHECK-NEXT: [[X0:%.*]] = extractelement <4 x i32> [[X:%.*]], i32 0
; CHECK-NEXT: [[X1:%.*]] = extractelement <4 x i32> [[X]], i32 1
; CHECK-NEXT: [[X2:%.*]] = extractelement <4 x i32> [[X]], i32 2
; CHECK-NEXT: [[X3:%.*]] = extractelement <4 x i32> [[X]], i32 3
; CHECK-NEXT: [[Y0:%.*]] = extractelement <4 x i32> [[Y:%.*]], i32 0
; CHECK-NEXT: [[Y1:%.*]] = extractelement <4 x i32> [[Y]], i32 1
; CHECK-NEXT: [[Y2:%.*]] = extractelement <4 x i32> [[Y]], i32 2
; CHECK-NEXT: [[Y3:%.*]] = extractelement <4 x i32> [[Y]], i32 3
; CHECK-NEXT: [[C0:%.*]] = icmp slt i32 [[X0]], [[Y0]]
; CHECK-NEXT: [[C1:%.*]] = icmp slt i32 [[X1]], [[Y1]]
; CHECK-NEXT: [[C2:%.*]] = icmp slt i32 [[X2]], [[Y2]]
; CHECK-NEXT: [[C3:%.*]] = icmp slt i32 [[X3]], [[Y3]]
; CHECK-NEXT: [[S1:%.*]] = select i1 [[C0]], i1 true, i1 [[C1]]
; CHECK-NEXT: [[S2:%.*]] = select i1 [[S1]], i1 true, i1 [[C2]]
; CHECK-NEXT: [[S3:%.*]] = select i1 [[S2]], i1 true, i1 [[C3]]
; CHECK-NEXT: ret i1 [[S3]]
;
%x0 = extractelement <4 x i32> %x, i32 0
%x1 = extractelement <4 x i32> %x, i32 1
%x2 = extractelement <4 x i32> %x, i32 2
%x3 = extractelement <4 x i32> %x, i32 3
%y0 = extractelement <4 x i32> %y, i32 0
%y1 = extractelement <4 x i32> %y, i32 1
%y2 = extractelement <4 x i32> %y, i32 2
%y3 = extractelement <4 x i32> %y, i32 3
%c0 = icmp slt i32 %x0, %y0
%c1 = icmp slt i32 %x1, %y1
%c2 = icmp slt i32 %x2, %y2
%c3 = icmp slt i32 %x3, %y3
%s1 = select i1 %c0, i1 true, i1 %c1
%s2 = select i1 %s1, i1 true, i1 %c2
%s3 = select i1 %s2, i1 true, i1 %c3
ret i1 %s3
}

define i1 @logical_and_fcmp(<4 x float> %x) {
; CHECK-LABEL: @logical_and_fcmp(
; CHECK-NEXT: [[X0:%.*]] = extractelement <4 x float> [[X:%.*]], i32 0
; CHECK-NEXT: [[X1:%.*]] = extractelement <4 x float> [[X]], i32 1
; CHECK-NEXT: [[X2:%.*]] = extractelement <4 x float> [[X]], i32 2
; CHECK-NEXT: [[X3:%.*]] = extractelement <4 x float> [[X]], i32 3
; CHECK-NEXT: [[C0:%.*]] = fcmp olt float [[X0]], 0.000000e+00
; CHECK-NEXT: [[C1:%.*]] = fcmp olt float [[X1]], 0.000000e+00
; CHECK-NEXT: [[C2:%.*]] = fcmp olt float [[X2]], 0.000000e+00
; CHECK-NEXT: [[C3:%.*]] = fcmp olt float [[X3]], 0.000000e+00
; CHECK-NEXT: [[S1:%.*]] = select i1 [[C0]], i1 [[C1]], i1 false
; CHECK-NEXT: [[S2:%.*]] = select i1 [[S1]], i1 [[C2]], i1 false
; CHECK-NEXT: [[S3:%.*]] = select i1 [[S2]], i1 [[C3]], i1 false
; CHECK-NEXT: ret i1 [[S3]]
;
%x0 = extractelement <4 x float> %x, i32 0
%x1 = extractelement <4 x float> %x, i32 1
%x2 = extractelement <4 x float> %x, i32 2
%x3 = extractelement <4 x float> %x, i32 3
%c0 = fcmp olt float %x0, 0.0
%c1 = fcmp olt float %x1, 0.0
%c2 = fcmp olt float %x2, 0.0
%c3 = fcmp olt float %x3, 0.0
%s1 = select i1 %c0, i1 %c1, i1 false
%s2 = select i1 %s1, i1 %c2, i1 false
%s3 = select i1 %s2, i1 %c3, i1 false
ret i1 %s3
}

define i1 @logical_or_fcmp(<4 x float> %x) {
; CHECK-LABEL: @logical_or_fcmp(
; CHECK-NEXT: [[X0:%.*]] = extractelement <4 x float> [[X:%.*]], i32 0
; CHECK-NEXT: [[X1:%.*]] = extractelement <4 x float> [[X]], i32 1
; CHECK-NEXT: [[X2:%.*]] = extractelement <4 x float> [[X]], i32 2
; CHECK-NEXT: [[X3:%.*]] = extractelement <4 x float> [[X]], i32 3
; CHECK-NEXT: [[C0:%.*]] = fcmp olt float [[X0]], 0.000000e+00
; CHECK-NEXT: [[C1:%.*]] = fcmp olt float [[X1]], 0.000000e+00
; CHECK-NEXT: [[C2:%.*]] = fcmp olt float [[X2]], 0.000000e+00
; CHECK-NEXT: [[C3:%.*]] = fcmp olt float [[X3]], 0.000000e+00
; CHECK-NEXT: [[S1:%.*]] = select i1 [[C0]], i1 true, i1 [[C1]]
; CHECK-NEXT: [[S2:%.*]] = select i1 [[S1]], i1 true, i1 [[C2]]
; CHECK-NEXT: [[S3:%.*]] = select i1 [[S2]], i1 true, i1 [[C3]]
; CHECK-NEXT: ret i1 [[S3]]
;
%x0 = extractelement <4 x float> %x, i32 0
%x1 = extractelement <4 x float> %x, i32 1
%x2 = extractelement <4 x float> %x, i32 2
%x3 = extractelement <4 x float> %x, i32 3
%c0 = fcmp olt float %x0, 0.0
%c1 = fcmp olt float %x1, 0.0
%c2 = fcmp olt float %x2, 0.0
%c3 = fcmp olt float %x3, 0.0
%s1 = select i1 %c0, i1 true, i1 %c1
%s2 = select i1 %s1, i1 true, i1 %c2
%s3 = select i1 %s2, i1 true, i1 %c3
ret i1 %s3
}

define i1 @logical_and_icmp_diff_preds(<4 x i32> %x) {
; CHECK-LABEL: @logical_and_icmp_diff_preds(
; CHECK-NEXT: [[X0:%.*]] = extractelement <4 x i32> [[X:%.*]], i32 0
; CHECK-NEXT: [[X1:%.*]] = extractelement <4 x i32> [[X]], i32 1
; CHECK-NEXT: [[X2:%.*]] = extractelement <4 x i32> [[X]], i32 2
; CHECK-NEXT: [[X3:%.*]] = extractelement <4 x i32> [[X]], i32 3
; CHECK-NEXT: [[C0:%.*]] = icmp ult i32 [[X0]], 0
; CHECK-NEXT: [[C1:%.*]] = icmp slt i32 [[X1]], 0
; CHECK-NEXT: [[C2:%.*]] = icmp sgt i32 [[X2]], 0
; CHECK-NEXT: [[C3:%.*]] = icmp slt i32 [[X3]], 0
; CHECK-NEXT: [[S1:%.*]] = select i1 [[C0]], i1 [[C1]], i1 false
; CHECK-NEXT: [[S2:%.*]] = select i1 [[S1]], i1 [[C2]], i1 false
; CHECK-NEXT: [[S3:%.*]] = select i1 [[S2]], i1 [[C3]], i1 false
; CHECK-NEXT: ret i1 [[S3]]
;
%x0 = extractelement <4 x i32> %x, i32 0
%x1 = extractelement <4 x i32> %x, i32 1
%x2 = extractelement <4 x i32> %x, i32 2
%x3 = extractelement <4 x i32> %x, i32 3
%c0 = icmp ult i32 %x0, 0
%c1 = icmp slt i32 %x1, 0
%c2 = icmp sgt i32 %x2, 0
%c3 = icmp slt i32 %x3, 0
%s1 = select i1 %c0, i1 %c1, i1 false
%s2 = select i1 %s1, i1 %c2, i1 false
%s3 = select i1 %s2, i1 %c3, i1 false
ret i1 %s3
}

define i1 @logical_and_icmp_diff_const(<4 x i32> %x) {
; CHECK-LABEL: @logical_and_icmp_diff_const(
; CHECK-NEXT: [[X0:%.*]] = extractelement <4 x i32> [[X:%.*]], i32 0
; CHECK-NEXT: [[X1:%.*]] = extractelement <4 x i32> [[X]], i32 1
; CHECK-NEXT: [[X2:%.*]] = extractelement <4 x i32> [[X]], i32 2
; CHECK-NEXT: [[X3:%.*]] = extractelement <4 x i32> [[X]], i32 3
; CHECK-NEXT: [[C0:%.*]] = icmp sgt i32 [[X0]], 0
; CHECK-NEXT: [[C1:%.*]] = icmp sgt i32 [[X1]], 1
; CHECK-NEXT: [[C2:%.*]] = icmp sgt i32 [[X2]], 2
; CHECK-NEXT: [[C3:%.*]] = icmp sgt i32 [[X3]], 3
; CHECK-NEXT: [[S1:%.*]] = select i1 [[C0]], i1 [[C1]], i1 false
; CHECK-NEXT: [[S2:%.*]] = select i1 [[S1]], i1 [[C2]], i1 false
; CHECK-NEXT: [[S3:%.*]] = select i1 [[S2]], i1 [[C3]], i1 false
; CHECK-NEXT: ret i1 [[S3]]
;
%x0 = extractelement <4 x i32> %x, i32 0
%x1 = extractelement <4 x i32> %x, i32 1
%x2 = extractelement <4 x i32> %x, i32 2
%x3 = extractelement <4 x i32> %x, i32 3
%c0 = icmp sgt i32 %x0, 0
%c1 = icmp sgt i32 %x1, 1
%c2 = icmp sgt i32 %x2, 2
%c3 = icmp sgt i32 %x3, 3
%s1 = select i1 %c0, i1 %c1, i1 false
%s2 = select i1 %s1, i1 %c2, i1 false
%s3 = select i1 %s2, i1 %c3, i1 false
ret i1 %s3
}

define i1 @mixed_logical_icmp(<4 x i32> %x) {
; CHECK-LABEL: @mixed_logical_icmp(
; CHECK-NEXT: [[X0:%.*]] = extractelement <4 x i32> [[X:%.*]], i32 0
; CHECK-NEXT: [[X1:%.*]] = extractelement <4 x i32> [[X]], i32 1
; CHECK-NEXT: [[X2:%.*]] = extractelement <4 x i32> [[X]], i32 2
; CHECK-NEXT: [[X3:%.*]] = extractelement <4 x i32> [[X]], i32 3
; CHECK-NEXT: [[C0:%.*]] = icmp sgt i32 [[X0]], 0
; CHECK-NEXT: [[C1:%.*]] = icmp sgt i32 [[X1]], 0
; CHECK-NEXT: [[C2:%.*]] = icmp sgt i32 [[X2]], 0
; CHECK-NEXT: [[C3:%.*]] = icmp sgt i32 [[X3]], 0
; CHECK-NEXT: [[S1:%.*]] = select i1 [[C0]], i1 [[C1]], i1 false
; CHECK-NEXT: [[S2:%.*]] = select i1 [[S1]], i1 true, i1 [[C2]]
; CHECK-NEXT: [[S3:%.*]] = select i1 [[S2]], i1 [[C3]], i1 false
; CHECK-NEXT: ret i1 [[S3]]
;
%x0 = extractelement <4 x i32> %x, i32 0
%x1 = extractelement <4 x i32> %x, i32 1
%x2 = extractelement <4 x i32> %x, i32 2
%x3 = extractelement <4 x i32> %x, i32 3
%c0 = icmp sgt i32 %x0, 0
%c1 = icmp sgt i32 %x1, 0
%c2 = icmp sgt i32 %x2, 0
%c3 = icmp sgt i32 %x3, 0
%s1 = select i1 %c0, i1 %c1, i1 false
%s2 = select i1 %s1, i1 true, i1 %c2
%s3 = select i1 %s2, i1 %c3, i1 false
ret i1 %s3
}