8 changes: 4 additions & 4 deletions llvm/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -3,11 +3,11 @@
%struct.rtunion = type { i64 }
%struct.rtx_def = type { i16, i8, i8, [1 x %struct.rtunion] }

define void @simplify_unary_real(i8* nocapture %p) nounwind {
define void @simplify_unary_real(ptr nocapture %p) nounwind {
entry:
%tmp121 = load i64, i64* null, align 4 ; <i64> [#uses=1]
%0 = getelementptr %struct.rtx_def, %struct.rtx_def* null, i32 0, i32 3, i32 3, i32 0 ; <i64*> [#uses=1]
%tmp122 = load i64, i64* %0, align 4 ; <i64> [#uses=1]
%tmp121 = load i64, ptr null, align 4 ; <i64> [#uses=1]
%0 = getelementptr %struct.rtx_def, ptr null, i32 0, i32 3, i32 3, i32 0 ; <ptr> [#uses=1]
%tmp122 = load i64, ptr %0, align 4 ; <i64> [#uses=1]
%1 = zext i64 undef to i192 ; <i192> [#uses=2]
%2 = zext i64 %tmp121 to i192 ; <i192> [#uses=1]
%3 = shl i192 %2, 64 ; <i192> [#uses=2]
Expand Down
50 changes: 25 additions & 25 deletions llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll
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Original file line number Diff line number Diff line change
@@ -1,18 +1,18 @@
; RUN: llc < %s -mtriple=armv6-apple-darwin9

@nn = external global i32 ; <i32*> [#uses=1]
@al_len = external global i32 ; <i32*> [#uses=2]
@no_mat = external global i32 ; <i32*> [#uses=2]
@no_mis = external global i32 ; <i32*> [#uses=2]
@"\01LC12" = external constant [29 x i8], align 1 ; <[29 x i8]*> [#uses=1]
@"\01LC16" = external constant [33 x i8], align 1 ; <[33 x i8]*> [#uses=1]
@"\01LC17" = external constant [47 x i8], align 1 ; <[47 x i8]*> [#uses=1]
@nn = external global i32 ; <ptr> [#uses=1]
@al_len = external global i32 ; <ptr> [#uses=2]
@no_mat = external global i32 ; <ptr> [#uses=2]
@no_mis = external global i32 ; <ptr> [#uses=2]
@"\01LC12" = external constant [29 x i8], align 1 ; <ptr> [#uses=1]
@"\01LC16" = external constant [33 x i8], align 1 ; <ptr> [#uses=1]
@"\01LC17" = external constant [47 x i8], align 1 ; <ptr> [#uses=1]

declare i32 @printf(i8* nocapture, ...) nounwind
declare i32 @printf(ptr nocapture, ...) nounwind

declare void @diff(i8*, i8*, i32, i32, i32, i32) nounwind
declare void @diff(ptr, ptr, i32, i32, i32, i32) nounwind

define void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind {
define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq) nounwind {
entry:
br i1 undef, label %bb5, label %bb

Expand All @@ -35,26 +35,26 @@ bb10: ; preds = %bb9
unreachable

bb11: ; preds = %bb9
%0 = load i32, i32* undef, align 4 ; <i32> [#uses=2]
%0 = load i32, ptr undef, align 4 ; <i32> [#uses=2]
%1 = add i32 %0, 1 ; <i32> [#uses=2]
store i32 %1, i32* undef, align 4
%2 = load i32, i32* undef, align 4 ; <i32> [#uses=1]
store i32 %2, i32* @nn, align 4
store i32 0, i32* @al_len, align 4
store i32 0, i32* @no_mat, align 4
store i32 0, i32* @no_mis, align 4
%3 = getelementptr i8, i8* %B, i32 %0 ; <i8*> [#uses=1]
tail call void @diff(i8* undef, i8* %3, i32 undef, i32 undef, i32 undef, i32 undef) nounwind
store i32 %1, ptr undef, align 4
%2 = load i32, ptr undef, align 4 ; <i32> [#uses=1]
store i32 %2, ptr @nn, align 4
store i32 0, ptr @al_len, align 4
store i32 0, ptr @no_mat, align 4
store i32 0, ptr @no_mis, align 4
%3 = getelementptr i8, ptr %B, i32 %0 ; <ptr> [#uses=1]
tail call void @diff(ptr undef, ptr %3, i32 undef, i32 undef, i32 undef, i32 undef) nounwind
%4 = sitofp i32 undef to double ; <double> [#uses=1]
%5 = fdiv double %4, 1.000000e+01 ; <double> [#uses=1]
%6 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([29 x i8], [29 x i8]* @"\01LC12", i32 0, i32 0), double %5) nounwind ; <i32> [#uses=0]
%7 = load i32, i32* @al_len, align 4 ; <i32> [#uses=1]
%8 = load i32, i32* @no_mat, align 4 ; <i32> [#uses=1]
%9 = load i32, i32* @no_mis, align 4 ; <i32> [#uses=1]
%6 = tail call i32 (ptr, ...) @printf(ptr @"\01LC12", double %5) nounwind ; <i32> [#uses=0]
%7 = load i32, ptr @al_len, align 4 ; <i32> [#uses=1]
%8 = load i32, ptr @no_mat, align 4 ; <i32> [#uses=1]
%9 = load i32, ptr @no_mis, align 4 ; <i32> [#uses=1]
%10 = sub i32 %7, %8 ; <i32> [#uses=1]
%11 = sub i32 %10, %9 ; <i32> [#uses=1]
%12 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([33 x i8], [33 x i8]* @"\01LC16", i32 0, i32 0), i32 %11) nounwind ; <i32> [#uses=0]
%13 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([47 x i8], [47 x i8]* @"\01LC17", i32 0, i32 0), i32 undef, i32 %1, i32 undef, i32 undef) nounwind ; <i32> [#uses=0]
%12 = tail call i32 (ptr, ...) @printf(ptr @"\01LC16", i32 %11) nounwind ; <i32> [#uses=0]
%13 = tail call i32 (ptr, ...) @printf(ptr @"\01LC17", i32 undef, i32 %1, i32 undef, i32 undef) nounwind ; <i32> [#uses=0]
br i1 undef, label %bb15, label %bb12

bb12: ; preds = %bb11
Expand Down
38 changes: 19 additions & 19 deletions llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll
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Original file line number Diff line number Diff line change
@@ -1,16 +1,16 @@
; RUN: llc < %s -mtriple=armv6-apple-darwin9

@no_mat = external global i32 ; <i32*> [#uses=1]
@no_mis = external global i32 ; <i32*> [#uses=2]
@"\01LC11" = external constant [33 x i8], align 1 ; <[33 x i8]*> [#uses=1]
@"\01LC15" = external constant [33 x i8], align 1 ; <[33 x i8]*> [#uses=1]
@"\01LC17" = external constant [47 x i8], align 1 ; <[47 x i8]*> [#uses=1]
@no_mat = external global i32 ; <ptr> [#uses=1]
@no_mis = external global i32 ; <ptr> [#uses=2]
@"\01LC11" = external constant [33 x i8], align 1 ; <ptr> [#uses=1]
@"\01LC15" = external constant [33 x i8], align 1 ; <ptr> [#uses=1]
@"\01LC17" = external constant [47 x i8], align 1 ; <ptr> [#uses=1]

declare i32 @printf(i8* nocapture, ...) nounwind
declare i32 @printf(ptr nocapture, ...) nounwind

declare void @diff(i8*, i8*, i32, i32, i32, i32) nounwind
declare void @diff(ptr, ptr, i32, i32, i32, i32) nounwind

define void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind {
define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq) nounwind {
entry:
br i1 undef, label %bb5, label %bb

Expand All @@ -33,19 +33,19 @@ bb10: ; preds = %bb9
unreachable

bb11: ; preds = %bb9
%0 = load i32, i32* undef, align 4 ; <i32> [#uses=3]
%0 = load i32, ptr undef, align 4 ; <i32> [#uses=3]
%1 = add i32 %0, 1 ; <i32> [#uses=2]
store i32 %1, i32* undef, align 4
%2 = load i32, i32* undef, align 4 ; <i32> [#uses=2]
store i32 %1, ptr undef, align 4
%2 = load i32, ptr undef, align 4 ; <i32> [#uses=2]
%3 = sub i32 %2, %0 ; <i32> [#uses=1]
store i32 0, i32* @no_mat, align 4
store i32 0, i32* @no_mis, align 4
%4 = getelementptr i8, i8* %B, i32 %0 ; <i8*> [#uses=1]
tail call void @diff(i8* undef, i8* %4, i32 undef, i32 %3, i32 undef, i32 undef) nounwind
%5 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([33 x i8], [33 x i8]* @"\01LC11", i32 0, i32 0), i32 %tmp13) nounwind ; <i32> [#uses=0]
%6 = load i32, i32* @no_mis, align 4 ; <i32> [#uses=1]
%7 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([33 x i8], [33 x i8]* @"\01LC15", i32 0, i32 0), i32 %6) nounwind ; <i32> [#uses=0]
%8 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([47 x i8], [47 x i8]* @"\01LC17", i32 0, i32 0), i32 undef, i32 %1, i32 undef, i32 %2) nounwind ; <i32> [#uses=0]
store i32 0, ptr @no_mat, align 4
store i32 0, ptr @no_mis, align 4
%4 = getelementptr i8, ptr %B, i32 %0 ; <ptr> [#uses=1]
tail call void @diff(ptr undef, ptr %4, i32 undef, i32 %3, i32 undef, i32 undef) nounwind
%5 = tail call i32 (ptr, ...) @printf(ptr @"\01LC11", i32 %tmp13) nounwind ; <i32> [#uses=0]
%6 = load i32, ptr @no_mis, align 4 ; <i32> [#uses=1]
%7 = tail call i32 (ptr, ...) @printf(ptr @"\01LC15", i32 %6) nounwind ; <i32> [#uses=0]
%8 = tail call i32 (ptr, ...) @printf(ptr @"\01LC17", i32 undef, i32 %1, i32 undef, i32 %2) nounwind ; <i32> [#uses=0]
br i1 undef, label %bb15, label %bb12

bb12: ; preds = %bb11
Expand Down
26 changes: 13 additions & 13 deletions llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll
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Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
; RUN: llc < %s -mtriple=armv6-apple-darwin9

@JJ = external global i32* ; <i32**> [#uses=1]
@JJ = external global ptr ; <ptr> [#uses=1]

define void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind {
define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq) nounwind {
entry:
br i1 undef, label %bb5, label %bb

Expand All @@ -28,7 +28,7 @@ bb11: ; preds = %bb9
br i1 undef, label %bb15, label %bb12

bb12: ; preds = %bb11
%0 = load i32*, i32** @JJ, align 4 ; <i32*> [#uses=1]
%0 = load ptr, ptr @JJ, align 4 ; <ptr> [#uses=1]
br label %bb228.i

bb74.i: ; preds = %bb228.i
Expand Down Expand Up @@ -84,22 +84,22 @@ bb167.i: ; preds = %bb163.i
bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i
%fi.5.i = phi i32 [ undef, %bb167.i ], [ %ci.910.i, %bb158.i ], [ undef, %bb160.i ], [ %ci.910.i, %bb161.i ], [ undef, %bb163.i ] ; <i32> [#uses=1]
%fj.4.i = phi i32 [ undef, %bb167.i ], [ undef, %bb158.i ], [ %fj.515.i, %bb160.i ], [ undef, %bb161.i ], [ %fj.515.i, %bb163.i ] ; <i32> [#uses=2]
%scevgep88.i = getelementptr i32, i32* null, i32 %i.121.i ; <i32*> [#uses=3]
%4 = load i32, i32* %scevgep88.i, align 4 ; <i32> [#uses=2]
%scevgep89.i = getelementptr i32, i32* %0, i32 %i.121.i ; <i32*> [#uses=3]
%5 = load i32, i32* %scevgep89.i, align 4 ; <i32> [#uses=1]
%scevgep88.i = getelementptr i32, ptr null, i32 %i.121.i ; <ptr> [#uses=3]
%4 = load i32, ptr %scevgep88.i, align 4 ; <i32> [#uses=2]
%scevgep89.i = getelementptr i32, ptr %0, i32 %i.121.i ; <ptr> [#uses=3]
%5 = load i32, ptr %scevgep89.i, align 4 ; <i32> [#uses=1]
%ci.10.i = select i1 undef, i32 %pi.316.i, i32 %i.121.i ; <i32> [#uses=0]
%cj.9.i = select i1 undef, i32 %pj.317.i, i32 undef ; <i32> [#uses=0]
%6 = icmp slt i32 undef, 0 ; <i1> [#uses=3]
%ci.12.i = select i1 %6, i32 %fi.5.i, i32 %4 ; <i32> [#uses=2]
%cj.11.i100 = select i1 %6, i32 %fj.4.i, i32 %5 ; <i32> [#uses=1]
%c.14.i = select i1 %6, i32 0, i32 undef ; <i32> [#uses=2]
store i32 %c.14.i, i32* undef, align 4
%7 = load i32, i32* %scevgep88.i, align 4 ; <i32> [#uses=1]
%8 = load i32, i32* %scevgep89.i, align 4 ; <i32> [#uses=1]
store i32 %ci.12.i, i32* %scevgep88.i, align 4
store i32 %cj.11.i100, i32* %scevgep89.i, align 4
store i32 %4, i32* undef, align 4
store i32 %c.14.i, ptr undef, align 4
%7 = load i32, ptr %scevgep88.i, align 4 ; <i32> [#uses=1]
%8 = load i32, ptr %scevgep89.i, align 4 ; <i32> [#uses=1]
store i32 %ci.12.i, ptr %scevgep88.i, align 4
store i32 %cj.11.i100, ptr %scevgep89.i, align 4
store i32 %4, ptr undef, align 4
br i1 undef, label %bb211.i, label %bb218.i

bb211.i: ; preds = %bb168.i
Expand Down
38 changes: 19 additions & 19 deletions llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll
View file
Original file line number Diff line number Diff line change
@@ -1,14 +1,14 @@
; RUN: llc < %s -mtriple=armv6-apple-darwin9

@r = external global i32 ; <i32*> [#uses=1]
@qr = external global i32 ; <i32*> [#uses=1]
@II = external global i32* ; <i32**> [#uses=1]
@no_mis = external global i32 ; <i32*> [#uses=1]
@name1 = external global i8* ; <i8**> [#uses=1]
@r = external global i32 ; <ptr> [#uses=1]
@qr = external global i32 ; <ptr> [#uses=1]
@II = external global ptr ; <ptr> [#uses=1]
@no_mis = external global i32 ; <ptr> [#uses=1]
@name1 = external global ptr ; <ptr> [#uses=1]

declare void @diff(i8*, i8*, i32, i32, i32, i32) nounwind
declare void @diff(ptr, ptr, i32, i32, i32, i32) nounwind

define void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind {
define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq) nounwind {
entry:
br i1 undef, label %bb5, label %bb

Expand All @@ -22,7 +22,7 @@ bb6: ; preds = %bb6, %bb5
br i1 undef, label %bb8, label %bb6

bb8: ; preds = %bb6, %bb5
%0 = load i8*, i8** @name1, align 4 ; <i8*> [#uses=0]
%0 = load ptr, ptr @name1, align 4 ; <ptr> [#uses=0]
br label %bb15

bb9: ; preds = %bb15
Expand All @@ -32,16 +32,16 @@ bb10: ; preds = %bb9
unreachable

bb11: ; preds = %bb9
store i32 0, i32* @no_mis, align 4
%1 = getelementptr i8, i8* %A, i32 0 ; <i8*> [#uses=1]
%2 = getelementptr i8, i8* %B, i32 0 ; <i8*> [#uses=1]
tail call void @diff(i8* %1, i8* %2, i32 undef, i32 undef, i32 undef, i32 undef) nounwind
store i32 0, ptr @no_mis, align 4
%1 = getelementptr i8, ptr %A, i32 0 ; <ptr> [#uses=1]
%2 = getelementptr i8, ptr %B, i32 0 ; <ptr> [#uses=1]
tail call void @diff(ptr %1, ptr %2, i32 undef, i32 undef, i32 undef, i32 undef) nounwind
br i1 undef, label %bb15, label %bb12

bb12: ; preds = %bb11
%3 = load i32*, i32** @II, align 4 ; <i32*> [#uses=1]
%4 = load i32, i32* @r, align 4 ; <i32> [#uses=1]
%5 = load i32, i32* @qr, align 4 ; <i32> [#uses=1]
%3 = load ptr, ptr @II, align 4 ; <ptr> [#uses=1]
%4 = load i32, ptr @r, align 4 ; <i32> [#uses=1]
%5 = load i32, ptr @qr, align 4 ; <i32> [#uses=1]
br label %bb228.i

bb74.i: ; preds = %bb228.i
Expand Down Expand Up @@ -95,12 +95,12 @@ bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i
%fi.5.i = phi i32 [ %fi.614.i, %bb167.i ], [ %ci.910.i, %bb158.i ], [ %fi.614.i, %bb160.i ], [ %ci.910.i, %bb161.i ], [ %fi.614.i, %bb163.i ] ; <i32> [#uses=2]
%fj.4.i = phi i32 [ %cj.811.i, %bb167.i ], [ %cj.811.i, %bb158.i ], [ %fj.515.i, %bb160.i ], [ %cj.811.i, %bb161.i ], [ %fj.515.i, %bb163.i ] ; <i32> [#uses=2]
%f.5.i = phi i32 [ %7, %bb167.i ], [ %8, %bb158.i ], [ %7, %bb160.i ], [ %7, %bb161.i ], [ %7, %bb163.i ] ; <i32> [#uses=2]
%scevgep88.i = getelementptr i32, i32* %3, i32 undef ; <i32*> [#uses=1]
%scevgep88.i = getelementptr i32, ptr %3, i32 undef ; <ptr> [#uses=1]
%ci.10.i = select i1 undef, i32 %pi.316.i, i32 undef ; <i32> [#uses=0]
%ci.12.i = select i1 undef, i32 %fi.5.i, i32 undef ; <i32> [#uses=1]
%cj.11.i100 = select i1 undef, i32 %fj.4.i, i32 undef ; <i32> [#uses=1]
%c.14.i = select i1 undef, i32 %f.5.i, i32 undef ; <i32> [#uses=1]
%10 = load i32, i32* %scevgep88.i, align 4 ; <i32> [#uses=1]
%10 = load i32, ptr %scevgep88.i, align 4 ; <i32> [#uses=1]
br i1 undef, label %bb211.i, label %bb218.i

bb211.i: ; preds = %bb168.i
Expand All @@ -110,8 +110,8 @@ bb218.i: ; preds = %bb211.i, %bb168.i
br i1 undef, label %bb220.i, label %bb158.i

bb220.i: ; preds = %bb218.i, %bb153.i
%11 = getelementptr i32, i32* null, i32 %6 ; <i32*> [#uses=1]
store i32 undef, i32* %11, align 4
%11 = getelementptr i32, ptr null, i32 %6 ; <ptr> [#uses=1]
store i32 undef, ptr %11, align 4
br i1 undef, label %bb221.i, label %bb228.i

bb221.i: ; preds = %bb220.i
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll
View file
Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
; RUN: llc < %s -mtriple=armv6-apple-darwin9

@XX = external global i32* ; <i32**> [#uses=1]
@XX = external global ptr ; <ptr> [#uses=1]

define void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind {
define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq) nounwind {
entry:
br i1 undef, label %bb5, label %bb

Expand All @@ -28,7 +28,7 @@ bb11: ; preds = %bb9
br i1 undef, label %bb15, label %bb12

bb12: ; preds = %bb11
%0 = load i32*, i32** @XX, align 4 ; <i32*> [#uses=0]
%0 = load ptr, ptr @XX, align 4 ; <ptr> [#uses=0]
br label %bb228.i

bb74.i: ; preds = %bb228.i
Expand Down Expand Up @@ -72,8 +72,8 @@ bb167.i: ; preds = %bb163.i
bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i
%f.5.i = phi i32 [ %1, %bb167.i ], [ %2, %bb158.i ], [ %1, %bb160.i ], [ %1, %bb161.i ], [ %1, %bb163.i ] ; <i32> [#uses=1]
%c.14.i = select i1 undef, i32 %f.5.i, i32 undef ; <i32> [#uses=1]
store i32 %c.14.i, i32* undef, align 4
store i32 undef, i32* null, align 4
store i32 %c.14.i, ptr undef, align 4
store i32 undef, ptr null, align 4
br i1 undef, label %bb211.i, label %bb218.i

bb211.i: ; preds = %bb168.i
Expand Down
26 changes: 13 additions & 13 deletions llvm/test/CodeGen/ARM/2009-07-01-CommuteBug.ll
View file
Original file line number Diff line number Diff line change
@@ -1,10 +1,10 @@
; RUN: llc < %s -mtriple=armv6-apple-darwin9

@qr = external global i32 ; <i32*> [#uses=1]
@II = external global i32* ; <i32**> [#uses=1]
@JJ = external global i32* ; <i32**> [#uses=1]
@qr = external global i32 ; <ptr> [#uses=1]
@II = external global ptr ; <ptr> [#uses=1]
@JJ = external global ptr ; <ptr> [#uses=1]

define void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind {
define void @SIM(ptr %A, ptr %B, i32 %M, i32 %N, i32 %K, ptr %V, i32 %Q, i32 %R, i32 %nseq) nounwind {
entry:
br i1 undef, label %bb5, label %bb

Expand All @@ -30,9 +30,9 @@ bb11: ; preds = %bb9
br i1 undef, label %bb15, label %bb12

bb12: ; preds = %bb11
%0 = load i32*, i32** @II, align 4 ; <i32*> [#uses=1]
%1 = load i32*, i32** @JJ, align 4 ; <i32*> [#uses=1]
%2 = load i32, i32* @qr, align 4 ; <i32> [#uses=1]
%0 = load ptr, ptr @II, align 4 ; <ptr> [#uses=1]
%1 = load ptr, ptr @JJ, align 4 ; <ptr> [#uses=1]
%2 = load i32, ptr @qr, align 4 ; <i32> [#uses=1]
br label %bb228.i

bb74.i: ; preds = %bb228.i
Expand Down Expand Up @@ -90,17 +90,17 @@ bb168.i: ; preds = %bb167.i, %bb163.i, %bb161.i, %bb160.i, %bb158.i
%fi.5.i = phi i32 [ %fi.614.i, %bb167.i ], [ %ci.910.i, %bb158.i ], [ %fi.614.i, %bb160.i ], [ %ci.910.i, %bb161.i ], [ %fi.614.i, %bb163.i ] ; <i32> [#uses=2]
%fj.4.i = phi i32 [ %cj.811.i, %bb167.i ], [ %cj.811.i, %bb158.i ], [ %fj.515.i, %bb160.i ], [ %cj.811.i, %bb161.i ], [ %fj.515.i, %bb163.i ] ; <i32> [#uses=2]
%f.5.i = phi i32 [ %3, %bb167.i ], [ %4, %bb158.i ], [ %3, %bb160.i ], [ %3, %bb161.i ], [ %3, %bb163.i ] ; <i32> [#uses=2]
%scevgep88.i = getelementptr i32, i32* %0, i32 undef ; <i32*> [#uses=2]
%scevgep89.i = getelementptr i32, i32* %1, i32 undef ; <i32*> [#uses=2]
%scevgep88.i = getelementptr i32, ptr %0, i32 undef ; <ptr> [#uses=2]
%scevgep89.i = getelementptr i32, ptr %1, i32 undef ; <ptr> [#uses=2]
%ci.10.i = select i1 undef, i32 %pi.316.i, i32 undef ; <i32> [#uses=0]
%cj.9.i = select i1 undef, i32 %pj.317.i, i32 undef ; <i32> [#uses=0]
%ci.12.i = select i1 undef, i32 %fi.5.i, i32 undef ; <i32> [#uses=2]
%cj.11.i100 = select i1 undef, i32 %fj.4.i, i32 undef ; <i32> [#uses=2]
%c.14.i = select i1 undef, i32 %f.5.i, i32 undef ; <i32> [#uses=1]
%6 = load i32, i32* %scevgep88.i, align 4 ; <i32> [#uses=1]
%7 = load i32, i32* %scevgep89.i, align 4 ; <i32> [#uses=1]
store i32 %ci.12.i, i32* %scevgep88.i, align 4
store i32 %cj.11.i100, i32* %scevgep89.i, align 4
%6 = load i32, ptr %scevgep88.i, align 4 ; <i32> [#uses=1]
%7 = load i32, ptr %scevgep89.i, align 4 ; <i32> [#uses=1]
store i32 %ci.12.i, ptr %scevgep88.i, align 4
store i32 %cj.11.i100, ptr %scevgep89.i, align 4
br i1 undef, label %bb211.i, label %bb218.i

bb211.i: ; preds = %bb168.i
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/ARM/2009-07-09-asm-p-constraint.ll
View file
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o /dev/null

define void @test(i8* %x) nounwind {
define void @test(ptr %x) nounwind {
entry:
call void asm sideeffect "pld\09${0:a}", "r,~{cc}"(i8* %x) nounwind
call void asm sideeffect "pld\09${0:a}", "r,~{cc}"(ptr %x) nounwind
ret void
}
22 changes: 11 additions & 11 deletions llvm/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll
View file
Original file line number Diff line number Diff line change
@@ -1,14 +1,14 @@
; RUN: llc < %s -mtriple=armv6-apple-darwin10

%struct.cli_ac_alt = type { i8, i8*, i16, i16, %struct.cli_ac_alt* }
%struct.cli_ac_node = type { i8, i8, %struct.cli_ac_patt*, %struct.cli_ac_node**, %struct.cli_ac_node* }
%struct.cli_ac_patt = type { i16*, i16*, i16, i16, i8, i32, i32, i8*, i8*, i32, i16, i16, i16, i16, %struct.cli_ac_alt**, i8, i16, %struct.cli_ac_patt*, %struct.cli_ac_patt* }
%struct.cli_bm_patt = type { i8*, i8*, i16, i16, i8*, i8*, i8, %struct.cli_bm_patt*, i16 }
%struct.cli_matcher = type { i16, i8, i8*, %struct.cli_bm_patt**, i32*, i32, i8, i8, %struct.cli_ac_node*, %struct.cli_ac_node**, %struct.cli_ac_patt**, i32, i32, i32 }
%struct.cli_ac_alt = type { i8, ptr, i16, i16, ptr }
%struct.cli_ac_node = type { i8, i8, ptr, ptr, ptr }
%struct.cli_ac_patt = type { ptr, ptr, i16, i16, i8, i32, i32, ptr, ptr, i32, i16, i16, i16, i16, ptr, i8, i16, ptr, ptr }
%struct.cli_bm_patt = type { ptr, ptr, i16, i16, ptr, ptr, i8, ptr, i16 }
%struct.cli_matcher = type { i16, i8, ptr, ptr, ptr, i32, i8, i8, ptr, ptr, ptr, i32, i32, i32 }

declare i32 @strlen(i8* nocapture) nounwind readonly
declare i32 @strlen(ptr nocapture) nounwind readonly

define i32 @cli_ac_addsig(%struct.cli_matcher* nocapture %root, i8* %virname, i8* %hexsig, i32 %sigid, i16 zeroext %parts, i16 zeroext %partno, i16 zeroext %type, i32 %mindist, i32 %maxdist, i8* %offset, i8 zeroext %target) nounwind {
define i32 @cli_ac_addsig(ptr nocapture %root, ptr %virname, ptr %hexsig, i32 %sigid, i16 zeroext %parts, i16 zeroext %partno, i16 zeroext %type, i32 %mindist, i32 %maxdist, ptr %offset, i8 zeroext %target) nounwind {
entry:
br i1 undef, label %bb126, label %bb1

Expand All @@ -19,7 +19,7 @@ cli_calloc.exit.thread: ; preds = %bb1
ret i32 -114

cli_calloc.exit: ; preds = %bb1
store i16 %parts, i16* undef, align 4
store i16 %parts, ptr undef, align 4
br i1 undef, label %bb52, label %bb4

bb4: ; preds = %cli_calloc.exit
Expand Down Expand Up @@ -83,10 +83,10 @@ bb45: ; preds = %bb43.preheader, %cli_calloc.exit54
br i1 undef, label %cli_calloc.exit70.thread, label %cli_calloc.exit70

bb52: ; preds = %cli_calloc.exit
%0 = load i16, i16* undef, align 4 ; <i16> [#uses=1]
%0 = load i16, ptr undef, align 4 ; <i16> [#uses=1]
%1 = icmp eq i16 %0, 0 ; <i1> [#uses=1]
%iftmp.20.0 = select i1 %1, i8* %hexsig, i8* null ; <i8*> [#uses=1]
%2 = tail call i32 @strlen(i8* %iftmp.20.0) nounwind readonly ; <i32> [#uses=0]
%iftmp.20.0 = select i1 %1, ptr %hexsig, ptr null ; <ptr> [#uses=1]
%2 = tail call i32 @strlen(ptr %iftmp.20.0) nounwind readonly ; <i32> [#uses=0]
unreachable

bb126: ; preds = %entry
Expand Down
29 changes: 14 additions & 15 deletions llvm/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll
View file
Original file line number Diff line number Diff line change
@@ -1,12 +1,12 @@
; RUN: llc -mtriple=arm-eabi %s -o /dev/null

%struct.cli_ac_alt = type { i8, i8*, i16, i16, %struct.cli_ac_alt* }
%struct.cli_ac_node = type { i8, i8, %struct.cli_ac_patt*, %struct.cli_ac_node**, %struct.cli_ac_node* }
%struct.cli_ac_patt = type { i16*, i16*, i16, i16, i8, i32, i32, i8*, i8*, i32, i16, i16, i16, i16, %struct.cli_ac_alt**, i8, i16, %struct.cli_ac_patt*, %struct.cli_ac_patt* }
%struct.cli_bm_patt = type { i8*, i8*, i16, i16, i8*, i8*, i8, %struct.cli_bm_patt*, i16 }
%struct.cli_matcher = type { i16, i8, i8*, %struct.cli_bm_patt**, i32*, i32, i8, i8, %struct.cli_ac_node*, %struct.cli_ac_node**, %struct.cli_ac_patt**, i32, i32, i32 }
%struct.cli_ac_alt = type { i8, ptr, i16, i16, ptr }
%struct.cli_ac_node = type { i8, i8, ptr, ptr, ptr }
%struct.cli_ac_patt = type { ptr, ptr, i16, i16, i8, i32, i32, ptr, ptr, i32, i16, i16, i16, i16, ptr, i8, i16, ptr, ptr }
%struct.cli_bm_patt = type { ptr, ptr, i16, i16, ptr, ptr, i8, ptr, i16 }
%struct.cli_matcher = type { i16, i8, ptr, ptr, ptr, i32, i8, i8, ptr, ptr, ptr, i32, i32, i32 }

define i32 @cli_ac_addsig(%struct.cli_matcher* nocapture %root, i8* %virname, i8* %hexsig, i32 %sigid, i16 zeroext %parts, i16 zeroext %partno, i16 zeroext %type, i32 %mindist, i32 %maxdist, i8* %offset, i8 zeroext %target) nounwind {
define i32 @cli_ac_addsig(ptr nocapture %root, ptr %virname, ptr %hexsig, i32 %sigid, i16 zeroext %parts, i16 zeroext %partno, i16 zeroext %type, i32 %mindist, i32 %maxdist, ptr %offset, i8 zeroext %target) nounwind {
entry:
br i1 undef, label %bb126, label %bb1

Expand Down Expand Up @@ -65,15 +65,14 @@ bb18: ; preds = %bb18, %bb.nph
br i1 undef, label %bb18, label %bb22

bb22: ; preds = %bb18, %bb17
%0 = getelementptr i8, i8* null, i32 10 ; <i8*> [#uses=1]
%1 = bitcast i8* %0 to i16* ; <i16*> [#uses=1]
%2 = load i16, i16* %1, align 2 ; <i16> [#uses=1]
%3 = add i16 %2, 1 ; <i16> [#uses=1]
%4 = zext i16 %3 to i32 ; <i32> [#uses=1]
%5 = mul i32 %4, 3 ; <i32> [#uses=1]
%6 = add i32 %5, -1 ; <i32> [#uses=1]
%7 = icmp eq i32 %6, undef ; <i1> [#uses=1]
br i1 %7, label %bb25, label %bb43.preheader
%0 = getelementptr i8, ptr null, i32 10 ; <ptr> [#uses=1]
%1 = load i16, ptr %0, align 2 ; <i16> [#uses=1]
%2 = add i16 %1, 1 ; <i16> [#uses=1]
%3 = zext i16 %2 to i32 ; <i32> [#uses=1]
%4 = mul i32 %3, 3 ; <i32> [#uses=1]
%5 = add i32 %4, -1 ; <i32> [#uses=1]
%6 = icmp eq i32 %5, undef ; <i1> [#uses=1]
br i1 %6, label %bb25, label %bb43.preheader

bb43.preheader: ; preds = %bb22
br i1 undef, label %bb28, label %bb45
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll
View file
Original file line number Diff line number Diff line change
@@ -1,18 +1,18 @@
; RUN: llc < %s -mtriple=armv7-apple-darwin10 -mattr=+vfp3

@a = external global double ; <double*> [#uses=1]
@a = external global double ; <ptr> [#uses=1]

declare double @llvm.exp.f64(double) nounwind readonly

define void @findratio(double* nocapture %res1, double* nocapture %res2) nounwind {
define void @findratio(ptr nocapture %res1, ptr nocapture %res2) nounwind {
entry:
br label %bb

bb: ; preds = %bb, %entry
br i1 undef, label %bb28, label %bb

bb28: ; preds = %bb
%0 = load double, double* @a, align 4 ; <double> [#uses=2]
%0 = load double, ptr @a, align 4 ; <double> [#uses=2]
%1 = fadd double %0, undef ; <double> [#uses=2]
br i1 undef, label %bb59, label %bb60

Expand Down
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,24 +6,24 @@ target triple = "armv7-apple-darwin9"

define <4 x i32> @scale(<4 x i32> %v, i32 %f) nounwind {
entry:
%v_addr = alloca <4 x i32> ; <<4 x i32>*> [#uses=2]
%f_addr = alloca i32 ; <i32*> [#uses=2]
%retval = alloca <4 x i32> ; <<4 x i32>*> [#uses=2]
%0 = alloca <4 x i32> ; <<4 x i32>*> [#uses=2]
%v_addr = alloca <4 x i32> ; <ptr> [#uses=2]
%f_addr = alloca i32 ; <ptr> [#uses=2]
%retval = alloca <4 x i32> ; <ptr> [#uses=2]
%0 = alloca <4 x i32> ; <ptr> [#uses=2]
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
store <4 x i32> %v, <4 x i32>* %v_addr
store i32 %f, i32* %f_addr
%1 = load <4 x i32>, <4 x i32>* %v_addr, align 16 ; <<4 x i32>> [#uses=1]
%2 = load i32, i32* %f_addr, align 4 ; <i32> [#uses=1]
store <4 x i32> %v, ptr %v_addr
store i32 %f, ptr %f_addr
%1 = load <4 x i32>, ptr %v_addr, align 16 ; <<4 x i32>> [#uses=1]
%2 = load i32, ptr %f_addr, align 4 ; <i32> [#uses=1]
%3 = insertelement <4 x i32> undef, i32 %2, i32 0 ; <<4 x i32>> [#uses=1]
%4 = shufflevector <4 x i32> %3, <4 x i32> undef, <4 x i32> zeroinitializer ; <<4 x i32>> [#uses=1]
%5 = mul <4 x i32> %1, %4 ; <<4 x i32>> [#uses=1]
store <4 x i32> %5, <4 x i32>* %0, align 16
%6 = load <4 x i32>, <4 x i32>* %0, align 16 ; <<4 x i32>> [#uses=1]
store <4 x i32> %6, <4 x i32>* %retval, align 16
store <4 x i32> %5, ptr %0, align 16
%6 = load <4 x i32>, ptr %0, align 16 ; <<4 x i32>> [#uses=1]
store <4 x i32> %6, ptr %retval, align 16
br label %return

return: ; preds = %entry
%retval1 = load <4 x i32>, <4 x i32>* %retval ; <<4 x i32>> [#uses=1]
%retval1 = load <4 x i32>, ptr %retval ; <<4 x i32>> [#uses=1]
ret <4 x i32> %retval1
}
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
target triple = "armv6-elf"

define i32 @file_read_actor(i32* nocapture %desc, i32* %page, i32 %offset, i32 %size) nounwind optsize {
define i32 @file_read_actor(ptr nocapture %desc, ptr %page, i32 %offset, i32 %size) nounwind optsize {
entry:
br i1 undef, label %fault_in_pages_writeable.exit, label %bb5.i

Expand All @@ -26,8 +26,8 @@ bb2: ; preds = %fault_in_pages_writeable.exit
unreachable

bb3: ; preds = %fault_in_pages_writeable.exit
%1 = tail call i32 @__copy_to_user(i8* undef, i8* undef, i32 undef) nounwind ; <i32> [#uses=0]
%1 = tail call i32 @__copy_to_user(ptr undef, ptr undef, i32 undef) nounwind ; <i32> [#uses=0]
unreachable
}

declare i32 @__copy_to_user(i8*, i8*, i32)
declare i32 @__copy_to_user(ptr, ptr, i32)
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -18,8 +18,8 @@ bb2: ; preds = %fault_in_pages_writeable.exit
unreachable

bb3: ; preds = %fault_in_pages_writeable.exit
%2 = tail call i32 @__copy_to_user(i8* undef, i8* undef, i32 undef) nounwind ; <i32> [#uses=0]
%2 = tail call i32 @__copy_to_user(ptr undef, ptr undef, i32 undef) nounwind ; <i32> [#uses=0]
unreachable
}

declare i32 @__copy_to_user(i8*, i8*, i32)
declare i32 @__copy_to_user(ptr, ptr, i32)
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,17 +4,17 @@
; Inline asm is allowed to contain operands "=&r", "0".

%struct.device_dma_parameters = type { i32, i32 }
%struct.iovec = type { i8*, i32 }
%struct.iovec = type { ptr, i32 }

define i32 @generic_segment_checks(%struct.iovec* nocapture %iov, i32* nocapture %nr_segs, i32* nocapture %count, i32 %access_flags) nounwind optsize {
define i32 @generic_segment_checks(ptr nocapture %iov, ptr nocapture %nr_segs, ptr nocapture %count, i32 %access_flags) nounwind optsize {
entry:
br label %bb8

bb: ; preds = %bb8
br i1 undef, label %bb10, label %bb2

bb2: ; preds = %bb
%asmtmp = tail call %struct.device_dma_parameters asm "adds $1, $2, $3; sbcccs $1, $1, $0; movcc $0, #0", "=&r,=&r,r,Ir,0,~{cc}"(i8* undef, i32 undef, i32 0) nounwind; <%struct.device_dma_parameters> [#uses=1]
%asmtmp = tail call %struct.device_dma_parameters asm "adds $1, $2, $3; sbcccs $1, $1, $0; movcc $0, #0", "=&r,=&r,r,Ir,0,~{cc}"(ptr undef, i32 undef, i32 0) nounwind; <%struct.device_dma_parameters> [#uses=1]
%asmresult = extractvalue %struct.device_dma_parameters %asmtmp, 0; <i32> [#uses=1]
%0 = icmp eq i32 %asmresult, 0 ; <i1> [#uses=1]
br i1 %0, label %bb7, label %bb4
Expand All @@ -28,13 +28,13 @@ bb7: ; preds = %bb2

bb8: ; preds = %bb7, %entry
%2 = phi i32 [ 0, %entry ], [ %1, %bb7 ] ; <i32> [#uses=3]
%scevgep22 = getelementptr %struct.iovec, %struct.iovec* %iov, i32 %2, i32 0; <i8**> [#uses=0]
%3 = load i32, i32* %nr_segs, align 4 ; <i32> [#uses=1]
%scevgep22 = getelementptr %struct.iovec, ptr %iov, i32 %2, i32 0; <ptr> [#uses=0]
%3 = load i32, ptr %nr_segs, align 4 ; <i32> [#uses=1]
%4 = icmp ult i32 %2, %3 ; <i1> [#uses=1]
br i1 %4, label %bb, label %bb9

bb9: ; preds = %bb8, %bb4
store i32 undef, i32* %count, align 4
store i32 undef, ptr %count, align 4
ret i32 0

bb10: ; preds = %bb4, %bb
Expand Down
18 changes: 9 additions & 9 deletions llvm/test/CodeGen/ARM/2009-08-21-PostRAKill.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,23 +4,23 @@
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
target triple = "armv7-apple-darwin9"

%struct.tree = type { i32, double, double, %struct.tree*, %struct.tree*, %struct.tree*, %struct.tree* }
@g = common global %struct.tree* null
%struct.tree = type { i32, double, double, ptr, ptr, ptr, ptr }
@g = common global ptr null

define %struct.tree* @tsp(%struct.tree* %t, i32 %nproc) nounwind {
define ptr @tsp(ptr %t, i32 %nproc) nounwind {
entry:
%t.idx51.val.i = load double, double* null ; <double> [#uses=1]
%t.idx51.val.i = load double, ptr null ; <double> [#uses=1]
br i1 undef, label %bb4.i, label %bb.i

bb.i: ; preds = %entry
unreachable

bb4.i: ; preds = %entry
%0 = load %struct.tree*, %struct.tree** @g, align 4 ; <%struct.tree*> [#uses=2]
%.idx45.i = getelementptr %struct.tree, %struct.tree* %0, i32 0, i32 1 ; <double*> [#uses=1]
%.idx45.val.i = load double, double* %.idx45.i ; <double> [#uses=1]
%.idx46.i = getelementptr %struct.tree, %struct.tree* %0, i32 0, i32 2 ; <double*> [#uses=1]
%.idx46.val.i = load double, double* %.idx46.i ; <double> [#uses=1]
%0 = load ptr, ptr @g, align 4 ; <ptr> [#uses=2]
%.idx45.i = getelementptr %struct.tree, ptr %0, i32 0, i32 1 ; <ptr> [#uses=1]
%.idx45.val.i = load double, ptr %.idx45.i ; <double> [#uses=1]
%.idx46.i = getelementptr %struct.tree, ptr %0, i32 0, i32 2 ; <ptr> [#uses=1]
%.idx46.val.i = load double, ptr %.idx46.i ; <double> [#uses=1]
%1 = fsub double 0.000000e+00, %.idx45.val.i ; <double> [#uses=2]
%2 = fmul double %1, %1 ; <double> [#uses=1]
%3 = fsub double %t.idx51.val.i, %.idx46.val.i ; <double> [#uses=2]
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,14 +4,14 @@
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
target triple = "armv7-apple-darwin9"

%struct.anon = type { [3 x double], double, %struct.node*, [64 x %struct.bnode*], [64 x %struct.bnode*] }
%struct.bnode = type { i16, double, [3 x double], i32, i32, [3 x double], [3 x double], [3 x double], double, %struct.bnode*, %struct.bnode* }
%struct.anon = type { [3 x double], double, ptr, [64 x ptr], [64 x ptr] }
%struct.bnode = type { i16, double, [3 x double], i32, i32, [3 x double], [3 x double], [3 x double], double, ptr, ptr }
%struct.icstruct = type { [3 x i32], i16 }
%struct.node = type { i16, double, [3 x double], i32, i32 }

declare double @floor(double) nounwind readnone

define void @intcoord(%struct.icstruct* noalias nocapture sret(%struct.icstruct) %agg.result, i1 %a, double %b) {
define void @intcoord(ptr noalias nocapture sret(%struct.icstruct) %agg.result, i1 %a, double %b) {
entry:
br i1 %a, label %bb3, label %bb1

Expand All @@ -32,7 +32,7 @@ bb9: ; preds = %bb7
br label %bb11

bb11: ; preds = %bb9, %bb7
%1 = getelementptr %struct.icstruct, %struct.icstruct* %agg.result, i32 0, i32 0, i32 0 ; <i32*> [#uses=1]
store i32 0, i32* %1
%1 = getelementptr %struct.icstruct, ptr %agg.result, i32 0, i32 0, i32 0 ; <ptr> [#uses=1]
store i32 0, ptr %1
ret void
}
27 changes: 13 additions & 14 deletions llvm/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,29 +5,28 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f3
target triple = "armv7-apple-darwin9"

%struct.Hosp = type { i32, i32, i32, %struct.List, %struct.List, %struct.List, %struct.List }
%struct.List = type { %struct.List*, %struct.Patient*, %struct.List* }
%struct.Patient = type { i32, i32, i32, %struct.Village* }
%struct.Village = type { [4 x %struct.Village*], %struct.Village*, %struct.List, %struct.Hosp, i32, i32 }
%struct.List = type { ptr, ptr, ptr }
%struct.Patient = type { i32, i32, i32, ptr }
%struct.Village = type { [4 x ptr], ptr, %struct.List, %struct.Hosp, i32, i32 }

define %struct.Village* @alloc_tree(i32 %level, i32 %label, %struct.Village* %back, i1 %p) nounwind {
define ptr @alloc_tree(i32 %level, i32 %label, ptr %back, i1 %p) nounwind {
entry:
br i1 %p, label %bb8, label %bb1

bb1: ; preds = %entry
%malloccall = tail call i8* @malloc(i32 ptrtoint (%struct.Village* getelementptr (%struct.Village, %struct.Village* null, i32 1) to i32))
%0 = bitcast i8* %malloccall to %struct.Village*
%malloccall = tail call ptr @malloc(i32 ptrtoint (ptr getelementptr (%struct.Village, ptr null, i32 1) to i32))
%exp2 = call double @ldexp(double 1.000000e+00, i32 %level) nounwind ; <double> [#uses=1]
%.c = fptosi double %exp2 to i32 ; <i32> [#uses=1]
store i32 %.c, i32* null
%1 = getelementptr %struct.Village, %struct.Village* %0, i32 0, i32 3, i32 6, i32 0 ; <%struct.List**> [#uses=1]
store %struct.List* null, %struct.List** %1
%2 = getelementptr %struct.Village, %struct.Village* %0, i32 0, i32 3, i32 6, i32 2 ; <%struct.List**> [#uses=1]
store %struct.List* null, %struct.List** %2
ret %struct.Village* %0
store i32 %.c, ptr null
%0 = getelementptr %struct.Village, ptr %malloccall, i32 0, i32 3, i32 6, i32 0 ; <ptr> [#uses=1]
store ptr null, ptr %0
%1 = getelementptr %struct.Village, ptr %malloccall, i32 0, i32 3, i32 6, i32 2 ; <ptr> [#uses=1]
store ptr null, ptr %1
ret ptr %malloccall

bb8: ; preds = %entry
ret %struct.Village* null
ret ptr null
}

declare double @ldexp(double, i32)
declare noalias i8* @malloc(i32)
declare noalias ptr @malloc(i32)
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/ARM/2009-08-26-ScalarToVector.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,12 +6,12 @@ target triple = "thumbv7-elf"
%bar = type { float, float, float }
%baz = type { i32, [16 x %bar], [16 x float], [16 x i32], i8 }
%foo = type { <4 x float> }
%quux = type { i32 (...)**, %baz*, i32 }
%quux = type { ptr, ptr, i32 }
%quuz = type { %quux, i32, %bar, [128 x i8], [16 x %foo], %foo, %foo, %foo }

declare <2 x i32> @llvm.arm.neon.vpadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone

define void @_ZN6squish10ClusterFit9Compress3EPv(%quuz* %this, i8* %block) {
define void @_ZN6squish10ClusterFit9Compress3EPv(ptr %this, ptr %block) {
entry:
%0 = lshr <4 x i32> zeroinitializer, <i32 31, i32 31, i32 31, i32 31>
%1 = shufflevector <4 x i32> %0, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/ARM/2009-08-27-ScalarToVector.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,10 +6,10 @@ target triple = "thumbv7-elf"
%bar = type { float, float, float }
%baz = type { i32, [16 x %bar], [16 x float], [16 x i32], i8 }
%foo = type { <4 x float> }
%quux = type { i32 (...)**, %baz*, i32 }
%quux = type { ptr, ptr, i32 }
%quuz = type { %quux, i32, %bar, [128 x i8], [16 x %foo], %foo, %foo, %foo }

define void @aaaa(%quuz* %this, i8* %block) {
define void @aaaa(ptr %this, ptr %block) {
entry:
br i1 undef, label %bb.nph269, label %bb201

Expand Down
80 changes: 38 additions & 42 deletions llvm/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,85 +7,81 @@
; CHECK: [[LSDA_LABEL]]:
; CHECK: .byte 255 @ @LPStart Encoding = omit

%struct.A = type { i32* }
%struct.A = type { ptr }

define void @"\01-[MyFunction Name:]"() personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) {
define void @"\01-[MyFunction Name:]"() personality ptr @__gxx_personality_sj0 {
entry:
%save_filt.1 = alloca i32
%save_eptr.0 = alloca i8*
%save_eptr.0 = alloca ptr
%a = alloca %struct.A
%eh_exception = alloca i8*
%eh_exception = alloca ptr
%eh_selector = alloca i32
%"alloca point" = bitcast i32 0 to i32
call void @_ZN1AC1Ev(%struct.A* %a)
call void @_ZN1AC1Ev(ptr %a)
invoke void @_Z3barv()
to label %invcont unwind label %lpad

invcont: ; preds = %entry
call void @_ZN1AD1Ev(%struct.A* %a) nounwind
call void @_ZN1AD1Ev(ptr %a) nounwind
br label %return

bb: ; preds = %ppad
%eh_select = load i32, i32* %eh_selector
store i32 %eh_select, i32* %save_filt.1, align 4
%eh_value = load i8*, i8** %eh_exception
store i8* %eh_value, i8** %save_eptr.0, align 4
call void @_ZN1AD1Ev(%struct.A* %a) nounwind
%0 = load i8*, i8** %save_eptr.0, align 4
store i8* %0, i8** %eh_exception, align 4
%1 = load i32, i32* %save_filt.1, align 4
store i32 %1, i32* %eh_selector, align 4
%eh_select = load i32, ptr %eh_selector
store i32 %eh_select, ptr %save_filt.1, align 4
%eh_value = load ptr, ptr %eh_exception
store ptr %eh_value, ptr %save_eptr.0, align 4
call void @_ZN1AD1Ev(ptr %a) nounwind
%0 = load ptr, ptr %save_eptr.0, align 4
store ptr %0, ptr %eh_exception, align 4
%1 = load i32, ptr %save_filt.1, align 4
store i32 %1, ptr %eh_selector, align 4
br label %Unwind

return: ; preds = %invcont
ret void

lpad: ; preds = %entry
%exn = landingpad {i8*, i32}
%exn = landingpad {ptr, i32}
cleanup
%eh_ptr = extractvalue {i8*, i32} %exn, 0
store i8* %eh_ptr, i8** %eh_exception
%eh_select2 = extractvalue {i8*, i32} %exn, 1
store i32 %eh_select2, i32* %eh_selector
%eh_ptr = extractvalue {ptr, i32} %exn, 0
store ptr %eh_ptr, ptr %eh_exception
%eh_select2 = extractvalue {ptr, i32} %exn, 1
store i32 %eh_select2, ptr %eh_selector
br label %ppad

ppad: ; preds = %lpad
br label %bb

Unwind: ; preds = %bb
%eh_ptr3 = load i8*, i8** %eh_exception
call void @_Unwind_SjLj_Resume(i8* %eh_ptr3)
%eh_ptr3 = load ptr, ptr %eh_exception
call void @_Unwind_SjLj_Resume(ptr %eh_ptr3)
unreachable
}

define linkonce_odr void @_ZN1AC1Ev(%struct.A* %this) {
define linkonce_odr void @_ZN1AC1Ev(ptr %this) {
entry:
%this_addr = alloca %struct.A*
%this_addr = alloca ptr
%"alloca point" = bitcast i32 0 to i32
store %struct.A* %this, %struct.A** %this_addr
%0 = call i8* @_Znwm(i32 4)
%1 = bitcast i8* %0 to i32*
%2 = load %struct.A*, %struct.A** %this_addr, align 4
%3 = getelementptr inbounds %struct.A, %struct.A* %2, i32 0, i32 0
store i32* %1, i32** %3, align 4
store ptr %this, ptr %this_addr
%0 = call ptr @_Znwm(i32 4)
%1 = load ptr, ptr %this_addr, align 4
store ptr %0, ptr %1, align 4
br label %return

return: ; preds = %entry
ret void
}

declare i8* @_Znwm(i32)
declare ptr @_Znwm(i32)

define linkonce_odr void @_ZN1AD1Ev(%struct.A* %this) nounwind {
define linkonce_odr void @_ZN1AD1Ev(ptr %this) nounwind {
entry:
%this_addr = alloca %struct.A*
%this_addr = alloca ptr
%"alloca point" = bitcast i32 0 to i32
store %struct.A* %this, %struct.A** %this_addr
%0 = load %struct.A*, %struct.A** %this_addr, align 4
%1 = getelementptr inbounds %struct.A, %struct.A* %0, i32 0, i32 0
%2 = load i32*, i32** %1, align 4
%3 = bitcast i32* %2 to i8*
call void @_ZdlPv(i8* %3) nounwind
store ptr %this, ptr %this_addr
%0 = load ptr, ptr %this_addr, align 4
%1 = load ptr, ptr %0, align 4
call void @_ZdlPv(ptr %1) nounwind
br label %bb

bb: ; preds = %entry
Expand All @@ -95,12 +91,12 @@ return: ; preds = %bb
ret void
}

declare void @_ZdlPv(i8*) nounwind
declare void @_ZdlPv(ptr) nounwind

declare void @_Z3barv()

declare i32 @llvm.eh.typeid.for(i8*) nounwind
declare i32 @llvm.eh.typeid.for(ptr) nounwind

declare i32 @__gxx_personality_sj0(...)

declare void @_Unwind_SjLj_Resume(i8*)
declare void @_Unwind_SjLj_Resume(ptr)
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll
View file
Original file line number Diff line number Diff line change
@@ -1,10 +1,10 @@
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
; pr4843

define <4 x i16> @v2regbug(<4 x i16>* %B) nounwind {
define <4 x i16> @v2regbug(ptr %B) nounwind {
;CHECK-LABEL: v2regbug:
;CHECK: vzip.16
%tmp1 = load <4 x i16>, <4 x i16>* %B
%tmp1 = load <4 x i16>, ptr %B
%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32><i32 0, i32 0, i32 1, i32 1>
ret <4 x i16> %tmp2
}
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/ARM/2009-09-09-AllOnes.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,6 +5,6 @@ target triple = "thumbv7-elf"
define void @foo() {
entry:
%0 = insertelement <4 x i32> undef, i32 -1, i32 3
store <4 x i32> %0, <4 x i32>* undef, align 16
store <4 x i32> %0, ptr undef, align 16
unreachable
}
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll
View file
Original file line number Diff line number Diff line change
@@ -1,16 +1,16 @@
; RUN: llc -O1 -mattr=+vfp2 -mtriple=arm-linux-gnueabi < %s | FileCheck %s
; pr4939

define void @test(double* %x, double* %y) nounwind {
%1 = load double, double* %x
%2 = load double, double* %y
define void @test(ptr %x, ptr %y) nounwind {
%1 = load double, ptr %x
%2 = load double, ptr %y
%3 = fsub double -0.000000e+00, %1
%4 = fcmp ugt double %2, %3
br i1 %4, label %bb1, label %bb2

bb1:
;CHECK: vstrhi
store double %1, double* %y
store double %1, ptr %y
br label %bb2

bb2:
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/ARM/2009-09-10-postdec.ll
View file
Original file line number Diff line number Diff line change
@@ -1,11 +1,11 @@
; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
; Radar 7213850

define i32 @test(i8* %d, i32 %x, i32 %y) nounwind {
%1 = ptrtoint i8* %d to i32
define i32 @test(ptr %d, i32 %x, i32 %y) nounwind {
%1 = ptrtoint ptr %d to i32
;CHECK: sub
%2 = sub i32 %x, %1
%3 = add nsw i32 %2, %y
store i8 0, i8* %d, align 1
store i8 0, ptr %d, align 1
ret i32 %3
}
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/ARM/2009-09-13-InvalidSubreg.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11,12 +11,12 @@ target triple = "armv7-eabi"

declare <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float>, <2 x float>) nounwind readnone

define arm_aapcs_vfpcc i8 @foo(%struct.fr* nocapture %this, %struct.obb* %box) nounwind {
define arm_aapcs_vfpcc i8 @foo(ptr nocapture %this, ptr %box) nounwind {
entry:
%val.i.i = load <4 x float>, <4 x float>* undef ; <<4 x float>> [#uses=1]
%val2.i.i = load <4 x float>, <4 x float>* null ; <<4 x float>> [#uses=1]
%elt3.i.i = getelementptr inbounds %struct.obb, %struct.obb* %box, i32 0, i32 0, i32 2, i32 0 ; <<4 x float>*> [#uses=1]
%val4.i.i = load <4 x float>, <4 x float>* %elt3.i.i ; <<4 x float>> [#uses=1]
%val.i.i = load <4 x float>, ptr undef ; <<4 x float>> [#uses=1]
%val2.i.i = load <4 x float>, ptr null ; <<4 x float>> [#uses=1]
%elt3.i.i = getelementptr inbounds %struct.obb, ptr %box, i32 0, i32 0, i32 2, i32 0 ; <ptr> [#uses=1]
%val4.i.i = load <4 x float>, ptr %elt3.i.i ; <<4 x float>> [#uses=1]
%0 = shufflevector <2 x float> undef, <2 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1]
%1 = fadd <4 x float> undef, zeroinitializer ; <<4 x float>> [#uses=1]
br label %bb33
Expand Down
32 changes: 16 additions & 16 deletions llvm/test/CodeGen/ARM/2009-09-13-InvalidSuperReg.ll
View file
Original file line number Diff line number Diff line change
@@ -1,28 +1,28 @@
; RUN: llc -mtriple=arm-eabi -mattr=+neon -mcpu=cortex-a9 %s -o /dev/null

define arm_aapcs_vfpcc <4 x float> @foo(i8* nocapture %pBuffer, i32 %numItems) nounwind {
%1 = ptrtoint i8* %pBuffer to i32
define arm_aapcs_vfpcc <4 x float> @foo(ptr nocapture %pBuffer, i32 %numItems) nounwind {
%1 = ptrtoint ptr %pBuffer to i32

%lsr.iv2641 = inttoptr i32 %1 to float*
%lsr.iv2641 = inttoptr i32 %1 to ptr
%tmp29 = add i32 %1, 4
%tmp2930 = inttoptr i32 %tmp29 to float*
%tmp2930 = inttoptr i32 %tmp29 to ptr
%tmp31 = add i32 %1, 8
%tmp3132 = inttoptr i32 %tmp31 to float*
%tmp3132 = inttoptr i32 %tmp31 to ptr
%tmp33 = add i32 %1, 12
%tmp3334 = inttoptr i32 %tmp33 to float*
%tmp3334 = inttoptr i32 %tmp33 to ptr
%tmp35 = add i32 %1, 16
%tmp3536 = inttoptr i32 %tmp35 to float*
%tmp3536 = inttoptr i32 %tmp35 to ptr
%tmp37 = add i32 %1, 20
%tmp3738 = inttoptr i32 %tmp37 to float*
%tmp3738 = inttoptr i32 %tmp37 to ptr
%tmp39 = add i32 %1, 24
%tmp3940 = inttoptr i32 %tmp39 to float*
%2 = load float, float* %lsr.iv2641, align 4
%3 = load float, float* %tmp2930, align 4
%4 = load float, float* %tmp3132, align 4
%5 = load float, float* %tmp3334, align 4
%6 = load float, float* %tmp3536, align 4
%7 = load float, float* %tmp3738, align 4
%8 = load float, float* %tmp3940, align 4
%tmp3940 = inttoptr i32 %tmp39 to ptr
%2 = load float, ptr %lsr.iv2641, align 4
%3 = load float, ptr %tmp2930, align 4
%4 = load float, ptr %tmp3132, align 4
%5 = load float, ptr %tmp3334, align 4
%6 = load float, ptr %tmp3536, align 4
%7 = load float, ptr %tmp3738, align 4
%8 = load float, ptr %tmp3940, align 4
%9 = insertelement <4 x float> undef, float %6, i32 0
%10 = shufflevector <4 x float> %9, <4 x float> undef, <4 x i32> zeroinitializer
%11 = insertelement <4 x float> %10, float %7, i32 1
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/ARM/2009-09-20-LiveIntervalsBug.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@

; PR4986

define arm_aapcs_vfpcc void @foo(i8* nocapture %pBuffer, i32 %numItems) nounwind {
define arm_aapcs_vfpcc void @foo(ptr nocapture %pBuffer, i32 %numItems) nounwind {
entry:
br i1 undef, label %return, label %bb.preheader

Expand All @@ -16,14 +16,14 @@ bb: ; preds = %bb, %bb.preheader
%3 = insertelement <4 x float> %2, float undef, i32 3 ; <<4 x float>> [#uses=1]
%4 = fmul <4 x float> undef, %3 ; <<4 x float>> [#uses=1]
%5 = extractelement <4 x float> %4, i32 3 ; <float> [#uses=1]
store float %5, float* undef, align 4
store float %5, ptr undef, align 4
br i1 undef, label %return, label %bb

return: ; preds = %bb, %entry
ret void
}

define arm_aapcs_vfpcc <4 x float> @bar(i8* nocapture %pBuffer, i32 %numItems) nounwind {
define arm_aapcs_vfpcc <4 x float> @bar(ptr nocapture %pBuffer, i32 %numItems) nounwind {
%1 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]
%2 = insertelement <4 x float> %1, float undef, i32 1 ; <<4 x float>> [#uses=1]
%3 = insertelement <4 x float> %2, float undef, i32 2 ; <<4 x float>> [#uses=1]
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/ARM/2009-09-21-LiveVariablesBug.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,10 +5,10 @@
%bar = type { <4 x float> }
%foo = type { %bar, %bar, %bar, %bar }

declare arm_aapcs_vfpcc <4 x float> @bbb(%bar*) nounwind
declare arm_aapcs_vfpcc <4 x float> @bbb(ptr) nounwind

define arm_aapcs_vfpcc void @aaa(%foo* noalias sret(%foo) %agg.result, %foo* %tfrm) nounwind {
define arm_aapcs_vfpcc void @aaa(ptr noalias sret(%foo) %agg.result, ptr %tfrm) nounwind {
entry:
%0 = call arm_aapcs_vfpcc <4 x float> @bbb(%bar* undef) nounwind ; <<4 x float>> [#uses=0]
%0 = call arm_aapcs_vfpcc <4 x float> @bbb(ptr undef) nounwind ; <<4 x float>> [#uses=0]
ret void
}
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/ARM/2009-09-22-LiveVariablesBug.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,17 +5,17 @@
%bar = type { %foo, %foo }
%foo = type { <4 x float> }

declare arm_aapcs_vfpcc float @aaa(%foo* nocapture) nounwind readonly
declare arm_aapcs_vfpcc float @aaa(ptr nocapture) nounwind readonly

declare arm_aapcs_vfpcc %bar* @bbb(%bar*, <4 x float>, <4 x float>) nounwind
declare arm_aapcs_vfpcc ptr @bbb(ptr, <4 x float>, <4 x float>) nounwind

define arm_aapcs_vfpcc void @ccc(i8* nocapture %pBuffer, i32 %numItems) nounwind {
define arm_aapcs_vfpcc void @ccc(ptr nocapture %pBuffer, i32 %numItems) nounwind {
entry:
br i1 undef, label %return, label %bb.nph

bb.nph: ; preds = %entry
%0 = call arm_aapcs_vfpcc %bar* @bbb(%bar* undef, <4 x float> undef, <4 x float> undef) nounwind ; <%bar*> [#uses=0]
%1 = call arm_aapcs_vfpcc float @aaa(%foo* undef) nounwind ; <float> [#uses=0]
%0 = call arm_aapcs_vfpcc ptr @bbb(ptr undef, <4 x float> undef, <4 x float> undef) nounwind ; <ptr> [#uses=0]
%1 = call arm_aapcs_vfpcc float @aaa(ptr undef) nounwind ; <float> [#uses=0]
unreachable

return: ; preds = %entry
Expand Down
18 changes: 9 additions & 9 deletions llvm/test/CodeGen/ARM/2009-09-23-LiveVariablesBug.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,17 +5,17 @@
%struct.1 = type { %struct.4, %struct.4 }
%struct.4 = type { <4 x float> }

define arm_aapcs_vfpcc %struct.1* @hhh3(%struct.1* %this, <4 x float> %lenation.0, <4 x float> %legalation.0) nounwind {
define arm_aapcs_vfpcc ptr @hhh3(ptr %this, <4 x float> %lenation.0, <4 x float> %legalation.0) nounwind {
entry:
%0 = call arm_aapcs_vfpcc %struct.4* @sss1(%struct.4* undef, float 0.000000e+00) nounwind ; <%struct.4*> [#uses=0]
%1 = call arm_aapcs_vfpcc %struct.4* @qqq1(%struct.4* null, float 5.000000e-01) nounwind ; <%struct.4*> [#uses=0]
%val92 = load <4 x float>, <4 x float>* null ; <<4 x float>> [#uses=1]
%2 = call arm_aapcs_vfpcc %struct.4* @zzz2(%struct.4* undef, <4 x float> %val92) nounwind ; <%struct.4*> [#uses=0]
ret %struct.1* %this
%0 = call arm_aapcs_vfpcc ptr @sss1(ptr undef, float 0.000000e+00) nounwind ; <ptr> [#uses=0]
%1 = call arm_aapcs_vfpcc ptr @qqq1(ptr null, float 5.000000e-01) nounwind ; <ptr> [#uses=0]
%val92 = load <4 x float>, ptr null ; <<4 x float>> [#uses=1]
%2 = call arm_aapcs_vfpcc ptr @zzz2(ptr undef, <4 x float> %val92) nounwind ; <ptr> [#uses=0]
ret ptr %this
}

declare arm_aapcs_vfpcc %struct.4* @qqq1(%struct.4*, float) nounwind
declare arm_aapcs_vfpcc ptr @qqq1(ptr, float) nounwind

declare arm_aapcs_vfpcc %struct.4* @sss1(%struct.4*, float) nounwind
declare arm_aapcs_vfpcc ptr @sss1(ptr, float) nounwind

declare arm_aapcs_vfpcc %struct.4* @zzz2(%struct.4*, <4 x float>) nounwind
declare arm_aapcs_vfpcc ptr @zzz2(ptr, <4 x float>) nounwind
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/ARM/2009-09-24-spill-align.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,13 +3,13 @@

define void @test_vget_lanep16() nounwind {
entry:
%arg0_poly16x4_t = alloca <4 x i16> ; <<4 x i16>*> [#uses=1]
%out_poly16_t = alloca i16 ; <i16*> [#uses=1]
%arg0_poly16x4_t = alloca <4 x i16> ; <ptr> [#uses=1]
%out_poly16_t = alloca i16 ; <ptr> [#uses=1]
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
; CHECK: vldr
%0 = load <4 x i16>, <4 x i16>* %arg0_poly16x4_t, align 8 ; <<4 x i16>> [#uses=1]
%0 = load <4 x i16>, ptr %arg0_poly16x4_t, align 8 ; <<4 x i16>> [#uses=1]
%1 = extractelement <4 x i16> %0, i32 1 ; <i16> [#uses=1]
store i16 %1, i16* %out_poly16_t, align 2
store i16 %1, ptr %out_poly16_t, align 2
br label %return

return: ; preds = %entry
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,17 +3,17 @@

%0 = type { double, double }

define void @foo(%0* noalias nocapture sret(%0) %agg.result, double %x.0, double %y.0) nounwind {
define void @foo(ptr noalias nocapture sret(%0) %agg.result, double %x.0, double %y.0) nounwind {
; CHECK-LABEL: foo:
; CHECK: bl __aeabi_dadd
; CHECK-NOT: strd
; CHECK: mov
%x76 = fmul double %y.0, 0.000000e+00 ; <double> [#uses=1]
%x77 = fadd double %y.0, 0.000000e+00 ; <double> [#uses=1]
%tmpr = fadd double %x.0, %x76 ; <double> [#uses=1]
%agg.result.0 = getelementptr %0, %0* %agg.result, i32 0, i32 0 ; <double*> [#uses=1]
store double %tmpr, double* %agg.result.0, align 8
%agg.result.1 = getelementptr %0, %0* %agg.result, i32 0, i32 1 ; <double*> [#uses=1]
store double %x77, double* %agg.result.1, align 8
%agg.result.0 = getelementptr %0, ptr %agg.result, i32 0, i32 0 ; <ptr> [#uses=1]
store double %tmpr, ptr %agg.result.0, align 8
%agg.result.1 = getelementptr %0, ptr %agg.result, i32 0, i32 1 ; <ptr> [#uses=1]
store double %x77, ptr %agg.result.1, align 8
ret void
}
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/ARM/2009-10-02-NEONSubregsBug.ll
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,13 @@
; RUN: llc -mtriple=armv7-eabi -mcpu=cortex-a8 -enable-unsafe-fp-math < %s
; PR5367

define arm_aapcs_vfpcc void @_Z27Benchmark_SceDualQuaternionPvm(i8* nocapture %pBuffer, i32 %numItems) nounwind {
define arm_aapcs_vfpcc void @_Z27Benchmark_SceDualQuaternionPvm(ptr nocapture %pBuffer, i32 %numItems) nounwind {
entry:
br i1 undef, label %return, label %bb

bb: ; preds = %bb, %entry
%0 = load float, float* undef, align 4 ; <float> [#uses=1]
%1 = load float, float* null, align 4 ; <float> [#uses=1]
%0 = load float, ptr undef, align 4 ; <float> [#uses=1]
%1 = load float, ptr null, align 4 ; <float> [#uses=1]
%2 = insertelement <4 x float> undef, float undef, i32 1 ; <<4 x float>> [#uses=1]
%3 = insertelement <4 x float> %2, float %1, i32 2 ; <<4 x float>> [#uses=2]
%4 = insertelement <4 x float> undef, float %0, i32 2 ; <<4 x float>> [#uses=1]
Expand Down Expand Up @@ -50,10 +50,10 @@ bb: ; preds = %bb, %entry
%41 = fadd <4 x float> %40, zeroinitializer ; <<4 x float>> [#uses=1]
%42 = shufflevector <4 x float> undef, <4 x float> %41, <4 x i32> <i32 0, i32 1, i32 6, i32 3> ; <<4 x float>> [#uses=1]
%43 = fmul <4 x float> %42, %31 ; <<4 x float>> [#uses=1]
store float undef, float* undef, align 4
store float 0.000000e+00, float* null, align 4
store float undef, ptr undef, align 4
store float 0.000000e+00, ptr null, align 4
%44 = extractelement <4 x float> %43, i32 1 ; <float> [#uses=1]
store float %44, float* undef, align 4
store float %44, ptr undef, align 4
br i1 undef, label %return, label %bb

return: ; preds = %bb, %entry
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/ARM/2009-10-16-Scope.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,12 +5,12 @@

define void @bar() nounwind ssp {
entry:
%count_ = alloca i32, align 4 ; <i32*> [#uses=2]
%count_ = alloca i32, align 4 ; <ptr> [#uses=2]
br label %do.body, !dbg !0

do.body: ; preds = %entry
call void @llvm.dbg.declare(metadata i32* %count_, metadata !4, metadata !DIExpression()), !dbg !DILocation(scope: !5)
%conv = ptrtoint i32* %count_ to i32, !dbg !0 ; <i32> [#uses=1]
call void @llvm.dbg.declare(metadata ptr %count_, metadata !4, metadata !DIExpression()), !dbg !DILocation(scope: !5)
%conv = ptrtoint ptr %count_ to i32, !dbg !0 ; <i32> [#uses=1]
%call = call i32 @foo(i32 %conv) ssp, !dbg !0 ; <i32> [#uses=0]
br label %do.end, !dbg !0

Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/ARM/2009-10-27-double-align.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10,8 +10,8 @@ entry:
;NOREGALLOC: [sp]
;REGALLOC: [sp]
;REGALLOC: [sp, #12]
tail call void (i8*, ...) @f(i8* getelementptr ([1 x i8], [1 x i8]* @.str, i32 0, i32 0), i32 1, double 2.000000e+00, i32 3, double 4.000000e+00)
tail call void (ptr, ...) @f(ptr @.str, i32 1, double 2.000000e+00, i32 3, double 4.000000e+00)
ret void
}

declare void @f(i8*, ...)
declare void @f(ptr, ...)
7 changes: 3 additions & 4 deletions llvm/test/CodeGen/ARM/2009-10-30.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,10 +8,9 @@ entry:
;CHECK: add r{{[0-9]+}}, sp, #8
;CHECK: str r{{[0-9]+}}, [sp], #4
;CHECK: bx lr
%ap = alloca i8*, align 4
%ap1 = bitcast i8** %ap to i8*
call void @llvm.va_start(i8* %ap1)
%ap = alloca ptr, align 4
call void @llvm.va_start(ptr %ap)
ret void
}

declare void @llvm.va_start(i8*) nounwind
declare void @llvm.va_start(ptr) nounwind
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/ARM/2009-11-01-NeonMoves.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,12 +5,12 @@ target triple = "armv7-eabi"

%foo = type { <4 x float> }

define arm_aapcs_vfpcc void @bar(%foo* noalias sret(%foo) %agg.result, <4 x float> %quat.0) nounwind {
define arm_aapcs_vfpcc void @bar(ptr noalias sret(%foo) %agg.result, <4 x float> %quat.0) nounwind {
entry:
%quat_addr = alloca %foo, align 16 ; <%foo*> [#uses=2]
%0 = getelementptr inbounds %foo, %foo* %quat_addr, i32 0, i32 0 ; <<4 x float>*> [#uses=1]
store <4 x float> %quat.0, <4 x float>* %0
%1 = call arm_aapcs_vfpcc <4 x float> @quux(%foo* %quat_addr) nounwind ; <<4 x float>> [#uses=3]
%quat_addr = alloca %foo, align 16 ; <ptr> [#uses=2]
%0 = getelementptr inbounds %foo, ptr %quat_addr, i32 0, i32 0 ; <ptr> [#uses=1]
store <4 x float> %quat.0, ptr %0
%1 = call arm_aapcs_vfpcc <4 x float> @quux(ptr %quat_addr) nounwind ; <<4 x float>> [#uses=3]
%2 = fmul <4 x float> %1, %1 ; <<4 x float>> [#uses=2]
%3 = shufflevector <4 x float> %2, <4 x float> undef, <2 x i32> <i32 0, i32 1> ; <<2 x float>> [#uses=1]
%4 = shufflevector <4 x float> %2, <4 x float> undef, <2 x i32> <i32 2, i32 3> ; <<2 x float>> [#uses=1]
Expand All @@ -25,13 +25,13 @@ entry:
%10 = call <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float> %9, <4 x float> %7) nounwind ; <<4 x float>> [#uses=1]
%11 = fmul <4 x float> %10, %8 ; <<4 x float>> [#uses=1]
%12 = fmul <4 x float> %11, %1 ; <<4 x float>> [#uses=1]
%13 = call arm_aapcs_vfpcc %foo* @baz(%foo* %agg.result, <4 x float> %12) nounwind ; <%foo*> [#uses=0]
%13 = call arm_aapcs_vfpcc ptr @baz(ptr %agg.result, <4 x float> %12) nounwind ; <ptr> [#uses=0]
ret void
}

declare arm_aapcs_vfpcc %foo* @baz(%foo*, <4 x float>) nounwind
declare arm_aapcs_vfpcc ptr @baz(ptr, <4 x float>) nounwind

declare arm_aapcs_vfpcc <4 x float> @quux(%foo* nocapture) nounwind readonly
declare arm_aapcs_vfpcc <4 x float> @quux(ptr nocapture) nounwind readonly

declare <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float>, <2 x float>) nounwind readnone

Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/ARM/2009-11-02-NegativeLane.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2,18 +2,18 @@
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
target triple = "armv7-eabi"

define arm_aapcs_vfpcc void @foo(i8* nocapture %pBuffer, i32 %numItems) nounwind {
define arm_aapcs_vfpcc void @foo(ptr nocapture %pBuffer, i32 %numItems) nounwind {
entry:
br i1 undef, label %return, label %bb

bb: ; preds = %bb, %entry
; CHECK: vld1.16 {d16[], d17[]}
%0 = load i16, i16* undef, align 2
%0 = load i16, ptr undef, align 2
%1 = insertelement <8 x i16> undef, i16 %0, i32 2
%2 = insertelement <8 x i16> %1, i16 undef, i32 3
%3 = mul <8 x i16> %2, %2
%4 = extractelement <8 x i16> %3, i32 2
store i16 %4, i16* undef, align 2
store i16 %4, ptr undef, align 2
br i1 undef, label %return, label %bb

return: ; preds = %bb, %entry
Expand Down
26 changes: 13 additions & 13 deletions llvm/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@ target triple = "armv7-eabi"

define arm_aapcs_vfpcc void @foo() {
entry:
%0 = load float, float* null, align 4 ; <float> [#uses=2]
%0 = load float, ptr null, align 4 ; <float> [#uses=2]
%1 = fmul float %0, %0 ; <float> [#uses=2]
%2 = fmul float 0.000000e+00, %1 ; <float> [#uses=2]
%3 = fmul float %0, %1 ; <float> [#uses=1]
Expand All @@ -18,7 +18,7 @@ entry:
%7 = fsub float %2, %2 ; <float> [#uses=1]
%8 = fsub float 0.000000e+00, %7 ; <float> [#uses=3]
%9 = fadd float %2, %2 ; <float> [#uses=3]
%10 = load float, float* undef, align 8 ; <float> [#uses=3]
%10 = load float, ptr undef, align 8 ; <float> [#uses=3]
%11 = fmul float %8, %10 ; <float> [#uses=1]
%12 = fadd float %11, %11 ; <float> [#uses=2]
%13 = fmul float %12, %12 ; <float> [#uses=1]
Expand All @@ -30,10 +30,10 @@ entry:
%19 = fadd float %18, 0.000000e+00 ; <float> [#uses=1]
%20 = fmul float %10, %10 ; <float> [#uses=1]
%21 = fadd float %19, %20 ; <float> [#uses=1]
%22 = load float, float* undef, align 8 ; <float> [#uses=1]
%22 = load float, ptr undef, align 8 ; <float> [#uses=1]
%23 = fmul float %5, %22 ; <float> [#uses=1]
%24 = fadd float %23, %23 ; <float> [#uses=1]
%25 = load float, float* undef, align 8 ; <float> [#uses=2]
%25 = load float, ptr undef, align 8 ; <float> [#uses=2]
%26 = fmul float %8, %25 ; <float> [#uses=1]
%27 = fadd float %24, %26 ; <float> [#uses=1]
%28 = fmul float %9, %25 ; <float> [#uses=1]
Expand All @@ -49,18 +49,18 @@ entry:
%38 = fadd float %36, %37 ; <float> [#uses=1]
%39 = fmul float %38, %38 ; <float> [#uses=1]
%40 = fadd float %38, %39 ; <float> [#uses=1]
store float %12, float* undef, align 8
store float %17, float* undef, align 4
store float %21, float* undef, align 8
store float %27, float* undef, align 8
store float %29, float* undef, align 4
store float %31, float* undef, align 8
store float %40, float* undef, align 8
store float %12, float* null, align 8
store float %12, ptr undef, align 8
store float %17, ptr undef, align 4
store float %21, ptr undef, align 8
store float %27, ptr undef, align 8
store float %29, ptr undef, align 4
store float %31, ptr undef, align 8
store float %40, ptr undef, align 8
store float %12, ptr null, align 8
%41 = fmul float %17, %17 ; <float> [#uses=1]
%42 = fadd float %41, %41 ; <float> [#uses=1]
%43 = fmul float %35, %35 ; <float> [#uses=1]
%44 = fadd float %42, %43 ; <float> [#uses=1]
store float %44, float* null, align 4
store float %44, ptr null, align 4
unreachable
}
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/ARM/2009-11-13-CoalescerCrash.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,16 +5,16 @@
%pln = type { %vec, float }
%vec = type { [4 x float] }

define arm_aapcs_vfpcc float @aaa(%vec* nocapture %ustart, %vec* nocapture %udir, %vec* nocapture %vstart, %vec* nocapture %vdir, %vec* %upoint, %vec* %vpoint) {
define arm_aapcs_vfpcc float @aaa(ptr nocapture %ustart, ptr nocapture %udir, ptr nocapture %vstart, ptr nocapture %vdir, ptr %upoint, ptr %vpoint) {
entry:
br i1 undef, label %bb81, label %bb48

bb48: ; preds = %entry
%0 = call arm_aapcs_vfpcc %0 @bbb(%pln* undef, %vec* %vstart, %vec* undef) nounwind ; <%0> [#uses=0]
%0 = call arm_aapcs_vfpcc %0 @bbb(ptr undef, ptr %vstart, ptr undef) nounwind ; <%0> [#uses=0]
ret float 0.000000e+00

bb81: ; preds = %entry
ret float 0.000000e+00
}

declare arm_aapcs_vfpcc %0 @bbb(%pln* nocapture, %vec* nocapture, %vec* nocapture) nounwind
declare arm_aapcs_vfpcc %0 @bbb(ptr nocapture, ptr nocapture, ptr nocapture) nounwind
22 changes: 11 additions & 11 deletions llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert.ll
View file
Original file line number Diff line number Diff line change
@@ -1,23 +1,23 @@
; RUN: llc -mtriple=armv7-eabi -mcpu=cortex-a8 < %s
; PR5411

%bar = type { %quad, float, float, [3 x %quux*], [3 x %bar*], [2 x %bar*], [3 x i8], i8 }
%baz = type { %bar*, i32 }
%bar = type { %quad, float, float, [3 x ptr], [3 x ptr], [2 x ptr], [3 x i8], i8 }
%baz = type { ptr, i32 }
%foo = type { i8, %quuz, %quad, float, [64 x %quux], [128 x %bar], i32, %baz, %baz }
%quad = type { [4 x float] }
%quux = type { %quad, %quad }
%quuz = type { [4 x %quux*], [4 x float], i32 }
%quuz = type { [4 x ptr], [4 x float], i32 }

define arm_aapcs_vfpcc %bar* @aaa(%foo* nocapture %this, %quux* %a, %quux* %b, %quux* %c, i8 zeroext %forced) {
define arm_aapcs_vfpcc ptr @aaa(ptr nocapture %this, ptr %a, ptr %b, ptr %c, i8 zeroext %forced) {
entry:
br i1 undef, label %bb85, label %bb

bb: ; preds = %entry
%0 = getelementptr inbounds %bar, %bar* null, i32 0, i32 0, i32 0, i32 2 ; <float*> [#uses=2]
%1 = load float, float* undef, align 4 ; <float> [#uses=1]
%0 = getelementptr inbounds %bar, ptr null, i32 0, i32 0, i32 0, i32 2 ; <ptr> [#uses=2]
%1 = load float, ptr undef, align 4 ; <float> [#uses=1]
%2 = fsub float 0.000000e+00, undef ; <float> [#uses=2]
%3 = fmul float 0.000000e+00, undef ; <float> [#uses=1]
%4 = load float, float* %0, align 4 ; <float> [#uses=3]
%4 = load float, ptr %0, align 4 ; <float> [#uses=3]
%5 = fmul float %4, %2 ; <float> [#uses=1]
%6 = fsub float %3, %5 ; <float> [#uses=1]
%7 = fmul float %4, undef ; <float> [#uses=1]
Expand All @@ -32,11 +32,11 @@ bb: ; preds = %entry
%16 = fadd float %14, %15 ; <float> [#uses=1]
%17 = select i1 undef, float undef, float %16 ; <float> [#uses=1]
%18 = fdiv float %17, 0.000000e+00 ; <float> [#uses=1]
store float %18, float* undef, align 4
store float %18, ptr undef, align 4
%19 = fmul float %4, undef ; <float> [#uses=1]
store float %19, float* %0, align 4
ret %bar* null
store float %19, ptr %0, align 4
ret ptr null

bb85: ; preds = %entry
ret %bar* null
ret ptr null
}
66 changes: 33 additions & 33 deletions llvm/test/CodeGen/ARM/2009-11-13-ScavengerAssert2.ll
View file
Original file line number Diff line number Diff line change
@@ -1,14 +1,14 @@
; RUN: llc -mtriple=armv7-eabi -mcpu=cortex-a8 < %s
; PR5412

%bar = type { %quad, float, float, [3 x %quuz*], [3 x %bar*], [2 x %bar*], [3 x i8], i8 }
%baz = type { %bar*, i32 }
%bar = type { %quad, float, float, [3 x ptr], [3 x ptr], [2 x ptr], [3 x i8], i8 }
%baz = type { ptr, i32 }
%foo = type { i8, %quux, %quad, float, [64 x %quuz], [128 x %bar], i32, %baz, %baz }
%quad = type { [4 x float] }
%quux = type { [4 x %quuz*], [4 x float], i32 }
%quux = type { [4 x ptr], [4 x float], i32 }
%quuz = type { %quad, %quad }

define arm_aapcs_vfpcc %bar* @aaa(%foo* nocapture %this, %quuz* %a, %quuz* %b, %quuz* %c, i8 zeroext %forced) {
define arm_aapcs_vfpcc ptr @aaa(ptr nocapture %this, ptr %a, ptr %b, ptr %c, i8 zeroext %forced) {
entry:
br i1 undef, label %bb85, label %bb

Expand All @@ -19,22 +19,22 @@ bb2.i: ; preds = %bb
br label %bb3.i

bb3.i: ; preds = %bb2.i, %bb
%0 = getelementptr inbounds %quuz, %quuz* %a, i32 0, i32 1, i32 0, i32 0 ; <float*> [#uses=0]
%0 = getelementptr inbounds %quuz, ptr %a, i32 0, i32 1, i32 0, i32 0 ; <ptr> [#uses=0]
%1 = fsub float 0.000000e+00, undef ; <float> [#uses=1]
%2 = getelementptr inbounds %quuz, %quuz* %b, i32 0, i32 1, i32 0, i32 1 ; <float*> [#uses=2]
%3 = load float, float* %2, align 4 ; <float> [#uses=1]
%4 = getelementptr inbounds %quuz, %quuz* %a, i32 0, i32 1, i32 0, i32 1 ; <float*> [#uses=1]
%2 = getelementptr inbounds %quuz, ptr %b, i32 0, i32 1, i32 0, i32 1 ; <ptr> [#uses=2]
%3 = load float, ptr %2, align 4 ; <float> [#uses=1]
%4 = getelementptr inbounds %quuz, ptr %a, i32 0, i32 1, i32 0, i32 1 ; <ptr> [#uses=1]
%5 = fsub float %3, undef ; <float> [#uses=2]
%6 = getelementptr inbounds %quuz, %quuz* %b, i32 0, i32 1, i32 0, i32 2 ; <float*> [#uses=2]
%7 = load float, float* %6, align 4 ; <float> [#uses=1]
%6 = getelementptr inbounds %quuz, ptr %b, i32 0, i32 1, i32 0, i32 2 ; <ptr> [#uses=2]
%7 = load float, ptr %6, align 4 ; <float> [#uses=1]
%8 = fsub float %7, undef ; <float> [#uses=1]
%9 = getelementptr inbounds %quuz, %quuz* %c, i32 0, i32 1, i32 0, i32 0 ; <float*> [#uses=2]
%10 = load float, float* %9, align 4 ; <float> [#uses=1]
%9 = getelementptr inbounds %quuz, ptr %c, i32 0, i32 1, i32 0, i32 0 ; <ptr> [#uses=2]
%10 = load float, ptr %9, align 4 ; <float> [#uses=1]
%11 = fsub float %10, undef ; <float> [#uses=2]
%12 = getelementptr inbounds %quuz, %quuz* %c, i32 0, i32 1, i32 0, i32 1 ; <float*> [#uses=2]
%13 = load float, float* %12, align 4 ; <float> [#uses=1]
%12 = getelementptr inbounds %quuz, ptr %c, i32 0, i32 1, i32 0, i32 1 ; <ptr> [#uses=2]
%13 = load float, ptr %12, align 4 ; <float> [#uses=1]
%14 = fsub float %13, undef ; <float> [#uses=1]
%15 = load float, float* undef, align 4 ; <float> [#uses=1]
%15 = load float, ptr undef, align 4 ; <float> [#uses=1]
%16 = fsub float %15, undef ; <float> [#uses=1]
%17 = fmul float %5, %16 ; <float> [#uses=1]
%18 = fsub float %17, 0.000000e+00 ; <float> [#uses=5]
Expand All @@ -43,20 +43,20 @@ bb3.i: ; preds = %bb2.i, %bb
%21 = fmul float %1, %14 ; <float> [#uses=1]
%22 = fmul float %5, %11 ; <float> [#uses=1]
%23 = fsub float %21, %22 ; <float> [#uses=2]
store float %18, float* undef
%24 = getelementptr inbounds %bar, %bar* null, i32 0, i32 0, i32 0, i32 1 ; <float*> [#uses=2]
store float %20, float* %24
store float %23, float* undef
%25 = getelementptr inbounds %bar, %bar* null, i32 0, i32 0, i32 0, i32 3 ; <float*> [#uses=0]
store float %18, ptr undef
%24 = getelementptr inbounds %bar, ptr null, i32 0, i32 0, i32 0, i32 1 ; <ptr> [#uses=2]
store float %20, ptr %24
store float %23, ptr undef
%25 = getelementptr inbounds %bar, ptr null, i32 0, i32 0, i32 0, i32 3 ; <ptr> [#uses=0]
%26 = fmul float %18, %18 ; <float> [#uses=1]
%27 = fadd float %26, undef ; <float> [#uses=1]
%28 = fadd float %27, undef ; <float> [#uses=1]
%29 = call arm_aapcs_vfpcc float @sqrtf(float %28) readnone ; <float> [#uses=1]
%30 = load float, float* null, align 4 ; <float> [#uses=2]
%31 = load float, float* %4, align 4 ; <float> [#uses=2]
%32 = load float, float* %2, align 4 ; <float> [#uses=2]
%33 = load float, float* null, align 4 ; <float> [#uses=3]
%34 = load float, float* %6, align 4 ; <float> [#uses=2]
%30 = load float, ptr null, align 4 ; <float> [#uses=2]
%31 = load float, ptr %4, align 4 ; <float> [#uses=2]
%32 = load float, ptr %2, align 4 ; <float> [#uses=2]
%33 = load float, ptr null, align 4 ; <float> [#uses=3]
%34 = load float, ptr %6, align 4 ; <float> [#uses=2]
%35 = fsub float %33, %34 ; <float> [#uses=2]
%36 = fmul float %20, %35 ; <float> [#uses=1]
%37 = fsub float %36, undef ; <float> [#uses=1]
Expand All @@ -71,12 +71,12 @@ bb3.i: ; preds = %bb2.i, %bb
%46 = fadd float %44, %45 ; <float> [#uses=1]
%47 = fmul float %33, %43 ; <float> [#uses=1]
%48 = fadd float %46, %47 ; <float> [#uses=2]
%49 = load float, float* %9, align 4 ; <float> [#uses=2]
%49 = load float, ptr %9, align 4 ; <float> [#uses=2]
%50 = fsub float %30, %49 ; <float> [#uses=1]
%51 = load float, float* %12, align 4 ; <float> [#uses=3]
%51 = load float, ptr %12, align 4 ; <float> [#uses=3]
%52 = fsub float %32, %51 ; <float> [#uses=2]
%53 = load float, float* undef, align 4 ; <float> [#uses=2]
%54 = load float, float* %24, align 4 ; <float> [#uses=2]
%53 = load float, ptr undef, align 4 ; <float> [#uses=2]
%54 = load float, ptr %24, align 4 ; <float> [#uses=2]
%55 = fmul float %54, undef ; <float> [#uses=1]
%56 = fmul float undef, %52 ; <float> [#uses=1]
%57 = fsub float %55, %56 ; <float> [#uses=1]
Expand All @@ -93,7 +93,7 @@ bb3.i: ; preds = %bb2.i, %bb
%68 = fsub float %51, %31 ; <float> [#uses=1]
%69 = fsub float %53, %33 ; <float> [#uses=1]
%70 = fmul float undef, %67 ; <float> [#uses=1]
%71 = load float, float* undef, align 4 ; <float> [#uses=2]
%71 = load float, ptr undef, align 4 ; <float> [#uses=2]
%72 = fmul float %71, %69 ; <float> [#uses=1]
%73 = fsub float %70, %72 ; <float> [#uses=1]
%74 = fmul float %71, %68 ; <float> [#uses=1]
Expand All @@ -107,17 +107,17 @@ bb3.i: ; preds = %bb2.i, %bb
%iftmp.164.0 = select i1 undef, float %29, float 1.000000e+00 ; <float> [#uses=1]
%82 = fdiv float %81, %iftmp.164.0 ; <float> [#uses=1]
%iftmp.165.0 = select i1 undef, float %82, float 0.000000e+00 ; <float> [#uses=1]
store float %iftmp.165.0, float* undef, align 4
store float %iftmp.165.0, ptr undef, align 4
br i1 false, label %bb4.i97, label %ccc.exit98

bb4.i97: ; preds = %bb3.i
br label %ccc.exit98

ccc.exit98: ; preds = %bb4.i97, %bb3.i
ret %bar* null
ret ptr null

bb85: ; preds = %entry
ret %bar* null
ret ptr null
}

declare arm_aapcs_vfpcc float @sqrtf(float) readnone
54 changes: 27 additions & 27 deletions llvm/test/CodeGen/ARM/2009-11-13-VRRewriterCrash.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2,16 +2,16 @@
; PR5412
; rdar://7384107

%bar = type { %quad, float, float, [3 x %quuz*], [3 x %bar*], [2 x %bar*], [3 x i8], i8 }
%baz = type { %bar*, i32 }
%bar = type { %quad, float, float, [3 x ptr], [3 x ptr], [2 x ptr], [3 x i8], i8 }
%baz = type { ptr, i32 }
%foo = type { i8, %quux, %quad, float, [64 x %quuz], [128 x %bar], i32, %baz, %baz }
%quad = type { [4 x float] }
%quux = type { [4 x %quuz*], [4 x float], i32 }
%quux = type { [4 x ptr], [4 x float], i32 }
%quuz = type { %quad, %quad }

define arm_aapcs_vfpcc %bar* @aaa(%foo* nocapture %this, %quuz* %a, %quuz* %b, %quuz* %c, i8 zeroext %forced) {
define arm_aapcs_vfpcc ptr @aaa(ptr nocapture %this, ptr %a, ptr %b, ptr %c, i8 zeroext %forced) {
entry:
%0 = load %bar*, %bar** undef, align 4 ; <%bar*> [#uses=2]
%0 = load ptr, ptr undef, align 4 ; <ptr> [#uses=2]
br i1 false, label %bb85, label %bb

bb: ; preds = %entry
Expand All @@ -21,32 +21,32 @@ bb2.i: ; preds = %bb
br label %bb3.i

bb3.i: ; preds = %bb2.i, %bb
%1 = getelementptr inbounds %quuz, %quuz* %a, i32 0, i32 1, i32 0, i32 0 ; <float*> [#uses=1]
%1 = getelementptr inbounds %quuz, ptr %a, i32 0, i32 1, i32 0, i32 0 ; <ptr> [#uses=1]
%2 = fsub float 0.000000e+00, undef ; <float> [#uses=1]
%3 = getelementptr inbounds %quuz, %quuz* %b, i32 0, i32 1, i32 0, i32 1 ; <float*> [#uses=1]
%4 = getelementptr inbounds %quuz, %quuz* %b, i32 0, i32 1, i32 0, i32 2 ; <float*> [#uses=1]
%3 = getelementptr inbounds %quuz, ptr %b, i32 0, i32 1, i32 0, i32 1 ; <ptr> [#uses=1]
%4 = getelementptr inbounds %quuz, ptr %b, i32 0, i32 1, i32 0, i32 2 ; <ptr> [#uses=1]
%5 = fsub float 0.000000e+00, undef ; <float> [#uses=1]
%6 = getelementptr inbounds %quuz, %quuz* %c, i32 0, i32 1, i32 0, i32 0 ; <float*> [#uses=1]
%7 = getelementptr inbounds %quuz, %quuz* %c, i32 0, i32 1, i32 0, i32 1 ; <float*> [#uses=1]
%6 = getelementptr inbounds %quuz, ptr %c, i32 0, i32 1, i32 0, i32 0 ; <ptr> [#uses=1]
%7 = getelementptr inbounds %quuz, ptr %c, i32 0, i32 1, i32 0, i32 1 ; <ptr> [#uses=1]
%8 = fsub float undef, undef ; <float> [#uses=1]
%9 = fmul float 0.000000e+00, %8 ; <float> [#uses=1]
%10 = fmul float %5, 0.000000e+00 ; <float> [#uses=1]
%11 = fsub float %9, %10 ; <float> [#uses=3]
%12 = fmul float %2, 0.000000e+00 ; <float> [#uses=1]
%13 = fmul float 0.000000e+00, undef ; <float> [#uses=1]
%14 = fsub float %12, %13 ; <float> [#uses=2]
store float %14, float* undef
%15 = getelementptr inbounds %bar, %bar* %0, i32 0, i32 0, i32 0, i32 3 ; <float*> [#uses=1]
store float 0.000000e+00, float* %15
store float %14, ptr undef
%15 = getelementptr inbounds %bar, ptr %0, i32 0, i32 0, i32 0, i32 3 ; <ptr> [#uses=1]
store float 0.000000e+00, ptr %15
%16 = fmul float %11, %11 ; <float> [#uses=1]
%17 = fadd float %16, 0.000000e+00 ; <float> [#uses=1]
%18 = fadd float %17, undef ; <float> [#uses=1]
%19 = call arm_aapcs_vfpcc float @sqrtf(float %18) readnone ; <float> [#uses=2]
%20 = fcmp ogt float %19, 0x3F1A36E2E0000000 ; <i1> [#uses=1]
%21 = load float, float* %1, align 4 ; <float> [#uses=2]
%22 = load float, float* %3, align 4 ; <float> [#uses=2]
%23 = load float, float* undef, align 4 ; <float> [#uses=2]
%24 = load float, float* %4, align 4 ; <float> [#uses=2]
%21 = load float, ptr %1, align 4 ; <float> [#uses=2]
%22 = load float, ptr %3, align 4 ; <float> [#uses=2]
%23 = load float, ptr undef, align 4 ; <float> [#uses=2]
%24 = load float, ptr %4, align 4 ; <float> [#uses=2]
%25 = fsub float %23, %24 ; <float> [#uses=2]
%26 = fmul float 0.000000e+00, %25 ; <float> [#uses=1]
%27 = fsub float %26, undef ; <float> [#uses=1]
Expand All @@ -59,11 +59,11 @@ bb3.i: ; preds = %bb2.i, %bb
%34 = fadd float %32, %33 ; <float> [#uses=1]
%35 = fmul float %23, %31 ; <float> [#uses=1]
%36 = fadd float %34, %35 ; <float> [#uses=1]
%37 = load float, float* %6, align 4 ; <float> [#uses=2]
%38 = load float, float* %7, align 4 ; <float> [#uses=2]
%37 = load float, ptr %6, align 4 ; <float> [#uses=2]
%38 = load float, ptr %7, align 4 ; <float> [#uses=2]
%39 = fsub float %22, %38 ; <float> [#uses=2]
%40 = load float, float* undef, align 4 ; <float> [#uses=1]
%41 = load float, float* null, align 4 ; <float> [#uses=2]
%40 = load float, ptr undef, align 4 ; <float> [#uses=1]
%41 = load float, ptr null, align 4 ; <float> [#uses=2]
%42 = fmul float %41, undef ; <float> [#uses=1]
%43 = fmul float undef, %39 ; <float> [#uses=1]
%44 = fsub float %42, %43 ; <float> [#uses=1]
Expand All @@ -80,7 +80,7 @@ bb3.i: ; preds = %bb2.i, %bb
%55 = fmul float undef, undef ; <float> [#uses=1]
%56 = fsub float %54, %55 ; <float> [#uses=1]
%57 = fmul float undef, %53 ; <float> [#uses=1]
%58 = load float, float* undef, align 4 ; <float> [#uses=2]
%58 = load float, ptr undef, align 4 ; <float> [#uses=2]
%59 = fmul float %58, undef ; <float> [#uses=1]
%60 = fsub float %57, %59 ; <float> [#uses=1]
%61 = fmul float %58, undef ; <float> [#uses=1]
Expand All @@ -95,19 +95,19 @@ bb3.i: ; preds = %bb2.i, %bb
%70 = select i1 undef, float %69, float %68 ; <float> [#uses=1]
%iftmp.164.0 = select i1 %20, float %19, float 1.000000e+00 ; <float> [#uses=1]
%71 = fdiv float %70, %iftmp.164.0 ; <float> [#uses=1]
store float %71, float* null, align 4
%72 = icmp eq %bar* null, %0 ; <i1> [#uses=1]
store float %71, ptr null, align 4
%72 = icmp eq ptr null, %0 ; <i1> [#uses=1]
br i1 %72, label %bb4.i97, label %ccc.exit98

bb4.i97: ; preds = %bb3.i
%73 = load %bar*, %bar** undef, align 4 ; <%bar*> [#uses=0]
%73 = load ptr, ptr undef, align 4 ; <ptr> [#uses=0]
br label %ccc.exit98

ccc.exit98: ; preds = %bb4.i97, %bb3.i
ret %bar* null
ret ptr null

bb85: ; preds = %entry
ret %bar* null
ret ptr null
}

declare arm_aapcs_vfpcc float @sqrtf(float) readnone
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/ARM/2009-11-30-LiveVariablesBug.ll
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,13 @@
; RUN: llc -mtriple=armv7-eabi -mcpu=cortex-a8 < %s
; PR5614

%"als" = type { i32 (...)** }
%"als" = type { ptr }
%"av" = type { %"als" }
%"c" = type { %"lsm", %"Vec3", %"av"*, float, i8, float, %"lsm", i8, %"Vec3", %"Vec3", %"Vec3", float, float, float, %"Vec3", %"Vec3" }
%"c" = type { %"lsm", %"Vec3", ptr, float, i8, float, %"lsm", i8, %"Vec3", %"Vec3", %"Vec3", float, float, float, %"Vec3", %"Vec3" }
%"lsm" = type { %"als", %"Vec3", %"Vec3", %"Vec3", %"Vec3" }
%"Vec3" = type { float, float, float }

define arm_aapcs_vfpcc void @foo(%"c"* %this, %"Vec3"* nocapture %adjustment) {
define arm_aapcs_vfpcc void @foo(ptr %this, ptr nocapture %adjustment) {
entry:
switch i32 undef, label %return [
i32 1, label %bb
Expand All @@ -21,10 +21,10 @@ bb: ; preds = %entry
ret void

bb31: ; preds = %entry
%0 = call arm_aapcs_vfpcc %"Vec3" undef(%"lsm"* undef) ; <%"Vec3"> [#uses=1]
%0 = call arm_aapcs_vfpcc %"Vec3" undef(ptr undef) ; <%"Vec3"> [#uses=1]
%mrv_gr69 = extractvalue %"Vec3" %0, 1 ; <float> [#uses=1]
%1 = fsub float %mrv_gr69, undef ; <float> [#uses=1]
store float %1, float* undef, align 4
store float %1, ptr undef, align 4
ret void

bb72: ; preds = %entry
Expand Down
19 changes: 9 additions & 10 deletions llvm/test/CodeGen/ARM/2009-12-02-vtrn-undef.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,28 +6,27 @@ target triple = "armv7-apple-darwin10"
%struct.int16x8_t = type { <8 x i16> }
%struct.int16x8x2_t = type { [2 x %struct.int16x8_t] }

define void @t(%struct.int16x8x2_t* noalias nocapture sret(%struct.int16x8x2_t) %agg.result, <8 x i16> %tmp.0, %struct.int16x8x2_t* nocapture %dst) nounwind {
define void @t(ptr noalias nocapture sret(%struct.int16x8x2_t) %agg.result, <8 x i16> %tmp.0, ptr nocapture %dst) nounwind {
entry:
;CHECK: vtrn.16
%0 = shufflevector <8 x i16> %tmp.0, <8 x i16> undef, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6>
%1 = shufflevector <8 x i16> %tmp.0, <8 x i16> undef, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7>
%agg.result1218.0 = getelementptr %struct.int16x8x2_t, %struct.int16x8x2_t* %agg.result, i32 0, i32 0, i32 0, i32 0 ; <<8 x i16>*>
store <8 x i16> %0, <8 x i16>* %agg.result1218.0, align 16
%agg.result12.1.0 = getelementptr %struct.int16x8x2_t, %struct.int16x8x2_t* %agg.result, i32 0, i32 0, i32 1, i32 0 ; <<8 x i16>*>
store <8 x i16> %1, <8 x i16>* %agg.result12.1.0, align 16
%agg.result1218.0 = getelementptr %struct.int16x8x2_t, ptr %agg.result, i32 0, i32 0, i32 0, i32 0 ; <ptr>
store <8 x i16> %0, ptr %agg.result1218.0, align 16
%agg.result12.1.0 = getelementptr %struct.int16x8x2_t, ptr %agg.result, i32 0, i32 0, i32 1, i32 0 ; <ptr>
store <8 x i16> %1, ptr %agg.result12.1.0, align 16
ret void
}

; Radar 8290937: Ignore undef shuffle indices.
; CHECK: t2
; CHECK: vtrn.16
define void @t2(%struct.int16x8x2_t* nocapture %ptr, <4 x i16> %a.0, <4 x i16> %b.0) nounwind {
define void @t2(ptr nocapture %ptr, <4 x i16> %a.0, <4 x i16> %b.0) nounwind {
entry:
%0 = shufflevector <4 x i16> %a.0, <4 x i16> undef, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 undef, i32 undef, i32 undef, i32 undef>
%1 = shufflevector <4 x i16> %a.0, <4 x i16> undef, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
%ptr26.0 = getelementptr inbounds %struct.int16x8x2_t, %struct.int16x8x2_t* %ptr, i32 0, i32 0, i32 0, i32 0
store <8 x i16> %0, <8 x i16>* %ptr26.0, align 16
%ptr20.1.0 = getelementptr inbounds %struct.int16x8x2_t, %struct.int16x8x2_t* %ptr, i32 0, i32 0, i32 1, i32 0
store <8 x i16> %1, <8 x i16>* %ptr20.1.0, align 16
store <8 x i16> %0, ptr %ptr, align 16
%ptr20.1.0 = getelementptr inbounds %struct.int16x8x2_t, ptr %ptr, i32 0, i32 0, i32 1, i32 0
store <8 x i16> %1, ptr %ptr20.1.0, align 16
ret void
}
56 changes: 26 additions & 30 deletions llvm/test/CodeGen/ARM/2010-03-04-eabi-fp-spill.ll
View file
Original file line number Diff line number Diff line change
@@ -1,22 +1,21 @@
; RUN: llc < %s -mtriple=arm-unknown-linux-gnueabi

define void @"java.lang.String::getChars"([84 x i8]* %method, i32 %base_pc, [788 x i8]* %thread) {
%1 = load i32, i32* undef ; <i32> [#uses=1]
define void @"java.lang.String::getChars"(ptr %method, i32 %base_pc, ptr %thread) {
%1 = load i32, ptr undef ; <i32> [#uses=1]
%2 = sub i32 %1, 48 ; <i32> [#uses=1]
br i1 undef, label %stack_overflow, label %no_overflow

stack_overflow: ; preds = %0
unreachable

no_overflow: ; preds = %0
%frame = inttoptr i32 %2 to [17 x i32]* ; <[17 x i32]*> [#uses=4]
%3 = load i32, i32* undef ; <i32> [#uses=1]
%4 = load i32, i32* null ; <i32> [#uses=1]
%5 = getelementptr inbounds [17 x i32], [17 x i32]* %frame, i32 0, i32 13 ; <i32*> [#uses=1]
%6 = bitcast i32* %5 to [8 x i8]** ; <[8 x i8]**> [#uses=1]
%7 = load [8 x i8]*, [8 x i8]** %6 ; <[8 x i8]*> [#uses=1]
%8 = getelementptr inbounds [17 x i32], [17 x i32]* %frame, i32 0, i32 12 ; <i32*> [#uses=1]
%9 = load i32, i32* %8 ; <i32> [#uses=1]
%frame = inttoptr i32 %2 to ptr ; <ptr> [#uses=4]
%3 = load i32, ptr undef ; <i32> [#uses=1]
%4 = load i32, ptr null ; <i32> [#uses=1]
%5 = getelementptr inbounds [17 x i32], ptr %frame, i32 0, i32 13 ; <ptr> [#uses=1]
%6 = load ptr, ptr %5 ; <ptr> [#uses=1]
%7 = getelementptr inbounds [17 x i32], ptr %frame, i32 0, i32 12 ; <ptr> [#uses=1]
%8 = load i32, ptr %7 ; <i32> [#uses=1]
br i1 undef, label %bci_13, label %bci_4

bci_13: ; preds = %no_overflow
Expand All @@ -26,26 +25,23 @@ bci_30: ; preds = %bci_13
br i1 undef, label %bci_46, label %bci_35

bci_46: ; preds = %bci_30
%10 = sub i32 %4, %3 ; <i32> [#uses=1]
%11 = load [8 x i8]*, [8 x i8]** null ; <[8 x i8]*> [#uses=1]
%callee = bitcast [8 x i8]* %11 to [84 x i8]* ; <[84 x i8]*> [#uses=1]
%12 = bitcast i8* undef to i32* ; <i32*> [#uses=1]
%base_pc7 = load i32, i32* %12 ; <i32> [#uses=2]
%13 = add i32 %base_pc7, 0 ; <i32> [#uses=1]
%14 = inttoptr i32 %13 to void ([84 x i8]*, i32, [788 x i8]*)** ; <void ([84 x i8]*, i32, [788 x i8]*)**> [#uses=1]
%entry_point = load void ([84 x i8]*, i32, [788 x i8]*)*, void ([84 x i8]*, i32, [788 x i8]*)** %14 ; <void ([84 x i8]*, i32, [788 x i8]*)*> [#uses=1]
%15 = getelementptr inbounds [17 x i32], [17 x i32]* %frame, i32 0, i32 1 ; <i32*> [#uses=1]
%16 = ptrtoint i32* %15 to i32 ; <i32> [#uses=1]
%stack_pointer_addr9 = bitcast i8* undef to i32* ; <i32*> [#uses=1]
store i32 %16, i32* %stack_pointer_addr9
%17 = getelementptr inbounds [17 x i32], [17 x i32]* %frame, i32 0, i32 2 ; <i32*> [#uses=1]
store i32 %9, i32* %17
store i32 %10, i32* undef
store [84 x i8]* %method, [84 x i8]** undef
%18 = add i32 %base_pc, 20 ; <i32> [#uses=1]
store i32 %18, i32* undef
store [8 x i8]* %7, [8 x i8]** undef
call void %entry_point([84 x i8]* %callee, i32 %base_pc7, [788 x i8]* %thread)
%9 = sub i32 %4, %3 ; <i32> [#uses=1]
%10 = load ptr, ptr null ; <ptr> [#uses=1]
%base_pc7 = load i32, ptr undef ; <i32> [#uses=2]
%11 = add i32 %base_pc7, 0 ; <i32> [#uses=1]
%12 = inttoptr i32 %11 to ptr ; <ptr> [#uses=1]
%entry_point = load ptr, ptr %12 ; <ptr> [#uses=1]
%13 = getelementptr inbounds [17 x i32], ptr %frame, i32 0, i32 1 ; <ptr> [#uses=1]
%14 = ptrtoint ptr %13 to i32 ; <i32> [#uses=1]
store i32 %14, ptr undef
%15 = getelementptr inbounds [17 x i32], ptr %frame, i32 0, i32 2 ; <ptr> [#uses=1]
store i32 %8, ptr %15
store i32 %9, ptr undef
store ptr %method, ptr undef
%16 = add i32 %base_pc, 20 ; <i32> [#uses=1]
store i32 %16, ptr undef
store ptr %6, ptr undef
call void %entry_point(ptr %10, i32 %base_pc7, ptr %thread)
br i1 undef, label %no_exception, label %exception

exception: ; preds = %bci_46
Expand Down
35 changes: 17 additions & 18 deletions llvm/test/CodeGen/ARM/2010-03-04-stm-undef-addr.ll
View file
Original file line number Diff line number Diff line change
@@ -1,18 +1,18 @@
; RUN: llc -mtriple=arm-eabi %s -o /dev/null

define void @"java.lang.String::getChars"([84 x i8]* %method, i32 %base_pc, [788 x i8]* %thread) {
define void @"java.lang.String::getChars"(ptr %method, i32 %base_pc, ptr %thread) {
%1 = sub i32 undef, 48 ; <i32> [#uses=1]
br i1 undef, label %stack_overflow, label %no_overflow

stack_overflow: ; preds = %0
unreachable

no_overflow: ; preds = %0
%frame = inttoptr i32 %1 to [17 x i32]* ; <[17 x i32]*> [#uses=4]
%2 = load i32, i32* null ; <i32> [#uses=2]
%3 = getelementptr inbounds [17 x i32], [17 x i32]* %frame, i32 0, i32 14 ; <i32*> [#uses=1]
%4 = load i32, i32* %3 ; <i32> [#uses=2]
%5 = load [8 x i8]*, [8 x i8]** undef ; <[8 x i8]*> [#uses=2]
%frame = inttoptr i32 %1 to ptr ; <ptr> [#uses=4]
%2 = load i32, ptr null ; <i32> [#uses=2]
%3 = getelementptr inbounds [17 x i32], ptr %frame, i32 0, i32 14 ; <ptr> [#uses=1]
%4 = load i32, ptr %3 ; <i32> [#uses=2]
%5 = load ptr, ptr undef ; <ptr> [#uses=2]
br i1 undef, label %bci_13, label %bci_4

bci_13: ; preds = %no_overflow
Expand All @@ -23,7 +23,7 @@ bci_30: ; preds = %bci_13
br i1 %6, label %bci_46, label %bci_35

bci_46: ; preds = %bci_30
store [84 x i8]* %method, [84 x i8]** undef
store ptr %method, ptr undef
br i1 false, label %no_exception, label %exception

exception: ; preds = %bci_46
Expand All @@ -33,22 +33,21 @@ no_exception: ; preds = %bci_46
ret void

bci_35: ; preds = %bci_30
%7 = getelementptr inbounds [17 x i32], [17 x i32]* %frame, i32 0, i32 15 ; <i32*> [#uses=1]
store i32 %2, i32* %7
%8 = getelementptr inbounds [17 x i32], [17 x i32]* %frame, i32 0, i32 14 ; <i32*> [#uses=1]
store i32 %4, i32* %8
%9 = getelementptr inbounds [17 x i32], [17 x i32]* %frame, i32 0, i32 13 ; <i32*> [#uses=1]
%10 = bitcast i32* %9 to [8 x i8]** ; <[8 x i8]**> [#uses=1]
store [8 x i8]* %5, [8 x i8]** %10
call void inttoptr (i32 13839116 to void ([788 x i8]*, i32)*)([788 x i8]* %thread, i32 7)
%7 = getelementptr inbounds [17 x i32], ptr %frame, i32 0, i32 15 ; <ptr> [#uses=1]
store i32 %2, ptr %7
%8 = getelementptr inbounds [17 x i32], ptr %frame, i32 0, i32 14 ; <ptr> [#uses=1]
store i32 %4, ptr %8
%9 = getelementptr inbounds [17 x i32], ptr %frame, i32 0, i32 13 ; <ptr> [#uses=1]
store ptr %5, ptr %9
call void inttoptr (i32 13839116 to ptr)(ptr %thread, i32 7)
ret void

bci_21: ; preds = %bci_13
ret void

bci_4: ; preds = %no_overflow
store [8 x i8]* %5, [8 x i8]** undef
store i32 undef, i32* undef
call void inttoptr (i32 13839116 to void ([788 x i8]*, i32)*)([788 x i8]* %thread, i32 7)
store ptr %5, ptr undef
store i32 undef, ptr undef
call void inttoptr (i32 13839116 to ptr)(ptr %thread, i32 7)
ret void
}
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/ARM/2010-04-09-NeonSelect.ll
View file
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o /dev/null
; rdar://7770501 : Don't crash on SELECT and SELECT_CC with NEON vector values.

define void @vDSP_FFT16_copv(float* nocapture %O, float* nocapture %I, i32 %Direction) nounwind {
define void @vDSP_FFT16_copv(ptr nocapture %O, ptr nocapture %I, i32 %Direction) nounwind {
entry:
%.22 = select i1 undef, <4 x float> undef, <4 x float> zeroinitializer ; <<4 x float>> [#uses=1]
%0 = fadd <4 x float> undef, %.22 ; <<4 x float>> [#uses=1]
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/ARM/2010-05-17-FastAllocCrash.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,8 +9,8 @@ target triple = "arm-pc-linux-gnu"

%struct.CHESS_POSITION = type { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32, i32, i8, i8, [64 x i8], i8, i8, i8, i8, i8 }

@search = external global %struct.CHESS_POSITION ; <%struct.CHESS_POSITION*> [#uses=1]
@bishop_mobility_rr45 = external global [64 x [256 x i32]] ; <[64 x [256 x i32]]*> [#uses=1]
@search = external global %struct.CHESS_POSITION ; <ptr> [#uses=1]
@bishop_mobility_rr45 = external global [64 x [256 x i32]] ; <ptr> [#uses=1]

declare fastcc i32 @FirstOne()

Expand Down Expand Up @@ -82,17 +82,17 @@ cond_true1369.preheader: ; preds = %cond_true1254
ret void

bb1567: ; preds = %cond_true1254
%tmp1591 = load i64, i64* getelementptr inbounds (%struct.CHESS_POSITION, %struct.CHESS_POSITION* @search, i32 0, i32 4) ; <i64> [#uses=1]
%tmp1591 = load i64, ptr getelementptr inbounds (%struct.CHESS_POSITION, ptr @search, i32 0, i32 4) ; <i64> [#uses=1]
%tmp1572 = tail call fastcc i32 @FirstOne() ; <i32> [#uses=1]
%tmp1594 = load i32, i32* undef ; <i32> [#uses=1]
%tmp1594 = load i32, ptr undef ; <i32> [#uses=1]
%tmp1594.upgrd.5 = trunc i32 %tmp1594 to i8 ; <i8> [#uses=1]
%shift.upgrd.6 = zext i8 %tmp1594.upgrd.5 to i64 ; <i64> [#uses=1]
%tmp1595 = lshr i64 %tmp1591, %shift.upgrd.6 ; <i64> [#uses=1]
%tmp1595.upgrd.7 = trunc i64 %tmp1595 to i32 ; <i32> [#uses=1]
%tmp1596 = and i32 %tmp1595.upgrd.7, 255 ; <i32> [#uses=1]
%gep.upgrd.8 = zext i32 %tmp1596 to i64 ; <i64> [#uses=1]
%tmp1598 = getelementptr [64 x [256 x i32]], [64 x [256 x i32]]* @bishop_mobility_rr45, i32 0, i32 %tmp1572, i64 %gep.upgrd.8 ; <i32*> [#uses=1]
%tmp1599 = load i32, i32* %tmp1598 ; <i32> [#uses=1]
%tmp1598 = getelementptr [64 x [256 x i32]], ptr @bishop_mobility_rr45, i32 0, i32 %tmp1572, i64 %gep.upgrd.8 ; <ptr> [#uses=1]
%tmp1599 = load i32, ptr %tmp1598 ; <i32> [#uses=1]
%tmp1602 = sub i32 0, %tmp1599 ; <i32> [#uses=1]
br i1 undef, label %cond_next1637, label %cond_true1607

Expand Down
22 changes: 11 additions & 11 deletions llvm/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,23 +8,23 @@ target triple = "armv6-apple-darwin"

%struct.q = type { i32, i32 }

@.str = external constant [1 x i8] ; <[1 x i8]*> [#uses=1]
@.str = external constant [1 x i8] ; <ptr> [#uses=1]

define void @yy(%struct.q* %qq) nounwind {
define void @yy(ptr %qq) nounwind {
entry:
%vla6 = alloca i8, i32 undef, align 1 ; <i8*> [#uses=1]
%vla10 = alloca i8, i32 undef, align 1 ; <i8*> [#uses=1]
%vla14 = alloca i8, i32 undef, align 1 ; <i8*> [#uses=1]
%vla18 = alloca i8, i32 undef, align 1 ; <i8*> [#uses=1]
%tmp21 = load i32, i32* undef ; <i32> [#uses=1]
%vla6 = alloca i8, i32 undef, align 1 ; <ptr> [#uses=1]
%vla10 = alloca i8, i32 undef, align 1 ; <ptr> [#uses=1]
%vla14 = alloca i8, i32 undef, align 1 ; <ptr> [#uses=1]
%vla18 = alloca i8, i32 undef, align 1 ; <ptr> [#uses=1]
%tmp21 = load i32, ptr undef ; <i32> [#uses=1]
%0 = mul i32 1, %tmp21 ; <i32> [#uses=1]
%vla22 = alloca i8, i32 %0, align 1 ; <i8*> [#uses=1]
call void (...) @zz(i8* getelementptr inbounds ([1 x i8], [1 x i8]* @.str, i32 0, i32 0), i32 2, i32 1)
%vla22 = alloca i8, i32 %0, align 1 ; <ptr> [#uses=1]
call void (...) @zz(ptr @.str, i32 2, i32 1)
br i1 undef, label %if.then, label %if.end36

if.then: ; preds = %entry
%call = call i32 (...) @x(%struct.q* undef, i8* undef, i8* %vla6, i8* %vla10, i32 undef) ; <i32> [#uses=0]
%call35 = call i32 (...) @x(%struct.q* undef, i8* %vla14, i8* %vla18, i8* %vla22, i32 undef) ; <i32> [#uses=0]
%call = call i32 (...) @x(ptr undef, ptr undef, ptr %vla6, ptr %vla10, i32 undef) ; <i32> [#uses=0]
%call35 = call i32 (...) @x(ptr undef, ptr %vla14, ptr %vla18, ptr %vla22, i32 undef) ; <i32> [#uses=0]
unreachable

if.end36: ; preds = %entry
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@

%struct.foo = type { i64, i64 }

define zeroext i8 @t(%struct.foo* %this, i1 %tst) noreturn optsize {
define zeroext i8 @t(ptr %this, i1 %tst) noreturn optsize {
entry:
; ARM-LABEL: t:
; ARM-DAG: mov r[[ADDR:[0-9]+]], #8
Expand All @@ -16,12 +16,12 @@ entry:
; THUMB-DAG: movs [[VAL:r[0-9]+]], #0
; THUMB-NOT: str {{[a-z0-9]+}}, [{{[a-z0-9]+}}], {{[a-z0-9]+}}
; THUMB: str [[VAL]], [r[[ADDR]]]
%0 = getelementptr inbounds %struct.foo, %struct.foo* %this, i32 0, i32 1 ; <i64*> [#uses=1]
store i32 0, i32* inttoptr (i32 8 to i32*), align 8
%0 = getelementptr inbounds %struct.foo, ptr %this, i32 0, i32 1 ; <ptr> [#uses=1]
store i32 0, ptr inttoptr (i32 8 to ptr), align 8
br i1 %tst, label %bb.nph96, label %bb3

bb3: ; preds = %entry
%1 = load i64, i64* %0, align 4 ; <i64> [#uses=0]
%1 = load i64, ptr %0, align 4 ; <i64> [#uses=0]
ret i8 42

bb.nph96: ; preds = %entry
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/ARM/2010-05-19-Shuffles.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,9 +13,9 @@ define <8 x i8> @f2(<8 x i8> %x) nounwind {
ret <8 x i8> %y
}

define void @f3(<4 x i64>* %xp) nounwind {
%x = load <4 x i64>, <4 x i64>* %xp
define void @f3(ptr %xp) nounwind {
%x = load <4 x i64>, ptr %xp
%y = shufflevector <4 x i64> %x, <4 x i64> undef, <4 x i32> <i32 0, i32 3, i32 2, i32 1>
store <4 x i64> %y, <4 x i64>* %xp
store <4 x i64> %y, ptr %xp
ret void
}
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