36 changes: 18 additions & 18 deletions llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -108,8 +108,8 @@ define i8 @test_cttz_i8(i8 %a) nounwind {
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: andi a1, a0, 255
; RV32I-NEXT: beqz a1, .LBB3_1
; RV32I-NEXT: # %bb.2: # %cond.false
; RV32I-NEXT: beqz a1, .LBB3_2
; RV32I-NEXT: # %bb.1: # %cond.false
; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: not a0, a0
; RV32I-NEXT: and a0, a0, a1
Expand All @@ -136,7 +136,7 @@ define i8 @test_cttz_i8(i8 %a) nounwind {
; RV32I-NEXT: jalr a2
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: j .LBB3_3
; RV32I-NEXT: .LBB3_1:
; RV32I-NEXT: .LBB3_2:
; RV32I-NEXT: addi a0, zero, 8
; RV32I-NEXT: .LBB3_3: # %cond.end
; RV32I-NEXT: lw s0, 8(sp)
Expand All @@ -157,8 +157,8 @@ define i16 @test_cttz_i16(i16 %a) nounwind {
; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: and a1, a0, a1
; RV32I-NEXT: beqz a1, .LBB4_1
; RV32I-NEXT: # %bb.2: # %cond.false
; RV32I-NEXT: beqz a1, .LBB4_2
; RV32I-NEXT: # %bb.1: # %cond.false
; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: not a0, a0
; RV32I-NEXT: and a0, a0, a1
Expand All @@ -185,7 +185,7 @@ define i16 @test_cttz_i16(i16 %a) nounwind {
; RV32I-NEXT: jalr a2
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: j .LBB4_3
; RV32I-NEXT: .LBB4_1:
; RV32I-NEXT: .LBB4_2:
; RV32I-NEXT: addi a0, zero, 16
; RV32I-NEXT: .LBB4_3: # %cond.end
; RV32I-NEXT: lw s0, 8(sp)
Expand All @@ -203,8 +203,8 @@ define i32 @test_cttz_i32(i32 %a) nounwind {
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: beqz a0, .LBB5_1
; RV32I-NEXT: # %bb.2: # %cond.false
; RV32I-NEXT: beqz a0, .LBB5_2
; RV32I-NEXT: # %bb.1: # %cond.false
; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: not a0, a0
; RV32I-NEXT: and a0, a0, a1
Expand All @@ -231,7 +231,7 @@ define i32 @test_cttz_i32(i32 %a) nounwind {
; RV32I-NEXT: jalr a2
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: j .LBB5_3
; RV32I-NEXT: .LBB5_1:
; RV32I-NEXT: .LBB5_2:
; RV32I-NEXT: addi a0, zero, 32
; RV32I-NEXT: .LBB5_3: # %cond.end
; RV32I-NEXT: lw s0, 8(sp)
Expand All @@ -249,8 +249,8 @@ define i32 @test_ctlz_i32(i32 %a) nounwind {
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: beqz a0, .LBB6_1
; RV32I-NEXT: # %bb.2: # %cond.false
; RV32I-NEXT: beqz a0, .LBB6_2
; RV32I-NEXT: # %bb.1: # %cond.false
; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: srli a1, a0, 2
Expand Down Expand Up @@ -285,7 +285,7 @@ define i32 @test_ctlz_i32(i32 %a) nounwind {
; RV32I-NEXT: jalr a2
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: j .LBB6_3
; RV32I-NEXT: .LBB6_1:
; RV32I-NEXT: .LBB6_2:
; RV32I-NEXT: addi a0, zero, 32
; RV32I-NEXT: .LBB6_3: # %cond.end
; RV32I-NEXT: lw s0, 8(sp)
Expand Down Expand Up @@ -354,12 +354,12 @@ define i64 @test_cttz_i64(i64 %a) nounwind {
; RV32I-NEXT: and a0, a0, s8
; RV32I-NEXT: mv a1, s4
; RV32I-NEXT: jalr s7
; RV32I-NEXT: bnez s3, .LBB7_1
; RV32I-NEXT: # %bb.2:
; RV32I-NEXT: bnez s3, .LBB7_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: addi a0, a0, 32
; RV32I-NEXT: j .LBB7_3
; RV32I-NEXT: .LBB7_1:
; RV32I-NEXT: .LBB7_2:
; RV32I-NEXT: srli a0, s1, 24
; RV32I-NEXT: .LBB7_3:
; RV32I-NEXT: mv a1, zero
Expand Down Expand Up @@ -557,12 +557,12 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
; RV32I-NEXT: and a0, a0, s8
; RV32I-NEXT: mv a1, s4
; RV32I-NEXT: jalr s7
; RV32I-NEXT: bnez s3, .LBB11_1
; RV32I-NEXT: # %bb.2:
; RV32I-NEXT: bnez s3, .LBB11_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: addi a0, a0, 32
; RV32I-NEXT: j .LBB11_3
; RV32I-NEXT: .LBB11_1:
; RV32I-NEXT: .LBB11_2:
; RV32I-NEXT: srli a0, s1, 24
; RV32I-NEXT: .LBB11_3:
; RV32I-NEXT: mv a1, zero
Expand Down
20 changes: 10 additions & 10 deletions llvm/test/CodeGen/RISCV/jumptable.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,30 +13,30 @@ define void @jt(i32 %in, i32* %out) {
; RV32I-NEXT: blt a2, a0, .LBB0_4
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: addi a3, zero, 1
; RV32I-NEXT: beq a0, a3, .LBB0_8
; RV32I-NEXT: beq a0, a3, .LBB0_7
; RV32I-NEXT: # %bb.2: # %entry
; RV32I-NEXT: bne a0, a2, .LBB0_10
; RV32I-NEXT: bne a0, a2, .LBB0_9
; RV32I-NEXT: # %bb.3: # %bb2
; RV32I-NEXT: addi a0, zero, 3
; RV32I-NEXT: sw a0, 0(a1)
; RV32I-NEXT: j .LBB0_10
; RV32I-NEXT: j .LBB0_9
; RV32I-NEXT: .LBB0_4: # %entry
; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: beq a0, a3, .LBB0_9
; RV32I-NEXT: beq a0, a3, .LBB0_8
; RV32I-NEXT: # %bb.5: # %entry
; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: bne a0, a2, .LBB0_10
; RV32I-NEXT: bne a0, a2, .LBB0_9
; RV32I-NEXT: # %bb.6: # %bb4
; RV32I-NEXT: addi a0, zero, 1
; RV32I-NEXT: sw a0, 0(a1)
; RV32I-NEXT: j .LBB0_10
; RV32I-NEXT: .LBB0_8: # %bb1
; RV32I-NEXT: j .LBB0_9
; RV32I-NEXT: .LBB0_7: # %bb1
; RV32I-NEXT: addi a0, zero, 4
; RV32I-NEXT: sw a0, 0(a1)
; RV32I-NEXT: j .LBB0_10
; RV32I-NEXT: .LBB0_9: # %bb3
; RV32I-NEXT: j .LBB0_9
; RV32I-NEXT: .LBB0_8: # %bb3
; RV32I-NEXT: sw a2, 0(a1)
; RV32I-NEXT: .LBB0_10: # %exit
; RV32I-NEXT: .LBB0_9: # %exit
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
Expand Down