4 changes: 2 additions & 2 deletions llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fabs_vec.mir
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# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |

define void @fabs_v4f32(<4 x float>* %a, <4 x float>* %c) { entry: ret void }
define void @fabs_v2f64(<2 x double>* %a, <2 x double>* %c) { entry: ret void }
define void @fabs_v4f32(ptr %a, ptr %c) { entry: ret void }
define void @fabs_v2f64(ptr %a, ptr %c) { entry: ret void }

...
---
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fence.mir
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Expand Up @@ -2,7 +2,7 @@
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |

define void @atomic_load_i32(i32* %ptr) { ret void }
define void @atomic_load_i32(ptr %ptr) { ret void }

...
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16 changes: 8 additions & 8 deletions ...t/CodeGen/Mips/GlobalISel/instruction-select/floating_point_vec_arithmetic_operations.mir
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Expand Up @@ -2,17 +2,17 @@
# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |

define void @fadd_v4f32(<4 x float>* %a, <4 x float>* %b, <4 x float>* %c) { entry: ret void }
define void @fadd_v2f64(<2 x double>* %a, <2 x double>* %b, <2 x double>* %c) { entry: ret void }
define void @fadd_v4f32(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @fadd_v2f64(ptr %a, ptr %b, ptr %c) { entry: ret void }

define void @fsub_v4f32(<4 x float>* %a, <4 x float>* %b, <4 x float>* %c) { entry: ret void }
define void @fsub_v2f64(<2 x double>* %a, <2 x double>* %b, <2 x double>* %c) { entry: ret void }
define void @fsub_v4f32(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @fsub_v2f64(ptr %a, ptr %b, ptr %c) { entry: ret void }

define void @fmul_v4f32(<4 x float>* %a, <4 x float>* %b, <4 x float>* %c) { entry: ret void }
define void @fmul_v2f64(<2 x double>* %a, <2 x double>* %b, <2 x double>* %c) { entry: ret void }
define void @fmul_v4f32(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @fmul_v2f64(ptr %a, ptr %b, ptr %c) { entry: ret void }

define void @fdiv_v4f32(<4 x float>* %a, <4 x float>* %b, <4 x float>* %c) { entry: ret void }
define void @fdiv_v2f64(<2 x double>* %a, <2 x double>* %b, <2 x double>* %c) { entry: ret void }
define void @fdiv_v4f32(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @fdiv_v2f64(ptr %a, ptr %b, ptr %c) { entry: ret void }

...
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fsqrt_vec.mir
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Expand Up @@ -2,8 +2,8 @@
# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |

define void @sqrt_v4f32(<4 x float>* %a, <4 x float>* %c) { entry: ret void }
define void @sqrt_v2f64(<2 x double>* %a, <2 x double>* %c) { entry: ret void }
define void @sqrt_v4f32(ptr %a, ptr %c) { entry: ret void }
define void @sqrt_v2f64(ptr %a, ptr %c) { entry: ret void }

...
---
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Mips/GlobalISel/instruction-select/gloal_address.mir
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Expand Up @@ -5,7 +5,7 @@
@.str = private unnamed_addr constant [11 x i8] c"hello %d \0A\00"

define void @main() {entry: ret void}
declare i32 @printf(i8*, ...)
declare i32 @printf(ptr, ...)

...
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6 changes: 3 additions & 3 deletions llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load.mir
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Expand Up @@ -3,9 +3,9 @@
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32FP64
--- |

define void @load_i32(i32* %ptr) {entry: ret void}
define void @load_float(float* %ptr) {entry: ret void}
define void @load_double(double* %ptr) {entry: ret void}
define void @load_i32(ptr %ptr) {entry: ret void}
define void @load_float(ptr %ptr) {entry: ret void}
define void @load_double(ptr %ptr) {entry: ret void}

...
---
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6 changes: 3 additions & 3 deletions llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_4_unaligned.mir
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Expand Up @@ -8,19 +8,19 @@

define float @load_float_align1() {
entry:
%0 = load float, float* @float_align1, align 1
%0 = load float, ptr @float_align1, align 1
ret float %0
}

define float @load_float_align4() {
entry:
%0 = load float, float* @float_align4, align 4
%0 = load float, ptr @float_align4, align 4
ret float %0
}

define i32 @load_i32_align8() {
entry:
%0 = load i32, i32* @i32_align8, align 8
%0 = load i32, ptr @i32_align8, align 8
ret i32 %0
}

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6 changes: 3 additions & 3 deletions llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_4_unaligned_r6.mir
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Expand Up @@ -8,19 +8,19 @@

define float @load_float_align1() {
entry:
%0 = load float, float* @float_align1, align 1
%0 = load float, ptr @float_align1, align 1
ret float %0
}

define float @load_float_align8() {
entry:
%0 = load float, float* @float_align8, align 8
%0 = load float, ptr @float_align8, align 8
ret float %0
}

define i32 @load_i32_align2() {
entry:
%0 = load i32, i32* @i32_align2, align 2
%0 = load i32, ptr @i32_align2, align 2
ret i32 %0
}

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12 changes: 6 additions & 6 deletions llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_store_vec.mir
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Expand Up @@ -2,12 +2,12 @@
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=msa,+fp64 -mattr=nan2008 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |

define void @load_store_v16i8(<16 x i8>* %a, <16 x i8>* %b) { entry: ret void }
define void @load_store_v8i16(<8 x i16>* %a, <8 x i16>* %b) { entry: ret void }
define void @load_store_v4i32(<4 x i32>* %a, <4 x i32>* %b) { entry: ret void }
define void @load_store_v2i64(<2 x i64>* %a, <2 x i64>* %b) { entry: ret void }
define void @load_store_v4f32(<4 x float>* %a, <4 x float>* %b) { entry: ret void }
define void @load_store_v2f64(<2 x double>* %a, <2 x double>* %b) { entry: ret void }
define void @load_store_v16i8(ptr %a, ptr %b) { entry: ret void }
define void @load_store_v8i16(ptr %a, ptr %b) { entry: ret void }
define void @load_store_v4i32(ptr %a, ptr %b) { entry: ret void }
define void @load_store_v2i64(ptr %a, ptr %b) { entry: ret void }
define void @load_store_v4f32(ptr %a, ptr %b) { entry: ret void }
define void @load_store_v2f64(ptr %a, ptr %b) { entry: ret void }

...
---
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir
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Expand Up @@ -3,7 +3,7 @@
--- |

define void @mul_i32(i32 %x, i32 %y) {entry: ret void}
define void @umul_with_overflow(i32 %lhs, i32 %rhs, i32* %pmul, i1* %pcarry_flag) { ret void }
define void @umul_with_overflow(i32 %lhs, i32 %rhs, ptr %pmul, ptr %pcarry_flag) { ret void }

...
---
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8 changes: 4 additions & 4 deletions llvm/test/CodeGen/Mips/GlobalISel/instruction-select/mul_vec.mir
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Expand Up @@ -2,10 +2,10 @@
# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |

define void @mul_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
define void @mul_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
define void @mul_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
define void @mul_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
define void @mul_v16i8(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @mul_v8i16(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @mul_v4i32(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @mul_v2i64(ptr %a, ptr %b, ptr %c) { entry: ret void }

...
---
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6 changes: 3 additions & 3 deletions llvm/test/CodeGen/Mips/GlobalISel/instruction-select/pointers.mir
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Expand Up @@ -2,9 +2,9 @@
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |

define void @ptr_arg_in_regs(i32* %p) {entry: ret void}
define void @ptr_arg_on_stack(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i32* %p) {entry: ret void}
define void @ret_ptr(i8* %p) {entry: ret void}
define void @ptr_arg_in_regs(ptr %p) {entry: ret void}
define void @ptr_arg_on_stack(i32 %x1, i32 %x2, i32 %x3, i32 %x4, ptr %p) {entry: ret void}
define void @ret_ptr(ptr %p) {entry: ret void}

...
---
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38 changes: 19 additions & 19 deletions llvm/test/CodeGen/Mips/GlobalISel/instruction-select/rem_and_div_vec.mir
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Expand Up @@ -2,25 +2,25 @@
# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |

define void @sdiv_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
define void @sdiv_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
define void @sdiv_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
define void @sdiv_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }

define void @srem_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
define void @srem_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
define void @srem_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
define void @srem_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }

define void @udiv_v16u8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
define void @udiv_v8u16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
define void @udiv_v4u32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
define void @udiv_v2u64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }

define void @urem_v16u8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
define void @urem_v8u16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
define void @urem_v4u32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
define void @urem_v2u64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
define void @sdiv_v16i8(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @sdiv_v8i16(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @sdiv_v4i32(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @sdiv_v2i64(ptr %a, ptr %b, ptr %c) { entry: ret void }

define void @srem_v16i8(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @srem_v8i16(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @srem_v4i32(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @srem_v2i64(ptr %a, ptr %b, ptr %c) { entry: ret void }

define void @udiv_v16u8(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @udiv_v8u16(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @udiv_v4u32(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @udiv_v2u64(ptr %a, ptr %b, ptr %c) { entry: ret void }

define void @urem_v16u8(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @urem_v8u16(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @urem_v4u32(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @urem_v2u64(ptr %a, ptr %b, ptr %c) { entry: ret void }

...
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6 changes: 3 additions & 3 deletions llvm/test/CodeGen/Mips/GlobalISel/instruction-select/store.mir
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Expand Up @@ -3,9 +3,9 @@
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32FP64
--- |

define void @store_i32(i32* %ptr) { entry: ret void }
define void @store_float(float* %ptr) { entry: ret void }
define void @store_double(double* %ptr) { entry: ret void }
define void @store_i32(ptr %ptr) { entry: ret void }
define void @store_float(ptr %ptr) { entry: ret void }
define void @store_double(ptr %ptr) { entry: ret void }

...
---
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6 changes: 3 additions & 3 deletions llvm/test/CodeGen/Mips/GlobalISel/instruction-select/store_4_unaligned.mir
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Expand Up @@ -8,19 +8,19 @@

define void @store_float_align1(float %a) {
entry:
store float %a, float* @float_align1, align 1
store float %a, ptr @float_align1, align 1
ret void
}

define void @store_float_align4(float %a) {
entry:
store float %a, float* @float_align4, align 4
store float %a, ptr @float_align4, align 4
ret void
}

define void @store_i32_align8(i32 signext %a) {
entry:
store i32 %a, i32* @i32_align8, align 8
store i32 %a, ptr @i32_align8, align 8
ret void
}

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6 changes: 3 additions & 3 deletions llvm/test/CodeGen/Mips/GlobalISel/instruction-select/store_4_unaligned_r6.mir
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Expand Up @@ -8,19 +8,19 @@

define void @store_float_align1(float %a) #0 {
entry:
store float %a, float* @float_align1, align 1
store float %a, ptr @float_align1, align 1
ret void
}

define void @store_float_align8(float %a) #0 {
entry:
store float %a, float* @float_align8, align 8
store float %a, ptr @float_align8, align 8
ret void
}

define void @store_i32_align2(i32 signext %a) #0 {
entry:
store i32 %a, i32* @i32_align2, align 2
store i32 %a, ptr @i32_align2, align 2
ret void
}

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8 changes: 4 additions & 4 deletions llvm/test/CodeGen/Mips/GlobalISel/instruction-select/sub_vec.mir
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Expand Up @@ -2,10 +2,10 @@
# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |

define void @sub_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
define void @sub_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
define void @sub_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
define void @sub_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
define void @sub_v16i8(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @sub_v8i16(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @sub_v4i32(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @sub_v2i64(ptr %a, ptr %b, ptr %c) { entry: ret void }

...
---
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6 changes: 3 additions & 3 deletions llvm/test/CodeGen/Mips/GlobalISel/instruction-select/truncStore_and_aExtLoad.mir
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Expand Up @@ -2,9 +2,9 @@
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |

define void @load_store_i8(i8* %px, i8* %py) {entry: ret void}
define void @load_store_i16(i16* %px, i16* %py) {entry: ret void}
define void @load_store_i32(i32* %px, i32* %py) {entry: ret void}
define void @load_store_i8(ptr %px, ptr %py) {entry: ret void}
define void @load_store_i16(ptr %px, ptr %py) {entry: ret void}
define void @load_store_i32(ptr %px, ptr %py) {entry: ret void}

...
---
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8 changes: 4 additions & 4 deletions llvm/test/CodeGen/Mips/GlobalISel/instruction-select/zextLoad_and_sextLoad.mir
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Expand Up @@ -2,10 +2,10 @@
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |

define void @load1_s8_to_zextLoad1_s32(i8* %px) {entry: ret void}
define void @load2_s16_to_zextLoad2_s32(i16* %px) {entry: ret void}
define void @load1_s8_to_sextLoad1_s32(i8* %px) {entry: ret void}
define void @load2_s16_to_sextLoad2_s32(i16* %px) {entry: ret void}
define void @load1_s8_to_zextLoad1_s32(ptr %px) {entry: ret void}
define void @load2_s16_to_zextLoad2_s32(ptr %px) {entry: ret void}
define void @load1_s8_to_sextLoad1_s32(ptr %px) {entry: ret void}
define void @load2_s16_to_sextLoad2_s32(ptr %px) {entry: ret void}

...
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir
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Expand Up @@ -11,7 +11,7 @@
define void @add_i16_aext() {entry: ret void}
define void @add_i64() {entry: ret void}
define void @add_i128() {entry: ret void}
define void @uadd_with_overflow(i32 %lhs, i32 %rhs, i32* %padd, i1* %pcarry_flag) { ret void }
define void @uadd_with_overflow(i32 %lhs, i32 %rhs, ptr %padd, ptr %pcarry_flag) { ret void }

...
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8 changes: 4 additions & 4 deletions llvm/test/CodeGen/Mips/GlobalISel/legalizer/add_vec.mir
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Expand Up @@ -2,10 +2,10 @@
# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |

define void @add_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
define void @add_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
define void @add_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
define void @add_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
define void @add_v16i8(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @add_v8i16(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @add_v4i32(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @add_v2i64(ptr %a, ptr %b, ptr %c) { entry: ret void }

...
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16 changes: 8 additions & 8 deletions llvm/test/CodeGen/Mips/GlobalISel/legalizer/add_vec_builtin.mir
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Expand Up @@ -3,28 +3,28 @@
--- |

declare <16 x i8> @llvm.mips.addv.b(<16 x i8>, <16 x i8>)
define void @add_v16i8_builtin(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
define void @add_v16i8_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }

declare <8 x i16> @llvm.mips.addv.h(<8 x i16>, <8 x i16>)
define void @add_v8i16_builtin(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
define void @add_v8i16_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }

declare <4 x i32> @llvm.mips.addv.w(<4 x i32>, <4 x i32>)
define void @add_v4i32_builtin(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
define void @add_v4i32_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }

declare <2 x i64> @llvm.mips.addv.d(<2 x i64>, <2 x i64>)
define void @add_v2i64_builtin(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
define void @add_v2i64_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }

declare <16 x i8> @llvm.mips.addvi.b(<16 x i8>, i32 immarg)
define void @add_v16i8_builtin_imm(<16 x i8>* %a, <16 x i8>* %c) { entry: ret void }
define void @add_v16i8_builtin_imm(ptr %a, ptr %c) { entry: ret void }

declare <8 x i16> @llvm.mips.addvi.h(<8 x i16>, i32 immarg)
define void @add_v8i16_builtin_imm(<8 x i16>* %a, <8 x i16>* %c) { entry: ret void }
define void @add_v8i16_builtin_imm(ptr %a, ptr %c) { entry: ret void }

declare <4 x i32> @llvm.mips.addvi.w(<4 x i32>, i32 immarg)
define void @add_v4i32_builtin_imm(<4 x i32>* %a, <4 x i32>* %c) { entry: ret void }
define void @add_v4i32_builtin_imm(ptr %a, ptr %c) { entry: ret void }

declare <2 x i64> @llvm.mips.addvi.d(<2 x i64>, i32 immarg)
define void @add_v2i64_builtin_imm(<2 x i64>* %a, <2 x i64>* %c) { entry: ret void }
define void @add_v2i64_builtin_imm(ptr %a, ptr %c) { entry: ret void }

...
---
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/Mips/GlobalISel/legalizer/brindirect.mir
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Expand Up @@ -2,9 +2,9 @@
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |

define i32 @indirectbr(i8* %addr) {
define i32 @indirectbr(ptr %addr) {
entry:
indirectbr i8* %addr, [label %L1, label %L2]
indirectbr ptr %addr, [label %L1, label %L2]

L1:
ret i32 0
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12 changes: 6 additions & 6 deletions llvm/test/CodeGen/Mips/GlobalISel/legalizer/dyn_stackalloc.mir
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Expand Up @@ -2,17 +2,17 @@
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |

declare i32 @puts(i8*)
declare void @llvm.memset.p0i8.i32(i8*, i8, i32, i1)
declare i32 @puts(ptr)
declare void @llvm.memset.p0.i32(ptr, i8, i32, i1)

define void @Print_c_N_times(i8 %c, i32 %N) {
entry:
%add = add i32 %N, 1
%vla = alloca i8, i32 %add, align 1
call void @llvm.memset.p0i8.i32(i8* align 1 %vla, i8 %c, i32 %N, i1 false)
%arrayidx = getelementptr inbounds i8, i8* %vla, i32 %N
store i8 0, i8* %arrayidx, align 1
%call = call i32 @puts(i8* %vla)
call void @llvm.memset.p0.i32(ptr align 1 %vla, i8 %c, i32 %N, i1 false)
%arrayidx = getelementptr inbounds i8, ptr %vla, i32 %N
store i8 0, ptr %arrayidx, align 1
%call = call i32 @puts(ptr %vla)
ret void
}

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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/Mips/GlobalISel/legalizer/fabs_vec.mir
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Expand Up @@ -2,8 +2,8 @@
# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |

define void @fabs_v4f32(<4 x float>* %a, <4 x float>* %c) { entry: ret void }
define void @fabs_v2f64(<2 x double>* %a, <2 x double>* %c) { entry: ret void }
define void @fabs_v4f32(ptr %a, ptr %c) { entry: ret void }
define void @fabs_v2f64(ptr %a, ptr %c) { entry: ret void }

...
---
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/Mips/GlobalISel/legalizer/fabs_vec_builtin.mir
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Expand Up @@ -3,10 +3,10 @@
--- |

declare <4 x float> @llvm.mips.fmax.a.w(<4 x float>, <4 x float>)
define void @fabs_v4f32_builtin(<4 x float>* %a, <4 x float>* %c) { entry: ret void }
define void @fabs_v4f32_builtin(ptr %a, ptr %c) { entry: ret void }

declare <2 x double> @llvm.mips.fmax.a.d(<2 x double>, <2 x double>)
define void @fabs_v2f64_builtin(<2 x double>* %a, <2 x double>* %c) { entry: ret void }
define void @fabs_v2f64_builtin(ptr %a, ptr %c) { entry: ret void }

...
---
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Mips/GlobalISel/legalizer/fence.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |

define void @atomic_load_i32(i32* %ptr) { ret void }
define void @atomic_load_i32(ptr %ptr) { ret void }

...
---
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16 changes: 8 additions & 8 deletions llvm/test/CodeGen/Mips/GlobalISel/legalizer/floating_point_vec_arithmetic_operations.mir
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Expand Up @@ -2,17 +2,17 @@
# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |

define void @fadd_v4f32(<4 x float>* %a, <4 x float>* %b, <4 x float>* %c) { entry: ret void }
define void @fadd_v2f64(<2 x double>* %a, <2 x double>* %b, <2 x double>* %c) { entry: ret void }
define void @fadd_v4f32(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @fadd_v2f64(ptr %a, ptr %b, ptr %c) { entry: ret void }

define void @fsub_v4f32(<4 x float>* %a, <4 x float>* %b, <4 x float>* %c) { entry: ret void }
define void @fsub_v2f64(<2 x double>* %a, <2 x double>* %b, <2 x double>* %c) { entry: ret void }
define void @fsub_v4f32(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @fsub_v2f64(ptr %a, ptr %b, ptr %c) { entry: ret void }

define void @fmul_v4f32(<4 x float>* %a, <4 x float>* %b, <4 x float>* %c) { entry: ret void }
define void @fmul_v2f64(<2 x double>* %a, <2 x double>* %b, <2 x double>* %c) { entry: ret void }
define void @fmul_v4f32(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @fmul_v2f64(ptr %a, ptr %b, ptr %c) { entry: ret void }

define void @fdiv_v4f32(<4 x float>* %a, <4 x float>* %b, <4 x float>* %c) { entry: ret void }
define void @fdiv_v2f64(<2 x double>* %a, <2 x double>* %b, <2 x double>* %c) { entry: ret void }
define void @fdiv_v4f32(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @fdiv_v2f64(ptr %a, ptr %b, ptr %c) { entry: ret void }

...
---
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16 changes: 8 additions & 8 deletions ...st/CodeGen/Mips/GlobalISel/legalizer/floating_point_vec_arithmetic_operations_builtin.mir
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Expand Up @@ -3,28 +3,28 @@
--- |

declare <4 x float> @llvm.mips.fadd.w(<4 x float>, <4 x float>)
define void @fadd_v4f32_builtin(<4 x float>* %a, <4 x float>* %b, <4 x float>* %c) { entry: ret void }
define void @fadd_v4f32_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }

declare <2 x double> @llvm.mips.fadd.d(<2 x double>, <2 x double>)
define void @fadd_v2f64_builtin(<2 x double>* %a, <2 x double>* %b, <2 x double>* %c) { entry: ret void }
define void @fadd_v2f64_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }

declare <4 x float> @llvm.mips.fsub.w(<4 x float>, <4 x float>)
define void @fsub_v4f32_builtin(<4 x float>* %a, <4 x float>* %b, <4 x float>* %c) { entry: ret void }
define void @fsub_v4f32_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }

declare <2 x double> @llvm.mips.fsub.d(<2 x double>, <2 x double>)
define void @fsub_v2f64_builtin(<2 x double>* %a, <2 x double>* %b, <2 x double>* %c) { entry: ret void }
define void @fsub_v2f64_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }

declare <4 x float> @llvm.mips.fmul.w(<4 x float>, <4 x float>)
define void @fmul_v4f32_builtin(<4 x float>* %a, <4 x float>* %b, <4 x float>* %c) { entry: ret void }
define void @fmul_v4f32_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }

declare <2 x double> @llvm.mips.fmul.d(<2 x double>, <2 x double>)
define void @fmul_v2f64_builtin(<2 x double>* %a, <2 x double>* %b, <2 x double>* %c) { entry: ret void }
define void @fmul_v2f64_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }

declare <4 x float> @llvm.mips.fdiv.w(<4 x float>, <4 x float>)
define void @fdiv_v4f32_builtin(<4 x float>* %a, <4 x float>* %b, <4 x float>* %c) { entry: ret void }
define void @fdiv_v4f32_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }

declare <2 x double> @llvm.mips.fdiv.d(<2 x double>, <2 x double>)
define void @fdiv_v2f64_builtin(<2 x double>* %a, <2 x double>* %b, <2 x double>* %c) { entry: ret void }
define void @fdiv_v2f64_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }

...
---
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/Mips/GlobalISel/legalizer/fsqrt_vec.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -2,8 +2,8 @@
# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |

define void @sqrt_v4f32(<4 x float>* %a, <4 x float>* %c) { entry: ret void }
define void @sqrt_v2f64(<2 x double>* %a, <2 x double>* %c) { entry: ret void }
define void @sqrt_v4f32(ptr %a, ptr %c) { entry: ret void }
define void @sqrt_v2f64(ptr %a, ptr %c) { entry: ret void }

...
---
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/Mips/GlobalISel/legalizer/fsqrt_vec_builtin.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -3,10 +3,10 @@
--- |

declare <4 x float> @llvm.mips.fsqrt.w(<4 x float>)
define void @fsqrt_v4f32_builtin(<4 x float>* %a, <4 x float>* %c) { entry: ret void }
define void @fsqrt_v4f32_builtin(ptr %a, ptr %c) { entry: ret void }

declare <2 x double> @llvm.mips.fsqrt.d(<2 x double>)
define void @fsqrt_v2f64_builtin(<2 x double>* %a, <2 x double>* %c) { entry: ret void }
define void @fsqrt_v2f64_builtin(ptr %a, ptr %c) { entry: ret void }

...
---
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Mips/GlobalISel/legalizer/global_address.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
@.str = private unnamed_addr constant [11 x i8] c"hello %d \0A\00"

define void @main() {entry: ret void}
declare i32 @printf(i8*, ...)
declare i32 @printf(ptr, ...)

...
---
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16 changes: 8 additions & 8 deletions llvm/test/CodeGen/Mips/GlobalISel/legalizer/load_4_unaligned.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -14,49 +14,49 @@

define float @load_float_align1() {
entry:
%0 = load float, float* @float_align1, align 1
%0 = load float, ptr @float_align1, align 1
ret float %0
}

define float @load_float_align2() {
entry:
%0 = load float, float* @float_align2, align 2
%0 = load float, ptr @float_align2, align 2
ret float %0
}

define float @load_float_align4() {
entry:
%0 = load float, float* @float_align4, align 4
%0 = load float, ptr @float_align4, align 4
ret float %0
}

define float @load_float_align8() {
entry:
%0 = load float, float* @float_align8, align 8
%0 = load float, ptr @float_align8, align 8
ret float %0
}

define i32 @load_i32_align1() {
entry:
%0 = load i32, i32* @i32_align1, align 1
%0 = load i32, ptr @i32_align1, align 1
ret i32 %0
}

define i32 @load_i32_align2() {
entry:
%0 = load i32, i32* @i32_align2, align 2
%0 = load i32, ptr @i32_align2, align 2
ret i32 %0
}

define i32 @load_i32_align4() {
entry:
%0 = load i32, i32* @i32_align4, align 4
%0 = load i32, ptr @i32_align4, align 4
ret i32 %0
}

define i32 @load_i32_align8() {
entry:
%0 = load i32, i32* @i32_align8, align 8
%0 = load i32, ptr @i32_align8, align 8
ret i32 %0
}

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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@
define void @mul_i64() {entry: ret void}
define void @mul_i128() {entry: ret void}
define void @umulh_i64() {entry: ret void}
define void @umul_with_overflow(i32 %lhs, i32 %rhs, i32* %pmul, i1* %pcarry_flag) { ret void }
define void @umul_with_overflow(i32 %lhs, i32 %rhs, ptr %pmul, ptr %pcarry_flag) { ret void }

...
---
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8 changes: 4 additions & 4 deletions llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul_vec.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -2,10 +2,10 @@
# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |

define void @mul_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
define void @mul_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
define void @mul_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
define void @mul_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
define void @mul_v16i8(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @mul_v8i16(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @mul_v4i32(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @mul_v2i64(ptr %a, ptr %b, ptr %c) { entry: ret void }

...
---
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8 changes: 4 additions & 4 deletions llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul_vec_builtin.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -3,16 +3,16 @@
--- |

declare <16 x i8> @llvm.mips.mulv.b(<16 x i8>, <16 x i8>)
define void @mul_v16i8_builtin(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
define void @mul_v16i8_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }

declare <8 x i16> @llvm.mips.mulv.h(<8 x i16>, <8 x i16>)
define void @mul_v8i16_builtin(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
define void @mul_v8i16_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }

declare <4 x i32> @llvm.mips.mulv.w(<4 x i32>, <4 x i32>)
define void @mul_v4i32_builtin(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
define void @mul_v4i32_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }

declare <2 x i64> @llvm.mips.mulv.d(<2 x i64>, <2 x i64>)
define void @mul_v2i64_builtin(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
define void @mul_v2i64_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }

...
---
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16 changes: 8 additions & 8 deletions llvm/test/CodeGen/Mips/GlobalISel/legalizer/phi.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -77,10 +77,10 @@
ret i64 %cond
}

define void @phi_ambiguous_i64_in_fpr(i1 %cnd, i64* %i64_ptr_a, i64* %i64_ptr_b, i64* %i64_ptr_c) {
define void @phi_ambiguous_i64_in_fpr(i1 %cnd, ptr %i64_ptr_a, ptr %i64_ptr_b, ptr %i64_ptr_c) {
entry:
%0 = load i64, i64* %i64_ptr_a, align 8
%1 = load i64, i64* %i64_ptr_b, align 8
%0 = load i64, ptr %i64_ptr_a, align 8
%1 = load i64, ptr %i64_ptr_b, align 8
br i1 %cnd, label %cond.true, label %cond.false

cond.true: ; preds = %entry
Expand All @@ -91,7 +91,7 @@

cond.end: ; preds = %cond.false, %cond.true
%cond = phi i64 [ %0, %cond.true ], [ %1, %cond.false ]
store i64 %cond, i64* %i64_ptr_c, align 8
store i64 %cond, ptr %i64_ptr_c, align 8
ret void
}

Expand All @@ -110,10 +110,10 @@
ret float %cond
}

define void @phi_ambiguous_float_in_gpr(i1 %cnd, float* %f32_ptr_a, float* %f32_ptr_b, float* %f32_ptr_c) {
define void @phi_ambiguous_float_in_gpr(i1 %cnd, ptr %f32_ptr_a, ptr %f32_ptr_b, ptr %f32_ptr_c) {
entry:
%0 = load float, float* %f32_ptr_a, align 4
%1 = load float, float* %f32_ptr_b, align 4
%0 = load float, ptr %f32_ptr_a, align 4
%1 = load float, ptr %f32_ptr_b, align 4
br i1 %cnd, label %cond.true, label %cond.false

cond.true: ; preds = %entry
Expand All @@ -124,7 +124,7 @@

cond.end: ; preds = %cond.false, %cond.true
%cond = phi float [ %0, %cond.true ], [ %1, %cond.false ]
store float %cond, float* %f32_ptr_c, align 4
store float %cond, ptr %f32_ptr_c, align 4
ret void
}

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6 changes: 3 additions & 3 deletions llvm/test/CodeGen/Mips/GlobalISel/legalizer/pointers.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -2,9 +2,9 @@
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |

define void @ptr_arg_in_regs(i32* %p) {entry: ret void}
define void @ptr_arg_on_stack(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i32* %p) {entry: ret void}
define void @ret_ptr(i8* %p) {entry: ret void}
define void @ptr_arg_in_regs(ptr %p) {entry: ret void}
define void @ptr_arg_on_stack(i32 %x1, i32 %x2, i32 %x3, i32 %x4, ptr %p) {entry: ret void}
define void @ret_ptr(ptr %p) {entry: ret void}

...
---
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38 changes: 19 additions & 19 deletions llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div_vec.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -2,25 +2,25 @@
# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |

define void @sdiv_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
define void @sdiv_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
define void @sdiv_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
define void @sdiv_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }

define void @srem_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
define void @srem_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
define void @srem_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
define void @srem_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }

define void @udiv_v16u8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
define void @udiv_v8u16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
define void @udiv_v4u32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
define void @udiv_v2u64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }

define void @urem_v16u8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
define void @urem_v8u16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
define void @urem_v4u32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
define void @urem_v2u64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
define void @sdiv_v16i8(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @sdiv_v8i16(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @sdiv_v4i32(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @sdiv_v2i64(ptr %a, ptr %b, ptr %c) { entry: ret void }

define void @srem_v16i8(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @srem_v8i16(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @srem_v4i32(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @srem_v2i64(ptr %a, ptr %b, ptr %c) { entry: ret void }

define void @udiv_v16u8(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @udiv_v8u16(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @udiv_v4u32(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @udiv_v2u64(ptr %a, ptr %b, ptr %c) { entry: ret void }

define void @urem_v16u8(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @urem_v8u16(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @urem_v4u32(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @urem_v2u64(ptr %a, ptr %b, ptr %c) { entry: ret void }

...
---
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32 changes: 16 additions & 16 deletions llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div_vec_builtin.mir
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Expand Up @@ -3,52 +3,52 @@
--- |

declare <16 x i8> @llvm.mips.div.s.b(<16 x i8>, <16 x i8>)
define void @sdiv_v16i8_builtin(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
define void @sdiv_v16i8_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }

declare <8 x i16> @llvm.mips.div.s.h(<8 x i16>, <8 x i16>)
define void @sdiv_v8i16_builtin(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
define void @sdiv_v8i16_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }

declare <4 x i32> @llvm.mips.div.s.w(<4 x i32>, <4 x i32>)
define void @sdiv_v4i32_builtin(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
define void @sdiv_v4i32_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }

declare <2 x i64> @llvm.mips.div.s.d(<2 x i64>, <2 x i64>)
define void @sdiv_v2i64_builtin(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
define void @sdiv_v2i64_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }

declare <16 x i8> @llvm.mips.mod.s.b(<16 x i8>, <16 x i8>)
define void @smod_v16i8_builtin(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
define void @smod_v16i8_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }

declare <8 x i16> @llvm.mips.mod.s.h(<8 x i16>, <8 x i16>)
define void @smod_v8i16_builtin(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
define void @smod_v8i16_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }

declare <4 x i32> @llvm.mips.mod.s.w(<4 x i32>, <4 x i32>)
define void @smod_v4i32_builtin(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
define void @smod_v4i32_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }

declare <2 x i64> @llvm.mips.mod.s.d(<2 x i64>, <2 x i64>)
define void @smod_v2i64_builtin(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
define void @smod_v2i64_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }

declare <16 x i8> @llvm.mips.div.u.b(<16 x i8>, <16 x i8>)
define void @udiv_v16i8_builtin(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
define void @udiv_v16i8_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }

declare <8 x i16> @llvm.mips.div.u.h(<8 x i16>, <8 x i16>)
define void @udiv_v8i16_builtin(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
define void @udiv_v8i16_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }

declare <4 x i32> @llvm.mips.div.u.w(<4 x i32>, <4 x i32>)
define void @udiv_v4i32_builtin(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
define void @udiv_v4i32_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }

declare <2 x i64> @llvm.mips.div.u.d(<2 x i64>, <2 x i64>)
define void @udiv_v2i64_builtin(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
define void @udiv_v2i64_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }

declare <16 x i8> @llvm.mips.mod.u.b(<16 x i8>, <16 x i8>)
define void @umod_v16i8_builtin(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
define void @umod_v16i8_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }

declare <8 x i16> @llvm.mips.mod.u.h(<8 x i16>, <8 x i16>)
define void @umod_v8i16_builtin(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
define void @umod_v8i16_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }

declare <4 x i32> @llvm.mips.mod.u.w(<4 x i32>, <4 x i32>)
define void @umod_v4i32_builtin(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
define void @umod_v4i32_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }

declare <2 x i64> @llvm.mips.mod.u.d(<2 x i64>, <2 x i64>)
define void @umod_v2i64_builtin(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
define void @umod_v2i64_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }

...
---
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16 changes: 8 additions & 8 deletions llvm/test/CodeGen/Mips/GlobalISel/legalizer/store_4_unaligned.mir
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Expand Up @@ -14,49 +14,49 @@

define void @store_float_align1(float %a) {
entry:
store float %a, float* @float_align1, align 1
store float %a, ptr @float_align1, align 1
ret void
}

define void @store_float_align2(float %a) {
entry:
store float %a, float* @float_align2, align 2
store float %a, ptr @float_align2, align 2
ret void
}

define void @store_float_align4(float %a) {
entry:
store float %a, float* @float_align4, align 4
store float %a, ptr @float_align4, align 4
ret void
}

define void @store_float_align8(float %a) {
entry:
store float %a, float* @float_align8, align 8
store float %a, ptr @float_align8, align 8
ret void
}

define void @store_i32_align1(i32 signext %a) {
entry:
store i32 %a, i32* @i32_align1, align 1
store i32 %a, ptr @i32_align1, align 1
ret void
}

define void @store_i32_align2(i32 signext %a) {
entry:
store i32 %a, i32* @i32_align2, align 2
store i32 %a, ptr @i32_align2, align 2
ret void
}

define void @store_i32_align4(i32 signext %a) {
entry:
store i32 %a, i32* @i32_align4, align 4
store i32 %a, ptr @i32_align4, align 4
ret void
}

define void @store_i32_align8(i32 signext %a) {
entry:
store i32 %a, i32* @i32_align8, align 8
store i32 %a, ptr @i32_align8, align 8
ret void
}

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8 changes: 4 additions & 4 deletions llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub_vec.mir
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Expand Up @@ -2,10 +2,10 @@
# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |

define void @sub_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
define void @sub_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
define void @sub_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
define void @sub_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
define void @sub_v16i8(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @sub_v8i16(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @sub_v4i32(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @sub_v2i64(ptr %a, ptr %b, ptr %c) { entry: ret void }

...
---
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16 changes: 8 additions & 8 deletions llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub_vec_builtin.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -3,28 +3,28 @@
--- |

declare <16 x i8> @llvm.mips.subv.b(<16 x i8>, <16 x i8>)
define void @sub_v16i8_builtin(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
define void @sub_v16i8_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }

declare <8 x i16> @llvm.mips.subv.h(<8 x i16>, <8 x i16>)
define void @sub_v8i16_builtin(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
define void @sub_v8i16_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }

declare <4 x i32> @llvm.mips.subv.w(<4 x i32>, <4 x i32>)
define void @sub_v4i32_builtin(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
define void @sub_v4i32_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }

declare <2 x i64> @llvm.mips.subv.d(<2 x i64>, <2 x i64>)
define void @sub_v2i64_builtin(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
define void @sub_v2i64_builtin(ptr %a, ptr %b, ptr %c) { entry: ret void }

declare <16 x i8> @llvm.mips.subvi.b(<16 x i8>, i32 immarg)
define void @sub_v16i8_builtin_imm(<16 x i8>* %a, <16 x i8>* %c) { entry: ret void }
define void @sub_v16i8_builtin_imm(ptr %a, ptr %c) { entry: ret void }

declare <8 x i16> @llvm.mips.subvi.h(<8 x i16>, i32 immarg)
define void @sub_v8i16_builtin_imm(<8 x i16>* %a, <8 x i16>* %c) { entry: ret void }
define void @sub_v8i16_builtin_imm(ptr %a, ptr %c) { entry: ret void }

declare <4 x i32> @llvm.mips.subvi.w(<4 x i32>, i32 immarg)
define void @sub_v4i32_builtin_imm(<4 x i32>* %a, <4 x i32>* %c) { entry: ret void }
define void @sub_v4i32_builtin_imm(ptr %a, ptr %c) { entry: ret void }

declare <2 x i64> @llvm.mips.subvi.d(<2 x i64>, i32 immarg)
define void @sub_v2i64_builtin_imm(<2 x i64>* %a, <2 x i64>* %c) { entry: ret void }
define void @sub_v2i64_builtin_imm(ptr %a, ptr %c) { entry: ret void }

...
---
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20 changes: 10 additions & 10 deletions llvm/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -2,16 +2,16 @@
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |

define void @load1_s8_to_zextLoad1_s32(i8* %px) {entry: ret void}
define void @load2_s16_to_zextLoad2_s32(i16* %px) {entry: ret void}
define void @load1_s8_to_zextLoad1_s16(i8* %px) {entry: ret void}
define void @load1_s8_to_zextLoad1_s16_to_zextLoad1_s32(i8* %px) {entry: ret void}
define void @load4_s32_to_zextLoad4_s64(i8* %px) {entry: ret void}
define void @load1_s8_to_sextLoad1_s32(i8* %px) {entry: ret void}
define void @load2_s16_to_sextLoad2_s32(i16* %px) {entry: ret void}
define void @load1_s8_to_sextLoad1_s16(i8* %px) {entry: ret void}
define void @load1_s8_to_sextLoad1_s16_to_sextLoad1_s32(i8* %px) {entry: ret void}
define void @load4_s32_to_sextLoad4_s64(i8* %px) {entry: ret void}
define void @load1_s8_to_zextLoad1_s32(ptr %px) {entry: ret void}
define void @load2_s16_to_zextLoad2_s32(ptr %px) {entry: ret void}
define void @load1_s8_to_zextLoad1_s16(ptr %px) {entry: ret void}
define void @load1_s8_to_zextLoad1_s16_to_zextLoad1_s32(ptr %px) {entry: ret void}
define void @load4_s32_to_zextLoad4_s64(ptr %px) {entry: ret void}
define void @load1_s8_to_sextLoad1_s32(ptr %px) {entry: ret void}
define void @load2_s16_to_sextLoad2_s32(ptr %px) {entry: ret void}
define void @load1_s8_to_sextLoad1_s16(ptr %px) {entry: ret void}
define void @load1_s8_to_sextLoad1_s16_to_sextLoad1_s32(ptr %px) {entry: ret void}
define void @load4_s32_to_sextLoad4_s64(ptr %px) {entry: ret void}

...
---
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/truncStore_and_aExtLoad.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -2,8 +2,8 @@
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=mips-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |

define void @load1_s8_to_load1_s32(i8* %px) {entry: ret void}
define void @load2_s16_to_load2_s32(i16* %px) {entry: ret void}
define void @load1_s8_to_load1_s32(ptr %px) {entry: ret void}
define void @load2_s16_to_load2_s32(ptr %px) {entry: ret void}

...
---
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20 changes: 10 additions & 10 deletions llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/zextLoad_and_sextLoad.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -2,16 +2,16 @@
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=mips-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |

define void @load1_s8_to_zextLoad1_s32(i8* %px) {entry: ret void}
define void @load2_s16_to_zextLoad2_s32(i16* %px) {entry: ret void}
define void @load1_s8_to_zextLoad1_s16(i8* %px) {entry: ret void}
define void @load1_s8_to_zextLoad1_s16_to_zextLoad1_s32(i8* %px) {entry: ret void}
define void @load4_s32_to_zextLoad4_s64(i8* %px) {entry: ret void}
define void @load1_s8_to_sextLoad1_s32(i8* %px) {entry: ret void}
define void @load2_s16_to_sextLoad2_s32(i16* %px) {entry: ret void}
define void @load1_s8_to_sextLoad1_s16(i8* %px) {entry: ret void}
define void @load1_s8_to_sextLoad1_s16_to_sextLoad1_s32(i8* %px) {entry: ret void}
define void @load4_s32_to_sextLoad4_s64(i8* %px) {entry: ret void}
define void @load1_s8_to_zextLoad1_s32(ptr %px) {entry: ret void}
define void @load2_s16_to_zextLoad2_s32(ptr %px) {entry: ret void}
define void @load1_s8_to_zextLoad1_s16(ptr %px) {entry: ret void}
define void @load1_s8_to_zextLoad1_s16_to_zextLoad1_s32(ptr %px) {entry: ret void}
define void @load4_s32_to_zextLoad4_s64(ptr %px) {entry: ret void}
define void @load1_s8_to_sextLoad1_s32(ptr %px) {entry: ret void}
define void @load2_s16_to_sextLoad2_s32(ptr %px) {entry: ret void}
define void @load1_s8_to_sextLoad1_s16(ptr %px) {entry: ret void}
define void @load1_s8_to_sextLoad1_s16_to_sextLoad1_s32(ptr %px) {entry: ret void}
define void @load4_s32_to_sextLoad4_s64(ptr %px) {entry: ret void}

...
---
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/Mips/GlobalISel/regbankselect/TypeInfoforMF_skipCopies.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -2,8 +2,8 @@
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |

define void @skipCopiesOutgoing(float* %ptr_a, float* %ptr_b, float* %ptr_c) {entry: ret void}
define void @skipCopiesIncoming(float* %float_ptr) {entry: ret void}
define void @skipCopiesOutgoing(ptr %ptr_a, ptr %ptr_b, ptr %ptr_c) {entry: ret void}
define void @skipCopiesIncoming(ptr %float_ptr) {entry: ret void}

...
---
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8 changes: 4 additions & 4 deletions llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add_vec.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -2,10 +2,10 @@
# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |

define void @add_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
define void @add_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
define void @add_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
define void @add_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
define void @add_v16i8(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @add_v8i16(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @add_v4i32(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @add_v2i64(ptr %a, ptr %b, ptr %c) { entry: ret void }

...
---
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/Mips/GlobalISel/regbankselect/brindirect.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -2,9 +2,9 @@
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |

define i32 @indirectbr(i8* %addr) {
define i32 @indirectbr(ptr %addr) {
entry:
indirectbr i8* %addr, [label %L1, label %L2]
indirectbr ptr %addr, [label %L1, label %L2]

L1:
ret i32 0
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fabs_vec.mir
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Expand Up @@ -2,8 +2,8 @@
# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |

define void @fabs_v4f32(<4 x float>* %a, <4 x float>* %c) { entry: ret void }
define void @fabs_v2f64(<2 x double>* %a, <2 x double>* %c) { entry: ret void }
define void @fabs_v4f32(ptr %a, ptr %c) { entry: ret void }
define void @fabs_v2f64(ptr %a, ptr %c) { entry: ret void }

...
---
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fence.mir
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Expand Up @@ -2,7 +2,7 @@
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |

define void @atomic_load_i32(i32* %ptr) { ret void }
define void @atomic_load_i32(ptr %ptr) { ret void }

...
---
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16 changes: 8 additions & 8 deletions llvm/test/CodeGen/Mips/GlobalISel/regbankselect/floating_point_vec_arithmetic_operations.mir
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Expand Up @@ -2,17 +2,17 @@
# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |

define void @fadd_v4f32(<4 x float>* %a, <4 x float>* %b, <4 x float>* %c) { entry: ret void }
define void @fadd_v2f64(<2 x double>* %a, <2 x double>* %b, <2 x double>* %c) { entry: ret void }
define void @fadd_v4f32(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @fadd_v2f64(ptr %a, ptr %b, ptr %c) { entry: ret void }

define void @fsub_v4f32(<4 x float>* %a, <4 x float>* %b, <4 x float>* %c) { entry: ret void }
define void @fsub_v2f64(<2 x double>* %a, <2 x double>* %b, <2 x double>* %c) { entry: ret void }
define void @fsub_v4f32(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @fsub_v2f64(ptr %a, ptr %b, ptr %c) { entry: ret void }

define void @fmul_v4f32(<4 x float>* %a, <4 x float>* %b, <4 x float>* %c) { entry: ret void }
define void @fmul_v2f64(<2 x double>* %a, <2 x double>* %b, <2 x double>* %c) { entry: ret void }
define void @fmul_v4f32(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @fmul_v2f64(ptr %a, ptr %b, ptr %c) { entry: ret void }

define void @fdiv_v4f32(<4 x float>* %a, <4 x float>* %b, <4 x float>* %c) { entry: ret void }
define void @fdiv_v2f64(<2 x double>* %a, <2 x double>* %b, <2 x double>* %c) { entry: ret void }
define void @fdiv_v4f32(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @fdiv_v2f64(ptr %a, ptr %b, ptr %c) { entry: ret void }

...
---
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fsqrt_vec.mir
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Expand Up @@ -2,8 +2,8 @@
# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |

define void @sqrt_v4f32(<4 x float>* %a, <4 x float>* %c) { entry: ret void }
define void @sqrt_v2f64(<2 x double>* %a, <2 x double>* %c) { entry: ret void }
define void @sqrt_v4f32(ptr %a, ptr %c) { entry: ret void }
define void @sqrt_v2f64(ptr %a, ptr %c) { entry: ret void }

...
---
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Mips/GlobalISel/regbankselect/global_address.mir
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Expand Up @@ -5,7 +5,7 @@
@.str = private unnamed_addr constant [11 x i8] c"hello %d \0A\00"

define void @main() {entry: ret void}
declare i32 @printf(i8*, ...)
declare i32 @printf(ptr, ...)

...
---
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12 changes: 6 additions & 6 deletions llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load.mir
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Expand Up @@ -2,12 +2,12 @@
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |

define void @load_i32(i32* %ptr) {entry: ret void}
define void @load_i64(i64* %ptr) {entry: ret void}
define void @load_ambiguous_i64_in_fpr(i64* %i64_ptr_a, i64* %i64_ptr_b) {entry: ret void}
define void @load_float(float* %ptr) {entry: ret void}
define void @load_ambiguous_float_in_gpr(float* %float_ptr_a, float* %float_ptr_b) {entry: ret void}
define void @load_double(double* %ptr) {entry: ret void}
define void @load_i32(ptr %ptr) {entry: ret void}
define void @load_i64(ptr %ptr) {entry: ret void}
define void @load_ambiguous_i64_in_fpr(ptr %i64_ptr_a, ptr %i64_ptr_b) {entry: ret void}
define void @load_float(ptr %ptr) {entry: ret void}
define void @load_ambiguous_float_in_gpr(ptr %float_ptr_a, ptr %float_ptr_b) {entry: ret void}
define void @load_double(ptr %ptr) {entry: ret void}

...
---
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6 changes: 3 additions & 3 deletions llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load_4_unaligned.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -9,19 +9,19 @@

define float @load_float_align1() {
entry:
%0 = load float, float* @float_align1, align 1
%0 = load float, ptr @float_align1, align 1
ret float %0
}

define float @load_float_align4() {
entry:
%0 = load float, float* @float_align4, align 4
%0 = load float, ptr @float_align4, align 4
ret float %0
}

define i32 @load_i32_align8() {
entry:
%0 = load i32, i32* @i32_align8, align 8
%0 = load i32, ptr @i32_align8, align 8
ret i32 %0
}

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12 changes: 6 additions & 6 deletions llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load_store_vec.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -2,12 +2,12 @@
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=msa,+fp64 -mattr=nan2008 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |

define void @load_store_v16i8(<16 x i8>* %a, <16 x i8>* %b) { entry: ret void }
define void @load_store_v8i16(<8 x i16>* %a, <8 x i16>* %b) { entry: ret void }
define void @load_store_v4i32(<4 x i32>* %a, <4 x i32>* %b) { entry: ret void }
define void @load_store_v2i64(<2 x i64>* %a, <2 x i64>* %b) { entry: ret void }
define void @load_store_v4f32(<4 x float>* %a, <4 x float>* %b) { entry: ret void }
define void @load_store_v2f64(<2 x double>* %a, <2 x double>* %b) { entry: ret void }
define void @load_store_v16i8(ptr %a, ptr %b) { entry: ret void }
define void @load_store_v8i16(ptr %a, ptr %b) { entry: ret void }
define void @load_store_v4i32(ptr %a, ptr %b) { entry: ret void }
define void @load_store_v2i64(ptr %a, ptr %b) { entry: ret void }
define void @load_store_v4f32(ptr %a, ptr %b) { entry: ret void }
define void @load_store_v2f64(ptr %a, ptr %b) { entry: ret void }

...
---
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80 changes: 40 additions & 40 deletions llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s32.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |

define void @long_chain_ambiguous_i64_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i64* %a, i64* %b, i64* %c, i64* %result) {
define void @long_chain_ambiguous_i64_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, ptr %a, ptr %b, ptr %c, ptr %result) {
entry:
br i1 %cnd0, label %pre.PHI.2, label %pre.PHI.1

Expand All @@ -13,55 +13,55 @@
br i1 %cnd2, label %b.PHI.1.2, label %b.PHI.1.0

b.PHI.1.0: ; preds = %pre.PHI.1.0
%phi1.0 = load i64, i64* %a
%phi1.0 = load i64, ptr %a
br label %b.PHI.1

b.PHI.1.1: ; preds = %pre.PHI.1
%phi1.1 = load i64, i64* %b
%phi1.1 = load i64, ptr %b
br label %b.PHI.1

b.PHI.1.2: ; preds = %pre.PHI.1.0
%phi1.2 = load i64, i64* %c
%phi1.2 = load i64, ptr %c
br label %b.PHI.1

b.PHI.1: ; preds = %b.PHI.1.2, %b.PHI.1.1, %b.PHI.1.0
%phi1 = phi i64 [ %phi1.0, %b.PHI.1.0 ], [ %phi1.1, %b.PHI.1.1 ], [ %phi1.2, %b.PHI.1.2 ]
br i1 %cnd2, label %b.PHI.1.end, label %b.PHI.3

b.PHI.1.end: ; preds = %b.PHI.1
store i64 %phi1, i64* %result
store i64 %phi1, ptr %result
ret void

pre.PHI.2: ; preds = %entry
br i1 %cnd0, label %b.PHI.2.0, label %b.PHI.2.1

b.PHI.2.0: ; preds = %pre.PHI.2
%phi2.0 = load i64, i64* %a
%phi2.0 = load i64, ptr %a
br label %b.PHI.2

b.PHI.2.1: ; preds = %pre.PHI.2
%phi2.1 = load i64, i64* %b
%phi2.1 = load i64, ptr %b
br label %b.PHI.2

b.PHI.2: ; preds = %b.PHI.2.1, %b.PHI.2.0
%phi2 = phi i64 [ %phi2.0, %b.PHI.2.0 ], [ %phi2.1, %b.PHI.2.1 ]
br i1 %cnd1, label %b.PHI.3, label %b.PHI.2.end

b.PHI.2.end: ; preds = %b.PHI.2
store i64 %phi2, i64* %result
store i64 %phi2, ptr %result
ret void

b.PHI.3: ; preds = %b.PHI.2, %b.PHI.1
%phi3 = phi i64 [ %phi2, %b.PHI.2 ], [ %phi1, %b.PHI.1 ]
%phi4 = phi i64 [ %phi2, %b.PHI.2 ], [ %phi1, %b.PHI.1 ]
%sel_1.2 = select i1 %cnd2, i64 %phi3, i64 %phi4
%sel_3_1.2 = select i1 %cnd1, i64 %sel_1.2, i64 %phi3
store i64 %sel_3_1.2, i64* %result
store i64 %phi3, i64* %result
store i64 %sel_3_1.2, ptr %result
store i64 %phi3, ptr %result
ret void
}

define void @long_chain_i64_in_gpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i64* %a, i64* %b, i64* %c, i64* %result) {
define void @long_chain_i64_in_gpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, ptr %a, ptr %b, ptr %c, ptr %result) {
entry:
br i1 %cnd0, label %pre.PHI.2, label %pre.PHI.1

Expand All @@ -72,55 +72,55 @@
br i1 %cnd2, label %b.PHI.1.2, label %b.PHI.1.0

b.PHI.1.0: ; preds = %pre.PHI.1.0
%phi1.0 = load i64, i64* %a
%phi1.0 = load i64, ptr %a
br label %b.PHI.1

b.PHI.1.1: ; preds = %pre.PHI.1
%phi1.1 = load i64, i64* %b
%phi1.1 = load i64, ptr %b
br label %b.PHI.1

b.PHI.1.2: ; preds = %pre.PHI.1.0
%phi1.2 = load i64, i64* %c
%phi1.2 = load i64, ptr %c
br label %b.PHI.1

b.PHI.1: ; preds = %b.PHI.1.2, %b.PHI.1.1, %b.PHI.1.0
%phi1 = phi i64 [ %phi1.0, %b.PHI.1.0 ], [ %phi1.1, %b.PHI.1.1 ], [ %phi1.2, %b.PHI.1.2 ]
br i1 %cnd2, label %b.PHI.1.end, label %b.PHI.3

b.PHI.1.end: ; preds = %b.PHI.1
store i64 %phi1, i64* %result
store i64 %phi1, ptr %result
ret void

pre.PHI.2: ; preds = %entry
br i1 %cnd0, label %b.PHI.2.0, label %b.PHI.2.1

b.PHI.2.0: ; preds = %pre.PHI.2
%phi2.0 = load i64, i64* %a
%phi2.0 = load i64, ptr %a
br label %b.PHI.2

b.PHI.2.1: ; preds = %pre.PHI.2
%phi2.1 = load i64, i64* %b
%phi2.1 = load i64, ptr %b
br label %b.PHI.2

b.PHI.2: ; preds = %b.PHI.2.1, %b.PHI.2.0
%phi2 = phi i64 [ %phi2.0, %b.PHI.2.0 ], [ %phi2.1, %b.PHI.2.1 ]
br i1 %cnd1, label %b.PHI.3, label %b.PHI.2.end

b.PHI.2.end: ; preds = %b.PHI.2
store i64 %phi2, i64* %result
store i64 %phi2, ptr %result
ret void

b.PHI.3: ; preds = %b.PHI.2, %b.PHI.1
%phi3 = phi i64 [ %phi2, %b.PHI.2 ], [ %phi1, %b.PHI.1 ]
%phi4 = phi i64 [ %phi2, %b.PHI.2 ], [ 0, %b.PHI.1 ]
%sel_1.2 = select i1 %cnd2, i64 %phi3, i64 %phi4
%sel_3_1.2 = select i1 %cnd1, i64 %sel_1.2, i64 %phi3
store i64 %sel_3_1.2, i64* %result
store i64 %phi3, i64* %result
store i64 %sel_3_1.2, ptr %result
store i64 %phi3, ptr %result
ret void
}

define void @long_chain_ambiguous_double_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, double* %a, double* %b, double* %c, double* %result) {
define void @long_chain_ambiguous_double_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, ptr %a, ptr %b, ptr %c, ptr %result) {
entry:
br i1 %cnd0, label %pre.PHI.2, label %pre.PHI.1

Expand All @@ -131,55 +131,55 @@
br i1 %cnd2, label %b.PHI.1.2, label %b.PHI.1.0

b.PHI.1.0: ; preds = %pre.PHI.1.0
%phi1.0 = load double, double* %a
%phi1.0 = load double, ptr %a
br label %b.PHI.1

b.PHI.1.1: ; preds = %pre.PHI.1
%phi1.1 = load double, double* %b
%phi1.1 = load double, ptr %b
br label %b.PHI.1

b.PHI.1.2: ; preds = %pre.PHI.1.0
%phi1.2 = load double, double* %c
%phi1.2 = load double, ptr %c
br label %b.PHI.1

b.PHI.1: ; preds = %b.PHI.1.2, %b.PHI.1.1, %b.PHI.1.0
%phi1 = phi double [ %phi1.0, %b.PHI.1.0 ], [ %phi1.1, %b.PHI.1.1 ], [ %phi1.2, %b.PHI.1.2 ]
br i1 %cnd2, label %b.PHI.1.end, label %b.PHI.3

b.PHI.1.end: ; preds = %b.PHI.1
store double %phi1, double* %result
store double %phi1, ptr %result
ret void

pre.PHI.2: ; preds = %entry
br i1 %cnd0, label %b.PHI.2.0, label %b.PHI.2.1

b.PHI.2.0: ; preds = %pre.PHI.2
%phi2.0 = load double, double* %a
%phi2.0 = load double, ptr %a
br label %b.PHI.2

b.PHI.2.1: ; preds = %pre.PHI.2
%phi2.1 = load double, double* %b
%phi2.1 = load double, ptr %b
br label %b.PHI.2

b.PHI.2: ; preds = %b.PHI.2.1, %b.PHI.2.0
%phi2 = phi double [ %phi2.0, %b.PHI.2.0 ], [ %phi2.1, %b.PHI.2.1 ]
br i1 %cnd1, label %b.PHI.3, label %b.PHI.2.end

b.PHI.2.end: ; preds = %b.PHI.2
store double %phi2, double* %result
store double %phi2, ptr %result
ret void

b.PHI.3: ; preds = %b.PHI.2, %b.PHI.1
%phi3 = phi double [ %phi2, %b.PHI.2 ], [ %phi1, %b.PHI.1 ]
%phi4 = phi double [ %phi2, %b.PHI.2 ], [ %phi1, %b.PHI.1 ]
%sel_1.2 = select i1 %cnd2, double %phi3, double %phi4
%sel_3_1.2 = select i1 %cnd1, double %sel_1.2, double %phi3
store double %sel_3_1.2, double* %result
store double %phi3, double* %result
store double %sel_3_1.2, ptr %result
store double %phi3, ptr %result
ret void
}

define void @long_chain_double_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, double* %a, double* %b, double* %c, double* %result) {
define void @long_chain_double_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, ptr %a, ptr %b, ptr %c, ptr %result) {
entry:
br i1 %cnd0, label %pre.PHI.2, label %pre.PHI.1

Expand All @@ -190,51 +190,51 @@
br i1 %cnd2, label %b.PHI.1.2, label %b.PHI.1.0

b.PHI.1.0: ; preds = %pre.PHI.1.0
%phi1.0 = load double, double* %a
%phi1.0 = load double, ptr %a
br label %b.PHI.1

b.PHI.1.1: ; preds = %pre.PHI.1
%phi1.1 = load double, double* %b
%phi1.1 = load double, ptr %b
br label %b.PHI.1

b.PHI.1.2: ; preds = %pre.PHI.1.0
%phi1.2 = load double, double* %c
%phi1.2 = load double, ptr %c
br label %b.PHI.1

b.PHI.1: ; preds = %b.PHI.1.2, %b.PHI.1.1, %b.PHI.1.0
%phi1 = phi double [ %phi1.0, %b.PHI.1.0 ], [ %phi1.1, %b.PHI.1.1 ], [ %phi1.2, %b.PHI.1.2 ]
br i1 %cnd2, label %b.PHI.1.end, label %b.PHI.3

b.PHI.1.end: ; preds = %b.PHI.1
store double %phi1, double* %result
store double %phi1, ptr %result
ret void

pre.PHI.2: ; preds = %entry
br i1 %cnd0, label %b.PHI.2.0, label %b.PHI.2.1

b.PHI.2.0: ; preds = %pre.PHI.2
%phi2.0 = load double, double* %a
%phi2.0 = load double, ptr %a
br label %b.PHI.2

b.PHI.2.1: ; preds = %pre.PHI.2
%phi2.1 = load double, double* %b
%phi2.1 = load double, ptr %b
br label %b.PHI.2

b.PHI.2: ; preds = %b.PHI.2.1, %b.PHI.2.0
%phi2 = phi double [ %phi2.0, %b.PHI.2.0 ], [ %phi2.1, %b.PHI.2.1 ]
br i1 %cnd1, label %b.PHI.3, label %b.PHI.2.end

b.PHI.2.end: ; preds = %b.PHI.2
store double %phi2, double* %result
store double %phi2, ptr %result
ret void

b.PHI.3: ; preds = %b.PHI.2, %b.PHI.1
%phi3 = phi double [ %phi2, %b.PHI.2 ], [ %phi1, %b.PHI.1 ]
%phi4 = phi double [ %phi2, %b.PHI.2 ], [ 0.000000e+00, %b.PHI.1 ]
%sel_1.2 = select i1 %cnd2, double %phi3, double %phi4
%sel_3_1.2 = select i1 %cnd1, double %sel_1.2, double %phi3
store double %sel_3_1.2, double* %result
store double %phi3, double* %result
store double %sel_3_1.2, ptr %result
store double %phi3, ptr %result
ret void
}

Expand Down
80 changes: 40 additions & 40 deletions llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s64.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |

define void @long_chain_ambiguous_i64_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i64* %a, i64* %b, i64* %c, i64* %result) {
define void @long_chain_ambiguous_i64_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, ptr %a, ptr %b, ptr %c, ptr %result) {
entry:
br i1 %cnd0, label %pre.PHI.2, label %pre.PHI.1

Expand All @@ -13,55 +13,55 @@
br i1 %cnd2, label %b.PHI.1.2, label %b.PHI.1.0

b.PHI.1.0: ; preds = %pre.PHI.1.0
%phi1.0 = load i64, i64* %a
%phi1.0 = load i64, ptr %a
br label %b.PHI.1

b.PHI.1.1: ; preds = %pre.PHI.1
%phi1.1 = load i64, i64* %b
%phi1.1 = load i64, ptr %b
br label %b.PHI.1

b.PHI.1.2: ; preds = %pre.PHI.1.0
%phi1.2 = load i64, i64* %c
%phi1.2 = load i64, ptr %c
br label %b.PHI.1

b.PHI.1: ; preds = %b.PHI.1.2, %b.PHI.1.1, %b.PHI.1.0
%phi1 = phi i64 [ %phi1.0, %b.PHI.1.0 ], [ %phi1.1, %b.PHI.1.1 ], [ %phi1.2, %b.PHI.1.2 ]
br i1 %cnd2, label %b.PHI.1.end, label %b.PHI.3

b.PHI.1.end: ; preds = %b.PHI.1
store i64 %phi1, i64* %result
store i64 %phi1, ptr %result
ret void

pre.PHI.2: ; preds = %entry
br i1 %cnd0, label %b.PHI.2.0, label %b.PHI.2.1

b.PHI.2.0: ; preds = %pre.PHI.2
%phi2.0 = load i64, i64* %a
%phi2.0 = load i64, ptr %a
br label %b.PHI.2

b.PHI.2.1: ; preds = %pre.PHI.2
%phi2.1 = load i64, i64* %b
%phi2.1 = load i64, ptr %b
br label %b.PHI.2

b.PHI.2: ; preds = %b.PHI.2.1, %b.PHI.2.0
%phi2 = phi i64 [ %phi2.0, %b.PHI.2.0 ], [ %phi2.1, %b.PHI.2.1 ]
br i1 %cnd1, label %b.PHI.3, label %b.PHI.2.end

b.PHI.2.end: ; preds = %b.PHI.2
store i64 %phi2, i64* %result
store i64 %phi2, ptr %result
ret void

b.PHI.3: ; preds = %b.PHI.2, %b.PHI.1
%phi3 = phi i64 [ %phi2, %b.PHI.2 ], [ %phi1, %b.PHI.1 ]
%phi4 = phi i64 [ %phi2, %b.PHI.2 ], [ %phi1, %b.PHI.1 ]
%sel_1.2 = select i1 %cnd2, i64 %phi3, i64 %phi4
%sel_3_1.2 = select i1 %cnd1, i64 %sel_1.2, i64 %phi3
store i64 %sel_3_1.2, i64* %result
store i64 %phi3, i64* %result
store i64 %sel_3_1.2, ptr %result
store i64 %phi3, ptr %result
ret void
}

define void @long_chain_i64_in_gpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i64* %a, i64* %b, i64* %c, i64* %result) {
define void @long_chain_i64_in_gpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, ptr %a, ptr %b, ptr %c, ptr %result) {
entry:
br i1 %cnd0, label %pre.PHI.2, label %pre.PHI.1

Expand All @@ -72,55 +72,55 @@
br i1 %cnd2, label %b.PHI.1.2, label %b.PHI.1.0

b.PHI.1.0: ; preds = %pre.PHI.1.0
%phi1.0 = load i64, i64* %a
%phi1.0 = load i64, ptr %a
br label %b.PHI.1

b.PHI.1.1: ; preds = %pre.PHI.1
%phi1.1 = load i64, i64* %b
%phi1.1 = load i64, ptr %b
br label %b.PHI.1

b.PHI.1.2: ; preds = %pre.PHI.1.0
%phi1.2 = load i64, i64* %c
%phi1.2 = load i64, ptr %c
br label %b.PHI.1

b.PHI.1: ; preds = %b.PHI.1.2, %b.PHI.1.1, %b.PHI.1.0
%phi1 = phi i64 [ %phi1.0, %b.PHI.1.0 ], [ %phi1.1, %b.PHI.1.1 ], [ %phi1.2, %b.PHI.1.2 ]
br i1 %cnd2, label %b.PHI.1.end, label %b.PHI.3

b.PHI.1.end: ; preds = %b.PHI.1
store i64 %phi1, i64* %result
store i64 %phi1, ptr %result
ret void

pre.PHI.2: ; preds = %entry
br i1 %cnd0, label %b.PHI.2.0, label %b.PHI.2.1

b.PHI.2.0: ; preds = %pre.PHI.2
%phi2.0 = load i64, i64* %a
%phi2.0 = load i64, ptr %a
br label %b.PHI.2

b.PHI.2.1: ; preds = %pre.PHI.2
%phi2.1 = load i64, i64* %b
%phi2.1 = load i64, ptr %b
br label %b.PHI.2

b.PHI.2: ; preds = %b.PHI.2.1, %b.PHI.2.0
%phi2 = phi i64 [ %phi2.0, %b.PHI.2.0 ], [ %phi2.1, %b.PHI.2.1 ]
br i1 %cnd1, label %b.PHI.3, label %b.PHI.2.end

b.PHI.2.end: ; preds = %b.PHI.2
store i64 %phi2, i64* %result
store i64 %phi2, ptr %result
ret void

b.PHI.3: ; preds = %b.PHI.2, %b.PHI.1
%phi3 = phi i64 [ %phi2, %b.PHI.2 ], [ %phi1, %b.PHI.1 ]
%phi4 = phi i64 [ %phi2, %b.PHI.2 ], [ 0, %b.PHI.1 ]
%sel_1.2 = select i1 %cnd2, i64 %phi3, i64 %phi4
%sel_3_1.2 = select i1 %cnd1, i64 %sel_1.2, i64 %phi3
store i64 %sel_3_1.2, i64* %result
store i64 %phi3, i64* %result
store i64 %sel_3_1.2, ptr %result
store i64 %phi3, ptr %result
ret void
}

define void @long_chain_ambiguous_double_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, double* %a, double* %b, double* %c, double* %result) {
define void @long_chain_ambiguous_double_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, ptr %a, ptr %b, ptr %c, ptr %result) {
entry:
br i1 %cnd0, label %pre.PHI.2, label %pre.PHI.1

Expand All @@ -131,55 +131,55 @@
br i1 %cnd2, label %b.PHI.1.2, label %b.PHI.1.0

b.PHI.1.0: ; preds = %pre.PHI.1.0
%phi1.0 = load double, double* %a
%phi1.0 = load double, ptr %a
br label %b.PHI.1

b.PHI.1.1: ; preds = %pre.PHI.1
%phi1.1 = load double, double* %b
%phi1.1 = load double, ptr %b
br label %b.PHI.1

b.PHI.1.2: ; preds = %pre.PHI.1.0
%phi1.2 = load double, double* %c
%phi1.2 = load double, ptr %c
br label %b.PHI.1

b.PHI.1: ; preds = %b.PHI.1.2, %b.PHI.1.1, %b.PHI.1.0
%phi1 = phi double [ %phi1.0, %b.PHI.1.0 ], [ %phi1.1, %b.PHI.1.1 ], [ %phi1.2, %b.PHI.1.2 ]
br i1 %cnd2, label %b.PHI.1.end, label %b.PHI.3

b.PHI.1.end: ; preds = %b.PHI.1
store double %phi1, double* %result
store double %phi1, ptr %result
ret void

pre.PHI.2: ; preds = %entry
br i1 %cnd0, label %b.PHI.2.0, label %b.PHI.2.1

b.PHI.2.0: ; preds = %pre.PHI.2
%phi2.0 = load double, double* %a
%phi2.0 = load double, ptr %a
br label %b.PHI.2

b.PHI.2.1: ; preds = %pre.PHI.2
%phi2.1 = load double, double* %b
%phi2.1 = load double, ptr %b
br label %b.PHI.2

b.PHI.2: ; preds = %b.PHI.2.1, %b.PHI.2.0
%phi2 = phi double [ %phi2.0, %b.PHI.2.0 ], [ %phi2.1, %b.PHI.2.1 ]
br i1 %cnd1, label %b.PHI.3, label %b.PHI.2.end

b.PHI.2.end: ; preds = %b.PHI.2
store double %phi2, double* %result
store double %phi2, ptr %result
ret void

b.PHI.3: ; preds = %b.PHI.2, %b.PHI.1
%phi3 = phi double [ %phi2, %b.PHI.2 ], [ %phi1, %b.PHI.1 ]
%phi4 = phi double [ %phi2, %b.PHI.2 ], [ %phi1, %b.PHI.1 ]
%sel_1.2 = select i1 %cnd2, double %phi3, double %phi4
%sel_3_1.2 = select i1 %cnd1, double %sel_1.2, double %phi3
store double %sel_3_1.2, double* %result
store double %phi3, double* %result
store double %sel_3_1.2, ptr %result
store double %phi3, ptr %result
ret void
}

define void @long_chain_double_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, double* %a, double* %b, double* %c, double* %result) {
define void @long_chain_double_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, ptr %a, ptr %b, ptr %c, ptr %result) {
entry:
br i1 %cnd0, label %pre.PHI.2, label %pre.PHI.1

Expand All @@ -190,51 +190,51 @@
br i1 %cnd2, label %b.PHI.1.2, label %b.PHI.1.0

b.PHI.1.0: ; preds = %pre.PHI.1.0
%phi1.0 = load double, double* %a
%phi1.0 = load double, ptr %a
br label %b.PHI.1

b.PHI.1.1: ; preds = %pre.PHI.1
%phi1.1 = load double, double* %b
%phi1.1 = load double, ptr %b
br label %b.PHI.1

b.PHI.1.2: ; preds = %pre.PHI.1.0
%phi1.2 = load double, double* %c
%phi1.2 = load double, ptr %c
br label %b.PHI.1

b.PHI.1: ; preds = %b.PHI.1.2, %b.PHI.1.1, %b.PHI.1.0
%phi1 = phi double [ %phi1.0, %b.PHI.1.0 ], [ %phi1.1, %b.PHI.1.1 ], [ %phi1.2, %b.PHI.1.2 ]
br i1 %cnd2, label %b.PHI.1.end, label %b.PHI.3

b.PHI.1.end: ; preds = %b.PHI.1
store double %phi1, double* %result
store double %phi1, ptr %result
ret void

pre.PHI.2: ; preds = %entry
br i1 %cnd0, label %b.PHI.2.0, label %b.PHI.2.1

b.PHI.2.0: ; preds = %pre.PHI.2
%phi2.0 = load double, double* %a
%phi2.0 = load double, ptr %a
br label %b.PHI.2

b.PHI.2.1: ; preds = %pre.PHI.2
%phi2.1 = load double, double* %b
%phi2.1 = load double, ptr %b
br label %b.PHI.2

b.PHI.2: ; preds = %b.PHI.2.1, %b.PHI.2.0
%phi2 = phi double [ %phi2.0, %b.PHI.2.0 ], [ %phi2.1, %b.PHI.2.1 ]
br i1 %cnd1, label %b.PHI.3, label %b.PHI.2.end

b.PHI.2.end: ; preds = %b.PHI.2
store double %phi2, double* %result
store double %phi2, ptr %result
ret void

b.PHI.3: ; preds = %b.PHI.2, %b.PHI.1
%phi3 = phi double [ %phi2, %b.PHI.2 ], [ %phi1, %b.PHI.1 ]
%phi4 = phi double [ %phi2, %b.PHI.2 ], [ 0.000000e+00, %b.PHI.1 ]
%sel_1.2 = select i1 %cnd2, double %phi3, double %phi4
%sel_3_1.2 = select i1 %cnd1, double %sel_1.2, double %phi3
store double %sel_3_1.2, double* %result
store double %phi3, double* %result
store double %sel_3_1.2, ptr %result
store double %phi3, ptr %result
ret void
}

Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@
--- |

define void @mul_i32(i32 %x, i32 %y) {entry: ret void}
define void @umul_with_overflow(i32 %lhs, i32 %rhs, i32* %pmul, i1* %pcarry_flag) { ret void }
define void @umul_with_overflow(i32 %lhs, i32 %rhs, ptr %pmul, ptr %pcarry_flag) { ret void }

...
---
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul_vec.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2,10 +2,10 @@
# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |

define void @mul_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
define void @mul_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
define void @mul_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
define void @mul_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
define void @mul_v16i8(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @mul_v8i16(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @mul_v4i32(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @mul_v2i64(ptr %a, ptr %b, ptr %c) { entry: ret void }

...
---
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/Mips/GlobalISel/regbankselect/phi.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -32,10 +32,10 @@
ret i64 %cond
}

define void @phi_ambiguous_i64_in_fpr(i1 %cnd, i64* %i64_ptr_a, i64* %i64_ptr_b, i64* %i64_ptr_c) {
define void @phi_ambiguous_i64_in_fpr(i1 %cnd, ptr %i64_ptr_a, ptr %i64_ptr_b, ptr %i64_ptr_c) {
entry:
%0 = load i64, i64* %i64_ptr_a, align 8
%1 = load i64, i64* %i64_ptr_b, align 8
%0 = load i64, ptr %i64_ptr_a, align 8
%1 = load i64, ptr %i64_ptr_b, align 8
br i1 %cnd, label %cond.true, label %cond.false

cond.true: ; preds = %entry
Expand All @@ -46,7 +46,7 @@

cond.end: ; preds = %cond.false, %cond.true
%cond = phi i64 [ %0, %cond.true ], [ %1, %cond.false ]
store i64 %cond, i64* %i64_ptr_c, align 8
store i64 %cond, ptr %i64_ptr_c, align 8
ret void
}

Expand All @@ -65,10 +65,10 @@
ret float %cond
}

define void @phi_ambiguous_float_in_gpr(i1 %cnd, float* %f32_ptr_a, float* %f32_ptr_b, float* %f32_ptr_c) {
define void @phi_ambiguous_float_in_gpr(i1 %cnd, ptr %f32_ptr_a, ptr %f32_ptr_b, ptr %f32_ptr_c) {
entry:
%0 = load float, float* %f32_ptr_a, align 4
%1 = load float, float* %f32_ptr_b, align 4
%0 = load float, ptr %f32_ptr_a, align 4
%1 = load float, ptr %f32_ptr_b, align 4
br i1 %cnd, label %cond.true, label %cond.false

cond.true: ; preds = %entry
Expand All @@ -79,7 +79,7 @@

cond.end: ; preds = %cond.false, %cond.true
%cond = phi float [ %0, %cond.true ], [ %1, %cond.false ]
store float %cond, float* %f32_ptr_c, align 4
store float %cond, ptr %f32_ptr_c, align 4
ret void
}

Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/Mips/GlobalISel/regbankselect/pointers.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -2,9 +2,9 @@
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |

define void @ptr_arg_in_regs(i32* %p) {entry: ret void}
define void @ptr_arg_on_stack(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i32* %p) {entry: ret void}
define void @ret_ptr(i8* %p) {entry: ret void}
define void @ptr_arg_in_regs(ptr %p) {entry: ret void}
define void @ptr_arg_on_stack(i32 %x1, i32 %x2, i32 %x3, i32 %x4, ptr %p) {entry: ret void}
define void @ret_ptr(ptr %p) {entry: ret void}

...
---
Expand Down
38 changes: 19 additions & 19 deletions llvm/test/CodeGen/Mips/GlobalISel/regbankselect/rem_and_div_vec.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -2,25 +2,25 @@
# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |

define void @sdiv_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
define void @sdiv_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
define void @sdiv_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
define void @sdiv_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }

define void @srem_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
define void @srem_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
define void @srem_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
define void @srem_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }

define void @udiv_v16u8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
define void @udiv_v8u16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
define void @udiv_v4u32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
define void @udiv_v2u64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }

define void @urem_v16u8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
define void @urem_v8u16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
define void @urem_v4u32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
define void @urem_v2u64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
define void @sdiv_v16i8(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @sdiv_v8i16(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @sdiv_v4i32(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @sdiv_v2i64(ptr %a, ptr %b, ptr %c) { entry: ret void }

define void @srem_v16i8(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @srem_v8i16(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @srem_v4i32(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @srem_v2i64(ptr %a, ptr %b, ptr %c) { entry: ret void }

define void @udiv_v16u8(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @udiv_v8u16(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @udiv_v4u32(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @udiv_v2u64(ptr %a, ptr %b, ptr %c) { entry: ret void }

define void @urem_v16u8(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @urem_v8u16(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @urem_v4u32(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @urem_v2u64(ptr %a, ptr %b, ptr %c) { entry: ret void }

...
---
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/Mips/GlobalISel/regbankselect/select.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,9 +5,9 @@
define void @select_i32(i32, i32) {entry: ret void}
define void @select_ptr(i32, i32) {entry: ret void}
define void @select_i64() {entry: ret void}
define void @select_ambiguous_i64_in_fpr(i64* %i64_ptr_a, i64* %i64_ptr_b, i64* %i64_ptr_c) {entry: ret void}
define void @select_ambiguous_i64_in_fpr(ptr %i64_ptr_a, ptr %i64_ptr_b, ptr %i64_ptr_c) {entry: ret void}
define void @select_float() {entry: ret void}
define void @select_ambiguous_float_in_gpr(float* %f32_ptr_a, float* %f32_ptr_b, float* %f32_ptr_c) {entry: ret void}
define void @select_ambiguous_float_in_gpr(ptr %f32_ptr_a, ptr %f32_ptr_b, ptr %f32_ptr_c) {entry: ret void}
define void @select_double() {entry: ret void}

...
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2,10 +2,10 @@
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |

define void @store_i32(i32* %ptr) { entry: ret void }
define void @store_i64(i64* %ptr) { entry: ret void }
define void @store_float(float* %ptr) { entry: ret void }
define void @store_double(double* %ptr) { entry: ret void }
define void @store_i32(ptr %ptr) { entry: ret void }
define void @store_i64(ptr %ptr) { entry: ret void }
define void @store_float(ptr %ptr) { entry: ret void }
define void @store_double(ptr %ptr) { entry: ret void }

...
---
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store_4_unaligned.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,19 +9,19 @@

define void @store_float_align1(float %a) {
entry:
store float %a, float* @float_align1, align 1
store float %a, ptr @float_align1, align 1
ret void
}

define void @store_float_align4(float %a) {
entry:
store float %a, float* @float_align4, align 4
store float %a, ptr @float_align4, align 4
ret void
}

define void @store_i32_align8(i32 signext %a) {
entry:
store i32 %a, i32* @i32_align8, align 8
store i32 %a, ptr @i32_align8, align 8
ret void
}

Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub_vec.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2,10 +2,10 @@
# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |

define void @sub_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
define void @sub_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
define void @sub_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
define void @sub_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
define void @sub_v16i8(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @sub_v8i16(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @sub_v4i32(ptr %a, ptr %b, ptr %c) { entry: ret void }
define void @sub_v2i64(ptr %a, ptr %b, ptr %c) { entry: ret void }

...
---
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/Mips/GlobalISel/regbankselect/test_TypeInfoforMF.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2,14 +2,14 @@
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |

define void @outgoing_gpr(i32* %i32_ptr) {entry: ret void}
define void @outgoing_fpr(float* %float_ptr) {entry: ret void}
define void @outgoing_gpr_instr(i32* %i32_ptr1, i32* %i32_ptr2) {entry: ret void}
define void @outgoing_fpr_instr(float* %float_ptr1, float* %float_ptr2) {entry: ret void}
define void @incoming_gpr(i32* %a) {entry: ret void}
define void @incoming_fpr(float* %a) {entry: ret void}
define void @incoming_i32_instr(i32* %i32_ptr) {entry: ret void}
define void @incoming_float_instr(float* %float_ptr) {entry: ret void}
define void @outgoing_gpr(ptr %i32_ptr) {entry: ret void}
define void @outgoing_fpr(ptr %float_ptr) {entry: ret void}
define void @outgoing_gpr_instr(ptr %i32_ptr1, ptr %i32_ptr2) {entry: ret void}
define void @outgoing_fpr_instr(ptr %float_ptr1, ptr %float_ptr2) {entry: ret void}
define void @incoming_gpr(ptr %a) {entry: ret void}
define void @incoming_fpr(ptr %a) {entry: ret void}
define void @incoming_i32_instr(ptr %i32_ptr) {entry: ret void}
define void @incoming_float_instr(ptr %float_ptr) {entry: ret void}

...
---
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/Mips/GlobalISel/regbankselect/truncStore_and_aExtLoad.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -2,9 +2,9 @@
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |

define void @load_store_i8(i8* %px, i8* %py) {entry: ret void}
define void @load_store_i16(i16* %px, i16* %py) {entry: ret void}
define void @load_store_i32(i32* %px, i32* %py) {entry: ret void}
define void @load_store_i8(ptr %px, ptr %py) {entry: ret void}
define void @load_store_i16(ptr %px, ptr %py) {entry: ret void}
define void @load_store_i32(ptr %px, ptr %py) {entry: ret void}

...
---
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zextLoad_and_sextLoad.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -2,12 +2,12 @@
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |

define void @load1_s8_to_zextLoad1_s32(i8* %px) {entry: ret void}
define void @load2_s16_to_zextLoad2_s32(i16* %px) {entry: ret void}
define void @load4_s32_to_zextLoad4_s64(i8* %px) {entry: ret void}
define void @load1_s8_to_sextLoad1_s32(i8* %px) {entry: ret void}
define void @load2_s16_to_sextLoad2_s32(i16* %px) {entry: ret void}
define void @load4_s32_to_sextLoad4_s64(i8* %px) {entry: ret void}
define void @load1_s8_to_zextLoad1_s32(ptr %px) {entry: ret void}
define void @load2_s16_to_zextLoad2_s32(ptr %px) {entry: ret void}
define void @load4_s32_to_zextLoad4_s64(ptr %px) {entry: ret void}
define void @load1_s8_to_sextLoad1_s32(ptr %px) {entry: ret void}
define void @load2_s16_to_sextLoad2_s32(ptr %px) {entry: ret void}
define void @load4_s32_to_sextLoad4_s64(ptr %px) {entry: ret void}

...
---
Expand Down
18 changes: 9 additions & 9 deletions llvm/test/CodeGen/Mips/compactbranches/compact-branch-implicit-def.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -14,33 +14,33 @@
entry:
%retval = alloca i32, align 4
%a.addr = alloca i32, align 4
store i32 %a, i32* %a.addr, align 4
%0 = load i32, i32* %a.addr, align 4
store i32 %a, ptr %a.addr, align 4
%0 = load i32, ptr %a.addr, align 4
%cmp = icmp sgt i32 %0, 5
br i1 %cmp, label %if.then, label %if.else

if.then: ; preds = %entry
%1 = load i32, i32* %a.addr, align 4
%2 = load i32, i32* %a.addr, align 4
%1 = load i32, ptr %a.addr, align 4
%2 = load i32, ptr %a.addr, align 4
%add = add nsw i32 %1, %2
store i32 %add, i32* %retval, align 4
store i32 %add, ptr %retval, align 4
br label %return

if.else: ; preds = %entry
%3 = load i32, i32* %a.addr, align 4
%3 = load i32, ptr %a.addr, align 4
%call = call i32 @g(i32 signext %3)
store i32 %call, i32* %retval, align 4
store i32 %call, ptr %retval, align 4
br label %return

return: ; preds = %if.else, %if.then
%4 = load i32, i32* %retval, align 4
%4 = load i32, ptr %retval, align 4
ret i32 %4
}

declare i32 @g(i32 signext)

; Function Attrs: nounwind
declare void @llvm.stackprotector(i8*, i8**)
declare void @llvm.stackprotector(ptr, ptr)

!llvm.ident = !{!0}

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16 changes: 8 additions & 8 deletions llvm/test/CodeGen/Mips/delay-slot-filler-bundled-insts.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -16,28 +16,28 @@
--- |
target datalayout = "E-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"
target triple = "mips64-unknown-freebsd"
declare i8* @func_a(i64 zeroext)
declare i8* @func_b(i64 zeroext)
declare ptr @func_a(i64 zeroext)
declare ptr @func_b(i64 zeroext)
; Function Attrs: nounwind
define i8* @test(i64 zeroext %nbytes) local_unnamed_addr #0 {
define ptr @test(i64 zeroext %nbytes) local_unnamed_addr #0 {
entry:
%cmp = icmp eq i64 %nbytes, 0
br i1 %cmp, label %if.else, label %if.then

if.then: ; preds = %entry
%call = tail call i8* @func_a(i64 zeroext %nbytes)
%call = tail call ptr @func_a(i64 zeroext %nbytes)
br label %return

if.else: ; preds = %entry
%call1 = tail call i8* @func_b(i64 zeroext 0)
%call1 = tail call ptr @func_b(i64 zeroext 0)
br label %return

return: ; preds = %if.else, %if.then
%retval.0 = phi i8* [ %call, %if.then ], [ %call1, %if.else ]
ret i8* %retval.0
%retval.0 = phi ptr [ %call, %if.then ], [ %call1, %if.else ]
ret ptr %retval.0
}
; Function Attrs: nounwind
declare void @llvm.stackprotector(i8*, i8**) #0
declare void @llvm.stackprotector(ptr, ptr) #0

attributes #0 = { nounwind }

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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-call.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@

# CHECK: Bad machine code: invalid instruction when using jump guards!
--- |
define i32 @fooTail(i32 (i32)* nocapture %f1) {
define i32 @fooTail(ptr nocapture %f1) {
entry:
%0 = tail call i32 %f1(i32 14)
ret i32 %0
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-tailcall.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@

# CHECK: Bad machine code: invalid instruction when using jump guards!
--- |
define i32 @fooTail(i32 (i32)* nocapture %f1) {
define i32 @fooTail(ptr nocapture %f1) {
entry:
%0 = tail call i32 %f1(i32 14)
ret i32 %0
Expand Down
50 changes: 25 additions & 25 deletions llvm/test/CodeGen/Mips/micromips-eva.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10,40 +10,40 @@
; Function Attrs: noinline nounwind optnone
define void @_Z3foov() {
entry:
%0 = load i8, i8* getelementptr inbounds ([13 x i8], [13 x i8]* @bArray, i32 0, i32 5), align 1
%0 = load i8, ptr getelementptr inbounds ([13 x i8], ptr @bArray, i32 0, i32 5), align 1
%conv = sext i8 %0 to i32
%sub = sub nsw i32 %conv, 7
%conv1 = trunc i32 %sub to i8
store i8 %conv1, i8* getelementptr inbounds ([13 x i8], [13 x i8]* @bArray, i32 0, i32 3), align 1
%1 = load i8, i8* getelementptr inbounds ([13 x i8], [13 x i8]* @bArray, i32 0, i32 5), align 1
store i8 %conv1, ptr getelementptr inbounds ([13 x i8], ptr @bArray, i32 0, i32 3), align 1
%1 = load i8, ptr getelementptr inbounds ([13 x i8], ptr @bArray, i32 0, i32 5), align 1
%conv2 = sext i8 %1 to i32
%sub3 = sub nsw i32 %conv2, 7
%conv4 = trunc i32 %sub3 to i8
store i8 %conv4, i8* getelementptr inbounds ([13 x i8], [13 x i8]* @bArray, i32 0, i32 3), align 1
%2 = load i16, i16* getelementptr inbounds ([13 x i16], [13 x i16]* @hArray, i32 0, i32 5), align 2
store i8 %conv4, ptr getelementptr inbounds ([13 x i8], ptr @bArray, i32 0, i32 3), align 1
%2 = load i16, ptr getelementptr inbounds ([13 x i16], ptr @hArray, i32 0, i32 5), align 2
%conv5 = sext i16 %2 to i32
%sub6 = sub nsw i32 %conv5, 7
%conv7 = trunc i32 %sub6 to i16
store i16 %conv7, i16* getelementptr inbounds ([13 x i16], [13 x i16]* @hArray, i32 0, i32 3), align 2
%3 = load i16, i16* getelementptr inbounds ([13 x i16], [13 x i16]* @hArray, i32 0, i32 5), align 2
store i16 %conv7, ptr getelementptr inbounds ([13 x i16], ptr @hArray, i32 0, i32 3), align 2
%3 = load i16, ptr getelementptr inbounds ([13 x i16], ptr @hArray, i32 0, i32 5), align 2
%conv8 = sext i16 %3 to i32
%sub9 = sub nsw i32 %conv8, 7
%conv10 = trunc i32 %sub9 to i16
store i16 %conv10, i16* getelementptr inbounds ([13 x i16], [13 x i16]* @hArray, i32 0, i32 3), align 2
%4 = load i32, i32* getelementptr inbounds ([13 x i32], [13 x i32]* @wArray, i32 0, i32 5), align 4
store i16 %conv10, ptr getelementptr inbounds ([13 x i16], ptr @hArray, i32 0, i32 3), align 2
%4 = load i32, ptr getelementptr inbounds ([13 x i32], ptr @wArray, i32 0, i32 5), align 4
%sub11 = sub nsw i32 %4, 7
store i32 %sub11, i32* getelementptr inbounds ([13 x i32], [13 x i32]* @wArray, i32 0, i32 3), align 4
store i32 %sub11, ptr getelementptr inbounds ([13 x i32], ptr @wArray, i32 0, i32 3), align 4
ret void
}

; Function Attrs: noinline nounwind optnone
define i32 @_Z3barPi(i32* %z) {
define i32 @_Z3barPi(ptr %z) {
entry:
%z.addr = alloca i32*, align 4
store i32* %z, i32** %z.addr, align 4
%0 = load i32*, i32** %z.addr, align 4
%z.addr = alloca ptr, align 4
store ptr %z, ptr %z.addr, align 4
%0 = load ptr, ptr %z.addr, align 4
fence seq_cst
%1 = atomicrmw add i32* %0, i32 42 monotonic
%1 = atomicrmw add ptr %0, i32 42 monotonic
fence seq_cst
%2 = add i32 %1, 42
ret i32 %2
Expand Down Expand Up @@ -100,25 +100,25 @@ body: |
bb.0.entry:
%0:gpr32 = LUi target-flags(mips-abs-hi) @bArray
%1:gpr32 = ADDiu killed %0, target-flags(mips-abs-lo) @bArray
%2:gpr32 = LBuE %1, 5 :: (dereferenceable load (s8) from `i8* getelementptr inbounds ([13 x i8], [13 x i8]* @bArray, i32 0, i32 5)`)
%2:gpr32 = LBuE %1, 5 :: (dereferenceable load (s8) from `ptr getelementptr inbounds ([13 x i8], ptr @bArray, i32 0, i32 5)`)
%3:gpr32 = ADDiu killed %2, -7
SBE killed %3, %1, 3 :: (store (s8) into `i8* getelementptr inbounds ([13 x i8], [13 x i8]* @bArray, i32 0, i32 3)`)
%4:gpr32 = LBE %1, 5 :: (dereferenceable load (s8) from `i8* getelementptr inbounds ([13 x i8], [13 x i8]* @bArray, i32 0, i32 5)`)
SBE killed %3, %1, 3 :: (store (s8) into `ptr getelementptr inbounds ([13 x i8], ptr @bArray, i32 0, i32 3)`)
%4:gpr32 = LBE %1, 5 :: (dereferenceable load (s8) from `ptr getelementptr inbounds ([13 x i8], ptr @bArray, i32 0, i32 5)`)
%5:gpr32 = ADDiu killed %4, -7
SBE killed %5, %1, 3 :: (store (s8) into `i8* getelementptr inbounds ([13 x i8], [13 x i8]* @bArray, i32 0, i32 3)`)
SBE killed %5, %1, 3 :: (store (s8) into `ptr getelementptr inbounds ([13 x i8], ptr @bArray, i32 0, i32 3)`)
%6:gpr32 = LUi target-flags(mips-abs-hi) @hArray
%7:gpr32 = ADDiu killed %6, target-flags(mips-abs-lo) @hArray
%8:gpr32 = LHuE %7, 10 :: (dereferenceable load (s16) from `i16* getelementptr inbounds ([13 x i16], [13 x i16]* @hArray, i32 0, i32 5)`)
%8:gpr32 = LHuE %7, 10 :: (dereferenceable load (s16) from `ptr getelementptr inbounds ([13 x i16], ptr @hArray, i32 0, i32 5)`)
%9:gpr32 = ADDiu killed %8, -7
SHE killed %9, %7, 6 :: (store (s16) into `i16* getelementptr inbounds ([13 x i16], [13 x i16]* @hArray, i32 0, i32 3)`)
%10:gpr32 = LHE %7, 10 :: (dereferenceable load (s16) from `i16* getelementptr inbounds ([13 x i16], [13 x i16]* @hArray, i32 0, i32 5)`)
SHE killed %9, %7, 6 :: (store (s16) into `ptr getelementptr inbounds ([13 x i16], ptr @hArray, i32 0, i32 3)`)
%10:gpr32 = LHE %7, 10 :: (dereferenceable load (s16) from `ptr getelementptr inbounds ([13 x i16], ptr @hArray, i32 0, i32 5)`)
%11:gpr32 = ADDiu killed %10, -7
SHE killed %11, %7, 6 :: (store (s16) into `i16* getelementptr inbounds ([13 x i16], [13 x i16]* @hArray, i32 0, i32 3)`)
SHE killed %11, %7, 6 :: (store (s16) into `ptr getelementptr inbounds ([13 x i16], ptr @hArray, i32 0, i32 3)`)
%12:gpr32 = LUi target-flags(mips-abs-hi) @wArray
%13:gpr32 = ADDiu killed %12, target-flags(mips-abs-lo) @wArray
%14:gpr32 = LWE %13, 20 :: (dereferenceable load (s32) from `i32* getelementptr inbounds ([13 x i32], [13 x i32]* @wArray, i32 0, i32 5)`)
%14:gpr32 = LWE %13, 20 :: (dereferenceable load (s32) from `ptr getelementptr inbounds ([13 x i32], ptr @wArray, i32 0, i32 5)`)
%15:gpr32 = ADDiu killed %14, -7
SWE killed %15, %13, 12 :: (store (s32) into `i32* getelementptr inbounds ([13 x i32], [13 x i32]* @wArray, i32 0, i32 3)`)
SWE killed %15, %13, 12 :: (store (s32) into `ptr getelementptr inbounds ([13 x i32], ptr @wArray, i32 0, i32 3)`)
RetRA

...
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lwp-swp.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,15 +3,15 @@
# RUN: %s -o - | FileCheck %s

--- |
define void @f1(i32* %adr, i32 %val) { ret void }
define void @f2(i32* %adr, i32 %val) { ret void }
define void @f3(i32* %adr, i32 %val) { ret void }
define void @f4(i32* %adr, i32 %val) { ret void }
define void @f1(ptr %adr, i32 %val) { ret void }
define void @f2(ptr %adr, i32 %val) { ret void }
define void @f3(ptr %adr, i32 %val) { ret void }
define void @f4(ptr %adr, i32 %val) { ret void }

declare i32* @f()
declare ptr @f()

; Function Attrs: nounwind
declare void @llvm.stackprotector(i8*, i8**)
declare void @llvm.stackprotector(ptr, ptr)

...
---
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-no-lwp-swp.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,15 +3,15 @@
# RUN: %s -o - | FileCheck %s

--- |
define void @f1(i32* %adr, i32 %val) { ret void }
define void @f2(i32* %adr, i32 %val) { ret void }
define void @f3(i32* %adr, i32 %val) { ret void }
define void @f4(i32* %adr, i32 %val) { ret void }
define void @f1(ptr %adr, i32 %val) { ret void }
define void @f2(ptr %adr, i32 %val) { ret void }
define void @f3(ptr %adr, i32 %val) { ret void }
define void @f4(ptr %adr, i32 %val) { ret void }

declare i32* @f()
declare ptr @f()

; Function Attrs: nounwind
declare void @llvm.stackprotector(i8*, i8**)
declare void @llvm.stackprotector(ptr, ptr)
...
---
# CHECK-LABEL: name: f1
Expand Down
14 changes: 7 additions & 7 deletions llvm/test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -19,32 +19,32 @@
entry:
%call = tail call i32 @_Z1gi(i32 signext %asd)
%add = add nsw i32 %call, %asd
%0 = load i32, i32* @v, align 4
%0 = load i32, ptr @v, align 4
%add1 = add nsw i32 %add, %0
%.b.i.i = load i1, i1* @__tls_guard, align 1
%.b.i.i = load i1, ptr @__tls_guard, align 1
br i1 %.b.i.i, label %entry._ZTW1k.exit_crit_edge, label %init.i.i

entry._ZTW1k.exit_crit_edge:
%.pre = load i32, i32* @k, align 4
%.pre = load i32, ptr @k, align 4
br label %_ZTW1k.exit

init.i.i:
store i1 true, i1* @__tls_guard, align 1
store i1 true, ptr @__tls_guard, align 1
%call.i.i.i = tail call i32 @_Z1gi(i32 signext 3)
store i32 %call.i.i.i, i32* @k, align 4
store i32 %call.i.i.i, ptr @k, align 4
br label %_ZTW1k.exit

_ZTW1k.exit:
%1 = phi i32 [ %.pre, %entry._ZTW1k.exit_crit_edge ], [ %call.i.i.i, %init.i.i ]
%add2 = add nsw i32 %add1, %1
br i1 icmp ne (void ()* @_ZTH1j, void ()* null), label %2, label %_ZTW1j.exit
br i1 icmp ne (ptr @_ZTH1j, ptr null), label %2, label %_ZTW1j.exit

; <label>:2:
tail call void @_ZTH1j()
br label %_ZTW1j.exit

_ZTW1j.exit:
%3 = load i32, i32* @j, align 4
%3 = load i32, ptr @j, align 4
%add3 = add nsw i32 %add2, %3
ret i32 %add3
}
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,9 +13,9 @@
entry:
%call = tail call i32 @_Z1gi(i32 signext %asd)
%add = add nsw i32 %call, %asd
%0 = load i32, i32* @v, align 4
%0 = load i32, ptr @v, align 4
%add1 = add nsw i32 %add, %0
%1 = load i32, i32* @j, align 4
%1 = load i32, ptr @j, align 4
%add2 = add nsw i32 %add1, %1
ret i32 %add2
}
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/Mips/mirparser/target-flags-pic.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,9 +13,9 @@
entry:
%call = tail call i32 @_Z1gi(i32 signext %asd)
%add = add nsw i32 %call, %asd
%0 = load i32, i32* @v, align 4
%0 = load i32, ptr @v, align 4
%add1 = add nsw i32 %add, %0
%1 = load i32, i32* @j, align 4
%1 = load i32, ptr @j, align 4
%add2 = add nsw i32 %add1, %1
ret i32 %add2
}
Expand Down
14 changes: 7 additions & 7 deletions llvm/test/CodeGen/Mips/mirparser/target-flags-static-tls.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -18,32 +18,32 @@
entry:
%call = tail call i32 @_Z1gi(i32 signext %asd)
%add = add nsw i32 %call, %asd
%0 = load i32, i32* @v, align 4
%0 = load i32, ptr @v, align 4
%add1 = add nsw i32 %add, %0
%.b.i.i = load i1, i1* @__tls_guard, align 1
%.b.i.i = load i1, ptr @__tls_guard, align 1
br i1 %.b.i.i, label %entry._ZTW1k.exit_crit_edge, label %init.i.i

entry._ZTW1k.exit_crit_edge:
%.pre = load i32, i32* @k, align 4
%.pre = load i32, ptr @k, align 4
br label %_ZTW1k.exit

init.i.i:
store i1 true, i1* @__tls_guard, align 1
store i1 true, ptr @__tls_guard, align 1
%call.i.i.i = tail call i32 @_Z1gi(i32 signext 3)
store i32 %call.i.i.i, i32* @k, align 4
store i32 %call.i.i.i, ptr @k, align 4
br label %_ZTW1k.exit

_ZTW1k.exit:
%1 = phi i32 [ %.pre, %entry._ZTW1k.exit_crit_edge ], [ %call.i.i.i, %init.i.i ]
%add2 = add nsw i32 %add1, %1
br i1 icmp ne (void ()* @_ZTH1j, void ()* null), label %2, label %_ZTW1j.exit
br i1 icmp ne (ptr @_ZTH1j, ptr null), label %2, label %_ZTW1j.exit

; <label>:2:
tail call void @_ZTH1j()
br label %_ZTW1j.exit

_ZTW1j.exit:
%3 = load i32, i32* @j, align 4
%3 = load i32, ptr @j, align 4
%add3 = add nsw i32 %add2, %3
ret i32 %add3
}
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/Mips/unaligned-memops-mapping.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,17 +4,17 @@
# Test that MIPS unaligned load/store instructions can be mapped to their
# corresponding microMIPS instructions.
--- |
define void @g(i32* %a, i32* %b) {
define void @g(ptr %a, ptr %b) {
entry:
%0 = load i32, i32* %a, align 1
store i32 %0, i32* %b, align 1
%0 = load i32, ptr %a, align 1
store i32 %0, ptr %b, align 1
ret void
}

define void @g2(i32* %a, i32* %b) {
define void @g2(ptr %a, ptr %b) {
entry:
%0 = load i32, i32* %a, align 1
store i32 %0, i32* %b, align 1
%0 = load i32, ptr %a, align 1
store i32 %0, ptr %b, align 1
ret void
}
...
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8 changes: 4 additions & 4 deletions llvm/test/CodeGen/PowerPC/DisableHoistingDueToBlockHotnessNoProfileData.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -20,7 +20,7 @@
--- |
target datalayout = "e-m:e-i64:64-n32:64"

define dso_local void @test(void (i32)* nocapture %fp, i32 signext %Arg, i32 signext %Len, i32* nocapture %Ptr) {
define dso_local void @test(ptr nocapture %fp, i32 signext %Arg, i32 signext %Len, ptr nocapture %Ptr) {
entry:
tail call void asm sideeffect "#NOTHING", "~{r2}"()
%cmp6 = icmp sgt i32 %Len, 0
Expand All @@ -35,9 +35,9 @@

for.body: ; preds = %for.inc, %for.body.lr.ph
%i.07 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.inc ]
%0 = load i32, i32* %Ptr, align 4
%0 = load i32, ptr %Ptr, align 4
%1 = add i32 %i.07, %0
store i32 %1, i32* %Ptr, align 4
store i32 %1, ptr %Ptr, align 4
br i1 %cmp1, label %if.then, label %for.inc

if.then: ; preds = %for.body
Expand All @@ -52,7 +52,7 @@
}

; Function Attrs: nounwind
declare void @llvm.stackprotector(i8*, i8**) #0
declare void @llvm.stackprotector(ptr, ptr) #0

attributes #0 = { nounwind }

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