14 changes: 0 additions & 14 deletions llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,6 @@
#include "HexagonMCAsmInfo.h"
#include "HexagonMCELFStreamer.h"
#include "MCTargetDesc/HexagonInstPrinter.h"
#include "llvm/MC/MCCodeGenInfo.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCELFStreamer.h"
#include "llvm/MC/MCInstrInfo.h"
Expand Down Expand Up @@ -199,15 +198,6 @@ static MCAsmInfo *createHexagonMCAsmInfo(const MCRegisterInfo &MRI,
return MAI;
}

static MCCodeGenInfo *createHexagonMCCodeGenInfo(const Triple &TT,
Reloc::Model RM,
CodeModel::Model CM,
CodeGenOpt::Level OL) {
MCCodeGenInfo *X = new MCCodeGenInfo();
X->initMCCodeGenInfo(RM, CM, OL);
return X;
}

static MCInstPrinter *createHexagonMCInstPrinter(const Triple &T,
unsigned SyntaxVariant,
const MCAsmInfo &MAI,
Expand Down Expand Up @@ -242,10 +232,6 @@ extern "C" void LLVMInitializeHexagonTargetMC() {
// Register the MC asm info.
RegisterMCAsmInfoFn X(TheHexagonTarget, createHexagonMCAsmInfo);

// Register the MC codegen info.
TargetRegistry::RegisterMCCodeGenInfo(TheHexagonTarget,
createHexagonMCCodeGenInfo);

// Register the MC instruction info.
TargetRegistry::RegisterMCInstrInfo(TheHexagonTarget,
createHexagonMCInstrInfo);
Expand Down
14 changes: 0 additions & 14 deletions llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,6 @@

#include "InstPrinter/LanaiInstPrinter.h"
#include "LanaiMCAsmInfo.h"
#include "llvm/MC/MCCodeGenInfo.h"
#include "llvm/MC/MCInstrAnalysis.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCStreamer.h"
Expand Down Expand Up @@ -55,15 +54,6 @@ createLanaiMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
return createLanaiMCSubtargetInfoImpl(TT, CPUName, FS);
}

static MCCodeGenInfo *createLanaiMCCodeGenInfo(const Triple &TT,
Reloc::Model RM,
CodeModel::Model CM,
CodeGenOpt::Level OL) {
MCCodeGenInfo *X = new MCCodeGenInfo();
X->initMCCodeGenInfo(RM, CM, OL);
return X;
}

static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
MCAsmBackend &MAB, raw_pwrite_stream &OS,
MCCodeEmitter *Emitter, bool RelaxAll) {
Expand Down Expand Up @@ -125,10 +115,6 @@ extern "C" void LLVMInitializeLanaiTargetMC() {
// Register the MC asm info.
RegisterMCAsmInfo<LanaiMCAsmInfo> X(TheLanaiTarget);

// Register the MC codegen info.
TargetRegistry::RegisterMCCodeGenInfo(TheLanaiTarget,
createLanaiMCCodeGenInfo);

// Register the MC instruction info.
TargetRegistry::RegisterMCInstrInfo(TheLanaiTarget, createLanaiMCInstrInfo);

Expand Down
14 changes: 0 additions & 14 deletions llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,6 @@
#include "MSP430MCTargetDesc.h"
#include "InstPrinter/MSP430InstPrinter.h"
#include "MSP430MCAsmInfo.h"
#include "llvm/MC/MCCodeGenInfo.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
Expand Down Expand Up @@ -48,15 +47,6 @@ createMSP430MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
return createMSP430MCSubtargetInfoImpl(TT, CPU, FS);
}

static MCCodeGenInfo *createMSP430MCCodeGenInfo(const Triple &TT,
Reloc::Model RM,
CodeModel::Model CM,
CodeGenOpt::Level OL) {
MCCodeGenInfo *X = new MCCodeGenInfo();
X->initMCCodeGenInfo(RM, CM, OL);
return X;
}

static MCInstPrinter *createMSP430MCInstPrinter(const Triple &T,
unsigned SyntaxVariant,
const MCAsmInfo &MAI,
Expand All @@ -71,10 +61,6 @@ extern "C" void LLVMInitializeMSP430TargetMC() {
// Register the MC asm info.
RegisterMCAsmInfo<MSP430MCAsmInfo> X(TheMSP430Target);

// Register the MC codegen info.
TargetRegistry::RegisterMCCodeGenInfo(TheMSP430Target,
createMSP430MCCodeGenInfo);

// Register the MC instruction info.
TargetRegistry::RegisterMCInstrInfo(TheMSP430Target, createMSP430MCInstrInfo);

Expand Down
12 changes: 0 additions & 12 deletions llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,6 @@
#include "MipsMCNaCl.h"
#include "MipsTargetStreamer.h"
#include "llvm/ADT/Triple.h"
#include "llvm/MC/MCCodeGenInfo.h"
#include "llvm/MC/MCELFStreamer.h"
#include "llvm/MC/MCInstrAnalysis.h"
#include "llvm/MC/MCInstrInfo.h"
Expand Down Expand Up @@ -82,14 +81,6 @@ static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI,
return MAI;
}

static MCCodeGenInfo *createMipsMCCodeGenInfo(const Triple &TT, Reloc::Model RM,
CodeModel::Model CM,
CodeGenOpt::Level OL) {
MCCodeGenInfo *X = new MCCodeGenInfo();
X->initMCCodeGenInfo(RM, CM, OL);
return X;
}

static MCInstPrinter *createMipsMCInstPrinter(const Triple &T,
unsigned SyntaxVariant,
const MCAsmInfo &MAI,
Expand Down Expand Up @@ -163,9 +154,6 @@ extern "C" void LLVMInitializeMipsTargetMC() {
// Register the MC asm info.
RegisterMCAsmInfoFn X(*T, createMipsMCAsmInfo);

// Register the MC codegen info.
TargetRegistry::RegisterMCCodeGenInfo(*T, createMipsMCCodeGenInfo);

// Register the MC instruction info.
TargetRegistry::RegisterMCInstrInfo(*T, createMipsMCInstrInfo);

Expand Down
14 changes: 0 additions & 14 deletions llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,6 @@
#include "NVPTXMCTargetDesc.h"
#include "InstPrinter/NVPTXInstPrinter.h"
#include "NVPTXMCAsmInfo.h"
#include "llvm/MC/MCCodeGenInfo.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
Expand Down Expand Up @@ -49,16 +48,6 @@ createNVPTXMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
return createNVPTXMCSubtargetInfoImpl(TT, CPU, FS);
}

static MCCodeGenInfo *createNVPTXMCCodeGenInfo(const Triple &TT,
Reloc::Model RM,
CodeModel::Model CM,
CodeGenOpt::Level OL) {
MCCodeGenInfo *X = new MCCodeGenInfo();

X->initMCCodeGenInfo(RM, CM, OL);
return X;
}

static MCInstPrinter *createNVPTXMCInstPrinter(const Triple &T,
unsigned SyntaxVariant,
const MCAsmInfo &MAI,
Expand All @@ -75,9 +64,6 @@ extern "C" void LLVMInitializeNVPTXTargetMC() {
// Register the MC asm info.
RegisterMCAsmInfo<NVPTXMCAsmInfo> X(*T);

// Register the MC codegen info.
TargetRegistry::RegisterMCCodeGenInfo(*T, createNVPTXMCCodeGenInfo);

// Register the MC instruction info.
TargetRegistry::RegisterMCInstrInfo(*T, createNVPTXMCInstrInfo);

Expand Down
12 changes: 3 additions & 9 deletions llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,6 @@
#include "InstPrinter/PPCInstPrinter.h"
#include "PPCMCAsmInfo.h"
#include "PPCTargetStreamer.h"
#include "llvm/MC/MCCodeGenInfo.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCELFStreamer.h"
#include "llvm/MC/MCExpr.h"
Expand Down Expand Up @@ -87,18 +86,13 @@ static MCAsmInfo *createPPCMCAsmInfo(const MCRegisterInfo &MRI,
return MAI;
}

static MCCodeGenInfo *createPPCMCCodeGenInfo(const Triple &TT, Reloc::Model RM,
CodeModel::Model CM,
CodeGenOpt::Level OL) {
MCCodeGenInfo *X = new MCCodeGenInfo();

static void adjustCodeGenOpts(const Triple &TT, Reloc::Model RM,
CodeModel::Model &CM) {
if (CM == CodeModel::Default) {
if (!TT.isOSDarwin() &&
(TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le))
CM = CodeModel::Medium;
}
X->initMCCodeGenInfo(RM, CM, OL);
return X;
}

namespace {
Expand Down Expand Up @@ -239,7 +233,7 @@ extern "C" void LLVMInitializePowerPCTargetMC() {
RegisterMCAsmInfoFn C(*T, createPPCMCAsmInfo);

// Register the MC codegen info.
TargetRegistry::RegisterMCCodeGenInfo(*T, createPPCMCCodeGenInfo);
TargetRegistry::registerMCAdjustCodeGenOpts(*T, adjustCodeGenOpts);

// Register the MC instruction info.
TargetRegistry::RegisterMCInstrInfo(*T, createPPCMCInstrInfo);
Expand Down
35 changes: 10 additions & 25 deletions llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,6 @@
#include "InstPrinter/SparcInstPrinter.h"
#include "SparcMCAsmInfo.h"
#include "SparcTargetStreamer.h"
#include "llvm/MC/MCCodeGenInfo.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
Expand Down Expand Up @@ -81,30 +80,19 @@ createSparcMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
//
// All code models require that the text segment is smaller than 2GB.

static MCCodeGenInfo *createSparcMCCodeGenInfo(const Triple &TT,
Reloc::Model RM,
CodeModel::Model CM,
CodeGenOpt::Level OL) {
MCCodeGenInfo *X = new MCCodeGenInfo();

static void adjustCodeGenOpts(const Triple &TT, Reloc::Model RM,
CodeModel::Model &CM) {
// The default 32-bit code model is abs32/pic32 and the default 32-bit
// code model for JIT is abs32.
switch (CM) {
default: break;
case CodeModel::Default:
case CodeModel::JITDefault: CM = CodeModel::Small; break;
}

X->initMCCodeGenInfo(RM, CM, OL);
return X;
}

static MCCodeGenInfo *createSparcV9MCCodeGenInfo(const Triple &TT,
Reloc::Model RM,
CodeModel::Model CM,
CodeGenOpt::Level OL) {
MCCodeGenInfo *X = new MCCodeGenInfo();

static void adjustCodeGenOptsV9(const Triple &TT, Reloc::Model RM,
CodeModel::Model &CM) {
// The default 64-bit code model is abs44/pic32 and the default 64-bit
// code model for JIT is abs64.
switch (CM) {
Expand All @@ -116,9 +104,6 @@ static MCCodeGenInfo *createSparcV9MCCodeGenInfo(const Triple &TT,
CM = CodeModel::Large;
break;
}

X->initMCCodeGenInfo(RM, CM, OL);
return X;
}

static MCTargetStreamer *
Expand Down Expand Up @@ -175,10 +160,10 @@ extern "C" void LLVMInitializeSparcTargetMC() {
}

// Register the MC codegen info.
TargetRegistry::RegisterMCCodeGenInfo(TheSparcTarget,
createSparcMCCodeGenInfo);
TargetRegistry::RegisterMCCodeGenInfo(TheSparcV9Target,
createSparcV9MCCodeGenInfo);
TargetRegistry::RegisterMCCodeGenInfo(TheSparcelTarget,
createSparcMCCodeGenInfo);
TargetRegistry::registerMCAdjustCodeGenOpts(TheSparcTarget,
adjustCodeGenOpts);
TargetRegistry::registerMCAdjustCodeGenOpts(TheSparcV9Target,
adjustCodeGenOptsV9);
TargetRegistry::registerMCAdjustCodeGenOpts(TheSparcelTarget,
adjustCodeGenOpts);
}
16 changes: 5 additions & 11 deletions llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,6 @@
#include "SystemZMCTargetDesc.h"
#include "InstPrinter/SystemZInstPrinter.h"
#include "SystemZMCAsmInfo.h"
#include "llvm/MC/MCCodeGenInfo.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCStreamer.h"
Expand Down Expand Up @@ -159,11 +158,8 @@ createSystemZMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
return createSystemZMCSubtargetInfoImpl(TT, CPU, FS);
}

static MCCodeGenInfo *createSystemZMCCodeGenInfo(const Triple &TT,
Reloc::Model RM,
CodeModel::Model CM,
CodeGenOpt::Level OL) {
MCCodeGenInfo *X = new MCCodeGenInfo();
static void adjustCodeGenOpts(const Triple &TT, Reloc::Model RM,
CodeModel::Model &CM) {
// For SystemZ we define the models as follows:
//
// Small: BRASL can call any function and will use a stub if necessary.
Expand Down Expand Up @@ -197,8 +193,6 @@ static MCCodeGenInfo *createSystemZMCCodeGenInfo(const Triple &TT,
CM = CodeModel::Small;
else if (CM == CodeModel::JITDefault)
CM = RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium;
X->initMCCodeGenInfo(RM, CM, OL);
return X;
}

static MCInstPrinter *createSystemZMCInstPrinter(const Triple &T,
Expand All @@ -214,9 +208,9 @@ extern "C" void LLVMInitializeSystemZTargetMC() {
TargetRegistry::RegisterMCAsmInfo(TheSystemZTarget,
createSystemZMCAsmInfo);

// Register the MCCodeGenInfo.
TargetRegistry::RegisterMCCodeGenInfo(TheSystemZTarget,
createSystemZMCCodeGenInfo);
// Register the adjustCodeGenOpts.
TargetRegistry::registerMCAdjustCodeGenOpts(TheSystemZTarget,
adjustCodeGenOpts);

// Register the MCCodeEmitter.
TargetRegistry::RegisterMCCodeEmitter(TheSystemZTarget,
Expand Down
30 changes: 6 additions & 24 deletions llvm/lib/Target/TargetMachine.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,6 @@
#include "llvm/IR/LegacyPassManager.h"
#include "llvm/IR/Mangler.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCCodeGenInfo.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCSectionMachO.h"
Expand All @@ -40,12 +39,10 @@ TargetMachine::TargetMachine(const Target &T, StringRef DataLayoutString,
const Triple &TT, StringRef CPU, StringRef FS,
const TargetOptions &Options)
: TheTarget(T), DL(DataLayoutString), TargetTriple(TT), TargetCPU(CPU),
TargetFS(FS), CodeGenInfo(nullptr), AsmInfo(nullptr), MRI(nullptr),
MII(nullptr), STI(nullptr), RequireStructuredCFG(false),
Options(Options) {}
TargetFS(FS), AsmInfo(nullptr), MRI(nullptr), MII(nullptr), STI(nullptr),
RequireStructuredCFG(false), Options(Options) {}

TargetMachine::~TargetMachine() {
delete CodeGenInfo;
delete AsmInfo;
delete MRI;
delete MII;
Expand Down Expand Up @@ -77,19 +74,11 @@ void TargetMachine::resetTargetOptions(const Function &F) const {

/// Returns the code generation relocation model. The choices are static, PIC,
/// and dynamic-no-pic.
Reloc::Model TargetMachine::getRelocationModel() const {
if (!CodeGenInfo)
return Reloc::Static; // FIXME
return CodeGenInfo->getRelocationModel();
}
Reloc::Model TargetMachine::getRelocationModel() const { return RM; }

/// Returns the code model. The choices are small, kernel, medium, large, and
/// target default.
CodeModel::Model TargetMachine::getCodeModel() const {
if (!CodeGenInfo)
return CodeModel::Default;
return CodeGenInfo->getCodeModel();
}
CodeModel::Model TargetMachine::getCodeModel() const { return CMModel; }

/// Get the IR-specified TLS model for Var.
static TLSModel::Model getSelectedTLSModel(const GlobalValue *GV) {
Expand Down Expand Up @@ -182,16 +171,9 @@ TLSModel::Model TargetMachine::getTLSModel(const GlobalValue *GV) const {
}

/// Returns the optimization level: None, Less, Default, or Aggressive.
CodeGenOpt::Level TargetMachine::getOptLevel() const {
if (!CodeGenInfo)
return CodeGenOpt::Default;
return CodeGenInfo->getOptLevel();
}
CodeGenOpt::Level TargetMachine::getOptLevel() const { return OptLevel; }

void TargetMachine::setOptLevel(CodeGenOpt::Level Level) const {
if (CodeGenInfo)
CodeGenInfo->setOptLevel(Level);
}
void TargetMachine::setOptLevel(CodeGenOpt::Level Level) { OptLevel = Level; }

TargetIRAnalysis TargetMachine::getTargetIRAnalysis() {
return TargetIRAnalysis([this](const Function &F) {
Expand Down
12 changes: 3 additions & 9 deletions llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,6 @@
#include "InstPrinter/WebAssemblyInstPrinter.h"
#include "WebAssemblyMCAsmInfo.h"
#include "WebAssemblyTargetStreamer.h"
#include "llvm/MC/MCCodeGenInfo.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
Expand All @@ -40,18 +39,13 @@ static MCAsmInfo *createMCAsmInfo(const MCRegisterInfo & /*MRI*/,
return new WebAssemblyMCAsmInfo(TT);
}

static MCCodeGenInfo *createMCCodeGenInfo(const Triple & /*TT*/,
Reloc::Model /*RM*/,
CodeModel::Model CM,
CodeGenOpt::Level OL) {
static void adjustCodeGenOpts(const Triple & /*TT*/, Reloc::Model /*RM*/,
CodeModel::Model &CM) {
CodeModel::Model M = (CM == CodeModel::Default || CM == CodeModel::JITDefault)
? CodeModel::Large
: CM;
if (M != CodeModel::Large)
report_fatal_error("Non-large code models are not supported yet");
MCCodeGenInfo *CGI = new MCCodeGenInfo();
CGI->initMCCodeGenInfo(Reloc::PIC_, CM, OL);
return CGI;
}

static MCInstrInfo *createMCInstrInfo() {
Expand Down Expand Up @@ -114,7 +108,7 @@ extern "C" void LLVMInitializeWebAssemblyTargetMC() {
TargetRegistry::RegisterMCInstrInfo(*T, createMCInstrInfo);

// Register the MC codegen info.
TargetRegistry::RegisterMCCodeGenInfo(*T, createMCCodeGenInfo);
TargetRegistry::registerMCAdjustCodeGenOpts(*T, adjustCodeGenOpts);

// Register the MC register info.
TargetRegistry::RegisterMCRegInfo(*T, createMCRegisterInfo);
Expand Down
13 changes: 3 additions & 10 deletions llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,6 @@
#include "InstPrinter/X86IntelInstPrinter.h"
#include "X86MCAsmInfo.h"
#include "llvm/ADT/Triple.h"
#include "llvm/MC/MCCodeGenInfo.h"
#include "llvm/MC/MCInstrAnalysis.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
Expand Down Expand Up @@ -199,11 +198,8 @@ static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI,
return MAI;
}

static MCCodeGenInfo *createX86MCCodeGenInfo(const Triple &TT, Reloc::Model RM,
CodeModel::Model CM,
CodeGenOpt::Level OL) {
MCCodeGenInfo *X = new MCCodeGenInfo();

static void adjustCodeGenOpts(const Triple &TT, Reloc::Model RM,
CodeModel::Model &CM) {
bool is64Bit = TT.getArch() == Triple::x86_64;

// For static codegen, if we're not already set, use Small codegen.
Expand All @@ -212,9 +208,6 @@ static MCCodeGenInfo *createX86MCCodeGenInfo(const Triple &TT, Reloc::Model RM,
else if (CM == CodeModel::JITDefault)
// 64-bit JIT places everything in the same buffer except external funcs.
CM = is64Bit ? CodeModel::Large : CodeModel::Small;

X->initMCCodeGenInfo(RM, CM, OL);
return X;
}

static MCInstPrinter *createX86MCInstPrinter(const Triple &T,
Expand Down Expand Up @@ -246,7 +239,7 @@ extern "C" void LLVMInitializeX86TargetMC() {
RegisterMCAsmInfoFn X(*T, createX86MCAsmInfo);

// Register the MC codegen info.
RegisterMCCodeGenInfoFn Y(*T, createX86MCCodeGenInfo);
RegisterMCAdjustCodeGenOptsFn Y(*T, adjustCodeGenOpts);

// Register the MC instruction info.
TargetRegistry::RegisterMCInstrInfo(*T, createX86MCInstrInfo);
Expand Down
15 changes: 4 additions & 11 deletions llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,6 @@
#include "InstPrinter/XCoreInstPrinter.h"
#include "XCoreMCAsmInfo.h"
#include "XCoreTargetStreamer.h"
#include "llvm/MC/MCCodeGenInfo.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
Expand Down Expand Up @@ -62,19 +61,13 @@ static MCAsmInfo *createXCoreMCAsmInfo(const MCRegisterInfo &MRI,
return MAI;
}

static MCCodeGenInfo *createXCoreMCCodeGenInfo(const Triple &TT,
Reloc::Model RM,
CodeModel::Model CM,
CodeGenOpt::Level OL) {
MCCodeGenInfo *X = new MCCodeGenInfo();
static void adjustCodeGenOpts(const Triple &TT, Reloc::Model RM,
CodeModel::Model &CM) {
if (CM == CodeModel::Default) {
CM = CodeModel::Small;
}
if (CM != CodeModel::Small && CM != CodeModel::Large)
report_fatal_error("Target only supports CodeModel Small or Large");

X->initMCCodeGenInfo(RM, CM, OL);
return X;
}

static MCInstPrinter *createXCoreMCInstPrinter(const Triple &T,
Expand Down Expand Up @@ -134,8 +127,8 @@ extern "C" void LLVMInitializeXCoreTargetMC() {
RegisterMCAsmInfoFn X(TheXCoreTarget, createXCoreMCAsmInfo);

// Register the MC codegen info.
TargetRegistry::RegisterMCCodeGenInfo(TheXCoreTarget,
createXCoreMCCodeGenInfo);
TargetRegistry::registerMCAdjustCodeGenOpts(TheXCoreTarget,
adjustCodeGenOpts);

// Register the MC instruction info.
TargetRegistry::RegisterMCInstrInfo(TheXCoreTarget, createXCoreMCInstrInfo);
Expand Down