551 changes: 551 additions & 0 deletions llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
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40 changes: 40 additions & 0 deletions llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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Expand Up @@ -924,6 +924,16 @@ bool SITargetLowering::isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode,
!hasFP32Denormals(DAG.getMachineFunction());
}

bool SITargetLowering::isFPExtFoldable(const MachineInstr &MI, unsigned Opcode,
LLT DestTy, LLT SrcTy) const {
return ((Opcode == TargetOpcode::G_FMAD && Subtarget->hasMadMixInsts()) ||
(Opcode == TargetOpcode::G_FMA && Subtarget->hasFmaMixInsts())) &&
DestTy.getScalarSizeInBits() == 32 &&
SrcTy.getScalarSizeInBits() == 16 &&
// TODO: This probably only requires no input flushing?
!hasFP32Denormals(*MI.getMF());
}

bool SITargetLowering::isShuffleMaskLegal(ArrayRef<int>, EVT) const {
// SI has some legal vector types, but no legal vector operations. Say no
// shuffles are legal in order to prefer scalarizing some vector operations.
Expand Down Expand Up @@ -4462,6 +4472,8 @@ bool SITargetLowering::enableAggressiveFMAFusion(EVT VT) const {
return true;
}

bool SITargetLowering::enableAggressiveFMAFusion(LLT Ty) const { return true; }

EVT SITargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &Ctx,
EVT VT) const {
if (!VT.isVector()) {
Expand Down Expand Up @@ -4527,6 +4539,34 @@ bool SITargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
return false;
}

bool SITargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
LLT Ty) const {
switch (Ty.getScalarSizeInBits()) {
case 16:
return isFMAFasterThanFMulAndFAdd(MF, MVT::f16);
case 32:
return isFMAFasterThanFMulAndFAdd(MF, MVT::f32);
case 64:
return isFMAFasterThanFMulAndFAdd(MF, MVT::f64);
default:
break;
}

return false;
}

bool SITargetLowering::isFMADLegal(const MachineInstr &MI, LLT Ty) const {
if (!Ty.isScalar())
return false;

if (Ty.getScalarSizeInBits() == 16)
return Subtarget->hasMadF16() && !hasFP64FP16Denormals(*MI.getMF());
if (Ty.getScalarSizeInBits() == 32)
return Subtarget->hasMadMacF32Insts() && !hasFP32Denormals(*MI.getMF());

return false;
}

bool SITargetLowering::isFMADLegal(const SelectionDAG &DAG,
const SDNode *N) const {
// TODO: Check future ftz flag
Expand Down
7 changes: 7 additions & 0 deletions llvm/lib/Target/AMDGPU/SIISelLowering.h
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Original file line number Diff line number Diff line change
Expand Up @@ -253,6 +253,9 @@ class SITargetLowering final : public AMDGPUTargetLowering {
bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT,
EVT SrcVT) const override;

bool isFPExtFoldable(const MachineInstr &MI, unsigned Opcode, LLT DestTy,
LLT SrcTy) const override;

bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const override;

bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
Expand Down Expand Up @@ -378,14 +381,18 @@ class SITargetLowering final : public AMDGPUTargetLowering {

bool hasBitPreservingFPLogic(EVT VT) const override;
bool enableAggressiveFMAFusion(EVT VT) const override;
bool enableAggressiveFMAFusion(LLT Ty) const override;
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
EVT VT) const override;
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override;
LLT getPreferredShiftAmountTy(LLT Ty) const override;

bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
EVT VT) const override;
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
const LLT Ty) const override;
bool isFMADLegal(const SelectionDAG &DAG, const SDNode *N) const override;
bool isFMADLegal(const MachineInstr &MI, const LLT Ty) const override;

SDValue splitUnaryVectorOp(SDValue Op, SelectionDAG &DAG) const;
SDValue splitBinaryVectorOp(SDValue Op, SelectionDAG &DAG) const;
Expand Down
499 changes: 499 additions & 0 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-fma.ll
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159 changes: 159 additions & 0 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-mul.ll
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@@ -0,0 +1,159 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX9-FAST-DENORM %s
; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX10-FAST-DENORM %s

; fold (fadd fast (fpext (fmul fast x, y)), z) -> (fma (fpext x), (fpext y), z)
; fold (fadd fast x, (fpext (fmul fast y, z))) -> (fma (fpext y), (fpext z), x)

define amdgpu_vs float @test_f16_f32_add_ext_mul(half inreg %x, half inreg %y, float inreg %z) {
; GFX9-FAST-DENORM-LABEL: test_f16_f32_add_ext_mul:
; GFX9-FAST-DENORM: ; %bb.0: ; %.entry
; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v0, s0
; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v1, s1
; GFX9-FAST-DENORM-NEXT: v_mad_f32 v0, v0, v1, s2
; GFX9-FAST-DENORM-NEXT: ; return to shader part epilog
;
; GFX10-FAST-DENORM-LABEL: test_f16_f32_add_ext_mul:
; GFX10-FAST-DENORM: ; %bb.0: ; %.entry
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v0, s0
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v1, s1
; GFX10-FAST-DENORM-NEXT: v_fma_f32 v0, v0, v1, s2
; GFX10-FAST-DENORM-NEXT: ; return to shader part epilog
.entry:
%a = fmul fast half %x, %y
%b = fpext half %a to float
%c = fadd fast float %b, %z
ret float %c
}

define amdgpu_vs float @test_f16_f32_add_ext_mul_rhs(half inreg %x, half inreg %y, float inreg %z) {
; GFX9-FAST-DENORM-LABEL: test_f16_f32_add_ext_mul_rhs:
; GFX9-FAST-DENORM: ; %bb.0: ; %.entry
; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v0, s0
; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v1, s1
; GFX9-FAST-DENORM-NEXT: v_mad_f32 v0, v0, v1, s2
; GFX9-FAST-DENORM-NEXT: ; return to shader part epilog
;
; GFX10-FAST-DENORM-LABEL: test_f16_f32_add_ext_mul_rhs:
; GFX10-FAST-DENORM: ; %bb.0: ; %.entry
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v0, s0
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v1, s1
; GFX10-FAST-DENORM-NEXT: v_fma_f32 v0, v0, v1, s2
; GFX10-FAST-DENORM-NEXT: ; return to shader part epilog
.entry:
%a = fmul fast half %x, %y
%b = fpext half %a to float
%c = fadd fast float %z, %b
ret float %c
}

define amdgpu_vs <5 x float> @test_5xf16_5xf32_add_ext_mul(<5 x half> inreg %x, <5 x half> inreg %y, <5 x float> inreg %z) {
; GFX9-FAST-DENORM-LABEL: test_5xf16_5xf32_add_ext_mul:
; GFX9-FAST-DENORM: ; %bb.0: ; %.entry
; GFX9-FAST-DENORM-NEXT: s_pack_lh_b32_b16 s3, s3, s3
; GFX9-FAST-DENORM-NEXT: s_pack_lh_b32_b16 s4, s4, s4
; GFX9-FAST-DENORM-NEXT: s_pack_lh_b32_b16 s0, s0, s0
; GFX9-FAST-DENORM-NEXT: s_pack_lh_b32_b16 s1, s1, s1
; GFX9-FAST-DENORM-NEXT: v_mov_b32_e32 v0, s3
; GFX9-FAST-DENORM-NEXT: v_mov_b32_e32 v1, s4
; GFX9-FAST-DENORM-NEXT: v_mov_b32_e32 v2, s5
; GFX9-FAST-DENORM-NEXT: v_pk_mul_f16 v0, s0, v0
; GFX9-FAST-DENORM-NEXT: v_pk_mul_f16 v1, s1, v1
; GFX9-FAST-DENORM-NEXT: v_pk_mul_f16 v2, s2, v2
; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v3, v0
; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_sdwa v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v5, v1
; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_sdwa v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v7, v2
; GFX9-FAST-DENORM-NEXT: v_add_f32_e32 v0, s6, v3
; GFX9-FAST-DENORM-NEXT: v_add_f32_e32 v1, s7, v4
; GFX9-FAST-DENORM-NEXT: v_add_f32_e32 v2, s8, v5
; GFX9-FAST-DENORM-NEXT: v_add_f32_e32 v3, s9, v6
; GFX9-FAST-DENORM-NEXT: v_add_f32_e32 v4, s10, v7
; GFX9-FAST-DENORM-NEXT: ; return to shader part epilog
;
; GFX10-FAST-DENORM-LABEL: test_5xf16_5xf32_add_ext_mul:
; GFX10-FAST-DENORM: ; %bb.0: ; %.entry
; GFX10-FAST-DENORM-NEXT: s_lshr_b32 s11, s0, 16
; GFX10-FAST-DENORM-NEXT: s_lshr_b32 s12, s1, 16
; GFX10-FAST-DENORM-NEXT: s_lshr_b32 s13, s3, 16
; GFX10-FAST-DENORM-NEXT: s_lshr_b32 s14, s4, 16
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v0, s0
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v1, s11
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v2, s1
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v3, s12
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v4, s2
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v5, s3
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v6, s13
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v7, s4
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v8, s14
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v9, s5
; GFX10-FAST-DENORM-NEXT: v_fma_f32 v0, v0, v5, s6
; GFX10-FAST-DENORM-NEXT: v_fma_f32 v1, v1, v6, s7
; GFX10-FAST-DENORM-NEXT: v_fma_f32 v2, v2, v7, s8
; GFX10-FAST-DENORM-NEXT: v_fma_f32 v3, v3, v8, s9
; GFX10-FAST-DENORM-NEXT: v_fma_f32 v4, v4, v9, s10
; GFX10-FAST-DENORM-NEXT: ; return to shader part epilog
.entry:
%a = fmul fast <5 x half> %x, %y
%b = fpext <5 x half> %a to <5 x float>
%c = fadd fast <5 x float> %b, %z
ret <5 x float> %c
}

define amdgpu_vs <6 x float> @test_6xf16_6xf32_add_ext_mul_rhs(<6 x half> inreg %x, <6 x half> inreg %y, <6 x float> inreg %z) {
; GFX9-FAST-DENORM-LABEL: test_6xf16_6xf32_add_ext_mul_rhs:
; GFX9-FAST-DENORM: ; %bb.0: ; %.entry
; GFX9-FAST-DENORM-NEXT: v_mov_b32_e32 v0, s3
; GFX9-FAST-DENORM-NEXT: v_mov_b32_e32 v1, s4
; GFX9-FAST-DENORM-NEXT: v_mov_b32_e32 v2, s5
; GFX9-FAST-DENORM-NEXT: v_pk_mul_f16 v0, s0, v0
; GFX9-FAST-DENORM-NEXT: v_pk_mul_f16 v1, s1, v1
; GFX9-FAST-DENORM-NEXT: v_pk_mul_f16 v2, s2, v2
; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v3, v0
; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_sdwa v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v5, v1
; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_sdwa v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v7, v2
; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_sdwa v8, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX9-FAST-DENORM-NEXT: v_add_f32_e32 v0, s6, v3
; GFX9-FAST-DENORM-NEXT: v_add_f32_e32 v1, s7, v4
; GFX9-FAST-DENORM-NEXT: v_add_f32_e32 v2, s8, v5
; GFX9-FAST-DENORM-NEXT: v_add_f32_e32 v3, s9, v6
; GFX9-FAST-DENORM-NEXT: v_add_f32_e32 v4, s10, v7
; GFX9-FAST-DENORM-NEXT: v_add_f32_e32 v5, s11, v8
; GFX9-FAST-DENORM-NEXT: ; return to shader part epilog
;
; GFX10-FAST-DENORM-LABEL: test_6xf16_6xf32_add_ext_mul_rhs:
; GFX10-FAST-DENORM: ; %bb.0: ; %.entry
; GFX10-FAST-DENORM-NEXT: s_lshr_b32 s12, s0, 16
; GFX10-FAST-DENORM-NEXT: s_lshr_b32 s13, s1, 16
; GFX10-FAST-DENORM-NEXT: s_lshr_b32 s14, s2, 16
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v0, s0
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v2, s1
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v4, s2
; GFX10-FAST-DENORM-NEXT: s_lshr_b32 s0, s3, 16
; GFX10-FAST-DENORM-NEXT: s_lshr_b32 s1, s4, 16
; GFX10-FAST-DENORM-NEXT: s_lshr_b32 s2, s5, 16
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v1, s12
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v3, s13
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v5, s14
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v6, s3
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v7, s0
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v8, s4
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v9, s1
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v10, s5
; GFX10-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v11, s2
; GFX10-FAST-DENORM-NEXT: v_fma_f32 v0, v0, v6, s6
; GFX10-FAST-DENORM-NEXT: v_fma_f32 v1, v1, v7, s7
; GFX10-FAST-DENORM-NEXT: v_fma_f32 v2, v2, v8, s8
; GFX10-FAST-DENORM-NEXT: v_fma_f32 v3, v3, v9, s9
; GFX10-FAST-DENORM-NEXT: v_fma_f32 v4, v4, v10, s10
; GFX10-FAST-DENORM-NEXT: v_fma_f32 v5, v5, v11, s11
; GFX10-FAST-DENORM-NEXT: ; return to shader part epilog
.entry:
%a = fmul fast <6 x half> %x, %y
%b = fpext <6 x half> %a to <6 x float>
%c = fadd fast <6 x float> %z, %b
ret <6 x float> %c
}
726 changes: 726 additions & 0 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
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123 changes: 123 additions & 0 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-mul.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX9-DENORM %s
; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX10-DENORM %s

; fold (fsub (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), (fneg z))
define amdgpu_vs float @test_f16_to_f32_sub_ext_mul(half %x, half %y, float %z) {
; GFX9-DENORM-LABEL: test_f16_to_f32_sub_ext_mul:
; GFX9-DENORM: ; %bb.0: ; %entry
; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX9-DENORM-NEXT: v_mad_f32 v0, v0, v1, -v2
; GFX9-DENORM-NEXT: ; return to shader part epilog
;
; GFX10-DENORM-LABEL: test_f16_to_f32_sub_ext_mul:
; GFX10-DENORM: ; %bb.0: ; %entry
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX10-DENORM-NEXT: v_fma_f32 v0, v0, v1, -v2
; GFX10-DENORM-NEXT: ; return to shader part epilog
entry:
%a = fmul fast half %x, %y
%b = fpext half %a to float
%c = fsub fast float %b, %z
ret float %c
}

; fold (fsub x, (fpext (fmul y, z))) -> (fma (fneg (fpext y)), (fpext z), x)
define amdgpu_vs float @test_f16_to_f32_sub_ext_mul_rhs(float %x, half %y, half %z) {
; GFX9-DENORM-LABEL: test_f16_to_f32_sub_ext_mul_rhs:
; GFX9-DENORM: ; %bb.0: ; %.entry
; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v2, v2
; GFX9-DENORM-NEXT: v_mad_f32 v0, -v1, v2, v0
; GFX9-DENORM-NEXT: ; return to shader part epilog
;
; GFX10-DENORM-LABEL: test_f16_to_f32_sub_ext_mul_rhs:
; GFX10-DENORM: ; %bb.0: ; %.entry
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v2, v2
; GFX10-DENORM-NEXT: v_fma_f32 v0, -v1, v2, v0
; GFX10-DENORM-NEXT: ; return to shader part epilog
.entry:
%a = fmul fast half %y, %z
%b = fpext half %a to float
%c = fsub fast float %x, %b
ret float %c
}

; fold (fsub (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), (fneg z))
define amdgpu_vs <4 x float> @test_v4f16_to_v4f32_sub_ext_mul(<4 x half> %x, <4 x half> %y, <4 x float> %z) {
; GFX9-DENORM-LABEL: test_v4f16_to_v4f32_sub_ext_mul:
; GFX9-DENORM: ; %bb.0: ; %entry
; GFX9-DENORM-NEXT: v_pk_mul_f16 v0, v0, v2
; GFX9-DENORM-NEXT: v_pk_mul_f16 v1, v1, v3
; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v2, v0
; GFX9-DENORM-NEXT: v_cvt_f32_f16_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v8, v1
; GFX9-DENORM-NEXT: v_cvt_f32_f16_sdwa v9, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX9-DENORM-NEXT: v_sub_f32_e32 v0, v2, v4
; GFX9-DENORM-NEXT: v_sub_f32_e32 v1, v3, v5
; GFX9-DENORM-NEXT: v_sub_f32_e32 v2, v8, v6
; GFX9-DENORM-NEXT: v_sub_f32_e32 v3, v9, v7
; GFX9-DENORM-NEXT: ; return to shader part epilog
;
; GFX10-DENORM-LABEL: test_v4f16_to_v4f32_sub_ext_mul:
; GFX10-DENORM: ; %bb.0: ; %entry
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v8, v0
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v10, v1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v11, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v0, v2
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v2, v3
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_fma_f32 v0, v8, v0, -v4
; GFX10-DENORM-NEXT: v_fma_f32 v1, v9, v1, -v5
; GFX10-DENORM-NEXT: v_fma_f32 v2, v10, v2, -v6
; GFX10-DENORM-NEXT: v_fma_f32 v3, v11, v3, -v7
; GFX10-DENORM-NEXT: ; return to shader part epilog
entry:
%a = fmul fast <4 x half> %x, %y
%b = fpext <4 x half> %a to <4 x float>
%c = fsub fast <4 x float> %b, %z
ret <4 x float> %c
}

; fold (fsub x, (fpext (fmul y, z))) -> (fma (fneg (fpext y)), (fpext z), x)
define amdgpu_vs <4 x float> @test_v4f16_to_v4f32_sub_ext_mul_rhs(<4 x float> %x, <4 x half> %y, <4 x half> %z) {
; GFX9-DENORM-LABEL: test_v4f16_to_v4f32_sub_ext_mul_rhs:
; GFX9-DENORM: ; %bb.0: ; %.entry
; GFX9-DENORM-NEXT: v_pk_mul_f16 v4, v4, v6
; GFX9-DENORM-NEXT: v_pk_mul_f16 v5, v5, v7
; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v6, v4
; GFX9-DENORM-NEXT: v_cvt_f32_f16_sdwa v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v7, v5
; GFX9-DENORM-NEXT: v_cvt_f32_f16_sdwa v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX9-DENORM-NEXT: v_sub_f32_e32 v0, v0, v6
; GFX9-DENORM-NEXT: v_sub_f32_e32 v1, v1, v4
; GFX9-DENORM-NEXT: v_sub_f32_e32 v2, v2, v7
; GFX9-DENORM-NEXT: v_sub_f32_e32 v3, v3, v5
; GFX9-DENORM-NEXT: ; return to shader part epilog
;
; GFX10-DENORM-LABEL: test_v4f16_to_v4f32_sub_ext_mul_rhs:
; GFX10-DENORM: ; %bb.0: ; %.entry
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v8, v4
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v9, v5
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v10, v6
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v6, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v11, v7
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v7, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_fma_f32 v0, -v8, v10, v0
; GFX10-DENORM-NEXT: v_fma_f32 v1, -v4, v6, v1
; GFX10-DENORM-NEXT: v_fma_f32 v2, -v9, v11, v2
; GFX10-DENORM-NEXT: v_fma_f32 v3, -v5, v7, v3
; GFX10-DENORM-NEXT: ; return to shader part epilog
.entry:
%a = fmul fast <4 x half> %y, %z
%b = fpext <4 x half> %a to <4 x float>
%c = fsub fast <4 x float> %x, %b
ret <4 x float> %c
}
265 changes: 265 additions & 0 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-neg-mul.ll
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,265 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX9-DENORM %s
; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 --denormal-fp-math=preserve-sign < %s | FileCheck -check-prefix=GFX10-DENORM %s

; fold (fsub (fpext (fneg (fmul, x, y))), z) -> (fneg (fma (fpext x), (fpext y), z))
define amdgpu_vs float @test_f16_to_f32_sub_ext_neg_mul(half %x, half %y, float %z) {
; GFX9-DENORM-LABEL: test_f16_to_f32_sub_ext_neg_mul:
; GFX9-DENORM: ; %bb.0: ; %entry
; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX9-DENORM-NEXT: v_cvt_f32_f16_e64 v1, -v1
; GFX9-DENORM-NEXT: v_mad_f32 v0, v0, v1, -v2
; GFX9-DENORM-NEXT: ; return to shader part epilog
;
; GFX10-DENORM-LABEL: test_f16_to_f32_sub_ext_neg_mul:
; GFX10-DENORM: ; %bb.0: ; %entry
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e64 v1, -v1
; GFX10-DENORM-NEXT: v_fma_f32 v0, v0, v1, -v2
; GFX10-DENORM-NEXT: ; return to shader part epilog
entry:
%a = fmul fast half %x, %y
%b = fneg half %a
%c = fpext half %b to float
%d = fsub fast float %c, %z
ret float %d
}

; fold (fsub (fneg (fpext (fmul, x, y))), z) -> (fneg (fma (fpext x)), (fpext y), z)
define amdgpu_vs float @test_f16_to_f32_sub_neg_ext_mul(half %x, half %y, float %z) {
; GFX9-DENORM-LABEL: test_f16_to_f32_sub_neg_ext_mul:
; GFX9-DENORM: ; %bb.0: ; %entry
; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX9-DENORM-NEXT: v_cvt_f32_f16_e64 v1, -v1
; GFX9-DENORM-NEXT: v_mad_f32 v0, v0, v1, -v2
; GFX9-DENORM-NEXT: ; return to shader part epilog
;
; GFX10-DENORM-LABEL: test_f16_to_f32_sub_neg_ext_mul:
; GFX10-DENORM: ; %bb.0: ; %entry
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e64 v1, -v1
; GFX10-DENORM-NEXT: v_fma_f32 v0, v0, v1, -v2
; GFX10-DENORM-NEXT: ; return to shader part epilog
entry:
%a = fmul fast half %x, %y
%b = fpext half %a to float
%c = fneg float %b
%d = fsub fast float %c, %z
ret float %d
}


; fold (fsub x, (fpext (fneg (fmul y, z)))) -> (fma (fpext y), (fpext z), x)
define amdgpu_vs float @test_f16_to_f32_sub_ext_neg_mul2(float %x, half %y, half %z) {
; GFX9-DENORM-LABEL: test_f16_to_f32_sub_ext_neg_mul2:
; GFX9-DENORM: ; %bb.0: ; %entry
; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX9-DENORM-NEXT: v_cvt_f32_f16_e64 v2, -v2
; GFX9-DENORM-NEXT: v_mad_f32 v0, -v1, v2, v0
; GFX9-DENORM-NEXT: ; return to shader part epilog
;
; GFX10-DENORM-LABEL: test_f16_to_f32_sub_ext_neg_mul2:
; GFX10-DENORM: ; %bb.0: ; %entry
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e64 v2, -v2
; GFX10-DENORM-NEXT: v_fma_f32 v0, -v1, v2, v0
; GFX10-DENORM-NEXT: ; return to shader part epilog
entry:
%a = fmul fast half %y, %z
%b = fneg half %a
%c = fpext half %b to float
%d = fsub fast float %x, %c
ret float %d
}

; fold (fsub x, (fneg (fpext (fmul y, z)))) -> (fma (fpext y), (fpext z), x)
define amdgpu_vs float @test_f16_to_f32_sub_neg_ext_mul2(float %x, half %y, half %z) {
; GFX9-DENORM-LABEL: test_f16_to_f32_sub_neg_ext_mul2:
; GFX9-DENORM: ; %bb.0: ; %entry
; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX9-DENORM-NEXT: v_cvt_f32_f16_e64 v2, -v2
; GFX9-DENORM-NEXT: v_mad_f32 v0, -v1, v2, v0
; GFX9-DENORM-NEXT: ; return to shader part epilog
;
; GFX10-DENORM-LABEL: test_f16_to_f32_sub_neg_ext_mul2:
; GFX10-DENORM: ; %bb.0: ; %entry
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e64 v2, -v2
; GFX10-DENORM-NEXT: v_fma_f32 v0, -v1, v2, v0
; GFX10-DENORM-NEXT: ; return to shader part epilog
entry:
%a = fmul fast half %y, %z
%b = fpext half %a to float
%c = fneg float %b
%d = fsub fast float %x, %c
ret float %d
}

; fold (fsub (fpext (fneg (fmul, x, y))), z) -> (fneg (fma (fpext x), (fpext y), z))
define amdgpu_vs <4 x float> @test_v4f16_to_v4f32_sub_ext_neg_mul(<4 x half> %x, <4 x half> %y, <4 x float> %z) {
; GFX9-DENORM-LABEL: test_v4f16_to_v4f32_sub_ext_neg_mul:
; GFX9-DENORM: ; %bb.0: ; %entry
; GFX9-DENORM-NEXT: v_pk_mul_f16 v0, v0, v2 neg_lo:[0,1] neg_hi:[0,1]
; GFX9-DENORM-NEXT: v_pk_mul_f16 v1, v1, v3 neg_lo:[0,1] neg_hi:[0,1]
; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v2, v0
; GFX9-DENORM-NEXT: v_cvt_f32_f16_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v8, v1
; GFX9-DENORM-NEXT: v_cvt_f32_f16_sdwa v9, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX9-DENORM-NEXT: v_sub_f32_e32 v0, v2, v4
; GFX9-DENORM-NEXT: v_sub_f32_e32 v1, v3, v5
; GFX9-DENORM-NEXT: v_sub_f32_e32 v2, v8, v6
; GFX9-DENORM-NEXT: v_sub_f32_e32 v3, v9, v7
; GFX9-DENORM-NEXT: ; return to shader part epilog
;
; GFX10-DENORM-LABEL: test_v4f16_to_v4f32_sub_ext_neg_mul:
; GFX10-DENORM: ; %bb.0: ; %entry
; GFX10-DENORM-NEXT: s_mov_b32 s0, 0x80008000
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v8, v0
; GFX10-DENORM-NEXT: v_xor_b32_e32 v2, s0, v2
; GFX10-DENORM-NEXT: v_xor_b32_e32 v3, s0, v3
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v10, v1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v11, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v0, v2
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v2, v3
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_fma_f32 v0, v8, v0, -v4
; GFX10-DENORM-NEXT: v_fma_f32 v1, v9, v1, -v5
; GFX10-DENORM-NEXT: v_fma_f32 v2, v10, v2, -v6
; GFX10-DENORM-NEXT: v_fma_f32 v3, v11, v3, -v7
; GFX10-DENORM-NEXT: ; return to shader part epilog
entry:
%a = fmul fast <4 x half> %x, %y
%b = fneg <4 x half> %a
%c = fpext <4 x half> %b to <4 x float>
%d = fsub fast <4 x float> %c, %z
ret <4 x float> %d
}

; fold (fsub (fneg (fpext (fmul, x, y))), z) -> (fneg (fma (fpext x)), (fpext y), z)
define amdgpu_vs <4 x float> @test_v4f16_to_v4f32_sub_neg_ext_mul(<4 x half> %x, <4 x half> %y, <4 x float> %z) {
; GFX9-DENORM-LABEL: test_v4f16_to_v4f32_sub_neg_ext_mul:
; GFX9-DENORM: ; %bb.0: ; %entry
; GFX9-DENORM-NEXT: v_pk_mul_f16 v0, v0, v2 neg_lo:[0,1] neg_hi:[0,1]
; GFX9-DENORM-NEXT: v_pk_mul_f16 v1, v1, v3 neg_lo:[0,1] neg_hi:[0,1]
; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v2, v0
; GFX9-DENORM-NEXT: v_cvt_f32_f16_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v8, v1
; GFX9-DENORM-NEXT: v_cvt_f32_f16_sdwa v9, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX9-DENORM-NEXT: v_sub_f32_e32 v0, v2, v4
; GFX9-DENORM-NEXT: v_sub_f32_e32 v1, v3, v5
; GFX9-DENORM-NEXT: v_sub_f32_e32 v2, v8, v6
; GFX9-DENORM-NEXT: v_sub_f32_e32 v3, v9, v7
; GFX9-DENORM-NEXT: ; return to shader part epilog
;
; GFX10-DENORM-LABEL: test_v4f16_to_v4f32_sub_neg_ext_mul:
; GFX10-DENORM: ; %bb.0: ; %entry
; GFX10-DENORM-NEXT: s_mov_b32 s0, 0x80008000
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v8, v0
; GFX10-DENORM-NEXT: v_xor_b32_e32 v2, s0, v2
; GFX10-DENORM-NEXT: v_xor_b32_e32 v3, s0, v3
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v10, v1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v11, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v0, v2
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v2, v3
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_fma_f32 v0, v8, v0, -v4
; GFX10-DENORM-NEXT: v_fma_f32 v1, v9, v1, -v5
; GFX10-DENORM-NEXT: v_fma_f32 v2, v10, v2, -v6
; GFX10-DENORM-NEXT: v_fma_f32 v3, v11, v3, -v7
; GFX10-DENORM-NEXT: ; return to shader part epilog
entry:
%a = fmul fast <4 x half> %x, %y
%b = fpext <4 x half> %a to <4 x float>
%c = fneg <4 x float> %b
%d = fsub fast <4 x float> %c, %z
ret <4 x float> %d
}


; fold (fsub x, (fpext (fneg (fmul y, z)))) -> (fma (fpext y), (fpext z), x)
define amdgpu_vs <4 x float> @test_v4f16_to_v4f32_sub_ext_neg_mul2(<4 x float> %x, <4 x half> %y, <4 x half> %z) {
; GFX9-DENORM-LABEL: test_v4f16_to_v4f32_sub_ext_neg_mul2:
; GFX9-DENORM: ; %bb.0: ; %entry
; GFX9-DENORM-NEXT: v_pk_mul_f16 v4, v4, v6 neg_lo:[0,1] neg_hi:[0,1]
; GFX9-DENORM-NEXT: v_pk_mul_f16 v5, v5, v7 neg_lo:[0,1] neg_hi:[0,1]
; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v6, v4
; GFX9-DENORM-NEXT: v_cvt_f32_f16_sdwa v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v7, v5
; GFX9-DENORM-NEXT: v_cvt_f32_f16_sdwa v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX9-DENORM-NEXT: v_sub_f32_e32 v0, v0, v6
; GFX9-DENORM-NEXT: v_sub_f32_e32 v1, v1, v4
; GFX9-DENORM-NEXT: v_sub_f32_e32 v2, v2, v7
; GFX9-DENORM-NEXT: v_sub_f32_e32 v3, v3, v5
; GFX9-DENORM-NEXT: ; return to shader part epilog
;
; GFX10-DENORM-LABEL: test_v4f16_to_v4f32_sub_ext_neg_mul2:
; GFX10-DENORM: ; %bb.0: ; %entry
; GFX10-DENORM-NEXT: s_mov_b32 s0, 0x80008000
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v8, v4
; GFX10-DENORM-NEXT: v_xor_b32_e32 v6, s0, v6
; GFX10-DENORM-NEXT: v_xor_b32_e32 v7, s0, v7
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v9, v5
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v10, v6
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v6, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v11, v7
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v7, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_fma_f32 v0, -v8, v10, v0
; GFX10-DENORM-NEXT: v_fma_f32 v1, -v4, v6, v1
; GFX10-DENORM-NEXT: v_fma_f32 v2, -v9, v11, v2
; GFX10-DENORM-NEXT: v_fma_f32 v3, -v5, v7, v3
; GFX10-DENORM-NEXT: ; return to shader part epilog
entry:
%a = fmul fast <4 x half> %y, %z
%b = fneg <4 x half> %a
%c = fpext <4 x half> %b to <4 x float>
%d = fsub fast <4 x float> %x, %c
ret <4 x float> %d
}

; fold (fsub x, (fneg (fpext (fmul y, z)))) -> (fma (fpext y), (fpext z), x)
define amdgpu_vs <4 x float> @test_v4f16_to_v4f32_sub_neg_ext_mul2(<4 x float> %x, <4 x half> %y, <4 x half> %z) {
; GFX9-DENORM-LABEL: test_v4f16_to_v4f32_sub_neg_ext_mul2:
; GFX9-DENORM: ; %bb.0: ; %entry
; GFX9-DENORM-NEXT: v_pk_mul_f16 v4, v4, v6 neg_lo:[0,1] neg_hi:[0,1]
; GFX9-DENORM-NEXT: v_pk_mul_f16 v5, v5, v7 neg_lo:[0,1] neg_hi:[0,1]
; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v6, v4
; GFX9-DENORM-NEXT: v_cvt_f32_f16_sdwa v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v7, v5
; GFX9-DENORM-NEXT: v_cvt_f32_f16_sdwa v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX9-DENORM-NEXT: v_sub_f32_e32 v0, v0, v6
; GFX9-DENORM-NEXT: v_sub_f32_e32 v1, v1, v4
; GFX9-DENORM-NEXT: v_sub_f32_e32 v2, v2, v7
; GFX9-DENORM-NEXT: v_sub_f32_e32 v3, v3, v5
; GFX9-DENORM-NEXT: ; return to shader part epilog
;
; GFX10-DENORM-LABEL: test_v4f16_to_v4f32_sub_neg_ext_mul2:
; GFX10-DENORM: ; %bb.0: ; %entry
; GFX10-DENORM-NEXT: s_mov_b32 s0, 0x80008000
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v8, v4
; GFX10-DENORM-NEXT: v_xor_b32_e32 v6, s0, v6
; GFX10-DENORM-NEXT: v_xor_b32_e32 v7, s0, v7
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v9, v5
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v10, v6
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v6, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v11, v7
; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v7, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-DENORM-NEXT: v_fma_f32 v0, -v8, v10, v0
; GFX10-DENORM-NEXT: v_fma_f32 v1, -v4, v6, v1
; GFX10-DENORM-NEXT: v_fma_f32 v2, -v9, v11, v2
; GFX10-DENORM-NEXT: v_fma_f32 v3, -v5, v7, v3
; GFX10-DENORM-NEXT: ; return to shader part epilog
entry:
%a = fmul fast <4 x half> %y, %z
%b = fpext <4 x half> %a to <4 x float>
%c = fneg <4 x float> %b
%d = fsub fast <4 x float> %x, %c
ret <4 x float> %d
}
760 changes: 760 additions & 0 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-mul.ll
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394 changes: 394 additions & 0 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-neg-mul.ll
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