25 changes: 10 additions & 15 deletions llvm/test/CodeGen/RISCV/imm.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -321,9 +321,8 @@ define i64 @imm_left_shifted_lui_1() nounwind {
;
; RV64I-LABEL: imm_left_shifted_lui_1:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a0, 64
; RV64I-NEXT: addiw a0, a0, 1
; RV64I-NEXT: slli a0, a0, 13
; RV64I-NEXT: lui a0, 262145
; RV64I-NEXT: slli a0, a0, 1
; RV64I-NEXT: ret
ret i64 2147491840 ; 0x8000_2000
}
Expand All @@ -337,9 +336,8 @@ define i64 @imm_left_shifted_lui_2() nounwind {
;
; RV64I-LABEL: imm_left_shifted_lui_2:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a0, 64
; RV64I-NEXT: addiw a0, a0, 1
; RV64I-NEXT: slli a0, a0, 14
; RV64I-NEXT: lui a0, 262145
; RV64I-NEXT: slli a0, a0, 2
; RV64I-NEXT: ret
ret i64 4294983680 ; 0x1_0000_4000
}
Expand All @@ -354,9 +352,8 @@ define i64 @imm_left_shifted_lui_3() nounwind {
;
; RV64I-LABEL: imm_left_shifted_lui_3:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a0, 1
; RV64I-NEXT: addiw a0, a0, 1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: lui a0, 4097
; RV64I-NEXT: slli a0, a0, 20
; RV64I-NEXT: ret
ret i64 17596481011712 ; 0x1001_0000_0000
}
Expand Down Expand Up @@ -391,10 +388,9 @@ define i64 @imm_right_shifted_lui_2() nounwind {
;
; RV64I-LABEL: imm_right_shifted_lui_2:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a0, 65536
; RV64I-NEXT: addiw a0, a0, -1
; RV64I-NEXT: lui a0, 1044481
; RV64I-NEXT: slli a0, a0, 12
; RV64I-NEXT: addi a0, a0, 1
; RV64I-NEXT: srli a0, a0, 24
; RV64I-NEXT: ret
ret i64 1099511623681 ; 0xFF_FFFF_F001
}
Expand All @@ -411,9 +407,8 @@ define i64 @imm_decoupled_lui_addi() nounwind {
;
; RV64I-LABEL: imm_decoupled_lui_addi:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a0, 1
; RV64I-NEXT: addiw a0, a0, 1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: lui a0, 4097
; RV64I-NEXT: slli a0, a0, 20
; RV64I-NEXT: addi a0, a0, -3
; RV64I-NEXT: ret
ret i64 17596481011709 ; 0x1000_FFFF_FFFD
Expand Down
10 changes: 4 additions & 6 deletions llvm/test/CodeGen/RISCV/rv64-large-stack.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -9,16 +9,14 @@ define void @foo() nounwind {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -2032
; CHECK-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill
; CHECK-NEXT: lui a0, 95
; CHECK-NEXT: addiw a0, a0, 1505
; CHECK-NEXT: slli a0, a0, 13
; CHECK-NEXT: lui a0, 390625
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -2000
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: call baz@plt
; CHECK-NEXT: lui a0, 95
; CHECK-NEXT: addiw a0, a0, 1505
; CHECK-NEXT: slli a0, a0, 13
; CHECK-NEXT: lui a0, 390625
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -2000
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
Expand Down
51 changes: 24 additions & 27 deletions llvm/test/CodeGen/RISCV/rv64zbp.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -930,14 +930,13 @@ define i64 @gorc16_i64(i64 %a) nounwind {
; RV64I-LABEL: gorc16_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a1, a0, 16
; RV64I-NEXT: lui a2, 1048560
; RV64I-NEXT: addiw a2, a2, 1
; RV64I-NEXT: slli a3, a2, 16
; RV64I-NEXT: lui a2, 983041
; RV64I-NEXT: slli a3, a2, 4
; RV64I-NEXT: addi a3, a3, -1
; RV64I-NEXT: slli a3, a3, 16
; RV64I-NEXT: and a1, a1, a3
; RV64I-NEXT: srli a3, a0, 16
; RV64I-NEXT: slli a2, a2, 32
; RV64I-NEXT: slli a2, a2, 20
; RV64I-NEXT: addi a2, a2, -1
; RV64I-NEXT: srli a2, a2, 16
; RV64I-NEXT: and a2, a3, a2
Expand Down Expand Up @@ -2160,14 +2159,13 @@ define i64 @grev16_i64(i64 %a) nounwind {
; RV64I-LABEL: grev16_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a1, a0, 16
; RV64I-NEXT: lui a2, 1048560
; RV64I-NEXT: addiw a2, a2, 1
; RV64I-NEXT: slli a3, a2, 16
; RV64I-NEXT: lui a2, 983041
; RV64I-NEXT: slli a3, a2, 4
; RV64I-NEXT: addi a3, a3, -1
; RV64I-NEXT: slli a3, a3, 16
; RV64I-NEXT: and a1, a1, a3
; RV64I-NEXT: srli a0, a0, 16
; RV64I-NEXT: slli a2, a2, 32
; RV64I-NEXT: slli a2, a2, 20
; RV64I-NEXT: addi a2, a2, -1
; RV64I-NEXT: srli a2, a2, 16
; RV64I-NEXT: and a0, a0, a2
Expand Down Expand Up @@ -3534,9 +3532,8 @@ define i64 @shfl2_i64(i64 %a, i64 %b) nounwind {
; RV64I-NEXT: addi a1, a1, 963
; RV64I-NEXT: and a1, a0, a1
; RV64I-NEXT: slli a2, a0, 2
; RV64I-NEXT: lui a3, 48
; RV64I-NEXT: addiw a3, a3, 771
; RV64I-NEXT: slli a3, a3, 16
; RV64I-NEXT: lui a3, 197379
; RV64I-NEXT: slli a3, a3, 4
; RV64I-NEXT: addi a3, a3, 771
; RV64I-NEXT: slli a4, a3, 16
; RV64I-NEXT: addi a4, a4, 771
Expand Down Expand Up @@ -3612,26 +3609,28 @@ define signext i32 @shfl4_i32(i32 signext %a, i32 signext %b) nounwind {
define i64 @shfl4_i64(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: shfl4_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1048560
; RV64I-NEXT: addiw a1, a1, 255
; RV64I-NEXT: slli a1, a1, 16
; RV64I-NEXT: lui a1, 983295
; RV64I-NEXT: slli a1, a1, 4
; RV64I-NEXT: addi a1, a1, 255
; RV64I-NEXT: slli a1, a1, 16
; RV64I-NEXT: addi a1, a1, 255
; RV64I-NEXT: slli a1, a1, 12
; RV64I-NEXT: addi a1, a1, 15
; RV64I-NEXT: and a1, a0, a1
; RV64I-NEXT: slli a2, a0, 4
; RV64I-NEXT: lui a3, 983055
; RV64I-NEXT: slli a3, a3, 4
; RV64I-NEXT: addi a3, a3, 15
; RV64I-NEXT: slli a3, a3, 16
; RV64I-NEXT: addi a3, a3, 15
; RV64I-NEXT: slli a3, a3, 12
; RV64I-NEXT: srli a3, a3, 4
; RV64I-NEXT: and a2, a2, a3
; RV64I-NEXT: srli a0, a0, 4
; RV64I-NEXT: lui a3, 240
; RV64I-NEXT: addiw a3, a3, 15
; RV64I-NEXT: slli a3, a3, 16
; RV64I-NEXT: addi a3, a3, 15
; RV64I-NEXT: slli a4, a3, 12
; RV64I-NEXT: addi a4, a4, 1
; RV64I-NEXT: slli a4, a4, 12
; RV64I-NEXT: addi a4, a4, -256
; RV64I-NEXT: and a2, a2, a4
; RV64I-NEXT: srli a0, a0, 4
; RV64I-NEXT: slli a3, a3, 20
; RV64I-NEXT: addi a3, a3, 240
; RV64I-NEXT: and a0, a0, a3
Expand Down Expand Up @@ -3697,9 +3696,8 @@ define signext i32 @shfl8_i32(i32 signext %a, i32 signext %b) nounwind {
define i64 @shfl8_i64(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: shfl8_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1048560
; RV64I-NEXT: addiw a1, a1, 1
; RV64I-NEXT: slli a1, a1, 16
; RV64I-NEXT: lui a1, 983041
; RV64I-NEXT: slli a1, a1, 4
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: slli a1, a1, 24
; RV64I-NEXT: addi a1, a1, 255
Expand Down Expand Up @@ -3749,13 +3747,12 @@ define i64 @shfl16(i64 %a, i64 %b) nounwind {
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: and a1, a0, a1
; RV64I-NEXT: slli a2, a0, 16
; RV64I-NEXT: lui a3, 16
; RV64I-NEXT: addiw a3, a3, -1
; RV64I-NEXT: slli a4, a3, 32
; RV64I-NEXT: lui a3, 65535
; RV64I-NEXT: slli a4, a3, 20
; RV64I-NEXT: and a2, a2, a4
; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: srli a0, a0, 16
; RV64I-NEXT: slli a2, a3, 16
; RV64I-NEXT: slli a2, a3, 4
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
Expand Down
5 changes: 2 additions & 3 deletions llvm/test/CodeGen/RISCV/rvv/constant-folding.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -28,9 +28,8 @@ define <2 x i16> @fixedlen(<2 x i32> %x) {
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV64-NEXT: vsrl.vi v25, v8, 16
; RV64-NEXT: lui a0, 32
; RV64-NEXT: addiw a0, a0, -1
; RV64-NEXT: slli a0, a0, 15
; RV64-NEXT: lui a0, 131071
; RV64-NEXT: slli a0, a0, 3
; RV64-NEXT: vand.vx v25, v25, a0
; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; RV64-NEXT: vnsrl.wi v8, v25, 0
Expand Down
5 changes: 2 additions & 3 deletions llvm/test/CodeGen/RISCV/urem-lkk.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -104,9 +104,8 @@ define i32 @fold_urem_positive_even(i32 %x) nounwind {
; RV64IM: # %bb.0:
; RV64IM-NEXT: slli a1, a0, 32
; RV64IM-NEXT: srli a1, a1, 32
; RV64IM-NEXT: lui a2, 62
; RV64IM-NEXT: addiw a2, a2, -711
; RV64IM-NEXT: slli a2, a2, 14
; RV64IM-NEXT: lui a2, 253241
; RV64IM-NEXT: slli a2, a2, 2
; RV64IM-NEXT: addi a2, a2, -61
; RV64IM-NEXT: mul a1, a1, a2
; RV64IM-NEXT: srli a1, a1, 42
Expand Down
25 changes: 10 additions & 15 deletions llvm/test/MC/RISCV/rv64i-aliases-valid.s
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Original file line number Diff line number Diff line change
Expand Up @@ -106,29 +106,24 @@ li t3, 0x700000000B00000F
li t4, 0x123456789abcdef0
# CHECK-EXPAND: addi t5, zero, -1
li t5, 0xFFFFFFFFFFFFFFFF
# CHECK-EXPAND: lui t6, 64
# CHECK-EXPAND-NEXT: addiw t6, t6, 1
# CHECK-EXPAND-NEXT: slli t6, t6, 13
# CHECK-EXPAND: lui t6, 262145
# CHECK-EXPAND-NEXT: slli t6, t6, 1
li t6, 0x80002000
# CHECK-EXPAND: lui t0, 64
# CHECK-EXPAND-NEXT: addiw t0, t0, 1
# CHECK-EXPAND-NEXT: slli t0, t0, 14
# CHECK-EXPAND: lui t0, 262145
# CHECK-EXPAND-NEXT: slli t0, t0, 2
li x5, 0x100004000
# CHECK-EXPAND: lui t1, 1
# CHECK-EXPAND-NEXT: addiw t1, t1, 1
# CHECK-EXPAND-NEXT: slli t1, t1, 32
# CHECK-EXPAND: lui t1, 4097
# CHECK-EXPAND-NEXT: slli t1, t1, 20
li x6, 0x100100000000
# CHECK-EXPAND: lui t2, 983056
# CHECK-EXPAND-NEXT: srli t2, t2, 16
li x7, 0xFFFFFFFFF001
# CHECK-EXPAND: lui s0, 65536
# CHECK-EXPAND-NEXT: addiw s0, s0, -1
# CHECK-EXPAND: lui s0, 1044481
# CHECK-EXPAND-NEXT: slli s0, s0, 12
# CHECK-EXPAND-NEXT: addi s0, s0, 1
# CHECK-EXPAND-NEXT: srli s0, s0, 24
li x8, 0xFFFFFFF001
# CHECK-EXPAND: lui s1, 1
# CHECK-EXPAND-NEXT: addiw s1, s1, 1
# CHECK-EXPAND-NEXT: slli s1, s1, 32
# CHECK-EXPAND: lui s1, 4097
# CHECK-EXPAND-NEXT: slli s1, s1, 20
# CHECK-EXPAND-NEXT: addi s1, s1, -3
li x9, 0x1000FFFFFFFD
# CHECK-EXPAND: addi a0, zero, -1
Expand Down