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@@ -160,8 +160,8 @@ static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
const void *Decoder);
static DecodeStatus DecodeAdrInstruction (MCInst &Inst, uint32_t insn,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeBaseAddSubImm (MCInst &Inst, uint32_t insn,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeAddSubImmShift (MCInst &Inst, uint32_t insn,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeUnconditionalBranch (MCInst &Inst, uint32_t insn,
uint64_t Address,
const void *Decoder);
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@@ -220,6 +220,11 @@ static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm,
static DecodeStatus DecodeSVEIncDecImm (MCInst &Inst, unsigned Imm,
uint64_t Addr, const void *Decoder);
static DecodeStatus DecodeLoadAllocTagArrayInstruction (MCInst &Inst,
uint32_t insn,
uint64_t address,
const void * Decoder);
static bool Check (DecodeStatus &Out, DecodeStatus In) {
switch (In) {
case MCDisassembler::Success:
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@@ -1403,6 +1408,8 @@ static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
case AArch64::STPSpost:
case AArch64::LDPSpre:
case AArch64::STPSpre:
case AArch64::STGPpre:
case AArch64::STGPpost:
DecodeGPR64spRegisterClass (Inst, Rn, Addr, Decoder);
break ;
}
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@@ -1416,13 +1423,16 @@ static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
case AArch64::LDPXpre:
case AArch64::STPXpre:
case AArch64::LDPSWpre:
case AArch64::STGPpre:
case AArch64::STGPpost:
NeedsDisjointWritebackTransfer = true ;
LLVM_FALLTHROUGH;
case AArch64::LDNPXi:
case AArch64::STNPXi:
case AArch64::LDPXi:
case AArch64::STPXi:
case AArch64::LDPSWi:
case AArch64::STGPi:
DecodeGPR64RegisterClass (Inst, Rt, Addr, Decoder);
DecodeGPR64RegisterClass (Inst, Rt2, Addr, Decoder);
break ;
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@@ -1653,8 +1663,8 @@ static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
return Success;
}
static DecodeStatus DecodeBaseAddSubImm (MCInst &Inst, uint32_t insn,
uint64_t Addr, const void *Decoder) {
static DecodeStatus DecodeAddSubImmShift (MCInst &Inst, uint32_t insn,
uint64_t Addr, const void *Decoder) {
unsigned Rd = fieldFromInstruction (insn, 0 , 5 );
unsigned Rn = fieldFromInstruction (insn, 5 , 5 );
unsigned Imm = fieldFromInstruction (insn, 10 , 14 );
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@@ -1842,3 +1852,25 @@ static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
Inst.addOperand (MCOperand::createImm (Imm + 1 ));
return Success;
}
static DecodeStatus DecodeLoadAllocTagArrayInstruction (MCInst &Inst,
uint32_t insn,
uint64_t address,
const void * Decoder) {
unsigned Rn = fieldFromInstruction (insn, 5 , 5 );
unsigned Rt = fieldFromInstruction (insn, 0 , 5 );
// Outputs
DecodeGPR64spRegisterClass (Inst, Rn, address, Decoder);
DecodeGPR64RegisterClass (Inst, Rt, address, Decoder);
// Input (Rn again)
Inst.addOperand (Inst.getOperand (0 ));
// Do this post decode since the raw number for xzr and sp is the same
if (Inst.getOperand (0 ).getReg () == Inst.getOperand (1 ).getReg ()) {
return SoftFail;
} else {
return Success;
}
}