132 changes: 66 additions & 66 deletions llvm/test/CodeGen/RISCV/half-convert.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -210,12 +210,12 @@ define i16 @fcvt_si_h_sat(half %a) nounwind {
; RV64IZFH: # %bb.0: # %start
; RV64IZFH-NEXT: fcvt.s.h fa5, fa0
; RV64IZFH-NEXT: feq.s a0, fa5, fa5
; RV64IZFH-NEXT: neg a0, a0
; RV64IZFH-NEXT: lui a1, %hi(.LCPI1_0)
; RV64IZFH-NEXT: flw fa4, %lo(.LCPI1_0)(a1)
; RV64IZFH-NEXT: lui a1, 815104
; RV64IZFH-NEXT: fmv.w.x fa3, a1
; RV64IZFH-NEXT: fmax.s fa5, fa5, fa3
; RV64IZFH-NEXT: neg a0, a0
; RV64IZFH-NEXT: fmin.s fa5, fa5, fa4
; RV64IZFH-NEXT: fcvt.l.s a1, fa5, rtz
; RV64IZFH-NEXT: and a0, a0, a1
Expand All @@ -240,12 +240,12 @@ define i16 @fcvt_si_h_sat(half %a) nounwind {
; RV64IDZFH: # %bb.0: # %start
; RV64IDZFH-NEXT: fcvt.s.h fa5, fa0
; RV64IDZFH-NEXT: feq.s a0, fa5, fa5
; RV64IDZFH-NEXT: neg a0, a0
; RV64IDZFH-NEXT: lui a1, %hi(.LCPI1_0)
; RV64IDZFH-NEXT: flw fa4, %lo(.LCPI1_0)(a1)
; RV64IDZFH-NEXT: lui a1, 815104
; RV64IDZFH-NEXT: fmv.w.x fa3, a1
; RV64IDZFH-NEXT: fmax.s fa5, fa5, fa3
; RV64IDZFH-NEXT: neg a0, a0
; RV64IDZFH-NEXT: fmin.s fa5, fa5, fa4
; RV64IDZFH-NEXT: fcvt.l.s a1, fa5, rtz
; RV64IDZFH-NEXT: and a0, a0, a1
Expand All @@ -268,15 +268,15 @@ define i16 @fcvt_si_h_sat(half %a) nounwind {
; RV64IZHINX-LABEL: fcvt_si_h_sat:
; RV64IZHINX: # %bb.0: # %start
; RV64IZHINX-NEXT: fcvt.s.h a0, a0
; RV64IZHINX-NEXT: lui a1, 815104
; RV64IZHINX-NEXT: feq.s a1, a0, a0
; RV64IZHINX-NEXT: lui a2, %hi(.LCPI1_0)
; RV64IZHINX-NEXT: lw a2, %lo(.LCPI1_0)(a2)
; RV64IZHINX-NEXT: fmax.s a1, a0, a1
; RV64IZHINX-NEXT: feq.s a0, a0, a0
; RV64IZHINX-NEXT: neg a0, a0
; RV64IZHINX-NEXT: fmin.s a1, a1, a2
; RV64IZHINX-NEXT: fcvt.l.s a1, a1, rtz
; RV64IZHINX-NEXT: and a0, a0, a1
; RV64IZHINX-NEXT: neg a1, a1
; RV64IZHINX-NEXT: lui a3, 815104
; RV64IZHINX-NEXT: fmax.s a0, a0, a3
; RV64IZHINX-NEXT: fmin.s a0, a0, a2
; RV64IZHINX-NEXT: fcvt.l.s a0, a0, rtz
; RV64IZHINX-NEXT: and a0, a1, a0
; RV64IZHINX-NEXT: ret
;
; RV32IZDINXZHINX-LABEL: fcvt_si_h_sat:
Expand All @@ -296,15 +296,15 @@ define i16 @fcvt_si_h_sat(half %a) nounwind {
; RV64IZDINXZHINX-LABEL: fcvt_si_h_sat:
; RV64IZDINXZHINX: # %bb.0: # %start
; RV64IZDINXZHINX-NEXT: fcvt.s.h a0, a0
; RV64IZDINXZHINX-NEXT: lui a1, 815104
; RV64IZDINXZHINX-NEXT: feq.s a1, a0, a0
; RV64IZDINXZHINX-NEXT: lui a2, %hi(.LCPI1_0)
; RV64IZDINXZHINX-NEXT: lw a2, %lo(.LCPI1_0)(a2)
; RV64IZDINXZHINX-NEXT: fmax.s a1, a0, a1
; RV64IZDINXZHINX-NEXT: feq.s a0, a0, a0
; RV64IZDINXZHINX-NEXT: neg a0, a0
; RV64IZDINXZHINX-NEXT: fmin.s a1, a1, a2
; RV64IZDINXZHINX-NEXT: fcvt.l.s a1, a1, rtz
; RV64IZDINXZHINX-NEXT: and a0, a0, a1
; RV64IZDINXZHINX-NEXT: neg a1, a1
; RV64IZDINXZHINX-NEXT: lui a3, 815104
; RV64IZDINXZHINX-NEXT: fmax.s a0, a0, a3
; RV64IZDINXZHINX-NEXT: fmin.s a0, a0, a2
; RV64IZDINXZHINX-NEXT: fcvt.l.s a0, a0, rtz
; RV64IZDINXZHINX-NEXT: and a0, a1, a0
; RV64IZDINXZHINX-NEXT: ret
;
; RV32I-LABEL: fcvt_si_h_sat:
Expand Down Expand Up @@ -420,12 +420,12 @@ define i16 @fcvt_si_h_sat(half %a) nounwind {
; RV64ID-LP64-NEXT: call __extendhfsf2
; RV64ID-LP64-NEXT: fmv.w.x fa5, a0
; RV64ID-LP64-NEXT: feq.s a0, fa5, fa5
; RV64ID-LP64-NEXT: neg a0, a0
; RV64ID-LP64-NEXT: lui a1, %hi(.LCPI1_0)
; RV64ID-LP64-NEXT: flw fa4, %lo(.LCPI1_0)(a1)
; RV64ID-LP64-NEXT: lui a1, 815104
; RV64ID-LP64-NEXT: fmv.w.x fa3, a1
; RV64ID-LP64-NEXT: fmax.s fa5, fa5, fa3
; RV64ID-LP64-NEXT: neg a0, a0
; RV64ID-LP64-NEXT: fmin.s fa5, fa5, fa4
; RV64ID-LP64-NEXT: fcvt.l.s a1, fa5, rtz
; RV64ID-LP64-NEXT: and a0, a0, a1
Expand Down Expand Up @@ -458,12 +458,12 @@ define i16 @fcvt_si_h_sat(half %a) nounwind {
; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64ID-NEXT: call __extendhfsf2
; RV64ID-NEXT: feq.s a0, fa0, fa0
; RV64ID-NEXT: neg a0, a0
; RV64ID-NEXT: lui a1, %hi(.LCPI1_0)
; RV64ID-NEXT: flw fa5, %lo(.LCPI1_0)(a1)
; RV64ID-NEXT: lui a1, 815104
; RV64ID-NEXT: fmv.w.x fa4, a1
; RV64ID-NEXT: fmax.s fa4, fa0, fa4
; RV64ID-NEXT: neg a0, a0
; RV64ID-NEXT: fmin.s fa5, fa4, fa5
; RV64ID-NEXT: fcvt.l.s a1, fa5, rtz
; RV64ID-NEXT: and a0, a0, a1
Expand All @@ -490,12 +490,12 @@ define i16 @fcvt_si_h_sat(half %a) nounwind {
; CHECK64-IZFHMIN: # %bb.0: # %start
; CHECK64-IZFHMIN-NEXT: fcvt.s.h fa5, fa0
; CHECK64-IZFHMIN-NEXT: feq.s a0, fa5, fa5
; CHECK64-IZFHMIN-NEXT: neg a0, a0
; CHECK64-IZFHMIN-NEXT: lui a1, %hi(.LCPI1_0)
; CHECK64-IZFHMIN-NEXT: flw fa4, %lo(.LCPI1_0)(a1)
; CHECK64-IZFHMIN-NEXT: lui a1, 815104
; CHECK64-IZFHMIN-NEXT: fmv.w.x fa3, a1
; CHECK64-IZFHMIN-NEXT: fmax.s fa5, fa5, fa3
; CHECK64-IZFHMIN-NEXT: neg a0, a0
; CHECK64-IZFHMIN-NEXT: fmin.s fa5, fa5, fa4
; CHECK64-IZFHMIN-NEXT: fcvt.l.s a1, fa5, rtz
; CHECK64-IZFHMIN-NEXT: and a0, a0, a1
Expand All @@ -518,15 +518,15 @@ define i16 @fcvt_si_h_sat(half %a) nounwind {
; CHECK64-IZHINXMIN-LABEL: fcvt_si_h_sat:
; CHECK64-IZHINXMIN: # %bb.0: # %start
; CHECK64-IZHINXMIN-NEXT: fcvt.s.h a0, a0
; CHECK64-IZHINXMIN-NEXT: lui a1, 815104
; CHECK64-IZHINXMIN-NEXT: feq.s a1, a0, a0
; CHECK64-IZHINXMIN-NEXT: lui a2, %hi(.LCPI1_0)
; CHECK64-IZHINXMIN-NEXT: lw a2, %lo(.LCPI1_0)(a2)
; CHECK64-IZHINXMIN-NEXT: fmax.s a1, a0, a1
; CHECK64-IZHINXMIN-NEXT: feq.s a0, a0, a0
; CHECK64-IZHINXMIN-NEXT: neg a0, a0
; CHECK64-IZHINXMIN-NEXT: fmin.s a1, a1, a2
; CHECK64-IZHINXMIN-NEXT: fcvt.l.s a1, a1, rtz
; CHECK64-IZHINXMIN-NEXT: and a0, a0, a1
; CHECK64-IZHINXMIN-NEXT: neg a1, a1
; CHECK64-IZHINXMIN-NEXT: lui a3, 815104
; CHECK64-IZHINXMIN-NEXT: fmax.s a0, a0, a3
; CHECK64-IZHINXMIN-NEXT: fmin.s a0, a0, a2
; CHECK64-IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
; CHECK64-IZHINXMIN-NEXT: and a0, a1, a0
; CHECK64-IZHINXMIN-NEXT: ret
;
; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_si_h_sat:
Expand All @@ -546,15 +546,15 @@ define i16 @fcvt_si_h_sat(half %a) nounwind {
; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_si_h_sat:
; CHECK64-IZDINXZHINXMIN: # %bb.0: # %start
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
; CHECK64-IZDINXZHINXMIN-NEXT: lui a1, 815104
; CHECK64-IZDINXZHINXMIN-NEXT: feq.s a1, a0, a0
; CHECK64-IZDINXZHINXMIN-NEXT: lui a2, %hi(.LCPI1_0)
; CHECK64-IZDINXZHINXMIN-NEXT: lw a2, %lo(.LCPI1_0)(a2)
; CHECK64-IZDINXZHINXMIN-NEXT: fmax.s a1, a0, a1
; CHECK64-IZDINXZHINXMIN-NEXT: feq.s a0, a0, a0
; CHECK64-IZDINXZHINXMIN-NEXT: neg a0, a0
; CHECK64-IZDINXZHINXMIN-NEXT: fmin.s a1, a1, a2
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.l.s a1, a1, rtz
; CHECK64-IZDINXZHINXMIN-NEXT: and a0, a0, a1
; CHECK64-IZDINXZHINXMIN-NEXT: neg a1, a1
; CHECK64-IZDINXZHINXMIN-NEXT: lui a3, 815104
; CHECK64-IZDINXZHINXMIN-NEXT: fmax.s a0, a0, a3
; CHECK64-IZDINXZHINXMIN-NEXT: fmin.s a0, a0, a2
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
; CHECK64-IZDINXZHINXMIN-NEXT: and a0, a1, a0
; CHECK64-IZDINXZHINXMIN-NEXT: ret
start:
%0 = tail call i16 @llvm.fptosi.sat.i16.f16(half %a)
Expand Down Expand Up @@ -6377,12 +6377,12 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind {
; RV64IZFH: # %bb.0: # %start
; RV64IZFH-NEXT: fcvt.s.h fa5, fa0
; RV64IZFH-NEXT: feq.s a0, fa5, fa5
; RV64IZFH-NEXT: neg a0, a0
; RV64IZFH-NEXT: lui a1, %hi(.LCPI32_0)
; RV64IZFH-NEXT: flw fa4, %lo(.LCPI32_0)(a1)
; RV64IZFH-NEXT: lui a1, 815104
; RV64IZFH-NEXT: fmv.w.x fa3, a1
; RV64IZFH-NEXT: fmax.s fa5, fa5, fa3
; RV64IZFH-NEXT: neg a0, a0
; RV64IZFH-NEXT: fmin.s fa5, fa5, fa4
; RV64IZFH-NEXT: fcvt.l.s a1, fa5, rtz
; RV64IZFH-NEXT: and a0, a0, a1
Expand All @@ -6407,12 +6407,12 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind {
; RV64IDZFH: # %bb.0: # %start
; RV64IDZFH-NEXT: fcvt.s.h fa5, fa0
; RV64IDZFH-NEXT: feq.s a0, fa5, fa5
; RV64IDZFH-NEXT: neg a0, a0
; RV64IDZFH-NEXT: lui a1, %hi(.LCPI32_0)
; RV64IDZFH-NEXT: flw fa4, %lo(.LCPI32_0)(a1)
; RV64IDZFH-NEXT: lui a1, 815104
; RV64IDZFH-NEXT: fmv.w.x fa3, a1
; RV64IDZFH-NEXT: fmax.s fa5, fa5, fa3
; RV64IDZFH-NEXT: neg a0, a0
; RV64IDZFH-NEXT: fmin.s fa5, fa5, fa4
; RV64IDZFH-NEXT: fcvt.l.s a1, fa5, rtz
; RV64IDZFH-NEXT: and a0, a0, a1
Expand All @@ -6435,15 +6435,15 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind {
; RV64IZHINX-LABEL: fcvt_w_s_sat_i16:
; RV64IZHINX: # %bb.0: # %start
; RV64IZHINX-NEXT: fcvt.s.h a0, a0
; RV64IZHINX-NEXT: lui a1, 815104
; RV64IZHINX-NEXT: feq.s a1, a0, a0
; RV64IZHINX-NEXT: lui a2, %hi(.LCPI32_0)
; RV64IZHINX-NEXT: lw a2, %lo(.LCPI32_0)(a2)
; RV64IZHINX-NEXT: fmax.s a1, a0, a1
; RV64IZHINX-NEXT: feq.s a0, a0, a0
; RV64IZHINX-NEXT: neg a0, a0
; RV64IZHINX-NEXT: fmin.s a1, a1, a2
; RV64IZHINX-NEXT: fcvt.l.s a1, a1, rtz
; RV64IZHINX-NEXT: and a0, a0, a1
; RV64IZHINX-NEXT: neg a1, a1
; RV64IZHINX-NEXT: lui a3, 815104
; RV64IZHINX-NEXT: fmax.s a0, a0, a3
; RV64IZHINX-NEXT: fmin.s a0, a0, a2
; RV64IZHINX-NEXT: fcvt.l.s a0, a0, rtz
; RV64IZHINX-NEXT: and a0, a1, a0
; RV64IZHINX-NEXT: ret
;
; RV32IZDINXZHINX-LABEL: fcvt_w_s_sat_i16:
Expand All @@ -6463,15 +6463,15 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind {
; RV64IZDINXZHINX-LABEL: fcvt_w_s_sat_i16:
; RV64IZDINXZHINX: # %bb.0: # %start
; RV64IZDINXZHINX-NEXT: fcvt.s.h a0, a0
; RV64IZDINXZHINX-NEXT: lui a1, 815104
; RV64IZDINXZHINX-NEXT: feq.s a1, a0, a0
; RV64IZDINXZHINX-NEXT: lui a2, %hi(.LCPI32_0)
; RV64IZDINXZHINX-NEXT: lw a2, %lo(.LCPI32_0)(a2)
; RV64IZDINXZHINX-NEXT: fmax.s a1, a0, a1
; RV64IZDINXZHINX-NEXT: feq.s a0, a0, a0
; RV64IZDINXZHINX-NEXT: neg a0, a0
; RV64IZDINXZHINX-NEXT: fmin.s a1, a1, a2
; RV64IZDINXZHINX-NEXT: fcvt.l.s a1, a1, rtz
; RV64IZDINXZHINX-NEXT: and a0, a0, a1
; RV64IZDINXZHINX-NEXT: neg a1, a1
; RV64IZDINXZHINX-NEXT: lui a3, 815104
; RV64IZDINXZHINX-NEXT: fmax.s a0, a0, a3
; RV64IZDINXZHINX-NEXT: fmin.s a0, a0, a2
; RV64IZDINXZHINX-NEXT: fcvt.l.s a0, a0, rtz
; RV64IZDINXZHINX-NEXT: and a0, a1, a0
; RV64IZDINXZHINX-NEXT: ret
;
; RV32I-LABEL: fcvt_w_s_sat_i16:
Expand Down Expand Up @@ -6591,12 +6591,12 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind {
; RV64ID-LP64-NEXT: call __extendhfsf2
; RV64ID-LP64-NEXT: fmv.w.x fa5, a0
; RV64ID-LP64-NEXT: feq.s a0, fa5, fa5
; RV64ID-LP64-NEXT: neg a0, a0
; RV64ID-LP64-NEXT: lui a1, %hi(.LCPI32_0)
; RV64ID-LP64-NEXT: flw fa4, %lo(.LCPI32_0)(a1)
; RV64ID-LP64-NEXT: lui a1, 815104
; RV64ID-LP64-NEXT: fmv.w.x fa3, a1
; RV64ID-LP64-NEXT: fmax.s fa5, fa5, fa3
; RV64ID-LP64-NEXT: neg a0, a0
; RV64ID-LP64-NEXT: fmin.s fa5, fa5, fa4
; RV64ID-LP64-NEXT: fcvt.l.s a1, fa5, rtz
; RV64ID-LP64-NEXT: and a0, a0, a1
Expand Down Expand Up @@ -6629,12 +6629,12 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind {
; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64ID-NEXT: call __extendhfsf2
; RV64ID-NEXT: feq.s a0, fa0, fa0
; RV64ID-NEXT: neg a0, a0
; RV64ID-NEXT: lui a1, %hi(.LCPI32_0)
; RV64ID-NEXT: flw fa5, %lo(.LCPI32_0)(a1)
; RV64ID-NEXT: lui a1, 815104
; RV64ID-NEXT: fmv.w.x fa4, a1
; RV64ID-NEXT: fmax.s fa4, fa0, fa4
; RV64ID-NEXT: neg a0, a0
; RV64ID-NEXT: fmin.s fa5, fa4, fa5
; RV64ID-NEXT: fcvt.l.s a1, fa5, rtz
; RV64ID-NEXT: and a0, a0, a1
Expand All @@ -6661,12 +6661,12 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind {
; CHECK64-IZFHMIN: # %bb.0: # %start
; CHECK64-IZFHMIN-NEXT: fcvt.s.h fa5, fa0
; CHECK64-IZFHMIN-NEXT: feq.s a0, fa5, fa5
; CHECK64-IZFHMIN-NEXT: neg a0, a0
; CHECK64-IZFHMIN-NEXT: lui a1, %hi(.LCPI32_0)
; CHECK64-IZFHMIN-NEXT: flw fa4, %lo(.LCPI32_0)(a1)
; CHECK64-IZFHMIN-NEXT: lui a1, 815104
; CHECK64-IZFHMIN-NEXT: fmv.w.x fa3, a1
; CHECK64-IZFHMIN-NEXT: fmax.s fa5, fa5, fa3
; CHECK64-IZFHMIN-NEXT: neg a0, a0
; CHECK64-IZFHMIN-NEXT: fmin.s fa5, fa5, fa4
; CHECK64-IZFHMIN-NEXT: fcvt.l.s a1, fa5, rtz
; CHECK64-IZFHMIN-NEXT: and a0, a0, a1
Expand All @@ -6689,15 +6689,15 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind {
; CHECK64-IZHINXMIN-LABEL: fcvt_w_s_sat_i16:
; CHECK64-IZHINXMIN: # %bb.0: # %start
; CHECK64-IZHINXMIN-NEXT: fcvt.s.h a0, a0
; CHECK64-IZHINXMIN-NEXT: lui a1, 815104
; CHECK64-IZHINXMIN-NEXT: feq.s a1, a0, a0
; CHECK64-IZHINXMIN-NEXT: lui a2, %hi(.LCPI32_0)
; CHECK64-IZHINXMIN-NEXT: lw a2, %lo(.LCPI32_0)(a2)
; CHECK64-IZHINXMIN-NEXT: fmax.s a1, a0, a1
; CHECK64-IZHINXMIN-NEXT: feq.s a0, a0, a0
; CHECK64-IZHINXMIN-NEXT: neg a0, a0
; CHECK64-IZHINXMIN-NEXT: fmin.s a1, a1, a2
; CHECK64-IZHINXMIN-NEXT: fcvt.l.s a1, a1, rtz
; CHECK64-IZHINXMIN-NEXT: and a0, a0, a1
; CHECK64-IZHINXMIN-NEXT: neg a1, a1
; CHECK64-IZHINXMIN-NEXT: lui a3, 815104
; CHECK64-IZHINXMIN-NEXT: fmax.s a0, a0, a3
; CHECK64-IZHINXMIN-NEXT: fmin.s a0, a0, a2
; CHECK64-IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
; CHECK64-IZHINXMIN-NEXT: and a0, a1, a0
; CHECK64-IZHINXMIN-NEXT: ret
;
; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_w_s_sat_i16:
Expand All @@ -6717,15 +6717,15 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind {
; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_w_s_sat_i16:
; CHECK64-IZDINXZHINXMIN: # %bb.0: # %start
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
; CHECK64-IZDINXZHINXMIN-NEXT: lui a1, 815104
; CHECK64-IZDINXZHINXMIN-NEXT: feq.s a1, a0, a0
; CHECK64-IZDINXZHINXMIN-NEXT: lui a2, %hi(.LCPI32_0)
; CHECK64-IZDINXZHINXMIN-NEXT: lw a2, %lo(.LCPI32_0)(a2)
; CHECK64-IZDINXZHINXMIN-NEXT: fmax.s a1, a0, a1
; CHECK64-IZDINXZHINXMIN-NEXT: feq.s a0, a0, a0
; CHECK64-IZDINXZHINXMIN-NEXT: neg a0, a0
; CHECK64-IZDINXZHINXMIN-NEXT: fmin.s a1, a1, a2
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.l.s a1, a1, rtz
; CHECK64-IZDINXZHINXMIN-NEXT: and a0, a0, a1
; CHECK64-IZDINXZHINXMIN-NEXT: neg a1, a1
; CHECK64-IZDINXZHINXMIN-NEXT: lui a3, 815104
; CHECK64-IZDINXZHINXMIN-NEXT: fmax.s a0, a0, a3
; CHECK64-IZDINXZHINXMIN-NEXT: fmin.s a0, a0, a2
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
; CHECK64-IZDINXZHINXMIN-NEXT: and a0, a1, a0
; CHECK64-IZDINXZHINXMIN-NEXT: ret
start:
%0 = tail call i16 @llvm.fptosi.sat.i16.f16(half %a)
Expand Down
46 changes: 17 additions & 29 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -125,35 +125,20 @@ define <4 x double> @vrgather_shuffle_xv_v4f64(<4 x double> %x) {
}

define <4 x double> @vrgather_shuffle_vx_v4f64(<4 x double> %x) {
; RV32-LABEL: vrgather_shuffle_vx_v4f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; RV32-NEXT: vid.v v12
; RV32-NEXT: li a0, 3
; RV32-NEXT: lui a1, %hi(.LCPI8_0)
; RV32-NEXT: addi a1, a1, %lo(.LCPI8_0)
; RV32-NEXT: vlse64.v v10, (a1), zero
; RV32-NEXT: vmul.vx v12, v12, a0
; RV32-NEXT: vmv.v.i v0, 3
; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu
; RV32-NEXT: vrgatherei16.vv v10, v8, v12, v0.t
; RV32-NEXT: vmv.v.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: vrgather_shuffle_vx_v4f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; RV64-NEXT: vid.v v12
; RV64-NEXT: lui a0, %hi(.LCPI8_0)
; RV64-NEXT: addi a0, a0, %lo(.LCPI8_0)
; RV64-NEXT: vlse64.v v10, (a0), zero
; RV64-NEXT: li a0, 3
; RV64-NEXT: vmul.vx v12, v12, a0
; RV64-NEXT: vmv.v.i v0, 3
; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, mu
; RV64-NEXT: vrgatherei16.vv v10, v8, v12, v0.t
; RV64-NEXT: vmv.v.v v8, v10
; RV64-NEXT: ret
; CHECK-LABEL: vrgather_shuffle_vx_v4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vid.v v12
; CHECK-NEXT: li a0, 3
; CHECK-NEXT: lui a1, %hi(.LCPI8_0)
; CHECK-NEXT: addi a1, a1, %lo(.LCPI8_0)
; CHECK-NEXT: vlse64.v v10, (a1), zero
; CHECK-NEXT: vmul.vx v12, v12, a0
; CHECK-NEXT: vmv.v.i v0, 3
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu
; CHECK-NEXT: vrgatherei16.vv v10, v8, v12, v0.t
; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret
%s = shufflevector <4 x double> %x, <4 x double> <double 2.0, double 2.0, double 2.0, double 2.0>, <4 x i32> <i32 0, i32 3, i32 6, i32 5>
ret <4 x double> %s
}
Expand Down Expand Up @@ -279,3 +264,6 @@ define <8 x double> @splice_binary2(<8 x double> %x, <8 x double> %y) {
%s = shufflevector <8 x double> %x, <8 x double> %y, <8 x i32> <i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4>
ret <8 x double> %s
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; RV32: {{.*}}
; RV64: {{.*}}
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -774,9 +774,9 @@ define void @insert_v2i64_nxv16i64_hi(ptr %psv, ptr %out) {
; RV64VLS-NEXT: vl1re64.v v8, (a0)
; RV64VLS-NEXT: addi a0, sp, 128
; RV64VLS-NEXT: vs1r.v v8, (a0)
; RV64VLS-NEXT: addi a0, sp, 192
; RV64VLS-NEXT: vl8re64.v v8, (a0)
; RV64VLS-NEXT: addi a0, sp, 64
; RV64VLS-NEXT: addi a2, sp, 192
; RV64VLS-NEXT: vl8re64.v v8, (a2)
; RV64VLS-NEXT: vl8re64.v v16, (a0)
; RV64VLS-NEXT: addi a0, a1, 128
; RV64VLS-NEXT: vs8r.v v8, (a0)
Expand Down
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2219,8 +2219,8 @@ define void @vpscatter_baseidx_nxv16i16_nxv16f64(<vscale x 16 x double> %val, pt
; RV64-NEXT: vsll.vi v16, v16, 3
; RV64-NEXT: addi a1, sp, 16
; RV64-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: vsext.vf4 v16, v24
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: vsll.vi v24, v16, 3
; RV64-NEXT: mv a3, a2
; RV64-NEXT: bltu a2, a1, .LBB100_2
Expand Down Expand Up @@ -2286,29 +2286,31 @@ define void @vpscatter_baseidx_sext_nxv16i16_nxv16f64(<vscale x 16 x double> %va
; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a3, vlenb
; RV64-NEXT: slli a3, a3, 4
; RV64-NEXT: li a4, 10
; RV64-NEXT: mul a3, a3, a4
; RV64-NEXT: sub sp, sp, a3
; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x0a, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 10 * vlenb
; RV64-NEXT: vl4re16.v v24, (a1)
; RV64-NEXT: addi a1, sp, 16
; RV64-NEXT: vs1r.v v0, (a1) # Unknown-size Folded Spill
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV64-NEXT: vsext.vf4 v0, v24
; RV64-NEXT: vsext.vf4 v16, v26
; RV64-NEXT: vsll.vi v16, v16, 3
; RV64-NEXT: addi a1, sp, 16
; RV64-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: vsext.vf4 v16, v24
; RV64-NEXT: vsll.vi v24, v16, 3
; RV64-NEXT: vsll.vi v24, v0, 3
; RV64-NEXT: mv a3, a2
; RV64-NEXT: bltu a2, a1, .LBB101_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: mv a3, a1
; RV64-NEXT: .LBB101_2:
; RV64-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; RV64-NEXT: addi a3, sp, 16
; RV64-NEXT: vl1r.v v0, (a3) # Unknown-size Folded Reload
; RV64-NEXT: vsoxei64.v v8, (a0), v24, v0.t
; RV64-NEXT: sub a3, a2, a1
; RV64-NEXT: sltu a2, a2, a3
Expand All @@ -2319,15 +2321,13 @@ define void @vpscatter_baseidx_sext_nxv16i16_nxv16f64(<vscale x 16 x double> %va
; RV64-NEXT: vslidedown.vx v0, v0, a1
; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: addi a1, sp, 16
; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 4
; RV64-NEXT: li a1, 10
; RV64-NEXT: mul a0, a0, a1
; RV64-NEXT: add sp, sp, a0
; RV64-NEXT: addi sp, sp, 16
; RV64-NEXT: ret
Expand Down
30 changes: 30 additions & 0 deletions llvm/test/Transforms/InstCombine/add.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3093,6 +3093,36 @@ define <2 x i32> @dec_zext_add_nonzero_vec(<2 x i8> %x) {
ret <2 x i32> %c
}

; Negative test: Folding this with undef is not safe.

define <2 x i32> @dec_zext_add_nonzero_vec_undef0(<2 x i8> %x) {
; CHECK-LABEL: @dec_zext_add_nonzero_vec_undef0(
; CHECK-NEXT: [[O:%.*]] = or <2 x i8> [[X:%.*]], <i8 8, i8 undef>
; CHECK-NEXT: [[A:%.*]] = add <2 x i8> [[O]], <i8 -1, i8 -1>
; CHECK-NEXT: [[B:%.*]] = zext <2 x i8> [[A]] to <2 x i32>
; CHECK-NEXT: [[C:%.*]] = add nuw nsw <2 x i32> [[B]], <i32 1, i32 1>
; CHECK-NEXT: ret <2 x i32> [[C]]
;
%o = or <2 x i8> %x, <i8 8, i8 undef>
%a = add <2 x i8> %o, <i8 -1, i8 -1>
%b = zext <2 x i8> %a to <2 x i32>
%c = add <2 x i32> %b, <i32 1, i32 1>
ret <2 x i32> %c
}

define <2 x i32> @dec_zext_add_nonzero_poison0(<2 x i8> %x) {
; CHECK-LABEL: @dec_zext_add_nonzero_poison0(
; CHECK-NEXT: [[O:%.*]] = or <2 x i8> [[X:%.*]], <i8 8, i8 poison>
; CHECK-NEXT: [[C:%.*]] = zext <2 x i8> [[O]] to <2 x i32>
; CHECK-NEXT: ret <2 x i32> [[C]]
;
%o = or <2 x i8> %x, <i8 8, i8 poison>
%a = add <2 x i8> %o, <i8 -1, i8 -1>
%b = zext <2 x i8> %a to <2 x i32>
%c = add <2 x i32> %b, <i32 1, i32 1>
ret <2 x i32> %c
}

define <2 x i32> @dec_zext_add_nonzero_vec_poison1(<2 x i8> %x) {
; CHECK-LABEL: @dec_zext_add_nonzero_vec_poison1(
; CHECK-NEXT: [[O:%.*]] = or <2 x i8> [[X:%.*]], <i8 8, i8 8>
Expand Down
17 changes: 14 additions & 3 deletions llvm/test/Transforms/InstSimplify/vec-cmp.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -21,13 +21,24 @@ define <2 x i1> @nonzero_vec_nonsplat(<2 x i32> %x) {

define <2 x i1> @nonzero_vec_undef_elt(<2 x i32> %x) {
; CHECK-LABEL: @nonzero_vec_undef_elt(
; CHECK-NEXT: ret <2 x i1> zeroinitializer
; CHECK-NEXT: [[Y:%.*]] = or <2 x i32> [[X:%.*]], <i32 undef, i32 1>
; CHECK-NEXT: [[C:%.*]] = icmp eq <2 x i32> [[Y]], zeroinitializer
; CHECK-NEXT: ret <2 x i1> [[C]]
;
%y = or <2 x i32> %x, <i32 undef, i32 1>
%c = icmp eq <2 x i32> %y, zeroinitializer
ret <2 x i1> %c
}

define <2 x i1> @nonzero_vec_poison_elt(<2 x i32> %x) {
; CHECK-LABEL: @nonzero_vec_poison_elt(
; CHECK-NEXT: ret <2 x i1> zeroinitializer
;
%y = or <2 x i32> %x, <i32 poison, i32 1>
%c = icmp eq <2 x i32> %y, zeroinitializer
ret <2 x i1> %c
}

define <2 x i1> @may_be_zero_vec(<2 x i32> %x) {
; CHECK-LABEL: @may_be_zero_vec(
; CHECK-NEXT: [[Y:%.*]] = or <2 x i32> [[X:%.*]], <i32 0, i32 1>
Expand All @@ -45,7 +56,7 @@ define <2 x i1> @nonzero_vec_mul_nuw(<2 x i32> %x, <2 x i32> %y) {
; CHECK-NEXT: ret <2 x i1> zeroinitializer
;
%xnz = or <2 x i32> %x, <i32 1, i32 2>
%ynz = or <2 x i32> %y, <i32 3, i32 undef>
%ynz = or <2 x i32> %y, <i32 3, i32 poison>
%m = mul nuw <2 x i32> %xnz, %ynz
%c = icmp eq <2 x i32> %m, zeroinitializer
ret <2 x i1> %c
Expand All @@ -56,7 +67,7 @@ define <2 x i1> @nonzero_vec_mul_nsw(<2 x i32> %x, <2 x i32> %y) {
; CHECK-LABEL: @nonzero_vec_mul_nsw(
; CHECK-NEXT: ret <2 x i1> <i1 true, i1 true>
;
%xnz = or <2 x i32> %x, <i32 undef, i32 2>
%xnz = or <2 x i32> %x, <i32 poison, i32 2>
%ynz = or <2 x i32> %y, <i32 3, i32 4>
%m = mul nsw <2 x i32> %xnz, %ynz
%c = icmp ne <2 x i32> %m, zeroinitializer
Expand Down
1 change: 1 addition & 0 deletions utils/bazel/llvm-project-overlay/clang/BUILD.bazel
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1928,6 +1928,7 @@ cc_library(
":frontend",
":lex",
":sema",
":serialization",
":type_nodes_gen",
"//llvm:AllTargetsAsmParsers",
"//llvm:Analysis",
Expand Down