93 changes: 32 additions & 61 deletions llvm/lib/Target/AArch64/SMEInstrFormats.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1194,69 +1194,47 @@ multiclass sve2_int_perm_sel_p<string asm, SDPatternOperator op> {
//===----------------------------------------------------------------------===//
// SME2 single-multi ternary int/fp, two/four registers

class sme2_mla_add_sub_array_vg24_single<bit vg4, bit sz, bits<2> op,
class sme2_dot_mla_add_sub_array_vg24_single<bits<7> op,
MatrixOperand matrix_ty,
RegisterOperand multi_vector_ty,
ZPRRegOp zpr_ty,
string mnemonic>
: I<(outs matrix_ty:$ZAd),
(ins matrix_ty:$_ZAd, MatrixIndexGPR32Op8_11:$Rv,
sme_elm_idx0_7:$imm3, multi_vector_ty:$Zn, zpr_ty:$Zm),
mnemonic,"\t$ZAd[$Rv, $imm3, " # !if(vg4, "vgx4", "vgx2") # "], $Zn, $Zm",
mnemonic,"\t$ZAd[$Rv, $imm3, " # !if(op{5}, "vgx4", "vgx2") # "], $Zn, $Zm",
"", []> , Sched<[]> {
bits<4> Zm;
bits<5> Zn;
bits<2> Rv;
bits<3> imm3;
let Inst{31-23} = 0b110000010;
let Inst{22} = sz;
let Inst{22} = op{6}; //sz
let Inst{21} = 0b1;
let Inst{20} = vg4;
let Inst{20} = op{5}; //vgx4
let Inst{19-16} = Zm;
let Inst{15} = 0b0;
let Inst{14-13} = Rv;
let Inst{12-10} = 0b110;
let Inst{12-10} = op{4-2};
let Inst{9-5} = Zn;
let Inst{4-3} = op;
let Inst{4-3} = op{1-0};
let Inst{2-0} = imm3;
let Constraints = "$ZAd = $_ZAd";
}

multiclass sme2_mla_add_sub_array_vg2_single_S<string mnemonic, bits<2> op>{
def NAME : sme2_mla_add_sub_array_vg24_single<0b0, 0b0, op, MatrixOp32, ZZ_s,
ZPR4b32, mnemonic>;

def : InstAlias<mnemonic # "\t$ZAd[$Rv, $imm3], $Zn, $Zm",
(!cast<Instruction>(NAME) MatrixOp32:$ZAd, MatrixIndexGPR32Op8_11:$Rv, sme_elm_idx0_7:$imm3, ZZ_s:$Zn, ZPR4b32:$Zm), 0>;
}

multiclass sme2_mla_add_sub_array_vg2_single_D<string mnemonic, bits<2> op>{
def NAME : sme2_mla_add_sub_array_vg24_single<0b0, 0b1, op, MatrixOp64,
ZZ_d, ZPR4b64, mnemonic>;

def : InstAlias<mnemonic # "\t$ZAd[$Rv, $imm3], $Zn, $Zm",
(!cast<Instruction>(NAME) MatrixOp64:$ZAd, MatrixIndexGPR32Op8_11:$Rv, sme_elm_idx0_7:$imm3, ZZ_d:$Zn, ZPR4b64:$Zm), 0>;
}

multiclass sme2_mla_add_sub_array_vg4_single_S<string mnemonic, bits<2> op>{
def NAME : sme2_mla_add_sub_array_vg24_single<0b1, 0b0, op, MatrixOp32, ZZZZ_s,
ZPR4b32, mnemonic>;

def : InstAlias<mnemonic # "\t$ZAd[$Rv, $imm3], $Zn, $Zm",
(!cast<Instruction>(NAME) MatrixOp32:$ZAd, MatrixIndexGPR32Op8_11:$Rv, sme_elm_idx0_7:$imm3, ZZZZ_s:$Zn, ZPR4b32:$Zm), 0>;
}

multiclass sme2_mla_add_sub_array_vg4_single_D<string mnemonic, bits<2> op>{
def NAME : sme2_mla_add_sub_array_vg24_single<0b1, 0b1, op, MatrixOp64, ZZZZ_d,
ZPR4b64, mnemonic>;
multiclass sme2_dot_mla_add_sub_array_vg24_single<string mnemonic, bits<7> op,
MatrixOperand matrix_ty,
RegisterOperand multi_vector_ty,
ZPRRegOp zpr_ty>{
def NAME: sme2_dot_mla_add_sub_array_vg24_single<op, matrix_ty, multi_vector_ty, zpr_ty, mnemonic>;

def : InstAlias<mnemonic # "\t$ZAd[$Rv, $imm3], $Zn, $Zm",
(!cast<Instruction>(NAME) MatrixOp64:$ZAd, MatrixIndexGPR32Op8_11:$Rv, sme_elm_idx0_7:$imm3, ZZZZ_d:$Zn, ZPR4b64:$Zm), 0>;
(!cast<Instruction>(NAME) matrix_ty:$ZAd, MatrixIndexGPR32Op8_11:$Rv, sme_elm_idx0_7:$imm3, multi_vector_ty:$Zn, zpr_ty:$Zm), 0>;
}

//===----------------------------------------------------------------------===//
// SME2 multiple vectors ternary INT/FP two and four registers
class sme2_mla_add_sub_array_vg2_multi<bit sz, bits<2> op,
class sme2_dot_mla_add_sub_array_vg2_multi<bits<6> op,
MatrixOperand matrix_ty,
RegisterOperand multi_vector_ty,
string mnemonic>
Expand All @@ -1270,34 +1248,30 @@ class sme2_mla_add_sub_array_vg2_multi<bit sz, bits<2> op,
bits<2> Rv;
bits<3> imm3;
let Inst{31-23} = 0b110000011;
let Inst{22} = sz;
let Inst{22} = op{5}; //sz
let Inst{21} = 0b1;
let Inst{20-17} = Zm;
let Inst{16-15} = 0b00;
let Inst{14-13} = Rv;
let Inst{12-10} = 0b110;
let Inst{12-10} = op{4-2};
let Inst{9-6} = Zn;
let Inst{5} = 0b0;
let Inst{4-3} = op;
let Inst{4-3} = op{1-0};
let Inst{2-0} = imm3;
let Constraints = "$ZAd = $_ZAd";
}

multiclass sme2_mla_add_sub_array_vg2_multi_S<string mnemonic, bits<2> op>{
def NAME : sme2_mla_add_sub_array_vg2_multi<0b0, op, MatrixOp32, ZZ_s_mul_r, mnemonic>;

def : InstAlias<mnemonic # "\t$ZAd[$Rv, $imm3], $Zn, $Zm",
(!cast<Instruction>(NAME) MatrixOp32:$ZAd, MatrixIndexGPR32Op8_11:$Rv, sme_elm_idx0_7:$imm3, ZZ_s_mul_r:$Zn, ZZ_s_mul_r:$Zm), 0>;
}
multiclass sme2_dot_mla_add_sub_array_vg2_multi<string mnemonic, bits<6> op,
MatrixOperand matrix_ty,
RegisterOperand multi_vector_ty>{
def NAME : sme2_dot_mla_add_sub_array_vg2_multi<op, matrix_ty, multi_vector_ty, mnemonic>;

multiclass sme2_mla_add_sub_array_vg2_multi_D<string mnemonic, bits<2> op>{
def NAME : sme2_mla_add_sub_array_vg2_multi<0b1, op, MatrixOp64, ZZ_d_mul_r, mnemonic>;
def : InstAlias<mnemonic # "\t$ZAd[$Rv, $imm3], $Zn, $Zm",
(!cast<Instruction>(NAME) matrix_ty:$ZAd, MatrixIndexGPR32Op8_11:$Rv, sme_elm_idx0_7:$imm3, multi_vector_ty:$Zn, multi_vector_ty:$Zm), 0>;

def : InstAlias<mnemonic # "\t$ZAd[$Rv, $imm3], $Zn, $Zm",
(!cast<Instruction>(NAME) MatrixOp64:$ZAd, MatrixIndexGPR32Op8_11:$Rv, sme_elm_idx0_7:$imm3, ZZ_d_mul_r:$Zn, ZZ_d_mul_r:$Zm), 0>;
}

class sme2_mla_add_sub_array_vg4_multi_base<bit sz, bits<2> op,
class sme2_dot_mla_add_sub_array_vg4_multi<bits<6> op,
MatrixOperand matrix_ty,
RegisterOperand multi_vector_ty,
string mnemonic>
Expand All @@ -1311,31 +1285,28 @@ class sme2_mla_add_sub_array_vg4_multi_base<bit sz, bits<2> op,
bits<2> Rv;
bits<3> imm3;
let Inst{31-23} = 0b110000011;
let Inst{22} = sz;
let Inst{22} = op{5}; //sz
let Inst{21} = 0b1;
let Inst{20-18} = Zm;
let Inst{17-15} = 0b010;
let Inst{14-13} = Rv;
let Inst{12-10} = 0b110;
let Inst{12-10} = op{4-2};
let Inst{9-7} = Zn;
let Inst{6-5} = 0b00;
let Inst{4-3} = op;
let Inst{4-3} = op{1-0};
let Inst{2-0} = imm3;
let Constraints = "$ZAd = $_ZAd";
}

multiclass sme2_mla_add_sub_array_vg4_multi_S<string mnemonic, bits<2> op>{
def NAME : sme2_mla_add_sub_array_vg4_multi_base<0b0, op, MatrixOp32, ZZZZ_s_mul_r, mnemonic>;

def : InstAlias<mnemonic # "\t$ZAd[$Rv, $imm3], $Zn, $Zm",
(!cast<Instruction>(NAME) MatrixOp32:$ZAd, MatrixIndexGPR32Op8_11:$Rv, sme_elm_idx0_7:$imm3, ZZZZ_s_mul_r:$Zn, ZZZZ_s_mul_r:$Zm), 0>;
}
multiclass sme2_dot_mla_add_sub_array_vg4_multi<string mnemonic, bits<6> op,
MatrixOperand matrix_ty,
RegisterOperand multi_vector_ty>{
def NAME : sme2_dot_mla_add_sub_array_vg4_multi<op, matrix_ty, multi_vector_ty, mnemonic>;

multiclass sme2_mla_add_sub_array_vg4_multi_D<string mnemonic, bits<2> op>{
def NAME : sme2_mla_add_sub_array_vg4_multi_base<0b1, op, MatrixOp64, ZZZZ_d_mul_r, mnemonic>;
def : InstAlias<mnemonic # "\t$ZAd[$Rv, $imm3], $Zn, $Zm",
(!cast<Instruction>(NAME) matrix_ty:$ZAd, MatrixIndexGPR32Op8_11:$Rv, sme_elm_idx0_7:$imm3, multi_vector_ty:$Zn, multi_vector_ty:$Zm), 0>;

def : InstAlias<mnemonic # "\t$ZAd[$Rv, $imm3], $Zn, $Zm",
(!cast<Instruction>(NAME) MatrixOp64:$ZAd, MatrixIndexGPR32Op8_11:$Rv, sme_elm_idx0_7:$imm3, ZZZZ_d_mul_r:$Zn, ZZZZ_d_mul_r:$Zm), 0>;
}

//===----------------------------------------------------------------------===//
Expand Down
27 changes: 27 additions & 0 deletions llvm/test/MC/AArch64/SME2/bfdot-diagnostics.s
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Original file line number Diff line number Diff line change
Expand Up @@ -8,9 +8,32 @@ bfdot za.s[w8, 0, vgx2], {z0.h-z2.h}, z0.h[0]
// CHECK-NEXT: bfdot za.s[w8, 0, vgx2], {z0.h-z2.h}, z0.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

bfdot za.s[w8, 0, vgx4], {z1.h-z5.h}, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
// CHECK-NEXT: bfdot za.s[w8, 0, vgx4], {z1.h-z5.h}, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

bfdot za.s[w8, 0, vgx2], {z0.h-z1.h}, {z3.h-z4.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
// CHECK-NEXT: bfdot za.s[w8, 0, vgx2], {z0.h-z1.h}, {z3.h-z4.h}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid single vector register

bfdot za.s[w8, 0, vgx4], {z0.h-z3.h}, z16.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
// CHECK-NEXT: bfdot za.s[w8, 0, vgx4], {z0.h-z3.h}, z16.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid vector select register

bfdot za.s[w7, 0, vgx2], {z0.h-z1.h}, {z3.h-z4.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
// CHECK-NEXT: bfdot za.s[w7, 0, vgx2], {z0.h-z1.h}, {z3.h-z4.h}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

bfdot za.s[w12, 0, vgx4], {z0.h-z3.h}, z0.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
// CHECK-NEXT: bfdot za.s[w12, 0, vgx4], {z0.h-z3.h}, z0.h[0]
Expand All @@ -29,6 +52,10 @@ bfdot za.s[w8, 8, vgx4], {z0.h-z3.h}, z0.h[0]
// CHECK-NEXT: bfdot za.s[w8, 8, vgx4], {z0.h-z3.h}, z0.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

bfdot za.s[w8, -1, vgx2], {z0.h-z1.h}, {z3.h-z4.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
// CHECK-NEXT: bfdot za.s[w8, -1, vgx2], {z0.h-z1.h}, {z3.h-z4.h}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid Register Suffix
Expand Down
580 changes: 580 additions & 0 deletions llvm/test/MC/AArch64/SME2/bfdot.s
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580 changes: 580 additions & 0 deletions llvm/test/MC/AArch64/SME2/fdot.s
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581 changes: 581 additions & 0 deletions llvm/test/MC/AArch64/SME2/sdot.s
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290 changes: 290 additions & 0 deletions llvm/test/MC/AArch64/SME2/sudot.s
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Expand Up @@ -12,6 +12,152 @@
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST


sudot za.s[w8, 0, vgx2], {z0.b, z1.b}, z0.b // 11000001-00100000-00010100-00011000
// CHECK-INST: sudot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b
// CHECK-ENCODING: [0x18,0x14,0x20,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1201418 <unknown>

sudot za.s[w8, 0], {z0.b, z1.b}, z0.b // 11000001-00100000-00010100-00011000
// CHECK-INST: sudot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b
// CHECK-ENCODING: [0x18,0x14,0x20,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1201418 <unknown>

sudot za.s[w10, 5, vgx2], {z10.b, z11.b}, z5.b // 11000001-00100101-01010101-01011101
// CHECK-INST: sudot za.s[w10, 5, vgx2], { z10.b, z11.b }, z5.b
// CHECK-ENCODING: [0x5d,0x55,0x25,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c125555d <unknown>

sudot za.s[w10, 5], {z10.b, z11.b}, z5.b // 11000001-00100101-01010101-01011101
// CHECK-INST: sudot za.s[w10, 5, vgx2], { z10.b, z11.b }, z5.b
// CHECK-ENCODING: [0x5d,0x55,0x25,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c125555d <unknown>

sudot za.s[w11, 7, vgx2], {z13.b, z14.b}, z8.b // 11000001-00101000-01110101-10111111
// CHECK-INST: sudot za.s[w11, 7, vgx2], { z13.b, z14.b }, z8.b
// CHECK-ENCODING: [0xbf,0x75,0x28,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c12875bf <unknown>

sudot za.s[w11, 7], {z13.b, z14.b}, z8.b // 11000001-00101000-01110101-10111111
// CHECK-INST: sudot za.s[w11, 7, vgx2], { z13.b, z14.b }, z8.b
// CHECK-ENCODING: [0xbf,0x75,0x28,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c12875bf <unknown>

sudot za.s[w11, 7, vgx2], {z31.b, z0.b}, z15.b // 11000001-00101111-01110111-11111111
// CHECK-INST: sudot za.s[w11, 7, vgx2], { z31.b, z0.b }, z15.b
// CHECK-ENCODING: [0xff,0x77,0x2f,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c12f77ff <unknown>

sudot za.s[w11, 7], {z31.b, z0.b}, z15.b // 11000001-00101111-01110111-11111111
// CHECK-INST: sudot za.s[w11, 7, vgx2], { z31.b, z0.b }, z15.b
// CHECK-ENCODING: [0xff,0x77,0x2f,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c12f77ff <unknown>

sudot za.s[w8, 5, vgx2], {z17.b, z18.b}, z0.b // 11000001-00100000-00010110-00111101
// CHECK-INST: sudot za.s[w8, 5, vgx2], { z17.b, z18.b }, z0.b
// CHECK-ENCODING: [0x3d,0x16,0x20,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c120163d <unknown>

sudot za.s[w8, 5], {z17.b, z18.b}, z0.b // 11000001-00100000-00010110-00111101
// CHECK-INST: sudot za.s[w8, 5, vgx2], { z17.b, z18.b }, z0.b
// CHECK-ENCODING: [0x3d,0x16,0x20,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c120163d <unknown>

sudot za.s[w8, 1, vgx2], {z1.b, z2.b}, z14.b // 11000001-00101110-00010100-00111001
// CHECK-INST: sudot za.s[w8, 1, vgx2], { z1.b, z2.b }, z14.b
// CHECK-ENCODING: [0x39,0x14,0x2e,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c12e1439 <unknown>

sudot za.s[w8, 1], {z1.b, z2.b}, z14.b // 11000001-00101110-00010100-00111001
// CHECK-INST: sudot za.s[w8, 1, vgx2], { z1.b, z2.b }, z14.b
// CHECK-ENCODING: [0x39,0x14,0x2e,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c12e1439 <unknown>


sudot za.s[w10, 0, vgx2], {z19.b, z20.b}, z4.b // 11000001-00100100-01010110-01111000
// CHECK-INST: sudot za.s[w10, 0, vgx2], { z19.b, z20.b }, z4.b
// CHECK-ENCODING: [0x78,0x56,0x24,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1245678 <unknown>

sudot za.s[w10, 0], {z19.b, z20.b}, z4.b // 11000001-00100100-01010110-01111000
// CHECK-INST: sudot za.s[w10, 0, vgx2], { z19.b, z20.b }, z4.b
// CHECK-ENCODING: [0x78,0x56,0x24,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1245678 <unknown>

sudot za.s[w8, 0, vgx2], {z12.b, z13.b}, z2.b // 11000001-00100010-00010101-10011000
// CHECK-INST: sudot za.s[w8, 0, vgx2], { z12.b, z13.b }, z2.b
// CHECK-ENCODING: [0x98,0x15,0x22,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1221598 <unknown>

sudot za.s[w8, 0], {z12.b, z13.b}, z2.b // 11000001-00100010-00010101-10011000
// CHECK-INST: sudot za.s[w8, 0, vgx2], { z12.b, z13.b }, z2.b
// CHECK-ENCODING: [0x98,0x15,0x22,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1221598 <unknown>

sudot za.s[w10, 1, vgx2], {z1.b, z2.b}, z10.b // 11000001-00101010-01010100-00111001
// CHECK-INST: sudot za.s[w10, 1, vgx2], { z1.b, z2.b }, z10.b
// CHECK-ENCODING: [0x39,0x54,0x2a,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c12a5439 <unknown>

sudot za.s[w10, 1], {z1.b, z2.b}, z10.b // 11000001-00101010-01010100-00111001
// CHECK-INST: sudot za.s[w10, 1, vgx2], { z1.b, z2.b }, z10.b
// CHECK-ENCODING: [0x39,0x54,0x2a,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c12a5439 <unknown>

sudot za.s[w8, 5, vgx2], {z22.b, z23.b}, z14.b // 11000001-00101110-00010110-11011101
// CHECK-INST: sudot za.s[w8, 5, vgx2], { z22.b, z23.b }, z14.b
// CHECK-ENCODING: [0xdd,0x16,0x2e,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c12e16dd <unknown>

sudot za.s[w8, 5], {z22.b, z23.b}, z14.b // 11000001-00101110-00010110-11011101
// CHECK-INST: sudot za.s[w8, 5, vgx2], { z22.b, z23.b }, z14.b
// CHECK-ENCODING: [0xdd,0x16,0x2e,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c12e16dd <unknown>

sudot za.s[w11, 2, vgx2], {z9.b, z10.b}, z1.b // 11000001-00100001-01110101-00111010
// CHECK-INST: sudot za.s[w11, 2, vgx2], { z9.b, z10.b }, z1.b
// CHECK-ENCODING: [0x3a,0x75,0x21,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c121753a <unknown>

sudot za.s[w11, 2], {z9.b, z10.b}, z1.b // 11000001-00100001-01110101-00111010
// CHECK-INST: sudot za.s[w11, 2, vgx2], { z9.b, z10.b }, z1.b
// CHECK-ENCODING: [0x3a,0x75,0x21,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c121753a <unknown>

sudot za.s[w9, 7, vgx2], {z12.b, z13.b}, z11.b // 11000001-00101011-00110101-10011111
// CHECK-INST: sudot za.s[w9, 7, vgx2], { z12.b, z13.b }, z11.b
// CHECK-ENCODING: [0x9f,0x35,0x2b,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c12b359f <unknown>

sudot za.s[w9, 7], {z12.b, z13.b}, z11.b // 11000001-00101011-00110101-10011111
// CHECK-INST: sudot za.s[w9, 7, vgx2], { z12.b, z13.b }, z11.b
// CHECK-ENCODING: [0x9f,0x35,0x2b,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c12b359f <unknown>


sudot za.s[w8, 0, vgx2], {z0.b, z1.b}, z0.b[0] // 11000001-01010000-00010000-00111000
// CHECK-INST: sudot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b[0]
// CHECK-ENCODING: [0x38,0x10,0x50,0xc1]
Expand Down Expand Up @@ -156,6 +302,150 @@ sudot za.s[w9, 7], {z12.b, z13.b}, z11.b[2] // 11000001-01011011-00111001-101
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c15b39bf <unknown>

sudot za.s[w8, 0, vgx4], {z0.b - z3.b}, z0.b // 11000001-00110000-00010100-00011000
// CHECK-INST: sudot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b
// CHECK-ENCODING: [0x18,0x14,0x30,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1301418 <unknown>

sudot za.s[w8, 0], {z0.b - z3.b}, z0.b // 11000001-00110000-00010100-00011000
// CHECK-INST: sudot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b
// CHECK-ENCODING: [0x18,0x14,0x30,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1301418 <unknown>

sudot za.s[w10, 5, vgx4], {z10.b - z13.b}, z5.b // 11000001-00110101-01010101-01011101
// CHECK-INST: sudot za.s[w10, 5, vgx4], { z10.b - z13.b }, z5.b
// CHECK-ENCODING: [0x5d,0x55,0x35,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c135555d <unknown>

sudot za.s[w10, 5], {z10.b - z13.b}, z5.b // 11000001-00110101-01010101-01011101
// CHECK-INST: sudot za.s[w10, 5, vgx4], { z10.b - z13.b }, z5.b
// CHECK-ENCODING: [0x5d,0x55,0x35,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c135555d <unknown>

sudot za.s[w11, 7, vgx4], {z13.b - z16.b}, z8.b // 11000001-00111000-01110101-10111111
// CHECK-INST: sudot za.s[w11, 7, vgx4], { z13.b - z16.b }, z8.b
// CHECK-ENCODING: [0xbf,0x75,0x38,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c13875bf <unknown>

sudot za.s[w11, 7], {z13.b - z16.b}, z8.b // 11000001-00111000-01110101-10111111
// CHECK-INST: sudot za.s[w11, 7, vgx4], { z13.b - z16.b }, z8.b
// CHECK-ENCODING: [0xbf,0x75,0x38,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c13875bf <unknown>

sudot za.s[w11, 7, vgx4], {z31.b - z2.b}, z15.b // 11000001-00111111-01110111-11111111
// CHECK-INST: sudot za.s[w11, 7, vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b
// CHECK-ENCODING: [0xff,0x77,0x3f,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c13f77ff <unknown>

sudot za.s[w11, 7], {z31.b - z2.b}, z15.b // 11000001-00111111-01110111-11111111
// CHECK-INST: sudot za.s[w11, 7, vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b
// CHECK-ENCODING: [0xff,0x77,0x3f,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c13f77ff <unknown>

sudot za.s[w8, 5, vgx4], {z17.b - z20.b}, z0.b // 11000001-00110000-00010110-00111101
// CHECK-INST: sudot za.s[w8, 5, vgx4], { z17.b - z20.b }, z0.b
// CHECK-ENCODING: [0x3d,0x16,0x30,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c130163d <unknown>

sudot za.s[w8, 5], {z17.b - z20.b}, z0.b // 11000001-00110000-00010110-00111101
// CHECK-INST: sudot za.s[w8, 5, vgx4], { z17.b - z20.b }, z0.b
// CHECK-ENCODING: [0x3d,0x16,0x30,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c130163d <unknown>

sudot za.s[w8, 1, vgx4], {z1.b - z4.b}, z14.b // 11000001-00111110-00010100-00111001
// CHECK-INST: sudot za.s[w8, 1, vgx4], { z1.b - z4.b }, z14.b
// CHECK-ENCODING: [0x39,0x14,0x3e,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c13e1439 <unknown>

sudot za.s[w8, 1], {z1.b - z4.b}, z14.b // 11000001-00111110-00010100-00111001
// CHECK-INST: sudot za.s[w8, 1, vgx4], { z1.b - z4.b }, z14.b
// CHECK-ENCODING: [0x39,0x14,0x3e,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c13e1439 <unknown>

sudot za.s[w10, 0, vgx4], {z19.b - z22.b}, z4.b // 11000001-00110100-01010110-01111000
// CHECK-INST: sudot za.s[w10, 0, vgx4], { z19.b - z22.b }, z4.b
// CHECK-ENCODING: [0x78,0x56,0x34,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1345678 <unknown>

sudot za.s[w10, 0], {z19.b - z22.b}, z4.b // 11000001-00110100-01010110-01111000
// CHECK-INST: sudot za.s[w10, 0, vgx4], { z19.b - z22.b }, z4.b
// CHECK-ENCODING: [0x78,0x56,0x34,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1345678 <unknown>

sudot za.s[w8, 0, vgx4], {z12.b - z15.b}, z2.b // 11000001-00110010-00010101-10011000
// CHECK-INST: sudot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b
// CHECK-ENCODING: [0x98,0x15,0x32,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1321598 <unknown>

sudot za.s[w8, 0], {z12.b - z15.b}, z2.b // 11000001-00110010-00010101-10011000
// CHECK-INST: sudot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b
// CHECK-ENCODING: [0x98,0x15,0x32,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1321598 <unknown>

sudot za.s[w10, 1, vgx4], {z1.b - z4.b}, z10.b // 11000001-00111010-01010100-00111001
// CHECK-INST: sudot za.s[w10, 1, vgx4], { z1.b - z4.b }, z10.b
// CHECK-ENCODING: [0x39,0x54,0x3a,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c13a5439 <unknown>

sudot za.s[w10, 1], {z1.b - z4.b}, z10.b // 11000001-00111010-01010100-00111001
// CHECK-INST: sudot za.s[w10, 1, vgx4], { z1.b - z4.b }, z10.b
// CHECK-ENCODING: [0x39,0x54,0x3a,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c13a5439 <unknown>

sudot za.s[w8, 5, vgx4], {z22.b - z25.b}, z14.b // 11000001-00111110-00010110-11011101
// CHECK-INST: sudot za.s[w8, 5, vgx4], { z22.b - z25.b }, z14.b
// CHECK-ENCODING: [0xdd,0x16,0x3e,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c13e16dd <unknown>

sudot za.s[w8, 5], {z22.b - z25.b}, z14.b // 11000001-00111110-00010110-11011101
// CHECK-INST: sudot za.s[w8, 5, vgx4], { z22.b - z25.b }, z14.b
// CHECK-ENCODING: [0xdd,0x16,0x3e,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c13e16dd <unknown>

sudot za.s[w11, 2, vgx4], {z9.b - z12.b}, z1.b // 11000001-00110001-01110101-00111010
// CHECK-INST: sudot za.s[w11, 2, vgx4], { z9.b - z12.b }, z1.b
// CHECK-ENCODING: [0x3a,0x75,0x31,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c131753a <unknown>

sudot za.s[w11, 2], {z9.b - z12.b}, z1.b // 11000001-00110001-01110101-00111010
// CHECK-INST: sudot za.s[w11, 2, vgx4], { z9.b - z12.b }, z1.b
// CHECK-ENCODING: [0x3a,0x75,0x31,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c131753a <unknown>

sudot za.s[w9, 7, vgx4], {z12.b - z15.b}, z11.b // 11000001-00111011-00110101-10011111
// CHECK-INST: sudot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b
// CHECK-ENCODING: [0x9f,0x35,0x3b,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c13b359f <unknown>

sudot za.s[w9, 7], {z12.b - z15.b}, z11.b // 11000001-00111011-00110101-10011111
// CHECK-INST: sudot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b
// CHECK-ENCODING: [0x9f,0x35,0x3b,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c13b359f <unknown>


sudot za.s[w8, 0, vgx4], {z0.b - z3.b}, z0.b[0] // 11000001-01010000-10010000-00111000
// CHECK-INST: sudot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]
Expand Down
580 changes: 580 additions & 0 deletions llvm/test/MC/AArch64/SME2/udot.s
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579 changes: 579 additions & 0 deletions llvm/test/MC/AArch64/SME2/usdot.s
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