83 changes: 77 additions & 6 deletions llvm/test/CodeGen/AArch64/GlobalISel/legalize-fmaximum.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,13 +9,17 @@ body: |
bb.0:
liveins: $h0, $h1
; FP16-LABEL: name: s16_legal_with_full_fp16
; FP16: %a:_(s16) = COPY $h0
; FP16: liveins: $h0, $h1
; FP16-NEXT: {{ $}}
; FP16-NEXT: %a:_(s16) = COPY $h0
; FP16-NEXT: %b:_(s16) = COPY $h1
; FP16-NEXT: %legalize_me:_(s16) = G_FMAXIMUM %a, %b
; FP16-NEXT: $h0 = COPY %legalize_me(s16)
; FP16-NEXT: RET_ReallyLR implicit $h0
; NO-FP16-LABEL: name: s16_legal_with_full_fp16
; NO-FP16: %a:_(s16) = COPY $h0
; NO-FP16: liveins: $h0, $h1
; NO-FP16-NEXT: {{ $}}
; NO-FP16-NEXT: %a:_(s16) = COPY $h0
; NO-FP16-NEXT: %b:_(s16) = COPY $h1
; NO-FP16-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT %a(s16)
; NO-FP16-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT %b(s16)
Expand All @@ -37,13 +41,17 @@ body: |
bb.0:
liveins: $s0, $s1
; FP16-LABEL: name: s32_legal
; FP16: %a:_(s32) = COPY $s0
; FP16: liveins: $s0, $s1
; FP16-NEXT: {{ $}}
; FP16-NEXT: %a:_(s32) = COPY $s0
; FP16-NEXT: %b:_(s32) = COPY $s1
; FP16-NEXT: %legalize_me:_(s32) = G_FMAXIMUM %a, %b
; FP16-NEXT: $s0 = COPY %legalize_me(s32)
; FP16-NEXT: RET_ReallyLR implicit $s0
; NO-FP16-LABEL: name: s32_legal
; NO-FP16: %a:_(s32) = COPY $s0
; NO-FP16: liveins: $s0, $s1
; NO-FP16-NEXT: {{ $}}
; NO-FP16-NEXT: %a:_(s32) = COPY $s0
; NO-FP16-NEXT: %b:_(s32) = COPY $s1
; NO-FP16-NEXT: %legalize_me:_(s32) = G_FMAXIMUM %a, %b
; NO-FP16-NEXT: $s0 = COPY %legalize_me(s32)
Expand All @@ -62,13 +70,17 @@ body: |
bb.0:
liveins: $d0, $d1
; FP16-LABEL: name: s64_legal
; FP16: %a:_(s64) = COPY $d0
; FP16: liveins: $d0, $d1
; FP16-NEXT: {{ $}}
; FP16-NEXT: %a:_(s64) = COPY $d0
; FP16-NEXT: %b:_(s64) = COPY $d1
; FP16-NEXT: %legalize_me:_(s64) = G_FMAXIMUM %a, %b
; FP16-NEXT: $d0 = COPY %legalize_me(s64)
; FP16-NEXT: RET_ReallyLR implicit $d0
; NO-FP16-LABEL: name: s64_legal
; NO-FP16: %a:_(s64) = COPY $d0
; NO-FP16: liveins: $d0, $d1
; NO-FP16-NEXT: {{ $}}
; NO-FP16-NEXT: %a:_(s64) = COPY $d0
; NO-FP16-NEXT: %b:_(s64) = COPY $d1
; NO-FP16-NEXT: %legalize_me:_(s64) = G_FMAXIMUM %a, %b
; NO-FP16-NEXT: $d0 = COPY %legalize_me(s64)
Expand All @@ -78,3 +90,62 @@ body: |
%legalize_me:_(s64) = G_FMAXIMUM %a, %b
$d0 = COPY %legalize_me(s64)
RET_ReallyLR implicit $d0
...
---
name: v2s32
alignment: 4
body: |
bb.0:
liveins: $d0, $d1
; FP16-LABEL: name: v2s32
; FP16: liveins: $d0, $d1
; FP16-NEXT: {{ $}}
; FP16-NEXT: %a:_(<2 x s32>) = COPY $d0
; FP16-NEXT: %b:_(<2 x s32>) = COPY $d1
; FP16-NEXT: %maximum:_(<2 x s32>) = G_FMAXIMUM %a, %b
; FP16-NEXT: $d0 = COPY %maximum(<2 x s32>)
; FP16-NEXT: RET_ReallyLR implicit $d0
; NO-FP16-LABEL: name: v2s32
; NO-FP16: liveins: $d0, $d1
; NO-FP16-NEXT: {{ $}}
; NO-FP16-NEXT: %a:_(<2 x s32>) = COPY $d0
; NO-FP16-NEXT: %b:_(<2 x s32>) = COPY $d1
; NO-FP16-NEXT: %maximum:_(<2 x s32>) = G_FMAXIMUM %a, %b
; NO-FP16-NEXT: $d0 = COPY %maximum(<2 x s32>)
; NO-FP16-NEXT: RET_ReallyLR implicit $d0
%a:_(<2 x s32>) = COPY $d0
%b:_(<2 x s32>) = COPY $d1
%maximum:_(<2 x s32>) = G_FMAXIMUM %a, %b
$d0 = COPY %maximum(<2 x s32>)
RET_ReallyLR implicit $d0
...
---
name: v4s32
alignment: 4
body: |
bb.0:
liveins: $q0, $q1
; FP16-LABEL: name: v4s32
; FP16: liveins: $q0, $q1
; FP16-NEXT: {{ $}}
; FP16-NEXT: %a:_(<4 x s32>) = COPY $q0
; FP16-NEXT: %b:_(<4 x s32>) = COPY $q1
; FP16-NEXT: %maximum:_(<4 x s32>) = G_FMAXIMUM %a, %b
; FP16-NEXT: $q0 = COPY %maximum(<4 x s32>)
; FP16-NEXT: RET_ReallyLR implicit $q0
; NO-FP16-LABEL: name: v4s32
; NO-FP16: liveins: $q0, $q1
; NO-FP16-NEXT: {{ $}}
; NO-FP16-NEXT: %a:_(<4 x s32>) = COPY $q0
; NO-FP16-NEXT: %b:_(<4 x s32>) = COPY $q1
; NO-FP16-NEXT: %maximum:_(<4 x s32>) = G_FMAXIMUM %a, %b
; NO-FP16-NEXT: $q0 = COPY %maximum(<4 x s32>)
; NO-FP16-NEXT: RET_ReallyLR implicit $q0
%a:_(<4 x s32>) = COPY $q0
%b:_(<4 x s32>) = COPY $q1
%maximum:_(<4 x s32>) = G_FMAXIMUM %a, %b
$q0 = COPY %maximum(<4 x s32>)
RET_ReallyLR implicit $q0
...
98 changes: 92 additions & 6 deletions llvm/test/CodeGen/AArch64/GlobalISel/legalize-fminimum.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,13 +9,17 @@ body: |
bb.0:
liveins: $h0, $h1
; FP16-LABEL: name: s16_legal_with_full_fp16
; FP16: %a:_(s16) = COPY $h0
; FP16: liveins: $h0, $h1
; FP16-NEXT: {{ $}}
; FP16-NEXT: %a:_(s16) = COPY $h0
; FP16-NEXT: %b:_(s16) = COPY $h1
; FP16-NEXT: %legalize_me:_(s16) = G_FMINIMUM %a, %b
; FP16-NEXT: $h0 = COPY %legalize_me(s16)
; FP16-NEXT: RET_ReallyLR implicit $h0
; NO-FP16-LABEL: name: s16_legal_with_full_fp16
; NO-FP16: %a:_(s16) = COPY $h0
; NO-FP16: liveins: $h0, $h1
; NO-FP16-NEXT: {{ $}}
; NO-FP16-NEXT: %a:_(s16) = COPY $h0
; NO-FP16-NEXT: %b:_(s16) = COPY $h1
; NO-FP16-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT %a(s16)
; NO-FP16-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT %b(s16)
Expand All @@ -37,13 +41,17 @@ body: |
bb.0:
liveins: $s0, $s1
; FP16-LABEL: name: s32_legal
; FP16: %a:_(s32) = COPY $s0
; FP16: liveins: $s0, $s1
; FP16-NEXT: {{ $}}
; FP16-NEXT: %a:_(s32) = COPY $s0
; FP16-NEXT: %b:_(s32) = COPY $s1
; FP16-NEXT: %legalize_me:_(s32) = G_FMINIMUM %a, %b
; FP16-NEXT: $s0 = COPY %legalize_me(s32)
; FP16-NEXT: RET_ReallyLR implicit $s0
; NO-FP16-LABEL: name: s32_legal
; NO-FP16: %a:_(s32) = COPY $s0
; NO-FP16: liveins: $s0, $s1
; NO-FP16-NEXT: {{ $}}
; NO-FP16-NEXT: %a:_(s32) = COPY $s0
; NO-FP16-NEXT: %b:_(s32) = COPY $s1
; NO-FP16-NEXT: %legalize_me:_(s32) = G_FMINIMUM %a, %b
; NO-FP16-NEXT: $s0 = COPY %legalize_me(s32)
Expand All @@ -62,13 +70,17 @@ body: |
bb.0:
liveins: $d0, $d1
; FP16-LABEL: name: s64_legal
; FP16: %a:_(s64) = COPY $d0
; FP16: liveins: $d0, $d1
; FP16-NEXT: {{ $}}
; FP16-NEXT: %a:_(s64) = COPY $d0
; FP16-NEXT: %b:_(s64) = COPY $d1
; FP16-NEXT: %legalize_me:_(s64) = G_FMINIMUM %a, %b
; FP16-NEXT: $d0 = COPY %legalize_me(s64)
; FP16-NEXT: RET_ReallyLR implicit $d0
; NO-FP16-LABEL: name: s64_legal
; NO-FP16: %a:_(s64) = COPY $d0
; NO-FP16: liveins: $d0, $d1
; NO-FP16-NEXT: {{ $}}
; NO-FP16-NEXT: %a:_(s64) = COPY $d0
; NO-FP16-NEXT: %b:_(s64) = COPY $d1
; NO-FP16-NEXT: %legalize_me:_(s64) = G_FMINIMUM %a, %b
; NO-FP16-NEXT: $d0 = COPY %legalize_me(s64)
Expand All @@ -78,3 +90,77 @@ body: |
%legalize_me:_(s64) = G_FMINIMUM %a, %b
$d0 = COPY %legalize_me(s64)
RET_ReallyLR implicit $d0
...
---
name: v4s32
alignment: 4
body: |
bb.0:
liveins: $q0, $q1
; FP16-LABEL: name: v4s32
; FP16: liveins: $q0, $q1
; FP16-NEXT: {{ $}}
; FP16-NEXT: %a:_(<4 x s32>) = COPY $q0
; FP16-NEXT: %b:_(<4 x s32>) = COPY $q1
; FP16-NEXT: %minimum:_(<4 x s32>) = G_FMINIMUM %a, %b
; FP16-NEXT: $q0 = COPY %minimum(<4 x s32>)
; FP16-NEXT: RET_ReallyLR implicit $q0
; NO-FP16-LABEL: name: v4s32
; NO-FP16: liveins: $q0, $q1
; NO-FP16-NEXT: {{ $}}
; NO-FP16-NEXT: %a:_(<4 x s32>) = COPY $q0
; NO-FP16-NEXT: %b:_(<4 x s32>) = COPY $q1
; NO-FP16-NEXT: %minimum:_(<4 x s32>) = G_FMINIMUM %a, %b
; NO-FP16-NEXT: $q0 = COPY %minimum(<4 x s32>)
; NO-FP16-NEXT: RET_ReallyLR implicit $q0
%a:_(<4 x s32>) = COPY $q0
%b:_(<4 x s32>) = COPY $q1
%minimum:_(<4 x s32>) = G_FMINIMUM %a, %b
$q0 = COPY %minimum(<4 x s32>)
RET_ReallyLR implicit $q0
...

---
name: v8s32
alignment: 4
body: |
bb.0:
liveins: $q0, $q1, $q2, $q3
; FP16-LABEL: name: v8s32
; FP16: liveins: $q0, $q1, $q2, $q3
; FP16-NEXT: {{ $}}
; FP16-NEXT: %a:_(<4 x s32>) = COPY $q0
; FP16-NEXT: %b:_(<4 x s32>) = COPY $q1
; FP16-NEXT: %c:_(<4 x s32>) = COPY $q2
; FP16-NEXT: %d:_(<4 x s32>) = COPY $q3
; FP16-NEXT: [[FMINIMUM:%[0-9]+]]:_(<4 x s32>) = G_FMINIMUM %a, %c
; FP16-NEXT: [[FMINIMUM1:%[0-9]+]]:_(<4 x s32>) = G_FMINIMUM %b, %d
; FP16-NEXT: $q0 = COPY [[FMINIMUM]](<4 x s32>)
; FP16-NEXT: $q1 = COPY [[FMINIMUM1]](<4 x s32>)
; FP16-NEXT: RET_ReallyLR implicit $q0
; NO-FP16-LABEL: name: v8s32
; NO-FP16: liveins: $q0, $q1, $q2, $q3
; NO-FP16-NEXT: {{ $}}
; NO-FP16-NEXT: %a:_(<4 x s32>) = COPY $q0
; NO-FP16-NEXT: %b:_(<4 x s32>) = COPY $q1
; NO-FP16-NEXT: %c:_(<4 x s32>) = COPY $q2
; NO-FP16-NEXT: %d:_(<4 x s32>) = COPY $q3
; NO-FP16-NEXT: [[FMINIMUM:%[0-9]+]]:_(<4 x s32>) = G_FMINIMUM %a, %c
; NO-FP16-NEXT: [[FMINIMUM1:%[0-9]+]]:_(<4 x s32>) = G_FMINIMUM %b, %d
; NO-FP16-NEXT: $q0 = COPY [[FMINIMUM]](<4 x s32>)
; NO-FP16-NEXT: $q1 = COPY [[FMINIMUM1]](<4 x s32>)
; NO-FP16-NEXT: RET_ReallyLR implicit $q0
%a:_(<4 x s32>) = COPY $q0
%b:_(<4 x s32>) = COPY $q1
%c:_(<4 x s32>) = COPY $q2
%d:_(<4 x s32>) = COPY $q3
%v1:_(<8 x s32>) = G_CONCAT_VECTORS %a, %b
%v2:_(<8 x s32>) = G_CONCAT_VECTORS %c, %d
%minimum:_(<8 x s32>) = G_FMINIMUM %v1, %v2
%uv1:_(<4 x s32>), %uv2:_(<4 x s32>) = G_UNMERGE_VALUES %minimum
$q0 = COPY %uv1(<4 x s32>)
$q1 = COPY %uv2(<4 x s32>)
RET_ReallyLR implicit $q0
...
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -510,11 +510,11 @@
# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
# DEBUG-NEXT: G_FMINIMUM (opcode {{[0-9]+}}): 1 type index
# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
# DEBUG-NEXT: .. the first uncovered type index: 1, OK
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: G_FMAXIMUM (opcode {{[0-9]+}}): 1 type index
# DEBUG-NEXT: .. the first uncovered type index: 1, OK
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: G_PTR_ADD (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
# DEBUG-NEXT: .. the first uncovered type index: 2, OK
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
Expand Down
146 changes: 146 additions & 0 deletions llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-sext-of-vcmp.mir
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,146 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
---
name: sext_of_fcmp_v4s32
legalized: true
liveins:
- { reg: '$q0' }
- { reg: '$x0' }
- { reg: '$x1' }
- { reg: '$x2' }
body: |
bb.1:
liveins: $q0, $x0, $x1, $x2
; CHECK-LABEL: name: sext_of_fcmp_v4s32
; CHECK: liveins: $q0, $x0, $x1, $x2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 6.000000e+00
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(<4 x s32>) = G_FCMP floatpred(ogt), [[COPY]](<4 x s32>), [[BUILD_VECTOR]]
; CHECK-NEXT: $q0 = COPY [[FCMP]](<4 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:_(<4 x s32>) = COPY $q0
%6:_(s32) = G_FCONSTANT float 6.000000e+00
%5:_(<4 x s32>) = G_BUILD_VECTOR %6(s32), %6(s32), %6(s32), %6(s32)
%17:_(<4 x s32>) = G_FCMP floatpred(ogt), %0(<4 x s32>), %5
%19:_(s32) = G_CONSTANT i32 31
%20:_(<4 x s32>) = G_BUILD_VECTOR %19(s32), %19(s32), %19(s32), %19(s32)
%18:_(<4 x s32>) = G_SHL %17, %20(<4 x s32>)
%11:_(<4 x s32>) = G_ASHR %18, %20(<4 x s32>)
$q0 = COPY %11(<4 x s32>)
RET_ReallyLR implicit $q0
...
---
name: sext_of_icmp_v4s32
legalized: true
liveins:
- { reg: '$q0' }
- { reg: '$x0' }
- { reg: '$x1' }
- { reg: '$x2' }
body: |
bb.1:
liveins: $q0, $x0, $x1, $x2
; CHECK-LABEL: name: sext_of_icmp_v4s32
; CHECK: liveins: $q0, $x0, $x1, $x2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(eq), [[COPY]](<4 x s32>), [[BUILD_VECTOR]]
; CHECK-NEXT: $q0 = COPY [[ICMP]](<4 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:_(<4 x s32>) = COPY $q0
%6:_(s32) = G_CONSTANT i32 42
%5:_(<4 x s32>) = G_BUILD_VECTOR %6(s32), %6(s32), %6(s32), %6(s32)
%17:_(<4 x s32>) = G_ICMP intpred(eq), %0(<4 x s32>), %5
%19:_(s32) = G_CONSTANT i32 31
%20:_(<4 x s32>) = G_BUILD_VECTOR %19(s32), %19(s32), %19(s32), %19(s32)
%18:_(<4 x s32>) = G_SHL %17, %20(<4 x s32>)
%11:_(<4 x s32>) = G_ASHR %18, %20(<4 x s32>)
$q0 = COPY %11(<4 x s32>)
RET_ReallyLR implicit $q0
...
---
name: sext_of_fcmp_wrong_shift
legalized: true
liveins:
- { reg: '$q0' }
- { reg: '$x0' }
- { reg: '$x1' }
- { reg: '$x2' }
body: |
bb.1:
liveins: $q0, $x0, $x1, $x2
; CHECK-LABEL: name: sext_of_fcmp_wrong_shift
; CHECK: liveins: $q0, $x0, $x1, $x2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 6.000000e+00
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(<4 x s32>) = G_FCMP floatpred(ogt), [[COPY]](<4 x s32>), [[BUILD_VECTOR]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 29
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32), [[C1]](s32), [[C1]](s32)
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(<4 x s32>) = G_SHL [[FCMP]], [[BUILD_VECTOR1]](<4 x s32>)
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(<4 x s32>) = G_ASHR [[SHL]], [[BUILD_VECTOR1]](<4 x s32>)
; CHECK-NEXT: $q0 = COPY [[ASHR]](<4 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:_(<4 x s32>) = COPY $q0
%6:_(s32) = G_FCONSTANT float 6.000000e+00
%5:_(<4 x s32>) = G_BUILD_VECTOR %6(s32), %6(s32), %6(s32), %6(s32)
%17:_(<4 x s32>) = G_FCMP floatpred(ogt), %0(<4 x s32>), %5
%19:_(s32) = G_CONSTANT i32 29
%20:_(<4 x s32>) = G_BUILD_VECTOR %19(s32), %19(s32), %19(s32), %19(s32)
%18:_(<4 x s32>) = G_SHL %17, %20(<4 x s32>)
%11:_(<4 x s32>) = G_ASHR %18, %20(<4 x s32>)
$q0 = COPY %11(<4 x s32>)
RET_ReallyLR implicit $q0
...
---
name: sext_of_fcmp_mismatch_shift
legalized: true
liveins:
- { reg: '$q0' }
- { reg: '$x0' }
- { reg: '$x1' }
- { reg: '$x2' }
body: |
bb.1:
liveins: $q0, $x0, $x1, $x2
; CHECK-LABEL: name: sext_of_fcmp_mismatch_shift
; CHECK: liveins: $q0, $x0, $x1, $x2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 6.000000e+00
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(<4 x s32>) = G_FCMP floatpred(ogt), [[COPY]](<4 x s32>), [[BUILD_VECTOR]]
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 29
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32), [[C1]](s32), [[C1]](s32)
; CHECK-NEXT: %cst2:_(s32) = G_CONSTANT i32 31
; CHECK-NEXT: %cstv2:_(<4 x s32>) = G_BUILD_VECTOR %cst2(s32), %cst2(s32), %cst2(s32), %cst2(s32)
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(<4 x s32>) = G_SHL [[FCMP]], [[BUILD_VECTOR1]](<4 x s32>)
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(<4 x s32>) = G_ASHR [[SHL]], %cstv2(<4 x s32>)
; CHECK-NEXT: $q0 = COPY [[ASHR]](<4 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:_(<4 x s32>) = COPY $q0
%6:_(s32) = G_FCONSTANT float 6.000000e+00
%5:_(<4 x s32>) = G_BUILD_VECTOR %6(s32), %6(s32), %6(s32), %6(s32)
%17:_(<4 x s32>) = G_FCMP floatpred(ogt), %0(<4 x s32>), %5
%19:_(s32) = G_CONSTANT i32 29
%20:_(<4 x s32>) = G_BUILD_VECTOR %19(s32), %19(s32), %19(s32), %19(s32)
%cst2:_(s32) = G_CONSTANT i32 31
%cstv2:_(<4 x s32>) = G_BUILD_VECTOR %cst2(s32), %cst2(s32), %cst2(s32), %cst2(s32)
%18:_(<4 x s32>) = G_SHL %17, %20(<4 x s32>)
%11:_(<4 x s32>) = G_ASHR %18, %cstv2(<4 x s32>)
$q0 = COPY %11(<4 x s32>)
RET_ReallyLR implicit $q0
...
188 changes: 188 additions & 0 deletions llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-select-to-fminmax.mir
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,188 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -mattr=+fullfp16 -run-pass=aarch64-prelegalizer-combiner -global-isel -verify-machineinstrs %s -o - | FileCheck %s
---
name: test_s16
body: |
bb.0:
liveins: $h0
; CHECK-LABEL: name: test_s16
; CHECK: liveins: $h0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $h0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
; CHECK-NEXT: [[FMAXIMUM:%[0-9]+]]:_(s16) = G_FMAXIMUM [[C]], [[COPY]]
; CHECK-NEXT: $h0 = COPY [[FMAXIMUM]](s16)
; CHECK-NEXT: RET_ReallyLR implicit $h0
%0:_(s16) = COPY $h0
%1:_(s16) = G_FCONSTANT half 0xH0000
%2:_(s1) = G_FCMP floatpred(olt), %0(s16), %1
%3:_(s16) = G_SELECT %2(s1), %1, %0
$h0 = COPY %3(s16)
RET_ReallyLR implicit $h0
...
---
name: test_s32
body: |
bb.0:
liveins: $s0
; CHECK-LABEL: name: test_s32
; CHECK: liveins: $s0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
; CHECK-NEXT: [[FMAXIMUM:%[0-9]+]]:_(s32) = G_FMAXIMUM [[C]], [[COPY]]
; CHECK-NEXT: $s0 = COPY [[FMAXIMUM]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $s0
%0:_(s32) = COPY $s0
%1:_(s32) = G_FCONSTANT float 0.000000e+00
%2:_(s1) = G_FCMP floatpred(olt), %0(s32), %1
%3:_(s32) = G_SELECT %2(s1), %1, %0
$s0 = COPY %3(s32)
RET_ReallyLR implicit $s0
...
---
name: test_s64
body: |
bb.0:
liveins: $d0
; CHECK-LABEL: name: test_s64
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00
; CHECK-NEXT: [[FMAXIMUM:%[0-9]+]]:_(s64) = G_FMAXIMUM [[C]], [[COPY]]
; CHECK-NEXT: $d0 = COPY [[FMAXIMUM]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:_(s64) = COPY $d0
%1:_(s64) = G_FCONSTANT double 0.000000e+00
%2:_(s1) = G_FCMP floatpred(olt), %0(s64), %1
%3:_(s64) = G_SELECT %2(s1), %1, %0
$d0 = COPY %3(s64)
RET_ReallyLR implicit $d0
...
---
name: test_s64_fmin
body: |
bb.0:
liveins: $d0
; CHECK-LABEL: name: test_s64_fmin
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00
; CHECK-NEXT: [[FMINIMUM:%[0-9]+]]:_(s64) = G_FMINIMUM [[C]], [[COPY]]
; CHECK-NEXT: $d0 = COPY [[FMINIMUM]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%0:_(s64) = COPY $d0
%1:_(s64) = G_FCONSTANT double 0.000000e+00
%2:_(s1) = G_FCMP floatpred(ogt), %0(s64), %1
%3:_(s64) = G_SELECT %2(s1), %1, %0
$d0 = COPY %3(s64)
RET_ReallyLR implicit $d0
...
---
name: test_v8s16
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: test_v8s16
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16)
; CHECK-NEXT: [[FMAXIMUM:%[0-9]+]]:_(<8 x s16>) = G_FMAXIMUM [[BUILD_VECTOR]], [[COPY]]
; CHECK-NEXT: $q0 = COPY [[FMAXIMUM]](<8 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:_(<8 x s16>) = COPY $q0
%2:_(s16) = G_FCONSTANT half 0xH0000
%1:_(<8 x s16>) = G_BUILD_VECTOR %2(s16), %2(s16), %2(s16), %2(s16), %2(s16), %2(s16), %2(s16), %2(s16)
%3:_(<8 x s1>) = G_FCMP floatpred(olt), %0(<8 x s16>), %1
%4:_(<8 x s16>) = G_SELECT %3(<8 x s1>), %1, %0
$q0 = COPY %4(<8 x s16>)
RET_ReallyLR implicit $q0
...
---
name: test_v4s32
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: test_v4s32
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY]](<2 x s64>)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK-NEXT: [[FMAXIMUM:%[0-9]+]]:_(<4 x s32>) = G_FMAXIMUM [[BUILD_VECTOR]], [[BITCAST]]
; CHECK-NEXT: $q0 = COPY [[FMAXIMUM]](<4 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%1:_(<2 x s64>) = COPY $q0
%0:_(<4 x s32>) = G_BITCAST %1(<2 x s64>)
%3:_(s32) = G_FCONSTANT float 0.000000e+00
%2:_(<4 x s32>) = G_BUILD_VECTOR %3(s32), %3(s32), %3(s32), %3(s32)
%4:_(<4 x s1>) = G_FCMP floatpred(olt), %0(<4 x s32>), %2
%5:_(<4 x s32>) = G_SELECT %4(<4 x s1>), %2, %0
$q0 = COPY %5(<4 x s32>)
RET_ReallyLR implicit $q0
...
---
name: test_v2s64
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: test_v2s64
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
; CHECK-NEXT: [[FMAXIMUM:%[0-9]+]]:_(<2 x s64>) = G_FMAXIMUM [[BUILD_VECTOR]], [[COPY]]
; CHECK-NEXT: $q0 = COPY [[FMAXIMUM]](<2 x s64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:_(<2 x s64>) = COPY $q0
%2:_(s64) = G_FCONSTANT double 0.000000e+00
%1:_(<2 x s64>) = G_BUILD_VECTOR %2(s64), %2(s64)
%3:_(<2 x s1>) = G_FCMP floatpred(olt), %0(<2 x s64>), %1
%4:_(<2 x s64>) = G_SELECT %3(<2 x s1>), %1, %0
$q0 = COPY %4(<2 x s64>)
RET_ReallyLR implicit $q0
...
---
name: test_v2s64_fmin
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: test_v2s64_fmin
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
; CHECK-NEXT: [[FMINIMUM:%[0-9]+]]:_(<2 x s64>) = G_FMINIMUM [[BUILD_VECTOR]], [[COPY]]
; CHECK-NEXT: $q0 = COPY [[FMINIMUM]](<2 x s64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:_(<2 x s64>) = COPY $q0
%2:_(s64) = G_FCONSTANT double 0.000000e+00
%1:_(<2 x s64>) = G_BUILD_VECTOR %2(s64), %2(s64)
%3:_(<2 x s1>) = G_FCMP floatpred(ogt), %0(<2 x s64>), %1
%4:_(<2 x s64>) = G_SELECT %3(<2 x s1>), %1, %0
$q0 = COPY %4(<2 x s64>)
RET_ReallyLR implicit $q0
...
103 changes: 103 additions & 0 deletions llvm/test/CodeGen/AArch64/GlobalISel/select-to-fmin-fmax.ll
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,103 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple aarch64 -mattr=+fullfp16 -global-isel -global-isel-abort=1 -verify-machineinstrs %s -o - | FileCheck %s
define half @test_s16(half %a) #0 {
; CHECK-LABEL: test_s16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movi d1, #0000000000000000
; CHECK-NEXT: fmax h0, h1, h0
; CHECK-NEXT: ret
entry:
%fcmp = fcmp olt half %a, 0.0
%sel = select i1 %fcmp, half 0.0, half %a
ret half %sel
}

define float @test_s32(float %a) #0 {
; CHECK-LABEL: test_s32:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movi d1, #0000000000000000
; CHECK-NEXT: fmax s0, s1, s0
; CHECK-NEXT: ret
entry:
%fcmp = fcmp olt float %a, 0.0
%sel = select i1 %fcmp, float 0.0, float %a
ret float %sel
}

define double @test_s64(double %a) #0 {
; CHECK-LABEL: test_s64:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movi d1, #0000000000000000
; CHECK-NEXT: fmax d0, d1, d0
; CHECK-NEXT: ret
entry:
%fcmp = fcmp olt double %a, 0.0
%sel = select i1 %fcmp, double 0.0, double %a
ret double %sel
}

define <4 x half> @test_v4s16(<4 x half> %a) #0 {
; CHECK-LABEL: test_v4s16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movi d1, #0000000000000000
; CHECK-NEXT: dup v1.4h, v1.h[0]
; CHECK-NEXT: fmax v0.4h, v1.4h, v0.4h
; CHECK-NEXT: ret
entry:
%fcmp = fcmp olt <4 x half> %a, zeroinitializer
%sel = select <4 x i1> %fcmp, <4 x half> zeroinitializer, <4 x half> %a
ret <4 x half> %sel
}

define <8 x half> @test_v8s16(<8 x half> %a) #0 {
; CHECK-LABEL: test_v8s16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movi d1, #0000000000000000
; CHECK-NEXT: dup v1.8h, v1.h[0]
; CHECK-NEXT: fmax v0.8h, v1.8h, v0.8h
; CHECK-NEXT: ret
entry:
%fcmp = fcmp olt <8 x half> %a, zeroinitializer
%sel = select <8 x i1> %fcmp, <8 x half> zeroinitializer, <8 x half> %a
ret <8 x half> %sel
}

define <2 x float> @test_v2s32(<2 x float> %a) #0 {
; CHECK-LABEL: test_v2s32:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movi d1, #0000000000000000
; CHECK-NEXT: dup v1.2s, v1.s[0]
; CHECK-NEXT: fmax v0.2s, v1.2s, v0.2s
; CHECK-NEXT: ret
entry:
%fcmp = fcmp olt <2 x float> %a, zeroinitializer
%sel = select <2 x i1> %fcmp, <2 x float> zeroinitializer, <2 x float> %a
ret <2 x float> %sel
}

define <4 x float> @test_v4s32(<4 x float> %a) #0 {
; CHECK-LABEL: test_v4s32:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movi d1, #0000000000000000
; CHECK-NEXT: dup v1.4s, v1.s[0]
; CHECK-NEXT: fmax v0.4s, v1.4s, v0.4s
; CHECK-NEXT: ret
entry:
%fcmp = fcmp olt <4 x float> %a, zeroinitializer
%sel = select <4 x i1> %fcmp, <4 x float> zeroinitializer, <4 x float> %a
ret <4 x float> %sel
}

define <2 x double> @test_v2s64(<2 x double> %a) #0 {
; CHECK-LABEL: test_v2s64:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movi d1, #0000000000000000
; CHECK-NEXT: dup v1.2d, v1.d[0]
; CHECK-NEXT: fmax v0.2d, v1.2d, v0.2d
; CHECK-NEXT: ret
entry:
%fcmp = fcmp olt <2 x double> %a, zeroinitializer
%sel = select <2 x i1> %fcmp, <2 x double> zeroinitializer, <2 x double> %a
ret <2 x double> %sel
}

22 changes: 2 additions & 20 deletions llvm/test/CodeGen/AArch64/arm64-vabs.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -305,8 +305,6 @@ define i32 @uabdl4s_rdx_i32(<4 x i16> %a, <4 x i16> %b) {
; GISEL-NEXT: usubl.4s v0, v0, v1
; GISEL-NEXT: cmgt.4s v1, v2, v0
; GISEL-NEXT: neg.4s v2, v0
; GISEL-NEXT: shl.4s v1, v1, #31
; GISEL-NEXT: sshr.4s v1, v1, #31
; GISEL-NEXT: bit.16b v0, v2, v1
; GISEL-NEXT: addv.4s s0, v0
; GISEL-NEXT: fmov w0, s0
Expand Down Expand Up @@ -378,8 +376,6 @@ define i64 @uabdl2d_rdx_i64(<2 x i32> %a, <2 x i32> %b) {
; GISEL-NEXT: usubl.2d v0, v0, v1
; GISEL-NEXT: cmgt.2d v1, v2, v0
; GISEL-NEXT: neg.2d v2, v0
; GISEL-NEXT: shl.2d v1, v1, #63
; GISEL-NEXT: sshr.2d v1, v1, #63
; GISEL-NEXT: bit.16b v0, v2, v1
; GISEL-NEXT: addp.2d d0, v0
; GISEL-NEXT: fmov x0, d0
Expand Down Expand Up @@ -1575,8 +1571,6 @@ define <2 x i32> @abspattern1(<2 x i32> %a) nounwind {
; GISEL-NEXT: movi.2d v1, #0000000000000000
; GISEL-NEXT: neg.2s v2, v0
; GISEL-NEXT: cmge.2s v1, v0, v1
; GISEL-NEXT: shl.2s v1, v1, #31
; GISEL-NEXT: sshr.2s v1, v1, #31
; GISEL-NEXT: bif.8b v0, v2, v1
; GISEL-NEXT: ret

Expand All @@ -1597,8 +1591,6 @@ define <4 x i16> @abspattern2(<4 x i16> %a) nounwind {
; GISEL-NEXT: movi.2d v1, #0000000000000000
; GISEL-NEXT: neg.4h v2, v0
; GISEL-NEXT: cmgt.4h v1, v0, v1
; GISEL-NEXT: shl.4h v1, v1, #15
; GISEL-NEXT: sshr.4h v1, v1, #15
; GISEL-NEXT: bif.8b v0, v2, v1
; GISEL-NEXT: ret
; For GlobalISel, this generates terrible code until we can pattern match this to abs.
Expand All @@ -1620,8 +1612,6 @@ define <8 x i8> @abspattern3(<8 x i8> %a) nounwind {
; GISEL-NEXT: movi.2d v1, #0000000000000000
; GISEL-NEXT: neg.8b v2, v0
; GISEL-NEXT: cmgt.8b v1, v1, v0
; GISEL-NEXT: shl.8b v1, v1, #7
; GISEL-NEXT: sshr.8b v1, v1, #7
; GISEL-NEXT: bit.8b v0, v2, v1
; GISEL-NEXT: ret

Expand All @@ -1642,8 +1632,6 @@ define <4 x i32> @abspattern4(<4 x i32> %a) nounwind {
; GISEL-NEXT: movi.2d v1, #0000000000000000
; GISEL-NEXT: neg.4s v2, v0
; GISEL-NEXT: cmge.4s v1, v0, v1
; GISEL-NEXT: shl.4s v1, v1, #31
; GISEL-NEXT: sshr.4s v1, v1, #31
; GISEL-NEXT: bif.16b v0, v2, v1
; GISEL-NEXT: ret

Expand All @@ -1664,8 +1652,6 @@ define <8 x i16> @abspattern5(<8 x i16> %a) nounwind {
; GISEL-NEXT: movi.2d v1, #0000000000000000
; GISEL-NEXT: neg.8h v2, v0
; GISEL-NEXT: cmgt.8h v1, v0, v1
; GISEL-NEXT: shl.8h v1, v1, #15
; GISEL-NEXT: sshr.8h v1, v1, #15
; GISEL-NEXT: bif.16b v0, v2, v1
; GISEL-NEXT: ret

Expand All @@ -1686,8 +1672,6 @@ define <16 x i8> @abspattern6(<16 x i8> %a) nounwind {
; GISEL-NEXT: movi.2d v1, #0000000000000000
; GISEL-NEXT: neg.16b v2, v0
; GISEL-NEXT: cmgt.16b v1, v1, v0
; GISEL-NEXT: shl.16b v1, v1, #7
; GISEL-NEXT: sshr.16b v1, v1, #7
; GISEL-NEXT: bit.16b v0, v2, v1
; GISEL-NEXT: ret

Expand All @@ -1708,8 +1692,6 @@ define <2 x i64> @abspattern7(<2 x i64> %a) nounwind {
; GISEL-NEXT: movi.2d v1, #0000000000000000
; GISEL-NEXT: neg.2d v2, v0
; GISEL-NEXT: cmge.2d v1, v1, v0
; GISEL-NEXT: shl.2d v1, v1, #63
; GISEL-NEXT: sshr.2d v1, v1, #63
; GISEL-NEXT: bit.16b v0, v2, v1
; GISEL-NEXT: ret

Expand All @@ -1731,8 +1713,6 @@ define <2 x i64> @uabd_i32(<2 x i32> %a, <2 x i32> %b) {
; GISEL-NEXT: ssubl.2d v0, v0, v1
; GISEL-NEXT: cmgt.2d v1, v2, v0
; GISEL-NEXT: neg.2d v2, v0
; GISEL-NEXT: shl.2d v1, v1, #63
; GISEL-NEXT: sshr.2d v1, v1, #63
; GISEL-NEXT: bit.16b v0, v2, v1
; GISEL-NEXT: ret
%aext = sext <2 x i32> %a to <2 x i64>
Expand Down Expand Up @@ -1782,3 +1762,5 @@ define <2 x i128> @uabd_i64(<2 x i64> %a, <2 x i64> %b) {
%absel = select <2 x i1> %abcmp, <2 x i128> %ababs, <2 x i128> %abdiff
ret <2 x i128> %absel
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; FALLBACK: {{.*}}
88 changes: 20 additions & 68 deletions llvm/test/CodeGen/AArch64/min-max.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -224,19 +224,11 @@ define <1 x i64> @smax1i64(<1 x i64> %a, <1 x i64> %b) {
declare <2 x i64> @llvm.smax.v2i64(<2 x i64> %a, <2 x i64> %b) readnone

define <2 x i64> @smax2i64(<2 x i64> %a, <2 x i64> %b) {
; CHECK-ISEL-LABEL: smax2i64:
; CHECK-ISEL: // %bb.0:
; CHECK-ISEL-NEXT: cmgt v2.2d, v0.2d, v1.2d
; CHECK-ISEL-NEXT: bif v0.16b, v1.16b, v2.16b
; CHECK-ISEL-NEXT: ret
;
; CHECK-GLOBAL-LABEL: smax2i64:
; CHECK-GLOBAL: // %bb.0:
; CHECK-GLOBAL-NEXT: cmgt v2.2d, v0.2d, v1.2d
; CHECK-GLOBAL-NEXT: shl v2.2d, v2.2d, #63
; CHECK-GLOBAL-NEXT: sshr v2.2d, v2.2d, #63
; CHECK-GLOBAL-NEXT: bif v0.16b, v1.16b, v2.16b
; CHECK-GLOBAL-NEXT: ret
; CHECK-LABEL: smax2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cmgt v2.2d, v0.2d, v1.2d
; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b
; CHECK-NEXT: ret
%c = call <2 x i64> @llvm.smax.v2i64(<2 x i64> %a, <2 x i64> %b)
ret <2 x i64> %c
}
Expand All @@ -257,10 +249,6 @@ define void @smax4i64(<4 x i64> %a, <4 x i64> %b, <4 x i64>* %p) {
; CHECK-GLOBAL: // %bb.0:
; CHECK-GLOBAL-NEXT: cmgt v4.2d, v0.2d, v2.2d
; CHECK-GLOBAL-NEXT: cmgt v5.2d, v1.2d, v3.2d
; CHECK-GLOBAL-NEXT: shl v4.2d, v4.2d, #63
; CHECK-GLOBAL-NEXT: shl v5.2d, v5.2d, #63
; CHECK-GLOBAL-NEXT: sshr v4.2d, v4.2d, #63
; CHECK-GLOBAL-NEXT: sshr v5.2d, v5.2d, #63
; CHECK-GLOBAL-NEXT: bif v0.16b, v2.16b, v4.16b
; CHECK-GLOBAL-NEXT: bif v1.16b, v3.16b, v5.16b
; CHECK-GLOBAL-NEXT: stp q0, q1, [x0]
Expand Down Expand Up @@ -488,19 +476,11 @@ define <1 x i64> @umax1i64(<1 x i64> %a, <1 x i64> %b) {
declare <2 x i64> @llvm.umax.v2i64(<2 x i64> %a, <2 x i64> %b) readnone

define <2 x i64> @umax2i64(<2 x i64> %a, <2 x i64> %b) {
; CHECK-ISEL-LABEL: umax2i64:
; CHECK-ISEL: // %bb.0:
; CHECK-ISEL-NEXT: cmhi v2.2d, v0.2d, v1.2d
; CHECK-ISEL-NEXT: bif v0.16b, v1.16b, v2.16b
; CHECK-ISEL-NEXT: ret
;
; CHECK-GLOBAL-LABEL: umax2i64:
; CHECK-GLOBAL: // %bb.0:
; CHECK-GLOBAL-NEXT: cmhi v2.2d, v0.2d, v1.2d
; CHECK-GLOBAL-NEXT: shl v2.2d, v2.2d, #63
; CHECK-GLOBAL-NEXT: sshr v2.2d, v2.2d, #63
; CHECK-GLOBAL-NEXT: bif v0.16b, v1.16b, v2.16b
; CHECK-GLOBAL-NEXT: ret
; CHECK-LABEL: umax2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cmhi v2.2d, v0.2d, v1.2d
; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b
; CHECK-NEXT: ret
%c = call <2 x i64> @llvm.umax.v2i64(<2 x i64> %a, <2 x i64> %b)
ret <2 x i64> %c
}
Expand All @@ -521,10 +501,6 @@ define void @umax4i64(<4 x i64> %a, <4 x i64> %b, <4 x i64>* %p) {
; CHECK-GLOBAL: // %bb.0:
; CHECK-GLOBAL-NEXT: cmhi v4.2d, v0.2d, v2.2d
; CHECK-GLOBAL-NEXT: cmhi v5.2d, v1.2d, v3.2d
; CHECK-GLOBAL-NEXT: shl v4.2d, v4.2d, #63
; CHECK-GLOBAL-NEXT: shl v5.2d, v5.2d, #63
; CHECK-GLOBAL-NEXT: sshr v4.2d, v4.2d, #63
; CHECK-GLOBAL-NEXT: sshr v5.2d, v5.2d, #63
; CHECK-GLOBAL-NEXT: bif v0.16b, v2.16b, v4.16b
; CHECK-GLOBAL-NEXT: bif v1.16b, v3.16b, v5.16b
; CHECK-GLOBAL-NEXT: stp q0, q1, [x0]
Expand Down Expand Up @@ -752,19 +728,11 @@ define <1 x i64> @smin1i64(<1 x i64> %a, <1 x i64> %b) {
declare <2 x i64> @llvm.smin.v2i64(<2 x i64> %a, <2 x i64> %b) readnone

define <2 x i64> @smin2i64(<2 x i64> %a, <2 x i64> %b) {
; CHECK-ISEL-LABEL: smin2i64:
; CHECK-ISEL: // %bb.0:
; CHECK-ISEL-NEXT: cmgt v2.2d, v1.2d, v0.2d
; CHECK-ISEL-NEXT: bif v0.16b, v1.16b, v2.16b
; CHECK-ISEL-NEXT: ret
;
; CHECK-GLOBAL-LABEL: smin2i64:
; CHECK-GLOBAL: // %bb.0:
; CHECK-GLOBAL-NEXT: cmgt v2.2d, v1.2d, v0.2d
; CHECK-GLOBAL-NEXT: shl v2.2d, v2.2d, #63
; CHECK-GLOBAL-NEXT: sshr v2.2d, v2.2d, #63
; CHECK-GLOBAL-NEXT: bif v0.16b, v1.16b, v2.16b
; CHECK-GLOBAL-NEXT: ret
; CHECK-LABEL: smin2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cmgt v2.2d, v1.2d, v0.2d
; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b
; CHECK-NEXT: ret
%c = call <2 x i64> @llvm.smin.v2i64(<2 x i64> %a, <2 x i64> %b)
ret <2 x i64> %c
}
Expand All @@ -785,10 +753,6 @@ define void @smin4i64(<4 x i64> %a, <4 x i64> %b, <4 x i64>* %p) {
; CHECK-GLOBAL: // %bb.0:
; CHECK-GLOBAL-NEXT: cmgt v4.2d, v2.2d, v0.2d
; CHECK-GLOBAL-NEXT: cmgt v5.2d, v3.2d, v1.2d
; CHECK-GLOBAL-NEXT: shl v4.2d, v4.2d, #63
; CHECK-GLOBAL-NEXT: shl v5.2d, v5.2d, #63
; CHECK-GLOBAL-NEXT: sshr v4.2d, v4.2d, #63
; CHECK-GLOBAL-NEXT: sshr v5.2d, v5.2d, #63
; CHECK-GLOBAL-NEXT: bif v0.16b, v2.16b, v4.16b
; CHECK-GLOBAL-NEXT: bif v1.16b, v3.16b, v5.16b
; CHECK-GLOBAL-NEXT: stp q0, q1, [x0]
Expand Down Expand Up @@ -1016,19 +980,11 @@ define <1 x i64> @umin1i64(<1 x i64> %a, <1 x i64> %b) {
declare <2 x i64> @llvm.umin.v2i64(<2 x i64> %a, <2 x i64> %b) readnone

define <2 x i64> @umin2i64(<2 x i64> %a, <2 x i64> %b) {
; CHECK-ISEL-LABEL: umin2i64:
; CHECK-ISEL: // %bb.0:
; CHECK-ISEL-NEXT: cmhi v2.2d, v1.2d, v0.2d
; CHECK-ISEL-NEXT: bif v0.16b, v1.16b, v2.16b
; CHECK-ISEL-NEXT: ret
;
; CHECK-GLOBAL-LABEL: umin2i64:
; CHECK-GLOBAL: // %bb.0:
; CHECK-GLOBAL-NEXT: cmhi v2.2d, v1.2d, v0.2d
; CHECK-GLOBAL-NEXT: shl v2.2d, v2.2d, #63
; CHECK-GLOBAL-NEXT: sshr v2.2d, v2.2d, #63
; CHECK-GLOBAL-NEXT: bif v0.16b, v1.16b, v2.16b
; CHECK-GLOBAL-NEXT: ret
; CHECK-LABEL: umin2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cmhi v2.2d, v1.2d, v0.2d
; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b
; CHECK-NEXT: ret
%c = call <2 x i64> @llvm.umin.v2i64(<2 x i64> %a, <2 x i64> %b)
ret <2 x i64> %c
}
Expand All @@ -1049,10 +1005,6 @@ define void @umin4i64(<4 x i64> %a, <4 x i64> %b, <4 x i64>* %p) {
; CHECK-GLOBAL: // %bb.0:
; CHECK-GLOBAL-NEXT: cmhi v4.2d, v2.2d, v0.2d
; CHECK-GLOBAL-NEXT: cmhi v5.2d, v3.2d, v1.2d
; CHECK-GLOBAL-NEXT: shl v4.2d, v4.2d, #63
; CHECK-GLOBAL-NEXT: shl v5.2d, v5.2d, #63
; CHECK-GLOBAL-NEXT: sshr v4.2d, v4.2d, #63
; CHECK-GLOBAL-NEXT: sshr v5.2d, v5.2d, #63
; CHECK-GLOBAL-NEXT: bif v0.16b, v2.16b, v4.16b
; CHECK-GLOBAL-NEXT: bif v1.16b, v3.16b, v5.16b
; CHECK-GLOBAL-NEXT: stp q0, q1, [x0]
Expand Down
630 changes: 0 additions & 630 deletions llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
View file

Large diffs are not rendered by default.