271 changes: 271 additions & 0 deletions llvm/test/CodeGen/RISCV/float-intrinsics.ll
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1,708 changes: 1,704 additions & 4 deletions llvm/test/CodeGen/RISCV/half-arith.ll
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1,643 changes: 1,427 additions & 216 deletions llvm/test/CodeGen/RISCV/half-convert.ll
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250 changes: 250 additions & 0 deletions llvm/test/CodeGen/RISCV/half-fcmp.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,10 @@
; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh -verify-machineinstrs \
; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh -verify-machineinstrs \
; RUN: < %s | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh -verify-machineinstrs \
; RUN: < %s | FileCheck -check-prefix=RV64I %s

define i32 @fcmp_false(half %a, half %b) nounwind {
; RV32IZFH-LABEL: fcmp_false:
Expand All @@ -14,6 +18,16 @@ define i32 @fcmp_false(half %a, half %b) nounwind {
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: mv a0, zero
; RV64IZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_false:
; RV32I: # %bb.0:
; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: ret
;
; RV64I-LABEL: fcmp_false:
; RV64I: # %bb.0:
; RV64I-NEXT: mv a0, zero
; RV64I-NEXT: ret
%1 = fcmp false half %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
Expand All @@ -29,6 +43,20 @@ define i32 @fcmp_oeq(half %a, half %b) nounwind {
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: feq.h a0, fa0, fa1
; RV64IZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_oeq:
; RV32I: # %bb.0:
; RV32I-NEXT: fmv.h.x ft0, a1
; RV32I-NEXT: fmv.h.x ft1, a0
; RV32I-NEXT: feq.h a0, ft1, ft0
; RV32I-NEXT: ret
;
; RV64I-LABEL: fcmp_oeq:
; RV64I: # %bb.0:
; RV64I-NEXT: fmv.h.x ft0, a1
; RV64I-NEXT: fmv.h.x ft1, a0
; RV64I-NEXT: feq.h a0, ft1, ft0
; RV64I-NEXT: ret
%1 = fcmp oeq half %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
Expand All @@ -44,6 +72,20 @@ define i32 @fcmp_ogt(half %a, half %b) nounwind {
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: flt.h a0, fa1, fa0
; RV64IZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_ogt:
; RV32I: # %bb.0:
; RV32I-NEXT: fmv.h.x ft0, a0
; RV32I-NEXT: fmv.h.x ft1, a1
; RV32I-NEXT: flt.h a0, ft1, ft0
; RV32I-NEXT: ret
;
; RV64I-LABEL: fcmp_ogt:
; RV64I: # %bb.0:
; RV64I-NEXT: fmv.h.x ft0, a0
; RV64I-NEXT: fmv.h.x ft1, a1
; RV64I-NEXT: flt.h a0, ft1, ft0
; RV64I-NEXT: ret
%1 = fcmp ogt half %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
Expand All @@ -59,6 +101,20 @@ define i32 @fcmp_oge(half %a, half %b) nounwind {
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fle.h a0, fa1, fa0
; RV64IZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_oge:
; RV32I: # %bb.0:
; RV32I-NEXT: fmv.h.x ft0, a0
; RV32I-NEXT: fmv.h.x ft1, a1
; RV32I-NEXT: fle.h a0, ft1, ft0
; RV32I-NEXT: ret
;
; RV64I-LABEL: fcmp_oge:
; RV64I: # %bb.0:
; RV64I-NEXT: fmv.h.x ft0, a0
; RV64I-NEXT: fmv.h.x ft1, a1
; RV64I-NEXT: fle.h a0, ft1, ft0
; RV64I-NEXT: ret
%1 = fcmp oge half %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
Expand All @@ -74,6 +130,20 @@ define i32 @fcmp_olt(half %a, half %b) nounwind {
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: flt.h a0, fa0, fa1
; RV64IZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_olt:
; RV32I: # %bb.0:
; RV32I-NEXT: fmv.h.x ft0, a1
; RV32I-NEXT: fmv.h.x ft1, a0
; RV32I-NEXT: flt.h a0, ft1, ft0
; RV32I-NEXT: ret
;
; RV64I-LABEL: fcmp_olt:
; RV64I: # %bb.0:
; RV64I-NEXT: fmv.h.x ft0, a1
; RV64I-NEXT: fmv.h.x ft1, a0
; RV64I-NEXT: flt.h a0, ft1, ft0
; RV64I-NEXT: ret
%1 = fcmp olt half %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
Expand All @@ -89,6 +159,20 @@ define i32 @fcmp_ole(half %a, half %b) nounwind {
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fle.h a0, fa0, fa1
; RV64IZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_ole:
; RV32I: # %bb.0:
; RV32I-NEXT: fmv.h.x ft0, a1
; RV32I-NEXT: fmv.h.x ft1, a0
; RV32I-NEXT: fle.h a0, ft1, ft0
; RV32I-NEXT: ret
;
; RV64I-LABEL: fcmp_ole:
; RV64I: # %bb.0:
; RV64I-NEXT: fmv.h.x ft0, a1
; RV64I-NEXT: fmv.h.x ft1, a0
; RV64I-NEXT: fle.h a0, ft1, ft0
; RV64I-NEXT: ret
%1 = fcmp ole half %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
Expand All @@ -108,6 +192,24 @@ define i32 @fcmp_one(half %a, half %b) nounwind {
; RV64IZFH-NEXT: flt.h a1, fa1, fa0
; RV64IZFH-NEXT: or a0, a1, a0
; RV64IZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_one:
; RV32I: # %bb.0:
; RV32I-NEXT: fmv.h.x ft0, a1
; RV32I-NEXT: fmv.h.x ft1, a0
; RV32I-NEXT: flt.h a0, ft1, ft0
; RV32I-NEXT: flt.h a1, ft0, ft1
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret
;
; RV64I-LABEL: fcmp_one:
; RV64I: # %bb.0:
; RV64I-NEXT: fmv.h.x ft0, a1
; RV64I-NEXT: fmv.h.x ft1, a0
; RV64I-NEXT: flt.h a0, ft1, ft0
; RV64I-NEXT: flt.h a1, ft0, ft1
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
%1 = fcmp one half %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
Expand All @@ -127,6 +229,24 @@ define i32 @fcmp_ord(half %a, half %b) nounwind {
; RV64IZFH-NEXT: feq.h a1, fa0, fa0
; RV64IZFH-NEXT: and a0, a1, a0
; RV64IZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_ord:
; RV32I: # %bb.0:
; RV32I-NEXT: fmv.h.x ft0, a0
; RV32I-NEXT: fmv.h.x ft1, a1
; RV32I-NEXT: feq.h a0, ft1, ft1
; RV32I-NEXT: feq.h a1, ft0, ft0
; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: ret
;
; RV64I-LABEL: fcmp_ord:
; RV64I: # %bb.0:
; RV64I-NEXT: fmv.h.x ft0, a0
; RV64I-NEXT: fmv.h.x ft1, a1
; RV64I-NEXT: feq.h a0, ft1, ft1
; RV64I-NEXT: feq.h a1, ft0, ft0
; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: ret
%1 = fcmp ord half %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
Expand All @@ -148,6 +268,26 @@ define i32 @fcmp_ueq(half %a, half %b) nounwind {
; RV64IZFH-NEXT: or a0, a1, a0
; RV64IZFH-NEXT: xori a0, a0, 1
; RV64IZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_ueq:
; RV32I: # %bb.0:
; RV32I-NEXT: fmv.h.x ft0, a1
; RV32I-NEXT: fmv.h.x ft1, a0
; RV32I-NEXT: flt.h a0, ft1, ft0
; RV32I-NEXT: flt.h a1, ft0, ft1
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: ret
;
; RV64I-LABEL: fcmp_ueq:
; RV64I: # %bb.0:
; RV64I-NEXT: fmv.h.x ft0, a1
; RV64I-NEXT: fmv.h.x ft1, a0
; RV64I-NEXT: flt.h a0, ft1, ft0
; RV64I-NEXT: flt.h a1, ft0, ft1
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: xori a0, a0, 1
; RV64I-NEXT: ret
%1 = fcmp ueq half %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
Expand All @@ -165,6 +305,22 @@ define i32 @fcmp_ugt(half %a, half %b) nounwind {
; RV64IZFH-NEXT: fle.h a0, fa0, fa1
; RV64IZFH-NEXT: xori a0, a0, 1
; RV64IZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_ugt:
; RV32I: # %bb.0:
; RV32I-NEXT: fmv.h.x ft0, a1
; RV32I-NEXT: fmv.h.x ft1, a0
; RV32I-NEXT: fle.h a0, ft1, ft0
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: ret
;
; RV64I-LABEL: fcmp_ugt:
; RV64I: # %bb.0:
; RV64I-NEXT: fmv.h.x ft0, a1
; RV64I-NEXT: fmv.h.x ft1, a0
; RV64I-NEXT: fle.h a0, ft1, ft0
; RV64I-NEXT: xori a0, a0, 1
; RV64I-NEXT: ret
%1 = fcmp ugt half %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
Expand All @@ -182,6 +338,22 @@ define i32 @fcmp_uge(half %a, half %b) nounwind {
; RV64IZFH-NEXT: flt.h a0, fa0, fa1
; RV64IZFH-NEXT: xori a0, a0, 1
; RV64IZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_uge:
; RV32I: # %bb.0:
; RV32I-NEXT: fmv.h.x ft0, a1
; RV32I-NEXT: fmv.h.x ft1, a0
; RV32I-NEXT: flt.h a0, ft1, ft0
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: ret
;
; RV64I-LABEL: fcmp_uge:
; RV64I: # %bb.0:
; RV64I-NEXT: fmv.h.x ft0, a1
; RV64I-NEXT: fmv.h.x ft1, a0
; RV64I-NEXT: flt.h a0, ft1, ft0
; RV64I-NEXT: xori a0, a0, 1
; RV64I-NEXT: ret
%1 = fcmp uge half %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
Expand All @@ -199,6 +371,22 @@ define i32 @fcmp_ult(half %a, half %b) nounwind {
; RV64IZFH-NEXT: fle.h a0, fa1, fa0
; RV64IZFH-NEXT: xori a0, a0, 1
; RV64IZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_ult:
; RV32I: # %bb.0:
; RV32I-NEXT: fmv.h.x ft0, a0
; RV32I-NEXT: fmv.h.x ft1, a1
; RV32I-NEXT: fle.h a0, ft1, ft0
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: ret
;
; RV64I-LABEL: fcmp_ult:
; RV64I: # %bb.0:
; RV64I-NEXT: fmv.h.x ft0, a0
; RV64I-NEXT: fmv.h.x ft1, a1
; RV64I-NEXT: fle.h a0, ft1, ft0
; RV64I-NEXT: xori a0, a0, 1
; RV64I-NEXT: ret
%1 = fcmp ult half %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
Expand All @@ -216,6 +404,22 @@ define i32 @fcmp_ule(half %a, half %b) nounwind {
; RV64IZFH-NEXT: flt.h a0, fa1, fa0
; RV64IZFH-NEXT: xori a0, a0, 1
; RV64IZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_ule:
; RV32I: # %bb.0:
; RV32I-NEXT: fmv.h.x ft0, a0
; RV32I-NEXT: fmv.h.x ft1, a1
; RV32I-NEXT: flt.h a0, ft1, ft0
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: ret
;
; RV64I-LABEL: fcmp_ule:
; RV64I: # %bb.0:
; RV64I-NEXT: fmv.h.x ft0, a0
; RV64I-NEXT: fmv.h.x ft1, a1
; RV64I-NEXT: flt.h a0, ft1, ft0
; RV64I-NEXT: xori a0, a0, 1
; RV64I-NEXT: ret
%1 = fcmp ule half %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
Expand All @@ -233,6 +437,22 @@ define i32 @fcmp_une(half %a, half %b) nounwind {
; RV64IZFH-NEXT: feq.h a0, fa0, fa1
; RV64IZFH-NEXT: xori a0, a0, 1
; RV64IZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_une:
; RV32I: # %bb.0:
; RV32I-NEXT: fmv.h.x ft0, a1
; RV32I-NEXT: fmv.h.x ft1, a0
; RV32I-NEXT: feq.h a0, ft1, ft0
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: ret
;
; RV64I-LABEL: fcmp_une:
; RV64I: # %bb.0:
; RV64I-NEXT: fmv.h.x ft0, a1
; RV64I-NEXT: fmv.h.x ft1, a0
; RV64I-NEXT: feq.h a0, ft1, ft0
; RV64I-NEXT: xori a0, a0, 1
; RV64I-NEXT: ret
%1 = fcmp une half %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
Expand All @@ -254,6 +474,26 @@ define i32 @fcmp_uno(half %a, half %b) nounwind {
; RV64IZFH-NEXT: and a0, a1, a0
; RV64IZFH-NEXT: xori a0, a0, 1
; RV64IZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_uno:
; RV32I: # %bb.0:
; RV32I-NEXT: fmv.h.x ft0, a0
; RV32I-NEXT: fmv.h.x ft1, a1
; RV32I-NEXT: feq.h a0, ft1, ft1
; RV32I-NEXT: feq.h a1, ft0, ft0
; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: ret
;
; RV64I-LABEL: fcmp_uno:
; RV64I: # %bb.0:
; RV64I-NEXT: fmv.h.x ft0, a0
; RV64I-NEXT: fmv.h.x ft1, a1
; RV64I-NEXT: feq.h a0, ft1, ft1
; RV64I-NEXT: feq.h a1, ft0, ft0
; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: xori a0, a0, 1
; RV64I-NEXT: ret
%1 = fcmp uno half %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
Expand All @@ -269,6 +509,16 @@ define i32 @fcmp_true(half %a, half %b) nounwind {
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi a0, zero, 1
; RV64IZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_true:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a0, zero, 1
; RV32I-NEXT: ret
;
; RV64I-LABEL: fcmp_true:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a0, zero, 1
; RV64I-NEXT: ret
%1 = fcmp true half %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
Expand Down
852 changes: 717 additions & 135 deletions llvm/test/CodeGen/RISCV/half-intrinsics.ll
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54 changes: 3 additions & 51 deletions llvm/test/CodeGen/RISCV/rv64i-double-softfloat.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -7,54 +7,6 @@
; The test cases check that we use the si versions of the conversions from
; double.

define i32 @fp64_to_ui32(double %a) nounwind {
; RV64I-LABEL: fp64_to_ui32:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __fixunsdfsi@plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
; RV64IF-LABEL: fp64_to_ui32:
; RV64IF: # %bb.0: # %entry
; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call __fixunsdfsi@plt
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
entry:
%conv = fptoui double %a to i32
ret i32 %conv
}

define i32 @fp64_to_si32(double %a) nounwind {
; RV64I-LABEL: fp64_to_si32:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __fixdfsi@plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
; RV64IF-LABEL: fp64_to_si32:
; RV64IF: # %bb.0: # %entry
; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call __fixdfsi@plt
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
entry:
%conv = fptosi double %a to i32
ret i32 %conv
}



declare i32 @llvm.experimental.constrained.fptosi.i32.f64(double, metadata)
declare i32 @llvm.experimental.constrained.fptoui.i32.f64(double, metadata)

Expand All @@ -81,8 +33,8 @@ entry:
ret i32 %conv
}

define i32 @struct_fp64_to_si32(double %a) nounwind strictfp {
; RV64I-LABEL: struct_fp64_to_si32:
define i32 @strict_fp64_to_si32(double %a) nounwind strictfp {
; RV64I-LABEL: strict_fp64_to_si32:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
Expand All @@ -91,7 +43,7 @@ define i32 @struct_fp64_to_si32(double %a) nounwind strictfp {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
; RV64IF-LABEL: struct_fp64_to_si32:
; RV64IF-LABEL: strict_fp64_to_si32:
; RV64IF: # %bb.0: # %entry
; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
Expand Down
732 changes: 2 additions & 730 deletions llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll
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