40 changes: 20 additions & 20 deletions llvm/test/Analysis/CostModel/RISCV/fround.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@

define void @floor() {
; CHECK-LABEL: 'floor'
; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %1 = call float @llvm.floor.f32(float undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %1 = call float @llvm.floor.f32(float undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %2 = call <2 x float> @llvm.floor.v2f32(<2 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %3 = call <4 x float> @llvm.floor.v4f32(<4 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %4 = call <8 x float> @llvm.floor.v8f32(<8 x float> undef)
Expand All @@ -13,7 +13,7 @@ define void @floor() {
; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %8 = call <vscale x 4 x float> @llvm.floor.nxv4f32(<vscale x 4 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %9 = call <vscale x 8 x float> @llvm.floor.nxv8f32(<vscale x 8 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %10 = call <vscale x 16 x float> @llvm.floor.nxv16f32(<vscale x 16 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %11 = call double @llvm.floor.f64(double undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %11 = call double @llvm.floor.f64(double undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %12 = call <2 x double> @llvm.floor.v2f64(<2 x double> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %13 = call <4 x double> @llvm.floor.v4f64(<4 x double> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %14 = call <8 x double> @llvm.floor.v8f64(<8 x double> undef)
Expand Down Expand Up @@ -48,7 +48,7 @@ define void @floor() {

define void @ceil() {
; CHECK-LABEL: 'ceil'
; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %1 = call float @llvm.ceil.f32(float undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %1 = call float @llvm.ceil.f32(float undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %2 = call <2 x float> @llvm.ceil.v2f32(<2 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %3 = call <4 x float> @llvm.ceil.v4f32(<4 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %4 = call <8 x float> @llvm.ceil.v8f32(<8 x float> undef)
Expand All @@ -58,7 +58,7 @@ define void @ceil() {
; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %8 = call <vscale x 4 x float> @llvm.ceil.nxv4f32(<vscale x 4 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %9 = call <vscale x 8 x float> @llvm.ceil.nxv8f32(<vscale x 8 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %10 = call <vscale x 16 x float> @llvm.ceil.nxv16f32(<vscale x 16 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %11 = call double @llvm.ceil.f64(double undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %11 = call double @llvm.ceil.f64(double undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %12 = call <2 x double> @llvm.ceil.v2f64(<2 x double> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %13 = call <4 x double> @llvm.ceil.v4f64(<4 x double> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %14 = call <8 x double> @llvm.ceil.v8f64(<8 x double> undef)
Expand Down Expand Up @@ -93,7 +93,7 @@ define void @ceil() {

define void @trunc() {
; CHECK-LABEL: 'trunc'
; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %1 = call float @llvm.trunc.f32(float undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %1 = call float @llvm.trunc.f32(float undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %2 = call <2 x float> @llvm.trunc.v2f32(<2 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %3 = call <4 x float> @llvm.trunc.v4f32(<4 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %4 = call <8 x float> @llvm.trunc.v8f32(<8 x float> undef)
Expand All @@ -103,7 +103,7 @@ define void @trunc() {
; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %8 = call <vscale x 4 x float> @llvm.trunc.nxv4f32(<vscale x 4 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %9 = call <vscale x 8 x float> @llvm.trunc.nxv8f32(<vscale x 8 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %10 = call <vscale x 16 x float> @llvm.trunc.nxv16f32(<vscale x 16 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %11 = call double @llvm.trunc.f64(double undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %11 = call double @llvm.trunc.f64(double undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %12 = call <2 x double> @llvm.trunc.v2f64(<2 x double> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %13 = call <4 x double> @llvm.trunc.v4f64(<4 x double> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %14 = call <8 x double> @llvm.trunc.v8f64(<8 x double> undef)
Expand Down Expand Up @@ -138,21 +138,21 @@ define void @trunc() {

define void @rint() {
; CHECK-LABEL: 'rint'
; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %1 = call float @llvm.rint.f32(float undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %2 = call <2 x float> @llvm.rint.v2f32(<2 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %3 = call <4 x float> @llvm.rint.v4f32(<4 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 95 for instruction: %4 = call <8 x float> @llvm.rint.v8f32(<8 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 191 for instruction: %5 = call <16 x float> @llvm.rint.v16f32(<16 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %1 = call float @llvm.rint.f32(float undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %2 = call <2 x float> @llvm.rint.v2f32(<2 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 39 for instruction: %3 = call <4 x float> @llvm.rint.v4f32(<4 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 79 for instruction: %4 = call <8 x float> @llvm.rint.v8f32(<8 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 159 for instruction: %5 = call <16 x float> @llvm.rint.v16f32(<16 x float> undef)
; CHECK-NEXT: Cost Model: Invalid cost for instruction: %6 = call <vscale x 1 x float> @llvm.rint.nxv1f32(<vscale x 1 x float> undef)
; CHECK-NEXT: Cost Model: Invalid cost for instruction: %7 = call <vscale x 2 x float> @llvm.rint.nxv2f32(<vscale x 2 x float> undef)
; CHECK-NEXT: Cost Model: Invalid cost for instruction: %8 = call <vscale x 4 x float> @llvm.rint.nxv4f32(<vscale x 4 x float> undef)
; CHECK-NEXT: Cost Model: Invalid cost for instruction: %9 = call <vscale x 8 x float> @llvm.rint.nxv8f32(<vscale x 8 x float> undef)
; CHECK-NEXT: Cost Model: Invalid cost for instruction: %10 = call <vscale x 16 x float> @llvm.rint.nxv16f32(<vscale x 16 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %11 = call double @llvm.rint.f64(double undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %12 = call <2 x double> @llvm.rint.v2f64(<2 x double> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %13 = call <4 x double> @llvm.rint.v4f64(<4 x double> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 95 for instruction: %14 = call <8 x double> @llvm.rint.v8f64(<8 x double> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 191 for instruction: %15 = call <16 x double> @llvm.rint.v16f64(<16 x double> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %11 = call double @llvm.rint.f64(double undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %12 = call <2 x double> @llvm.rint.v2f64(<2 x double> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 39 for instruction: %13 = call <4 x double> @llvm.rint.v4f64(<4 x double> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 79 for instruction: %14 = call <8 x double> @llvm.rint.v8f64(<8 x double> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 159 for instruction: %15 = call <16 x double> @llvm.rint.v16f64(<16 x double> undef)
; CHECK-NEXT: Cost Model: Invalid cost for instruction: %16 = call <vscale x 1 x double> @llvm.rint.nxv1f64(<vscale x 1 x double> undef)
; CHECK-NEXT: Cost Model: Invalid cost for instruction: %17 = call <vscale x 2 x double> @llvm.rint.nxv2f64(<vscale x 2 x double> undef)
; CHECK-NEXT: Cost Model: Invalid cost for instruction: %18 = call <vscale x 4 x double> @llvm.rint.nxv4f64(<vscale x 4 x double> undef)
Expand Down Expand Up @@ -228,7 +228,7 @@ define void @nearbyint() {

define void @round() {
; CHECK-LABEL: 'round'
; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %1 = call float @llvm.round.f32(float undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %1 = call float @llvm.round.f32(float undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %2 = call <2 x float> @llvm.round.v2f32(<2 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %3 = call <4 x float> @llvm.round.v4f32(<4 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %4 = call <8 x float> @llvm.round.v8f32(<8 x float> undef)
Expand All @@ -238,7 +238,7 @@ define void @round() {
; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %8 = call <vscale x 4 x float> @llvm.round.nxv4f32(<vscale x 4 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %9 = call <vscale x 8 x float> @llvm.round.nxv8f32(<vscale x 8 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %10 = call <vscale x 16 x float> @llvm.round.nxv16f32(<vscale x 16 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %11 = call double @llvm.round.f64(double undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %11 = call double @llvm.round.f64(double undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %12 = call <2 x double> @llvm.round.v2f64(<2 x double> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %13 = call <4 x double> @llvm.round.v4f64(<4 x double> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %14 = call <8 x double> @llvm.round.v8f64(<8 x double> undef)
Expand Down Expand Up @@ -273,7 +273,7 @@ define void @round() {

define void @roundeven() {
; CHECK-LABEL: 'roundeven'
; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %1 = call float @llvm.roundeven.f32(float undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %1 = call float @llvm.roundeven.f32(float undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %2 = call <2 x float> @llvm.roundeven.v2f32(<2 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %3 = call <4 x float> @llvm.roundeven.v4f32(<4 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %4 = call <8 x float> @llvm.roundeven.v8f32(<8 x float> undef)
Expand All @@ -283,7 +283,7 @@ define void @roundeven() {
; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %8 = call <vscale x 4 x float> @llvm.roundeven.nxv4f32(<vscale x 4 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %9 = call <vscale x 8 x float> @llvm.roundeven.nxv8f32(<vscale x 8 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %10 = call <vscale x 16 x float> @llvm.roundeven.nxv16f32(<vscale x 16 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %11 = call double @llvm.roundeven.f64(double undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %11 = call double @llvm.roundeven.f64(double undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %12 = call <2 x double> @llvm.roundeven.v2f64(<2 x double> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %13 = call <4 x double> @llvm.roundeven.v4f64(<4 x double> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %14 = call <8 x double> @llvm.roundeven.v8f64(<8 x double> undef)
Expand Down
120 changes: 102 additions & 18 deletions llvm/test/CodeGen/RISCV/double-intrinsics.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -596,9 +596,23 @@ define double @copysign_f64(double %a, double %b) nounwind {
declare double @llvm.floor.f64(double)

define double @floor_f64(double %a) nounwind {
; CHECKIFD-LABEL: floor_f64:
; CHECKIFD: # %bb.0:
; CHECKIFD-NEXT: tail floor@plt
; RV32IFD-LABEL: floor_f64:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: tail floor@plt
;
; RV64IFD-LABEL: floor_f64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: lui a0, %hi(.LCPI17_0)
; RV64IFD-NEXT: fld ft0, %lo(.LCPI17_0)(a0)
; RV64IFD-NEXT: fabs.d ft1, fa0
; RV64IFD-NEXT: flt.d a0, ft1, ft0
; RV64IFD-NEXT: beqz a0, .LBB17_2
; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: fcvt.l.d a0, fa0, rdn
; RV64IFD-NEXT: fcvt.d.l ft0, a0, rdn
; RV64IFD-NEXT: fsgnj.d fa0, ft0, fa0
; RV64IFD-NEXT: .LBB17_2:
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: floor_f64:
; RV32I: # %bb.0:
Expand All @@ -624,9 +638,23 @@ define double @floor_f64(double %a) nounwind {
declare double @llvm.ceil.f64(double)

define double @ceil_f64(double %a) nounwind {
; CHECKIFD-LABEL: ceil_f64:
; CHECKIFD: # %bb.0:
; CHECKIFD-NEXT: tail ceil@plt
; RV32IFD-LABEL: ceil_f64:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: tail ceil@plt
;
; RV64IFD-LABEL: ceil_f64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: lui a0, %hi(.LCPI18_0)
; RV64IFD-NEXT: fld ft0, %lo(.LCPI18_0)(a0)
; RV64IFD-NEXT: fabs.d ft1, fa0
; RV64IFD-NEXT: flt.d a0, ft1, ft0
; RV64IFD-NEXT: beqz a0, .LBB18_2
; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: fcvt.l.d a0, fa0, rup
; RV64IFD-NEXT: fcvt.d.l ft0, a0, rup
; RV64IFD-NEXT: fsgnj.d fa0, ft0, fa0
; RV64IFD-NEXT: .LBB18_2:
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: ceil_f64:
; RV32I: # %bb.0:
Expand All @@ -652,9 +680,23 @@ define double @ceil_f64(double %a) nounwind {
declare double @llvm.trunc.f64(double)

define double @trunc_f64(double %a) nounwind {
; CHECKIFD-LABEL: trunc_f64:
; CHECKIFD: # %bb.0:
; CHECKIFD-NEXT: tail trunc@plt
; RV32IFD-LABEL: trunc_f64:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: tail trunc@plt
;
; RV64IFD-LABEL: trunc_f64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: lui a0, %hi(.LCPI19_0)
; RV64IFD-NEXT: fld ft0, %lo(.LCPI19_0)(a0)
; RV64IFD-NEXT: fabs.d ft1, fa0
; RV64IFD-NEXT: flt.d a0, ft1, ft0
; RV64IFD-NEXT: beqz a0, .LBB19_2
; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: fcvt.l.d a0, fa0, rtz
; RV64IFD-NEXT: fcvt.d.l ft0, a0, rtz
; RV64IFD-NEXT: fsgnj.d fa0, ft0, fa0
; RV64IFD-NEXT: .LBB19_2:
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: trunc_f64:
; RV32I: # %bb.0:
Expand All @@ -680,9 +722,23 @@ define double @trunc_f64(double %a) nounwind {
declare double @llvm.rint.f64(double)

define double @rint_f64(double %a) nounwind {
; CHECKIFD-LABEL: rint_f64:
; CHECKIFD: # %bb.0:
; CHECKIFD-NEXT: tail rint@plt
; RV32IFD-LABEL: rint_f64:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: tail rint@plt
;
; RV64IFD-LABEL: rint_f64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: lui a0, %hi(.LCPI20_0)
; RV64IFD-NEXT: fld ft0, %lo(.LCPI20_0)(a0)
; RV64IFD-NEXT: fabs.d ft1, fa0
; RV64IFD-NEXT: flt.d a0, ft1, ft0
; RV64IFD-NEXT: beqz a0, .LBB20_2
; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: fcvt.l.d a0, fa0
; RV64IFD-NEXT: fcvt.d.l ft0, a0
; RV64IFD-NEXT: fsgnj.d fa0, ft0, fa0
; RV64IFD-NEXT: .LBB20_2:
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: rint_f64:
; RV32I: # %bb.0:
Expand Down Expand Up @@ -736,9 +792,23 @@ define double @nearbyint_f64(double %a) nounwind {
declare double @llvm.round.f64(double)

define double @round_f64(double %a) nounwind {
; CHECKIFD-LABEL: round_f64:
; CHECKIFD: # %bb.0:
; CHECKIFD-NEXT: tail round@plt
; RV32IFD-LABEL: round_f64:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: tail round@plt
;
; RV64IFD-LABEL: round_f64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: lui a0, %hi(.LCPI22_0)
; RV64IFD-NEXT: fld ft0, %lo(.LCPI22_0)(a0)
; RV64IFD-NEXT: fabs.d ft1, fa0
; RV64IFD-NEXT: flt.d a0, ft1, ft0
; RV64IFD-NEXT: beqz a0, .LBB22_2
; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: fcvt.l.d a0, fa0, rmm
; RV64IFD-NEXT: fcvt.d.l ft0, a0, rmm
; RV64IFD-NEXT: fsgnj.d fa0, ft0, fa0
; RV64IFD-NEXT: .LBB22_2:
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: round_f64:
; RV32I: # %bb.0:
Expand All @@ -764,9 +834,23 @@ define double @round_f64(double %a) nounwind {
declare double @llvm.roundeven.f64(double)

define double @roundeven_f64(double %a) nounwind {
; CHECKIFD-LABEL: roundeven_f64:
; CHECKIFD: # %bb.0:
; CHECKIFD-NEXT: tail roundeven@plt
; RV32IFD-LABEL: roundeven_f64:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: tail roundeven@plt
;
; RV64IFD-LABEL: roundeven_f64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: lui a0, %hi(.LCPI23_0)
; RV64IFD-NEXT: fld ft0, %lo(.LCPI23_0)(a0)
; RV64IFD-NEXT: fabs.d ft1, fa0
; RV64IFD-NEXT: flt.d a0, ft1, ft0
; RV64IFD-NEXT: beqz a0, .LBB23_2
; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: fcvt.l.d a0, fa0, rne
; RV64IFD-NEXT: fcvt.d.l ft0, a0, rne
; RV64IFD-NEXT: fsgnj.d fa0, ft0, fa0
; RV64IFD-NEXT: .LBB23_2:
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: roundeven_f64:
; RV32I: # %bb.0:
Expand Down
100 changes: 85 additions & 15 deletions llvm/test/CodeGen/RISCV/double-round-conv.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -625,41 +625,111 @@ define i64 @test_roundeven_ui64(double %x) {
}

define double @test_floor_double(double %x) {
; CHECKIFD-LABEL: test_floor_double:
; CHECKIFD: # %bb.0:
; CHECKIFD-NEXT: tail floor@plt
; RV32IFD-LABEL: test_floor_double:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: tail floor@plt
;
; RV64IFD-LABEL: test_floor_double:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: lui a0, %hi(.LCPI40_0)
; RV64IFD-NEXT: fld ft0, %lo(.LCPI40_0)(a0)
; RV64IFD-NEXT: fabs.d ft1, fa0
; RV64IFD-NEXT: flt.d a0, ft1, ft0
; RV64IFD-NEXT: beqz a0, .LBB40_2
; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: fcvt.l.d a0, fa0, rdn
; RV64IFD-NEXT: fcvt.d.l ft0, a0, rdn
; RV64IFD-NEXT: fsgnj.d fa0, ft0, fa0
; RV64IFD-NEXT: .LBB40_2:
; RV64IFD-NEXT: ret
%a = call double @llvm.floor.f64(double %x)
ret double %a
}

define double @test_ceil_double(double %x) {
; CHECKIFD-LABEL: test_ceil_double:
; CHECKIFD: # %bb.0:
; CHECKIFD-NEXT: tail ceil@plt
; RV32IFD-LABEL: test_ceil_double:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: tail ceil@plt
;
; RV64IFD-LABEL: test_ceil_double:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: lui a0, %hi(.LCPI41_0)
; RV64IFD-NEXT: fld ft0, %lo(.LCPI41_0)(a0)
; RV64IFD-NEXT: fabs.d ft1, fa0
; RV64IFD-NEXT: flt.d a0, ft1, ft0
; RV64IFD-NEXT: beqz a0, .LBB41_2
; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: fcvt.l.d a0, fa0, rup
; RV64IFD-NEXT: fcvt.d.l ft0, a0, rup
; RV64IFD-NEXT: fsgnj.d fa0, ft0, fa0
; RV64IFD-NEXT: .LBB41_2:
; RV64IFD-NEXT: ret
%a = call double @llvm.ceil.f64(double %x)
ret double %a
}

define double @test_trunc_double(double %x) {
; CHECKIFD-LABEL: test_trunc_double:
; CHECKIFD: # %bb.0:
; CHECKIFD-NEXT: tail trunc@plt
; RV32IFD-LABEL: test_trunc_double:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: tail trunc@plt
;
; RV64IFD-LABEL: test_trunc_double:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: lui a0, %hi(.LCPI42_0)
; RV64IFD-NEXT: fld ft0, %lo(.LCPI42_0)(a0)
; RV64IFD-NEXT: fabs.d ft1, fa0
; RV64IFD-NEXT: flt.d a0, ft1, ft0
; RV64IFD-NEXT: beqz a0, .LBB42_2
; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: fcvt.l.d a0, fa0, rtz
; RV64IFD-NEXT: fcvt.d.l ft0, a0, rtz
; RV64IFD-NEXT: fsgnj.d fa0, ft0, fa0
; RV64IFD-NEXT: .LBB42_2:
; RV64IFD-NEXT: ret
%a = call double @llvm.trunc.f64(double %x)
ret double %a
}

define double @test_round_double(double %x) {
; CHECKIFD-LABEL: test_round_double:
; CHECKIFD: # %bb.0:
; CHECKIFD-NEXT: tail round@plt
; RV32IFD-LABEL: test_round_double:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: tail round@plt
;
; RV64IFD-LABEL: test_round_double:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: lui a0, %hi(.LCPI43_0)
; RV64IFD-NEXT: fld ft0, %lo(.LCPI43_0)(a0)
; RV64IFD-NEXT: fabs.d ft1, fa0
; RV64IFD-NEXT: flt.d a0, ft1, ft0
; RV64IFD-NEXT: beqz a0, .LBB43_2
; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: fcvt.l.d a0, fa0, rmm
; RV64IFD-NEXT: fcvt.d.l ft0, a0, rmm
; RV64IFD-NEXT: fsgnj.d fa0, ft0, fa0
; RV64IFD-NEXT: .LBB43_2:
; RV64IFD-NEXT: ret
%a = call double @llvm.round.f64(double %x)
ret double %a
}

define double @test_roundeven_double(double %x) {
; CHECKIFD-LABEL: test_roundeven_double:
; CHECKIFD: # %bb.0:
; CHECKIFD-NEXT: tail roundeven@plt
; RV32IFD-LABEL: test_roundeven_double:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: tail roundeven@plt
;
; RV64IFD-LABEL: test_roundeven_double:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: lui a0, %hi(.LCPI44_0)
; RV64IFD-NEXT: fld ft0, %lo(.LCPI44_0)(a0)
; RV64IFD-NEXT: fabs.d ft1, fa0
; RV64IFD-NEXT: flt.d a0, ft1, ft0
; RV64IFD-NEXT: beqz a0, .LBB44_2
; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: fcvt.l.d a0, fa0, rne
; RV64IFD-NEXT: fcvt.d.l ft0, a0, rne
; RV64IFD-NEXT: fsgnj.d fa0, ft0, fa0
; RV64IFD-NEXT: .LBB44_2:
; RV64IFD-NEXT: ret
%a = call double @llvm.roundeven.f64(double %x)
ret double %a
}
Expand Down
144 changes: 132 additions & 12 deletions llvm/test/CodeGen/RISCV/float-intrinsics.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -640,11 +640,31 @@ declare float @llvm.floor.f32(float)
define float @floor_f32(float %a) nounwind {
; RV32IF-LABEL: floor_f32:
; RV32IF: # %bb.0:
; RV32IF-NEXT: tail floorf@plt
; RV32IF-NEXT: lui a0, %hi(.LCPI17_0)
; RV32IF-NEXT: flw ft0, %lo(.LCPI17_0)(a0)
; RV32IF-NEXT: fabs.s ft1, fa0
; RV32IF-NEXT: flt.s a0, ft1, ft0
; RV32IF-NEXT: beqz a0, .LBB17_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.w.s a0, fa0, rdn
; RV32IF-NEXT: fcvt.s.w ft0, a0, rdn
; RV32IF-NEXT: fsgnj.s fa0, ft0, fa0
; RV32IF-NEXT: .LBB17_2:
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: floor_f32:
; RV64IF: # %bb.0:
; RV64IF-NEXT: tail floorf@plt
; RV64IF-NEXT: lui a0, %hi(.LCPI17_0)
; RV64IF-NEXT: flw ft0, %lo(.LCPI17_0)(a0)
; RV64IF-NEXT: fabs.s ft1, fa0
; RV64IF-NEXT: flt.s a0, ft1, ft0
; RV64IF-NEXT: beqz a0, .LBB17_2
; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: fcvt.w.s a0, fa0, rdn
; RV64IF-NEXT: fcvt.s.w ft0, a0, rdn
; RV64IF-NEXT: fsgnj.s fa0, ft0, fa0
; RV64IF-NEXT: .LBB17_2:
; RV64IF-NEXT: ret
;
; RV32I-LABEL: floor_f32:
; RV32I: # %bb.0:
Expand Down Expand Up @@ -672,11 +692,31 @@ declare float @llvm.ceil.f32(float)
define float @ceil_f32(float %a) nounwind {
; RV32IF-LABEL: ceil_f32:
; RV32IF: # %bb.0:
; RV32IF-NEXT: tail ceilf@plt
; RV32IF-NEXT: lui a0, %hi(.LCPI18_0)
; RV32IF-NEXT: flw ft0, %lo(.LCPI18_0)(a0)
; RV32IF-NEXT: fabs.s ft1, fa0
; RV32IF-NEXT: flt.s a0, ft1, ft0
; RV32IF-NEXT: beqz a0, .LBB18_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.w.s a0, fa0, rup
; RV32IF-NEXT: fcvt.s.w ft0, a0, rup
; RV32IF-NEXT: fsgnj.s fa0, ft0, fa0
; RV32IF-NEXT: .LBB18_2:
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: ceil_f32:
; RV64IF: # %bb.0:
; RV64IF-NEXT: tail ceilf@plt
; RV64IF-NEXT: lui a0, %hi(.LCPI18_0)
; RV64IF-NEXT: flw ft0, %lo(.LCPI18_0)(a0)
; RV64IF-NEXT: fabs.s ft1, fa0
; RV64IF-NEXT: flt.s a0, ft1, ft0
; RV64IF-NEXT: beqz a0, .LBB18_2
; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: fcvt.w.s a0, fa0, rup
; RV64IF-NEXT: fcvt.s.w ft0, a0, rup
; RV64IF-NEXT: fsgnj.s fa0, ft0, fa0
; RV64IF-NEXT: .LBB18_2:
; RV64IF-NEXT: ret
;
; RV32I-LABEL: ceil_f32:
; RV32I: # %bb.0:
Expand Down Expand Up @@ -704,11 +744,31 @@ declare float @llvm.trunc.f32(float)
define float @trunc_f32(float %a) nounwind {
; RV32IF-LABEL: trunc_f32:
; RV32IF: # %bb.0:
; RV32IF-NEXT: tail truncf@plt
; RV32IF-NEXT: lui a0, %hi(.LCPI19_0)
; RV32IF-NEXT: flw ft0, %lo(.LCPI19_0)(a0)
; RV32IF-NEXT: fabs.s ft1, fa0
; RV32IF-NEXT: flt.s a0, ft1, ft0
; RV32IF-NEXT: beqz a0, .LBB19_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz
; RV32IF-NEXT: fcvt.s.w ft0, a0, rtz
; RV32IF-NEXT: fsgnj.s fa0, ft0, fa0
; RV32IF-NEXT: .LBB19_2:
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: trunc_f32:
; RV64IF: # %bb.0:
; RV64IF-NEXT: tail truncf@plt
; RV64IF-NEXT: lui a0, %hi(.LCPI19_0)
; RV64IF-NEXT: flw ft0, %lo(.LCPI19_0)(a0)
; RV64IF-NEXT: fabs.s ft1, fa0
; RV64IF-NEXT: flt.s a0, ft1, ft0
; RV64IF-NEXT: beqz a0, .LBB19_2
; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz
; RV64IF-NEXT: fcvt.s.w ft0, a0, rtz
; RV64IF-NEXT: fsgnj.s fa0, ft0, fa0
; RV64IF-NEXT: .LBB19_2:
; RV64IF-NEXT: ret
;
; RV32I-LABEL: trunc_f32:
; RV32I: # %bb.0:
Expand Down Expand Up @@ -736,11 +796,31 @@ declare float @llvm.rint.f32(float)
define float @rint_f32(float %a) nounwind {
; RV32IF-LABEL: rint_f32:
; RV32IF: # %bb.0:
; RV32IF-NEXT: tail rintf@plt
; RV32IF-NEXT: lui a0, %hi(.LCPI20_0)
; RV32IF-NEXT: flw ft0, %lo(.LCPI20_0)(a0)
; RV32IF-NEXT: fabs.s ft1, fa0
; RV32IF-NEXT: flt.s a0, ft1, ft0
; RV32IF-NEXT: beqz a0, .LBB20_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.w.s a0, fa0
; RV32IF-NEXT: fcvt.s.w ft0, a0
; RV32IF-NEXT: fsgnj.s fa0, ft0, fa0
; RV32IF-NEXT: .LBB20_2:
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: rint_f32:
; RV64IF: # %bb.0:
; RV64IF-NEXT: tail rintf@plt
; RV64IF-NEXT: lui a0, %hi(.LCPI20_0)
; RV64IF-NEXT: flw ft0, %lo(.LCPI20_0)(a0)
; RV64IF-NEXT: fabs.s ft1, fa0
; RV64IF-NEXT: flt.s a0, ft1, ft0
; RV64IF-NEXT: beqz a0, .LBB20_2
; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: fcvt.w.s a0, fa0
; RV64IF-NEXT: fcvt.s.w ft0, a0
; RV64IF-NEXT: fsgnj.s fa0, ft0, fa0
; RV64IF-NEXT: .LBB20_2:
; RV64IF-NEXT: ret
;
; RV32I-LABEL: rint_f32:
; RV32I: # %bb.0:
Expand Down Expand Up @@ -800,11 +880,31 @@ declare float @llvm.round.f32(float)
define float @round_f32(float %a) nounwind {
; RV32IF-LABEL: round_f32:
; RV32IF: # %bb.0:
; RV32IF-NEXT: tail roundf@plt
; RV32IF-NEXT: lui a0, %hi(.LCPI22_0)
; RV32IF-NEXT: flw ft0, %lo(.LCPI22_0)(a0)
; RV32IF-NEXT: fabs.s ft1, fa0
; RV32IF-NEXT: flt.s a0, ft1, ft0
; RV32IF-NEXT: beqz a0, .LBB22_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.w.s a0, fa0, rmm
; RV32IF-NEXT: fcvt.s.w ft0, a0, rmm
; RV32IF-NEXT: fsgnj.s fa0, ft0, fa0
; RV32IF-NEXT: .LBB22_2:
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: round_f32:
; RV64IF: # %bb.0:
; RV64IF-NEXT: tail roundf@plt
; RV64IF-NEXT: lui a0, %hi(.LCPI22_0)
; RV64IF-NEXT: flw ft0, %lo(.LCPI22_0)(a0)
; RV64IF-NEXT: fabs.s ft1, fa0
; RV64IF-NEXT: flt.s a0, ft1, ft0
; RV64IF-NEXT: beqz a0, .LBB22_2
; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: fcvt.w.s a0, fa0, rmm
; RV64IF-NEXT: fcvt.s.w ft0, a0, rmm
; RV64IF-NEXT: fsgnj.s fa0, ft0, fa0
; RV64IF-NEXT: .LBB22_2:
; RV64IF-NEXT: ret
;
; RV32I-LABEL: round_f32:
; RV32I: # %bb.0:
Expand Down Expand Up @@ -832,11 +932,31 @@ declare float @llvm.roundeven.f32(float)
define float @roundeven_f32(float %a) nounwind {
; RV32IF-LABEL: roundeven_f32:
; RV32IF: # %bb.0:
; RV32IF-NEXT: tail roundevenf@plt
; RV32IF-NEXT: lui a0, %hi(.LCPI23_0)
; RV32IF-NEXT: flw ft0, %lo(.LCPI23_0)(a0)
; RV32IF-NEXT: fabs.s ft1, fa0
; RV32IF-NEXT: flt.s a0, ft1, ft0
; RV32IF-NEXT: beqz a0, .LBB23_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.w.s a0, fa0, rne
; RV32IF-NEXT: fcvt.s.w ft0, a0, rne
; RV32IF-NEXT: fsgnj.s fa0, ft0, fa0
; RV32IF-NEXT: .LBB23_2:
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: roundeven_f32:
; RV64IF: # %bb.0:
; RV64IF-NEXT: tail roundevenf@plt
; RV64IF-NEXT: lui a0, %hi(.LCPI23_0)
; RV64IF-NEXT: flw ft0, %lo(.LCPI23_0)(a0)
; RV64IF-NEXT: fabs.s ft1, fa0
; RV64IF-NEXT: flt.s a0, ft1, ft0
; RV64IF-NEXT: beqz a0, .LBB23_2
; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: fcvt.w.s a0, fa0, rne
; RV64IF-NEXT: fcvt.s.w ft0, a0, rne
; RV64IF-NEXT: fsgnj.s fa0, ft0, fa0
; RV64IF-NEXT: .LBB23_2:
; RV64IF-NEXT: ret
;
; RV32I-LABEL: roundeven_f32:
; RV32I: # %bb.0:
Expand Down
325 changes: 215 additions & 110 deletions llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
View file

Large diffs are not rendered by default.

230 changes: 210 additions & 20 deletions llvm/test/CodeGen/RISCV/float-round-conv.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -56,7 +56,16 @@ define i64 @test_floor_si64(float %x) {
; RV32IF-NEXT: .cfi_def_cfa_offset 16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: .cfi_offset ra, -4
; RV32IF-NEXT: call floorf@plt
; RV32IF-NEXT: lui a0, %hi(.LCPI3_0)
; RV32IF-NEXT: flw ft0, %lo(.LCPI3_0)(a0)
; RV32IF-NEXT: fabs.s ft1, fa0
; RV32IF-NEXT: flt.s a0, ft1, ft0
; RV32IF-NEXT: beqz a0, .LBB3_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.w.s a0, fa0, rdn
; RV32IF-NEXT: fcvt.s.w ft0, a0, rdn
; RV32IF-NEXT: fsgnj.s fa0, ft0, fa0
; RV32IF-NEXT: .LBB3_2:
; RV32IF-NEXT: call __fixsfdi@plt
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16
Expand Down Expand Up @@ -123,7 +132,16 @@ define i64 @test_floor_ui64(float %x) {
; RV32IF-NEXT: .cfi_def_cfa_offset 16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: .cfi_offset ra, -4
; RV32IF-NEXT: call floorf@plt
; RV32IF-NEXT: lui a0, %hi(.LCPI7_0)
; RV32IF-NEXT: flw ft0, %lo(.LCPI7_0)(a0)
; RV32IF-NEXT: fabs.s ft1, fa0
; RV32IF-NEXT: flt.s a0, ft1, ft0
; RV32IF-NEXT: beqz a0, .LBB7_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.w.s a0, fa0, rdn
; RV32IF-NEXT: fcvt.s.w ft0, a0, rdn
; RV32IF-NEXT: fsgnj.s fa0, ft0, fa0
; RV32IF-NEXT: .LBB7_2:
; RV32IF-NEXT: call __fixunssfdi@plt
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16
Expand Down Expand Up @@ -190,7 +208,16 @@ define i64 @test_ceil_si64(float %x) {
; RV32IF-NEXT: .cfi_def_cfa_offset 16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: .cfi_offset ra, -4
; RV32IF-NEXT: call ceilf@plt
; RV32IF-NEXT: lui a0, %hi(.LCPI11_0)
; RV32IF-NEXT: flw ft0, %lo(.LCPI11_0)(a0)
; RV32IF-NEXT: fabs.s ft1, fa0
; RV32IF-NEXT: flt.s a0, ft1, ft0
; RV32IF-NEXT: beqz a0, .LBB11_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.w.s a0, fa0, rup
; RV32IF-NEXT: fcvt.s.w ft0, a0, rup
; RV32IF-NEXT: fsgnj.s fa0, ft0, fa0
; RV32IF-NEXT: .LBB11_2:
; RV32IF-NEXT: call __fixsfdi@plt
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16
Expand Down Expand Up @@ -257,7 +284,16 @@ define i64 @test_ceil_ui64(float %x) {
; RV32IF-NEXT: .cfi_def_cfa_offset 16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: .cfi_offset ra, -4
; RV32IF-NEXT: call ceilf@plt
; RV32IF-NEXT: lui a0, %hi(.LCPI15_0)
; RV32IF-NEXT: flw ft0, %lo(.LCPI15_0)(a0)
; RV32IF-NEXT: fabs.s ft1, fa0
; RV32IF-NEXT: flt.s a0, ft1, ft0
; RV32IF-NEXT: beqz a0, .LBB15_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.w.s a0, fa0, rup
; RV32IF-NEXT: fcvt.s.w ft0, a0, rup
; RV32IF-NEXT: fsgnj.s fa0, ft0, fa0
; RV32IF-NEXT: .LBB15_2:
; RV32IF-NEXT: call __fixunssfdi@plt
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16
Expand Down Expand Up @@ -324,7 +360,16 @@ define i64 @test_trunc_si64(float %x) {
; RV32IF-NEXT: .cfi_def_cfa_offset 16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: .cfi_offset ra, -4
; RV32IF-NEXT: call truncf@plt
; RV32IF-NEXT: lui a0, %hi(.LCPI19_0)
; RV32IF-NEXT: flw ft0, %lo(.LCPI19_0)(a0)
; RV32IF-NEXT: fabs.s ft1, fa0
; RV32IF-NEXT: flt.s a0, ft1, ft0
; RV32IF-NEXT: beqz a0, .LBB19_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz
; RV32IF-NEXT: fcvt.s.w ft0, a0, rtz
; RV32IF-NEXT: fsgnj.s fa0, ft0, fa0
; RV32IF-NEXT: .LBB19_2:
; RV32IF-NEXT: call __fixsfdi@plt
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16
Expand Down Expand Up @@ -391,7 +436,16 @@ define i64 @test_trunc_ui64(float %x) {
; RV32IF-NEXT: .cfi_def_cfa_offset 16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: .cfi_offset ra, -4
; RV32IF-NEXT: call truncf@plt
; RV32IF-NEXT: lui a0, %hi(.LCPI23_0)
; RV32IF-NEXT: flw ft0, %lo(.LCPI23_0)(a0)
; RV32IF-NEXT: fabs.s ft1, fa0
; RV32IF-NEXT: flt.s a0, ft1, ft0
; RV32IF-NEXT: beqz a0, .LBB23_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz
; RV32IF-NEXT: fcvt.s.w ft0, a0, rtz
; RV32IF-NEXT: fsgnj.s fa0, ft0, fa0
; RV32IF-NEXT: .LBB23_2:
; RV32IF-NEXT: call __fixunssfdi@plt
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16
Expand Down Expand Up @@ -458,7 +512,16 @@ define i64 @test_round_si64(float %x) {
; RV32IF-NEXT: .cfi_def_cfa_offset 16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: .cfi_offset ra, -4
; RV32IF-NEXT: call roundf@plt
; RV32IF-NEXT: lui a0, %hi(.LCPI27_0)
; RV32IF-NEXT: flw ft0, %lo(.LCPI27_0)(a0)
; RV32IF-NEXT: fabs.s ft1, fa0
; RV32IF-NEXT: flt.s a0, ft1, ft0
; RV32IF-NEXT: beqz a0, .LBB27_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.w.s a0, fa0, rmm
; RV32IF-NEXT: fcvt.s.w ft0, a0, rmm
; RV32IF-NEXT: fsgnj.s fa0, ft0, fa0
; RV32IF-NEXT: .LBB27_2:
; RV32IF-NEXT: call __fixsfdi@plt
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16
Expand Down Expand Up @@ -525,7 +588,16 @@ define i64 @test_round_ui64(float %x) {
; RV32IF-NEXT: .cfi_def_cfa_offset 16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: .cfi_offset ra, -4
; RV32IF-NEXT: call roundf@plt
; RV32IF-NEXT: lui a0, %hi(.LCPI31_0)
; RV32IF-NEXT: flw ft0, %lo(.LCPI31_0)(a0)
; RV32IF-NEXT: fabs.s ft1, fa0
; RV32IF-NEXT: flt.s a0, ft1, ft0
; RV32IF-NEXT: beqz a0, .LBB31_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.w.s a0, fa0, rmm
; RV32IF-NEXT: fcvt.s.w ft0, a0, rmm
; RV32IF-NEXT: fsgnj.s fa0, ft0, fa0
; RV32IF-NEXT: .LBB31_2:
; RV32IF-NEXT: call __fixunssfdi@plt
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16
Expand Down Expand Up @@ -592,7 +664,16 @@ define i64 @test_roundeven_si64(float %x) {
; RV32IF-NEXT: .cfi_def_cfa_offset 16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: .cfi_offset ra, -4
; RV32IF-NEXT: call roundevenf@plt
; RV32IF-NEXT: lui a0, %hi(.LCPI35_0)
; RV32IF-NEXT: flw ft0, %lo(.LCPI35_0)(a0)
; RV32IF-NEXT: fabs.s ft1, fa0
; RV32IF-NEXT: flt.s a0, ft1, ft0
; RV32IF-NEXT: beqz a0, .LBB35_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.w.s a0, fa0, rne
; RV32IF-NEXT: fcvt.s.w ft0, a0, rne
; RV32IF-NEXT: fsgnj.s fa0, ft0, fa0
; RV32IF-NEXT: .LBB35_2:
; RV32IF-NEXT: call __fixsfdi@plt
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16
Expand Down Expand Up @@ -659,7 +740,16 @@ define i64 @test_roundeven_ui64(float %x) {
; RV32IF-NEXT: .cfi_def_cfa_offset 16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: .cfi_offset ra, -4
; RV32IF-NEXT: call roundevenf@plt
; RV32IF-NEXT: lui a0, %hi(.LCPI39_0)
; RV32IF-NEXT: flw ft0, %lo(.LCPI39_0)(a0)
; RV32IF-NEXT: fabs.s ft1, fa0
; RV32IF-NEXT: flt.s a0, ft1, ft0
; RV32IF-NEXT: beqz a0, .LBB39_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.w.s a0, fa0, rne
; RV32IF-NEXT: fcvt.s.w ft0, a0, rne
; RV32IF-NEXT: fsgnj.s fa0, ft0, fa0
; RV32IF-NEXT: .LBB39_2:
; RV32IF-NEXT: call __fixunssfdi@plt
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16
Expand Down Expand Up @@ -698,11 +788,31 @@ define float @test_floor_float(float %x) {
; RV64IFD-NEXT: ret
; RV32IF-LABEL: test_floor_float:
; RV32IF: # %bb.0:
; RV32IF-NEXT: tail floorf@plt
; RV32IF-NEXT: lui a0, %hi(.LCPI40_0)
; RV32IF-NEXT: flw ft0, %lo(.LCPI40_0)(a0)
; RV32IF-NEXT: fabs.s ft1, fa0
; RV32IF-NEXT: flt.s a0, ft1, ft0
; RV32IF-NEXT: beqz a0, .LBB40_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.w.s a0, fa0, rdn
; RV32IF-NEXT: fcvt.s.w ft0, a0, rdn
; RV32IF-NEXT: fsgnj.s fa0, ft0, fa0
; RV32IF-NEXT: .LBB40_2:
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: test_floor_float:
; RV64IF: # %bb.0:
; RV64IF-NEXT: tail floorf@plt
; RV64IF-NEXT: lui a0, %hi(.LCPI40_0)
; RV64IF-NEXT: flw ft0, %lo(.LCPI40_0)(a0)
; RV64IF-NEXT: fabs.s ft1, fa0
; RV64IF-NEXT: flt.s a0, ft1, ft0
; RV64IF-NEXT: beqz a0, .LBB40_2
; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: fcvt.w.s a0, fa0, rdn
; RV64IF-NEXT: fcvt.s.w ft0, a0, rdn
; RV64IF-NEXT: fsgnj.s fa0, ft0, fa0
; RV64IF-NEXT: .LBB40_2:
; RV64IF-NEXT: ret
%a = call float @llvm.floor.f32(float %x)
ret float %a
}
Expand Down Expand Up @@ -731,11 +841,31 @@ define float @test_ceil_float(float %x) {
; RV64IFD-NEXT: ret
; RV32IF-LABEL: test_ceil_float:
; RV32IF: # %bb.0:
; RV32IF-NEXT: tail ceilf@plt
; RV32IF-NEXT: lui a0, %hi(.LCPI41_0)
; RV32IF-NEXT: flw ft0, %lo(.LCPI41_0)(a0)
; RV32IF-NEXT: fabs.s ft1, fa0
; RV32IF-NEXT: flt.s a0, ft1, ft0
; RV32IF-NEXT: beqz a0, .LBB41_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.w.s a0, fa0, rup
; RV32IF-NEXT: fcvt.s.w ft0, a0, rup
; RV32IF-NEXT: fsgnj.s fa0, ft0, fa0
; RV32IF-NEXT: .LBB41_2:
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: test_ceil_float:
; RV64IF: # %bb.0:
; RV64IF-NEXT: tail ceilf@plt
; RV64IF-NEXT: lui a0, %hi(.LCPI41_0)
; RV64IF-NEXT: flw ft0, %lo(.LCPI41_0)(a0)
; RV64IF-NEXT: fabs.s ft1, fa0
; RV64IF-NEXT: flt.s a0, ft1, ft0
; RV64IF-NEXT: beqz a0, .LBB41_2
; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: fcvt.w.s a0, fa0, rup
; RV64IF-NEXT: fcvt.s.w ft0, a0, rup
; RV64IF-NEXT: fsgnj.s fa0, ft0, fa0
; RV64IF-NEXT: .LBB41_2:
; RV64IF-NEXT: ret
%a = call float @llvm.ceil.f32(float %x)
ret float %a
}
Expand Down Expand Up @@ -764,11 +894,31 @@ define float @test_trunc_float(float %x) {
; RV64IFD-NEXT: ret
; RV32IF-LABEL: test_trunc_float:
; RV32IF: # %bb.0:
; RV32IF-NEXT: tail truncf@plt
; RV32IF-NEXT: lui a0, %hi(.LCPI42_0)
; RV32IF-NEXT: flw ft0, %lo(.LCPI42_0)(a0)
; RV32IF-NEXT: fabs.s ft1, fa0
; RV32IF-NEXT: flt.s a0, ft1, ft0
; RV32IF-NEXT: beqz a0, .LBB42_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz
; RV32IF-NEXT: fcvt.s.w ft0, a0, rtz
; RV32IF-NEXT: fsgnj.s fa0, ft0, fa0
; RV32IF-NEXT: .LBB42_2:
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: test_trunc_float:
; RV64IF: # %bb.0:
; RV64IF-NEXT: tail truncf@plt
; RV64IF-NEXT: lui a0, %hi(.LCPI42_0)
; RV64IF-NEXT: flw ft0, %lo(.LCPI42_0)(a0)
; RV64IF-NEXT: fabs.s ft1, fa0
; RV64IF-NEXT: flt.s a0, ft1, ft0
; RV64IF-NEXT: beqz a0, .LBB42_2
; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz
; RV64IF-NEXT: fcvt.s.w ft0, a0, rtz
; RV64IF-NEXT: fsgnj.s fa0, ft0, fa0
; RV64IF-NEXT: .LBB42_2:
; RV64IF-NEXT: ret
%a = call float @llvm.trunc.f32(float %x)
ret float %a
}
Expand Down Expand Up @@ -797,11 +947,31 @@ define float @test_round_float(float %x) {
; RV64IFD-NEXT: ret
; RV32IF-LABEL: test_round_float:
; RV32IF: # %bb.0:
; RV32IF-NEXT: tail roundf@plt
; RV32IF-NEXT: lui a0, %hi(.LCPI43_0)
; RV32IF-NEXT: flw ft0, %lo(.LCPI43_0)(a0)
; RV32IF-NEXT: fabs.s ft1, fa0
; RV32IF-NEXT: flt.s a0, ft1, ft0
; RV32IF-NEXT: beqz a0, .LBB43_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.w.s a0, fa0, rmm
; RV32IF-NEXT: fcvt.s.w ft0, a0, rmm
; RV32IF-NEXT: fsgnj.s fa0, ft0, fa0
; RV32IF-NEXT: .LBB43_2:
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: test_round_float:
; RV64IF: # %bb.0:
; RV64IF-NEXT: tail roundf@plt
; RV64IF-NEXT: lui a0, %hi(.LCPI43_0)
; RV64IF-NEXT: flw ft0, %lo(.LCPI43_0)(a0)
; RV64IF-NEXT: fabs.s ft1, fa0
; RV64IF-NEXT: flt.s a0, ft1, ft0
; RV64IF-NEXT: beqz a0, .LBB43_2
; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: fcvt.w.s a0, fa0, rmm
; RV64IF-NEXT: fcvt.s.w ft0, a0, rmm
; RV64IF-NEXT: fsgnj.s fa0, ft0, fa0
; RV64IF-NEXT: .LBB43_2:
; RV64IF-NEXT: ret
%a = call float @llvm.round.f32(float %x)
ret float %a
}
Expand Down Expand Up @@ -830,11 +1000,31 @@ define float @test_roundeven_float(float %x) {
; RV64IFD-NEXT: ret
; RV32IF-LABEL: test_roundeven_float:
; RV32IF: # %bb.0:
; RV32IF-NEXT: tail roundevenf@plt
; RV32IF-NEXT: lui a0, %hi(.LCPI44_0)
; RV32IF-NEXT: flw ft0, %lo(.LCPI44_0)(a0)
; RV32IF-NEXT: fabs.s ft1, fa0
; RV32IF-NEXT: flt.s a0, ft1, ft0
; RV32IF-NEXT: beqz a0, .LBB44_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.w.s a0, fa0, rne
; RV32IF-NEXT: fcvt.s.w ft0, a0, rne
; RV32IF-NEXT: fsgnj.s fa0, ft0, fa0
; RV32IF-NEXT: .LBB44_2:
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: test_roundeven_float:
; RV64IF: # %bb.0:
; RV64IF-NEXT: tail roundevenf@plt
; RV64IF-NEXT: lui a0, %hi(.LCPI44_0)
; RV64IF-NEXT: flw ft0, %lo(.LCPI44_0)(a0)
; RV64IF-NEXT: fabs.s ft1, fa0
; RV64IF-NEXT: flt.s a0, ft1, ft0
; RV64IF-NEXT: beqz a0, .LBB44_2
; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: fcvt.w.s a0, fa0, rne
; RV64IF-NEXT: fcvt.s.w ft0, a0, rne
; RV64IF-NEXT: fsgnj.s fa0, ft0, fa0
; RV64IF-NEXT: .LBB44_2:
; RV64IF-NEXT: ret
%a = call float @llvm.roundeven.f32(float %x)
ret float %a
}
Expand Down
204 changes: 78 additions & 126 deletions llvm/test/CodeGen/RISCV/half-intrinsics.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1097,27 +1097,19 @@ define half @copysign_f16(half %a, half %b) nounwind {
declare half @llvm.floor.f16(half)

define half @floor_f16(half %a) nounwind {
; RV32IZFH-LABEL: floor_f16:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: call floorf@plt
; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: floor_f16:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
; RV64IZFH-NEXT: call floorf@plt
; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
; CHECKIZFH-LABEL: floor_f16:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: lui a0, %hi(.LCPI17_0)
; CHECKIZFH-NEXT: flh ft0, %lo(.LCPI17_0)(a0)
; CHECKIZFH-NEXT: fabs.h ft1, fa0
; CHECKIZFH-NEXT: flt.h a0, ft1, ft0
; CHECKIZFH-NEXT: beqz a0, .LBB17_2
; CHECKIZFH-NEXT: # %bb.1:
; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rdn
; CHECKIZFH-NEXT: fcvt.h.w ft0, a0, rdn
; CHECKIZFH-NEXT: fsgnj.h fa0, ft0, fa0
; CHECKIZFH-NEXT: .LBB17_2:
; CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: floor_f16:
; RV32I: # %bb.0:
Expand Down Expand Up @@ -1151,27 +1143,19 @@ define half @floor_f16(half %a) nounwind {
declare half @llvm.ceil.f16(half)

define half @ceil_f16(half %a) nounwind {
; RV32IZFH-LABEL: ceil_f16:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: call ceilf@plt
; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: ceil_f16:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
; RV64IZFH-NEXT: call ceilf@plt
; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
; CHECKIZFH-LABEL: ceil_f16:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: lui a0, %hi(.LCPI18_0)
; CHECKIZFH-NEXT: flh ft0, %lo(.LCPI18_0)(a0)
; CHECKIZFH-NEXT: fabs.h ft1, fa0
; CHECKIZFH-NEXT: flt.h a0, ft1, ft0
; CHECKIZFH-NEXT: beqz a0, .LBB18_2
; CHECKIZFH-NEXT: # %bb.1:
; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rup
; CHECKIZFH-NEXT: fcvt.h.w ft0, a0, rup
; CHECKIZFH-NEXT: fsgnj.h fa0, ft0, fa0
; CHECKIZFH-NEXT: .LBB18_2:
; CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: ceil_f16:
; RV32I: # %bb.0:
Expand Down Expand Up @@ -1205,27 +1189,19 @@ define half @ceil_f16(half %a) nounwind {
declare half @llvm.trunc.f16(half)

define half @trunc_f16(half %a) nounwind {
; RV32IZFH-LABEL: trunc_f16:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: call truncf@plt
; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: trunc_f16:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
; RV64IZFH-NEXT: call truncf@plt
; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
; CHECKIZFH-LABEL: trunc_f16:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: lui a0, %hi(.LCPI19_0)
; CHECKIZFH-NEXT: flh ft0, %lo(.LCPI19_0)(a0)
; CHECKIZFH-NEXT: fabs.h ft1, fa0
; CHECKIZFH-NEXT: flt.h a0, ft1, ft0
; CHECKIZFH-NEXT: beqz a0, .LBB19_2
; CHECKIZFH-NEXT: # %bb.1:
; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rtz
; CHECKIZFH-NEXT: fcvt.h.w ft0, a0, rtz
; CHECKIZFH-NEXT: fsgnj.h fa0, ft0, fa0
; CHECKIZFH-NEXT: .LBB19_2:
; CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: trunc_f16:
; RV32I: # %bb.0:
Expand Down Expand Up @@ -1259,27 +1235,19 @@ define half @trunc_f16(half %a) nounwind {
declare half @llvm.rint.f16(half)

define half @rint_f16(half %a) nounwind {
; RV32IZFH-LABEL: rint_f16:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: call rintf@plt
; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: rint_f16:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
; RV64IZFH-NEXT: call rintf@plt
; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
; CHECKIZFH-LABEL: rint_f16:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: lui a0, %hi(.LCPI20_0)
; CHECKIZFH-NEXT: flh ft0, %lo(.LCPI20_0)(a0)
; CHECKIZFH-NEXT: fabs.h ft1, fa0
; CHECKIZFH-NEXT: flt.h a0, ft1, ft0
; CHECKIZFH-NEXT: beqz a0, .LBB20_2
; CHECKIZFH-NEXT: # %bb.1:
; CHECKIZFH-NEXT: fcvt.w.h a0, fa0
; CHECKIZFH-NEXT: fcvt.h.w ft0, a0
; CHECKIZFH-NEXT: fsgnj.h fa0, ft0, fa0
; CHECKIZFH-NEXT: .LBB20_2:
; CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: rint_f16:
; RV32I: # %bb.0:
Expand Down Expand Up @@ -1367,27 +1335,19 @@ define half @nearbyint_f16(half %a) nounwind {
declare half @llvm.round.f16(half)

define half @round_f16(half %a) nounwind {
; RV32IZFH-LABEL: round_f16:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: call roundf@plt
; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: round_f16:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
; RV64IZFH-NEXT: call roundf@plt
; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
; CHECKIZFH-LABEL: round_f16:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: lui a0, %hi(.LCPI22_0)
; CHECKIZFH-NEXT: flh ft0, %lo(.LCPI22_0)(a0)
; CHECKIZFH-NEXT: fabs.h ft1, fa0
; CHECKIZFH-NEXT: flt.h a0, ft1, ft0
; CHECKIZFH-NEXT: beqz a0, .LBB22_2
; CHECKIZFH-NEXT: # %bb.1:
; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rmm
; CHECKIZFH-NEXT: fcvt.h.w ft0, a0, rmm
; CHECKIZFH-NEXT: fsgnj.h fa0, ft0, fa0
; CHECKIZFH-NEXT: .LBB22_2:
; CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: round_f16:
; RV32I: # %bb.0:
Expand Down Expand Up @@ -1421,27 +1381,19 @@ define half @round_f16(half %a) nounwind {
declare half @llvm.roundeven.f16(half)

define half @roundeven_f16(half %a) nounwind {
; RV32IZFH-LABEL: roundeven_f16:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: call roundevenf@plt
; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: roundeven_f16:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
; RV64IZFH-NEXT: call roundevenf@plt
; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
; CHECKIZFH-LABEL: roundeven_f16:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: lui a0, %hi(.LCPI23_0)
; CHECKIZFH-NEXT: flh ft0, %lo(.LCPI23_0)(a0)
; CHECKIZFH-NEXT: fabs.h ft1, fa0
; CHECKIZFH-NEXT: flt.h a0, ft1, ft0
; CHECKIZFH-NEXT: beqz a0, .LBB23_2
; CHECKIZFH-NEXT: # %bb.1:
; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rne
; CHECKIZFH-NEXT: fcvt.h.w ft0, a0, rne
; CHECKIZFH-NEXT: fsgnj.h fa0, ft0, fa0
; CHECKIZFH-NEXT: .LBB23_2:
; CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: roundeven_f16:
; RV32I: # %bb.0:
Expand Down
365 changes: 220 additions & 145 deletions llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
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320 changes: 165 additions & 155 deletions llvm/test/CodeGen/RISCV/half-round-conv.ll
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