56 changes: 30 additions & 26 deletions llvm/test/CodeGen/AArch64/rm_redundant_cmp.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -49,16 +49,16 @@ define void @test_i16_2cmp_signed_2() {
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adrp x8, :got:cost_s_i8_i16
; CHECK-NEXT: ldr x8, [x8, :got_lo12:cost_s_i8_i16]
; CHECK-NEXT: ldrh w10, [x8, #2]
; CHECK-NEXT: ldrh w11, [x8, #4]
; CHECK-NEXT: sxth w9, w10
; CHECK-NEXT: cmp w9, w11, sxth
; CHECK-NEXT: csel w9, w10, w11, gt
; CHECK-NEXT: cmp w10, w11
; CHECK-NEXT: b.eq .LBB1_2
; CHECK-NEXT: // %bb.1: // %if.end8.sink.split
; CHECK-NEXT: ldrsh w9, [x8, #2]
; CHECK-NEXT: ldrsh w10, [x8, #4]
; CHECK-NEXT: cmp w9, w10
; CHECK-NEXT: b.gt .LBB1_2
; CHECK-NEXT: // %bb.1: // %if.else
; CHECK-NEXT: mov w9, w10
; CHECK-NEXT: b.ge .LBB1_3
; CHECK-NEXT: .LBB1_2: // %if.end8.sink.split
; CHECK-NEXT: strh w9, [x8]
; CHECK-NEXT: .LBB1_2: // %if.end8
; CHECK-NEXT: .LBB1_3: // %if.end8
; CHECK-NEXT: ret
entry:
%0 = load i16, ptr getelementptr inbounds (%struct.s_signed_i16, ptr @cost_s_i8_i16, i64 0, i32 1), align 2
Expand Down Expand Up @@ -125,11 +125,13 @@ define void @test_i16_2cmp_unsigned_2() {
; CHECK-NEXT: ldrh w9, [x8, #2]
; CHECK-NEXT: ldrh w10, [x8, #4]
; CHECK-NEXT: cmp w9, w10
; CHECK-NEXT: csel w9, w9, w10, hi
; CHECK-NEXT: b.eq .LBB3_2
; CHECK-NEXT: // %bb.1: // %if.end8.sink.split
; CHECK-NEXT: b.hi .LBB3_2
; CHECK-NEXT: // %bb.1: // %if.else
; CHECK-NEXT: mov w9, w10
; CHECK-NEXT: b.hs .LBB3_3
; CHECK-NEXT: .LBB3_2: // %if.end8.sink.split
; CHECK-NEXT: strh w9, [x8]
; CHECK-NEXT: .LBB3_2: // %if.end8
; CHECK-NEXT: .LBB3_3: // %if.end8
; CHECK-NEXT: ret
entry:
%0 = load i16, ptr getelementptr inbounds (%struct.s_unsigned_i16, ptr @cost_u_i16, i64 0, i32 1), align 2
Expand Down Expand Up @@ -202,16 +204,16 @@ define void @test_i8_2cmp_signed_2() {
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adrp x8, :got:cost_s
; CHECK-NEXT: ldr x8, [x8, :got_lo12:cost_s]
; CHECK-NEXT: ldrb w10, [x8, #1]
; CHECK-NEXT: ldrb w11, [x8, #2]
; CHECK-NEXT: sxtb w9, w10
; CHECK-NEXT: cmp w9, w11, sxtb
; CHECK-NEXT: csel w9, w10, w11, gt
; CHECK-NEXT: cmp w10, w11
; CHECK-NEXT: b.eq .LBB5_2
; CHECK-NEXT: // %bb.1: // %if.end8.sink.split
; CHECK-NEXT: ldrsb w9, [x8, #1]
; CHECK-NEXT: ldrsb w10, [x8, #2]
; CHECK-NEXT: cmp w9, w10
; CHECK-NEXT: b.gt .LBB5_2
; CHECK-NEXT: // %bb.1: // %if.else
; CHECK-NEXT: mov w9, w10
; CHECK-NEXT: b.ge .LBB5_3
; CHECK-NEXT: .LBB5_2: // %if.end8.sink.split
; CHECK-NEXT: strb w9, [x8]
; CHECK-NEXT: .LBB5_2: // %if.end8
; CHECK-NEXT: .LBB5_3: // %if.end8
; CHECK-NEXT: ret
entry:
%0 = load i8, ptr getelementptr inbounds (%struct.s_signed_i8, ptr @cost_s, i64 0, i32 1), align 2
Expand Down Expand Up @@ -278,11 +280,13 @@ define void @test_i8_2cmp_unsigned_2() {
; CHECK-NEXT: ldrb w9, [x8, #1]
; CHECK-NEXT: ldrb w10, [x8, #2]
; CHECK-NEXT: cmp w9, w10
; CHECK-NEXT: csel w9, w9, w10, hi
; CHECK-NEXT: b.eq .LBB7_2
; CHECK-NEXT: // %bb.1: // %if.end8.sink.split
; CHECK-NEXT: b.hi .LBB7_2
; CHECK-NEXT: // %bb.1: // %if.else
; CHECK-NEXT: mov w9, w10
; CHECK-NEXT: b.hs .LBB7_3
; CHECK-NEXT: .LBB7_2: // %if.end8.sink.split
; CHECK-NEXT: strb w9, [x8]
; CHECK-NEXT: .LBB7_2: // %if.end8
; CHECK-NEXT: .LBB7_3: // %if.end8
; CHECK-NEXT: ret
entry:
%0 = load i8, ptr getelementptr inbounds (%struct.s_unsigned_i8, ptr @cost_u_i8, i64 0, i32 1), align 2
Expand Down
33 changes: 17 additions & 16 deletions llvm/test/CodeGen/AArch64/tailmerging_in_mbp.ll
View file
Original file line number Diff line number Diff line change
@@ -1,22 +1,23 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: llc <%s -mtriple=aarch64-eabi -verify-machine-dom-info | FileCheck %s

; CHECK-LABEL: test:
; CHECK-LABEL: %cond.false12.i
; CHECK: csel x10, x8, x9, gt
; CHECK-NEXT: b.le .LBB0_11
define i64 @test(i64 %n, ptr %a, ptr %b, ptr %c, ptr %d, ptr %e, ptr %f) {
; CHECK: b.gt
; CHECK-NEXT: LBB0_8:
; CHECK-NEXT: mov x8, x9
; CHECK-NEXT: LBB0_9:
define i64 @test(i64 %n, i64* %a, i64* %b, i64* %c, i64* %d, i64* %e, i64* %f) {
entry:
%cmp28 = icmp sgt i64 %n, 1
br i1 %cmp28, label %for.body, label %for.end

for.body: ; preds = %for.body.lr.ph, %if.end
%j = phi i64 [ %n, %entry ], [ %div, %if.end ]
%div = lshr i64 %j, 1
%a.arrayidx = getelementptr inbounds i64, ptr %a, i64 %div
%a.j = load i64, ptr %a.arrayidx
%b.arrayidx = getelementptr inbounds i64, ptr %b, i64 %div
%b.j = load i64, ptr %b.arrayidx
%a.arrayidx = getelementptr inbounds i64, i64* %a, i64 %div
%a.j = load i64, i64* %a.arrayidx
%b.arrayidx = getelementptr inbounds i64, i64* %b, i64 %div
%b.j = load i64, i64* %b.arrayidx
%cmp.i = icmp slt i64 %a.j, %b.j
br i1 %cmp.i, label %for.end.loopexit, label %cond.false.i

Expand All @@ -25,10 +26,10 @@ cond.false.i: ; preds = %for.body
br i1 %cmp4.i, label %if.end, label %cond.false6.i

cond.false6.i: ; preds = %cond.false.i
%c.arrayidx = getelementptr inbounds i64, ptr %c, i64 %div
%c.j = load i64, ptr %c.arrayidx
%d.arrayidx = getelementptr inbounds i64, ptr %d, i64 %div
%d.j = load i64, ptr %d.arrayidx
%c.arrayidx = getelementptr inbounds i64, i64* %c, i64 %div
%c.j = load i64, i64* %c.arrayidx
%d.arrayidx = getelementptr inbounds i64, i64* %d, i64 %div
%d.j = load i64, i64* %d.arrayidx
%cmp9.i = icmp slt i64 %c.j, %d.j
br i1 %cmp9.i, label %for.end.loopexit, label %cond.false11.i

Expand All @@ -37,10 +38,10 @@ cond.false11.i: ; preds = %cond.false6.i
br i1 %cmp14.i, label %if.end, label %cond.false12.i

cond.false12.i: ; preds = %cond.false11.i
%e.arrayidx = getelementptr inbounds i64, ptr %e, i64 %div
%e.j = load i64, ptr %e.arrayidx
%f.arrayidx = getelementptr inbounds i64, ptr %f, i64 %div
%f.j = load i64, ptr %f.arrayidx
%e.arrayidx = getelementptr inbounds i64, i64* %e, i64 %div
%e.j = load i64, i64* %e.arrayidx
%f.arrayidx = getelementptr inbounds i64, i64* %f, i64 %div
%f.j = load i64, i64* %f.arrayidx
%cmp19.i = icmp sgt i64 %e.j, %f.j
br i1 %cmp19.i, label %if.end, label %for.end.loopexit

Expand Down
51 changes: 31 additions & 20 deletions llvm/test/CodeGen/AArch64/typepromotion-cost.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,30 +6,41 @@
define i32 @needless_promotion(ptr nocapture noundef readonly %S, i64 noundef %red_cost) {
; CHECK-O2-LABEL: needless_promotion:
; CHECK-O2: // %bb.0: // %entry
; CHECK-O2-NEXT: ldrsh w9, [x0, #4]
; CHECK-O2-NEXT: mov w8, #1
; CHECK-O2-NEXT: mov w10, #-1
; CHECK-O2-NEXT: cmp w9, #0
; CHECK-O2-NEXT: cinc w8, w8, ge
; CHECK-O2-NEXT: cmp w8, w9, uxth
; CHECK-O2-NEXT: cset w8, eq
; CHECK-O2-NEXT: cmp x1, #0
; CHECK-O2-NEXT: ccmp w9, w10, #4, eq
; CHECK-O2-NEXT: csel w0, wzr, w8, gt
; CHECK-O2-NEXT: ldrsh w8, [x0, #4]
; CHECK-O2-NEXT: tbnz w8, #31, .LBB0_3
; CHECK-O2-NEXT: // %bb.1: // %lor.rhs
; CHECK-O2-NEXT: cbz x1, .LBB0_5
; CHECK-O2-NEXT: // %bb.2:
; CHECK-O2-NEXT: mov w9, #2
; CHECK-O2-NEXT: b .LBB0_4
; CHECK-O2-NEXT: .LBB0_3:
; CHECK-O2-NEXT: mov w9, #1
; CHECK-O2-NEXT: .LBB0_4: // %lor.end.sink.split
; CHECK-O2-NEXT: cmp w8, w9
; CHECK-O2-NEXT: cset w0, eq
; CHECK-O2-NEXT: ret
; CHECK-O2-NEXT: .LBB0_5:
; CHECK-O2-NEXT: mov w0, wzr
; CHECK-O2-NEXT: ret
;
; CHECK-O3-LABEL: needless_promotion:
; CHECK-O3: // %bb.0: // %entry
; CHECK-O3-NEXT: ldrsh w9, [x0, #4]
; CHECK-O3-NEXT: mov w8, #1
; CHECK-O3-NEXT: mov w10, #-1
; CHECK-O3-NEXT: cmp w9, #0
; CHECK-O3-NEXT: cinc w8, w8, ge
; CHECK-O3-NEXT: cmp w8, w9, uxth
; CHECK-O3-NEXT: cset w8, eq
; CHECK-O3-NEXT: cmp x1, #0
; CHECK-O3-NEXT: ccmp w9, w10, #4, eq
; CHECK-O3-NEXT: csel w0, wzr, w8, gt
; CHECK-O3-NEXT: ldrsh w8, [x0, #4]
; CHECK-O3-NEXT: tbnz w8, #31, .LBB0_3
; CHECK-O3-NEXT: // %bb.1: // %lor.rhs
; CHECK-O3-NEXT: cbz x1, .LBB0_4
; CHECK-O3-NEXT: // %bb.2:
; CHECK-O3-NEXT: mov w9, #2
; CHECK-O3-NEXT: cmp w8, w9
; CHECK-O3-NEXT: cset w0, eq
; CHECK-O3-NEXT: ret
; CHECK-O3-NEXT: .LBB0_3:
; CHECK-O3-NEXT: mov w9, #1
; CHECK-O3-NEXT: cmp w8, w9
; CHECK-O3-NEXT: cset w0, eq
; CHECK-O3-NEXT: ret
; CHECK-O3-NEXT: .LBB0_4:
; CHECK-O3-NEXT: mov w0, wzr
; CHECK-O3-NEXT: ret
entry:
%ident = getelementptr inbounds %struct.S, ptr %S, i64 0, i32 1
Expand Down
72 changes: 46 additions & 26 deletions llvm/test/CodeGen/PowerPC/ppc-ctr-dead-code.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,30 +6,51 @@

; Function Attrs: norecurse nounwind readonly
define signext i32 @limit_loop(i32 signext %iters, ptr nocapture readonly %vec, i32 signext %limit) local_unnamed_addr {
; CHECK-LABEL: limit_loop:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpwi 3, 0
; CHECK-NEXT: ble 0, .LBB0_4
; CHECK-NEXT: # %bb.1: # %for.body.preheader
; CHECK-NEXT: addi 4, 4, -4
; CHECK-NEXT: li 6, 1
; CHECK-NEXT: .p2align 5
; CHECK-NEXT: .LBB0_2: # %for.body
; CHECK-NEXT: #
; CHECK-NEXT: lwzu 7, 4(4)
; CHECK-NEXT: cmpd 1, 6, 3
; CHECK-NEXT: addi 6, 6, 1
; CHECK-NEXT: cmpw 7, 5
; CHECK-NEXT: crand 20, 0, 4
; CHECK-NEXT: bc 12, 20, .LBB0_2
; CHECK-NEXT: # %bb.3: # %cleanup.loopexit
; CHECK-NEXT: li 3, 1
; CHECK-NEXT: isellt 3, 0, 3
; CHECK-NEXT: clrldi 3, 3, 32
; CHECK-NEXT: blr
; CHECK-NEXT: .LBB0_4:
; CHECK-NEXT: li 3, 0
; CHECK-NEXT: blr
; V01-LABEL: limit_loop:
; V01: # %bb.0: # %entry
; V01-NEXT: mr 6, 3
; V01-NEXT: li 3, 0
; V01-NEXT: cmpwi 6, 0
; V01-NEXT: blelr 0
; V01-NEXT: # %bb.1: # %for.body.preheader
; V01-NEXT: mtctr 6
; V01-NEXT: addi 4, 4, -4
; V01-NEXT: b .LBB0_3
; V01-NEXT: .p2align 4
; V01-NEXT: .LBB0_2: # %for.cond
; V01-NEXT: #
; V01-NEXT: bdzlr
; V01-NEXT: .LBB0_3: # %for.body
; V01-NEXT: #
; V01-NEXT: lwzu 6, 4(4)
; V01-NEXT: cmpw 6, 5
; V01-NEXT: blt 0, .LBB0_2
; V01-NEXT: # %bb.4:
; V01-NEXT: li 3, 1
; V01-NEXT: blr
;
; V23-LABEL: limit_loop:
; V23: # %bb.0: # %entry
; V23-NEXT: mr 6, 3
; V23-NEXT: li 3, 0
; V23-NEXT: cmpwi 6, 0
; V23-NEXT: blelr 0
; V23-NEXT: # %bb.1: # %for.body.preheader
; V23-NEXT: addi 4, 4, -4
; V23-NEXT: mtctr 6
; V23-NEXT: b .LBB0_3
; V23-NEXT: .p2align 4
; V23-NEXT: .LBB0_2: # %for.cond
; V23-NEXT: #
; V23-NEXT: bdzlr
; V23-NEXT: .LBB0_3: # %for.body
; V23-NEXT: #
; V23-NEXT: lwzu 6, 4(4)
; V23-NEXT: cmpw 6, 5
; V23-NEXT: blt 0, .LBB0_2
; V23-NEXT: # %bb.4:
; V23-NEXT: li 3, 1
; V23-NEXT: blr
entry:
%cmp5 = icmp sgt i32 %iters, 0
br i1 %cmp5, label %for.body.preheader, label %cleanup
Expand Down Expand Up @@ -57,9 +78,8 @@ cleanup: ; preds = %for.body, %for.cond


;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; CHECK: {{.*}}
; CHECK-V0: {{.*}}
; CHECK-V1: {{.*}}
; CHECK-V2: {{.*}}
; CHECK-V3: {{.*}}
; V01: {{.*}}
; V23: {{.*}}
48 changes: 25 additions & 23 deletions llvm/test/CodeGen/PowerPC/pr48527.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11,36 +11,38 @@ define void @_ZNK1q1rEv() local_unnamed_addr #0 align 2 {
; CHECK-LABEL: _ZNK1q1rEv:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 29, -24(1) # 8-byte Folded Spill
; CHECK-NEXT: std 30, -16(1) # 8-byte Folded Spill
; CHECK-NEXT: stdu 1, -48(1)
; CHECK-NEXT: std 0, 64(1)
; CHECK-NEXT: addis 4, 2, .LC0@toc@ha
; CHECK-NEXT: lwz 3, 0(3)
; CHECK-NEXT: ld 4, .LC0@toc@l(4)
; CHECK-NEXT: addi 3, 3, -1
; CHECK-NEXT: .p2align 5
; CHECK-NEXT: .LBB0_1: # %monotonic.i
; CHECK-NEXT: #
; CHECK-NEXT: lwz 5, 0(4)
; CHECK-NEXT: cmpwi 1, 3, 0
; CHECK-NEXT: addi 3, 3, -1
; CHECK-NEXT: andi. 5, 5, 255
; CHECK-NEXT: crorc 20, 6, 2
; CHECK-NEXT: bc 4, 20, .LBB0_1
; CHECK-NEXT: # %bb.2: # %if.end
; CHECK-NEXT: crnot 20, 2
; CHECK-NEXT: li 3, 0
; CHECK-NEXT: li 4, 8
; CHECK-NEXT: isel 30, 4, 3, 20
; CHECK-NEXT: stdu 1, -64(1)
; CHECK-NEXT: std 0, 80(1)
; CHECK-NEXT: lwz 30, 0(3)
; CHECK-NEXT: addis 3, 2, .LC0@toc@ha
; CHECK-NEXT: ld 29, .LC0@toc@l(3)
; CHECK-NEXT: addis 3, 2, aj@got@tlsgd@ha
; CHECK-NEXT: addi 3, 3, aj@got@tlsgd@l
; CHECK-NEXT: bl __tls_get_addr(aj@tlsgd)
; CHECK-NEXT: nop
; CHECK-NEXT: li 4, 1
; CHECK-NEXT: stdx 4, 3, 30
; CHECK-NEXT: addi 1, 1, 48
; CHECK-NEXT: addi 4, 3, 8
; CHECK-NEXT: .p2align 5
; CHECK-NEXT: .LBB0_1: # %monotonic.i
; CHECK-NEXT: #
; CHECK-NEXT: lwz 5, 0(29)
; CHECK-NEXT: andi. 5, 5, 255
; CHECK-NEXT: bne 0, .LBB0_4
; CHECK-NEXT: # %bb.2: # %for.cond.i
; CHECK-NEXT: #
; CHECK-NEXT: addi 30, 30, -1
; CHECK-NEXT: cmplwi 30, 0
; CHECK-NEXT: bne 0, .LBB0_1
; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: mr 4, 3
; CHECK-NEXT: .LBB0_4: # %if.end
; CHECK-NEXT: li 3, 1
; CHECK-NEXT: std 3, 0(4)
; CHECK-NEXT: addi 1, 1, 64
; CHECK-NEXT: ld 0, 16(1)
; CHECK-NEXT: ld 30, -16(1) # 8-byte Folded Reload
; CHECK-NEXT: ld 29, -24(1) # 8-byte Folded Reload
; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr
entry:
Expand Down
27 changes: 11 additions & 16 deletions llvm/test/CodeGen/X86/loop-search.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10,29 +10,24 @@ define zeroext i1 @search(i32 %needle, ptr nocapture readonly %haystack, i32 %co
; CHECK-NEXT: testl %edx, %edx
; CHECK-NEXT: jle LBB0_5
; CHECK-NEXT: ## %bb.1: ## %for.body.preheader
; CHECK-NEXT: movslq %edx, %rcx
; CHECK-NEXT: movl $1, %edx
; CHECK-NEXT: movslq %edx, %rax
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB0_2: ## %for.body
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movl -4(%rsi,%rdx,4), %r8d
; CHECK-NEXT: cmpl %edi, %r8d
; CHECK-NEXT: sete %al
; CHECK-NEXT: negb %al
; CHECK-NEXT: cmpl %edi, %r8d
; CHECK-NEXT: je LBB0_4
; CHECK-NEXT: ## %bb.3: ## %for.body
; CHECK-NEXT: cmpl %edi, (%rsi,%rcx,4)
; CHECK-NEXT: je LBB0_6
; CHECK-NEXT: ## %bb.3: ## %for.cond
; CHECK-NEXT: ## in Loop: Header=BB0_2 Depth=1
; CHECK-NEXT: cmpq %rcx, %rdx
; CHECK-NEXT: leaq 1(%rdx), %rdx
; CHECK-NEXT: incq %rcx
; CHECK-NEXT: cmpq %rax, %rcx
; CHECK-NEXT: jl LBB0_2
; CHECK-NEXT: LBB0_4: ## %cleanup
; CHECK-NEXT: andb $1, %al
; CHECK-NEXT: ## kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
; CHECK-NEXT: LBB0_5:
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: andb $1, %al
; CHECK-NEXT: ## kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
; CHECK-NEXT: LBB0_6:
; CHECK-NEXT: movb $1, %al
; CHECK-NEXT: ## kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
entry:
Expand Down
204 changes: 108 additions & 96 deletions llvm/test/Transforms/InstCombine/nested-select.ll
View file

Large diffs are not rendered by default.

55 changes: 33 additions & 22 deletions llvm/test/Transforms/InstCombine/select-factorize.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -138,8 +138,9 @@ define <3 x i1> @logic_and_logic_or_vector_poison2(<3 x i1> %c, <3 x i1> %a, <3

define <3 x i1> @logic_and_logic_or_vector_poison3(<3 x i1> %c, <3 x i1> %a, <3 x i1> %b) {
; CHECK-LABEL: @logic_and_logic_or_vector_poison3(
; CHECK-NEXT: [[BC:%.*]] = select <3 x i1> [[A:%.*]], <3 x i1> <i1 true, i1 true, i1 true>, <3 x i1> [[B:%.*]]
; CHECK-NEXT: [[OR:%.*]] = select <3 x i1> [[C:%.*]], <3 x i1> [[BC]], <3 x i1> <i1 poison, i1 false, i1 false>
; CHECK-NEXT: [[AC:%.*]] = select <3 x i1> [[C:%.*]], <3 x i1> [[A:%.*]], <3 x i1> zeroinitializer
; CHECK-NEXT: [[BC:%.*]] = select <3 x i1> [[C]], <3 x i1> [[B:%.*]], <3 x i1> <i1 poison, i1 false, i1 false>
; CHECK-NEXT: [[OR:%.*]] = select <3 x i1> [[AC]], <3 x i1> <i1 true, i1 true, i1 true>, <3 x i1> [[BC]]
; CHECK-NEXT: ret <3 x i1> [[OR]]
;
%ac = select <3 x i1> %c, <3 x i1> %a, <3 x i1> <i1 false, i1 false, i1 false>
Expand Down Expand Up @@ -169,8 +170,9 @@ define i1 @logic_and_logic_or_not_one_use(i1 %c, i1 %a, i1 %b) {

define i1 @and_logic_and_logic_or_1(i1 %c, i1 %a, i1 %b) {
; CHECK-LABEL: @and_logic_and_logic_or_1(
; CHECK-NEXT: [[BC:%.*]] = select i1 [[A:%.*]], i1 true, i1 [[B:%.*]]
; CHECK-NEXT: [[OR:%.*]] = select i1 [[C:%.*]], i1 [[BC]], i1 false
; CHECK-NEXT: [[AC:%.*]] = and i1 [[C:%.*]], [[A:%.*]]
; CHECK-NEXT: [[BC:%.*]] = select i1 [[C]], i1 [[B:%.*]], i1 false
; CHECK-NEXT: [[OR:%.*]] = select i1 [[AC]], i1 true, i1 [[BC]]
; CHECK-NEXT: ret i1 [[OR]]
;
%ac = and i1 %c, %a
Expand All @@ -194,8 +196,9 @@ define i1 @and_logic_and_logic_or_2(i1 %c, i1 %a, i1 %b) {

define i1 @and_logic_and_logic_or_3(i1 %c, i1 %a, i1 %b) {
; CHECK-LABEL: @and_logic_and_logic_or_3(
; CHECK-NEXT: [[BC:%.*]] = select i1 [[A:%.*]], i1 true, i1 [[B:%.*]]
; CHECK-NEXT: [[OR:%.*]] = select i1 [[C:%.*]], i1 [[BC]], i1 false
; CHECK-NEXT: [[AC:%.*]] = and i1 [[A:%.*]], [[C:%.*]]
; CHECK-NEXT: [[BC:%.*]] = select i1 [[C]], i1 [[B:%.*]], i1 false
; CHECK-NEXT: [[OR:%.*]] = select i1 [[AC]], i1 true, i1 [[BC]]
; CHECK-NEXT: ret i1 [[OR]]
;
%ac = and i1 %a, %c
Expand All @@ -219,8 +222,9 @@ define i1 @and_logic_and_logic_or_4(i1 %c, i1 %a, i1 %b) {

define <3 x i1> @and_logic_and_logic_or_vector(<3 x i1> %c, <3 x i1> %a, <3 x i1> %b) {
; CHECK-LABEL: @and_logic_and_logic_or_vector(
; CHECK-NEXT: [[BC:%.*]] = select <3 x i1> [[A:%.*]], <3 x i1> <i1 true, i1 true, i1 true>, <3 x i1> [[B:%.*]]
; CHECK-NEXT: [[OR:%.*]] = select <3 x i1> [[C:%.*]], <3 x i1> [[BC]], <3 x i1> zeroinitializer
; CHECK-NEXT: [[AC:%.*]] = and <3 x i1> [[C:%.*]], [[A:%.*]]
; CHECK-NEXT: [[BC:%.*]] = select <3 x i1> [[C]], <3 x i1> [[B:%.*]], <3 x i1> zeroinitializer
; CHECK-NEXT: [[OR:%.*]] = select <3 x i1> [[AC]], <3 x i1> <i1 true, i1 true, i1 true>, <3 x i1> [[BC]]
; CHECK-NEXT: ret <3 x i1> [[OR]]
;
%ac = and <3 x i1> %c, %a
Expand All @@ -231,8 +235,9 @@ define <3 x i1> @and_logic_and_logic_or_vector(<3 x i1> %c, <3 x i1> %a, <3 x i1

define <3 x i1> @and_logic_and_logic_or_vector_poison1(<3 x i1> %c, <3 x i1> %a, <3 x i1> %b) {
; CHECK-LABEL: @and_logic_and_logic_or_vector_poison1(
; CHECK-NEXT: [[BC:%.*]] = select <3 x i1> [[A:%.*]], <3 x i1> <i1 true, i1 true, i1 true>, <3 x i1> [[B:%.*]]
; CHECK-NEXT: [[OR:%.*]] = select <3 x i1> [[C:%.*]], <3 x i1> [[BC]], <3 x i1> <i1 false, i1 poison, i1 false>
; CHECK-NEXT: [[AC:%.*]] = and <3 x i1> [[C:%.*]], [[A:%.*]]
; CHECK-NEXT: [[BC:%.*]] = select <3 x i1> [[C]], <3 x i1> [[B:%.*]], <3 x i1> <i1 false, i1 poison, i1 false>
; CHECK-NEXT: [[OR:%.*]] = select <3 x i1> [[AC]], <3 x i1> <i1 true, i1 true, i1 true>, <3 x i1> [[BC]]
; CHECK-NEXT: ret <3 x i1> [[OR]]
;
%ac = and <3 x i1> %c, %a
Expand All @@ -243,8 +248,9 @@ define <3 x i1> @and_logic_and_logic_or_vector_poison1(<3 x i1> %c, <3 x i1> %a,

define <3 x i1> @and_logic_and_logic_or_vector_poison2(<3 x i1> %c, <3 x i1> %a, <3 x i1> %b) {
; CHECK-LABEL: @and_logic_and_logic_or_vector_poison2(
; CHECK-NEXT: [[BC:%.*]] = select <3 x i1> [[A:%.*]], <3 x i1> <i1 poison, i1 true, i1 true>, <3 x i1> [[B:%.*]]
; CHECK-NEXT: [[OR:%.*]] = select <3 x i1> [[C:%.*]], <3 x i1> [[BC]], <3 x i1> zeroinitializer
; CHECK-NEXT: [[AC:%.*]] = and <3 x i1> [[C:%.*]], [[A:%.*]]
; CHECK-NEXT: [[BC:%.*]] = select <3 x i1> [[C]], <3 x i1> [[B:%.*]], <3 x i1> zeroinitializer
; CHECK-NEXT: [[OR:%.*]] = select <3 x i1> [[AC]], <3 x i1> <i1 poison, i1 true, i1 true>, <3 x i1> [[BC]]
; CHECK-NEXT: ret <3 x i1> [[OR]]
;
%ac = and <3 x i1> %c, %a
Expand Down Expand Up @@ -462,8 +468,9 @@ define <3 x i1> @logic_or_logic_and_vector_poison1(<3 x i1> %c, <3 x i1> %a, <3

define <3 x i1> @logic_or_logic_and_vector_poison2(<3 x i1> %c, <3 x i1> %a, <3 x i1> %b) {
; CHECK-LABEL: @logic_or_logic_and_vector_poison2(
; CHECK-NEXT: [[BC:%.*]] = select <3 x i1> [[A:%.*]], <3 x i1> [[B:%.*]], <3 x i1> zeroinitializer
; CHECK-NEXT: [[OR:%.*]] = select <3 x i1> [[C:%.*]], <3 x i1> <i1 true, i1 poison, i1 true>, <3 x i1> [[BC]]
; CHECK-NEXT: [[AC:%.*]] = select <3 x i1> [[C:%.*]], <3 x i1> <i1 true, i1 true, i1 true>, <3 x i1> [[A:%.*]]
; CHECK-NEXT: [[BC:%.*]] = select <3 x i1> [[C]], <3 x i1> <i1 true, i1 poison, i1 true>, <3 x i1> [[B:%.*]]
; CHECK-NEXT: [[OR:%.*]] = select <3 x i1> [[AC]], <3 x i1> [[BC]], <3 x i1> zeroinitializer
; CHECK-NEXT: ret <3 x i1> [[OR]]
;
%ac = select <3 x i1> %c, <3 x i1> <i1 true, i1 true, i1 true>, <3 x i1> %a
Expand Down Expand Up @@ -505,8 +512,9 @@ define i1 @logic_or_logic_and_not_one_use(i1 %c, i1 %a, i1 %b) {

define i1 @or_logic_or_logic_and_1(i1 %c, i1 %a, i1 %b) {
; CHECK-LABEL: @or_logic_or_logic_and_1(
; CHECK-NEXT: [[BC:%.*]] = select i1 [[A:%.*]], i1 [[B:%.*]], i1 false
; CHECK-NEXT: [[OR:%.*]] = select i1 [[C:%.*]], i1 true, i1 [[BC]]
; CHECK-NEXT: [[AC:%.*]] = or i1 [[C:%.*]], [[A:%.*]]
; CHECK-NEXT: [[BC:%.*]] = select i1 [[C]], i1 true, i1 [[B:%.*]]
; CHECK-NEXT: [[OR:%.*]] = select i1 [[AC]], i1 [[BC]], i1 false
; CHECK-NEXT: ret i1 [[OR]]
;
%ac = or i1 %c, %a
Expand Down Expand Up @@ -556,8 +564,9 @@ define i1 @or_logic_or_logic_and_4(i1 %c, i1 %a, i1 %b) {

define <3 x i1> @or_logic_or_logic_and_vector(<3 x i1> %c, <3 x i1> %a, <3 x i1> %b) {
; CHECK-LABEL: @or_logic_or_logic_and_vector(
; CHECK-NEXT: [[BC:%.*]] = select <3 x i1> [[A:%.*]], <3 x i1> [[B:%.*]], <3 x i1> zeroinitializer
; CHECK-NEXT: [[OR:%.*]] = select <3 x i1> [[C:%.*]], <3 x i1> <i1 true, i1 true, i1 true>, <3 x i1> [[BC]]
; CHECK-NEXT: [[AC:%.*]] = or <3 x i1> [[C:%.*]], [[A:%.*]]
; CHECK-NEXT: [[BC:%.*]] = select <3 x i1> [[C]], <3 x i1> <i1 true, i1 true, i1 true>, <3 x i1> [[B:%.*]]
; CHECK-NEXT: [[OR:%.*]] = select <3 x i1> [[AC]], <3 x i1> [[BC]], <3 x i1> zeroinitializer
; CHECK-NEXT: ret <3 x i1> [[OR]]
;
%ac = or <3 x i1> %c, %a
Expand All @@ -568,8 +577,9 @@ define <3 x i1> @or_logic_or_logic_and_vector(<3 x i1> %c, <3 x i1> %a, <3 x i1>

define <3 x i1> @or_logic_or_logic_and_vector_poison1(<3 x i1> %c, <3 x i1> %a, <3 x i1> %b) {
; CHECK-LABEL: @or_logic_or_logic_and_vector_poison1(
; CHECK-NEXT: [[BC:%.*]] = select <3 x i1> [[A:%.*]], <3 x i1> [[B:%.*]], <3 x i1> zeroinitializer
; CHECK-NEXT: [[OR:%.*]] = select <3 x i1> [[C:%.*]], <3 x i1> <i1 true, i1 poison, i1 true>, <3 x i1> [[BC]]
; CHECK-NEXT: [[AC:%.*]] = or <3 x i1> [[C:%.*]], [[A:%.*]]
; CHECK-NEXT: [[BC:%.*]] = select <3 x i1> [[C]], <3 x i1> <i1 true, i1 poison, i1 true>, <3 x i1> [[B:%.*]]
; CHECK-NEXT: [[OR:%.*]] = select <3 x i1> [[AC]], <3 x i1> [[BC]], <3 x i1> zeroinitializer
; CHECK-NEXT: ret <3 x i1> [[OR]]
;
%ac = or <3 x i1> %c, %a
Expand All @@ -580,8 +590,9 @@ define <3 x i1> @or_logic_or_logic_and_vector_poison1(<3 x i1> %c, <3 x i1> %a,

define <3 x i1> @or_logic_or_logic_and_vector_poison2(<3 x i1> %c, <3 x i1> %a, <3 x i1> %b) {
; CHECK-LABEL: @or_logic_or_logic_and_vector_poison2(
; CHECK-NEXT: [[BC:%.*]] = select <3 x i1> [[A:%.*]], <3 x i1> [[B:%.*]], <3 x i1> <i1 false, i1 false, i1 poison>
; CHECK-NEXT: [[OR:%.*]] = select <3 x i1> [[C:%.*]], <3 x i1> <i1 true, i1 true, i1 true>, <3 x i1> [[BC]]
; CHECK-NEXT: [[AC:%.*]] = or <3 x i1> [[C:%.*]], [[A:%.*]]
; CHECK-NEXT: [[BC:%.*]] = select <3 x i1> [[C]], <3 x i1> <i1 true, i1 true, i1 true>, <3 x i1> [[B:%.*]]
; CHECK-NEXT: [[OR:%.*]] = select <3 x i1> [[AC]], <3 x i1> [[BC]], <3 x i1> <i1 false, i1 false, i1 poison>
; CHECK-NEXT: ret <3 x i1> [[OR]]
;
%ac = or <3 x i1> %c, %a
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/Transforms/InstCombine/unused-nonnull.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11,9 +11,9 @@ define i32 @main(i32 %argc, ptr %argv) #0 {
; CHECK-LABEL: define {{[^@]+}}@main
; CHECK-SAME: (i32 [[ARGC:%.*]], ptr nocapture readonly [[ARGV:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[DOTNOT:%.*]] = icmp sgt i32 [[ARGC]], 1
; CHECK-NEXT: [[RETVAL_SEL:%.*]] = select i1 [[DOTNOT]], i32 [[ARGC]], i32 0
; CHECK-NEXT: ret i32 [[RETVAL_SEL]]
; CHECK-NEXT: [[TMP0:%.*]] = icmp slt i32 [[ARGC]], 2
; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[TMP0]], i32 0, i32 [[ARGC]]
; CHECK-NEXT: ret i32 [[SPEC_SELECT]]
;
entry:
%ptr = load ptr, ptr %argv
Expand Down
55 changes: 39 additions & 16 deletions llvm/test/Transforms/LICM/hoist-phi.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -625,22 +625,45 @@ end:
; We can hoist blocks that contain an edge that exits the loop by ignoring that
; edge in the hoisted block.
define void @triangle_phi_loopexit(i32 %x, ptr %p) {
; CHECK-LABEL: @triangle_phi_loopexit(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[ADD:%.*]] = add i32 [[X:%.*]], 1
; CHECK-NEXT: [[CMP1_NOT:%.*]] = icmp sle i32 [[X]], 0
; CHECK-NEXT: [[CMP2:%.*]] = icmp sgt i32 10, [[ADD]]
; CHECK-NEXT: [[PHI_SEL:%.*]] = select i1 [[CMP1_NOT]], i32 [[X]], i32 [[ADD]]
; CHECK-NEXT: [[OR_COND:%.*]] = or i1 [[CMP1_NOT]], [[CMP2]]
; CHECK-NEXT: [[CMP3:%.*]] = icmp ne i32 [[PHI_SEL]], 0
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: br i1 [[OR_COND]], label [[THEN:%.*]], label [[END:%.*]]
; CHECK: then:
; CHECK-NEXT: store i32 [[PHI_SEL]], ptr [[P:%.*]], align 4
; CHECK-NEXT: br i1 [[CMP3]], label [[LOOP]], label [[END]]
; CHECK: end:
; CHECK-NEXT: ret void
; CHECK-DISABLED-LABEL: @triangle_phi_loopexit(
; CHECK-DISABLED-NEXT: entry:
; CHECK-DISABLED-NEXT: [[ADD:%.*]] = add i32 [[X:%.*]], 1
; CHECK-DISABLED-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[X]], 0
; CHECK-DISABLED-NEXT: [[CMP2:%.*]] = icmp sgt i32 10, [[ADD]]
; CHECK-DISABLED-NEXT: br label [[LOOP:%.*]]
; CHECK-DISABLED: loop:
; CHECK-DISABLED-NEXT: br i1 [[CMP1]], label [[IF:%.*]], label [[THEN:%.*]]
; CHECK-DISABLED: if:
; CHECK-DISABLED-NEXT: br i1 [[CMP2]], label [[THEN]], label [[END:%.*]]
; CHECK-DISABLED: then:
; CHECK-DISABLED-NEXT: [[PHI:%.*]] = phi i32 [ [[ADD]], [[IF]] ], [ [[X]], [[LOOP]] ]
; CHECK-DISABLED-NEXT: store i32 [[PHI]], ptr [[P:%.*]], align 4
; CHECK-DISABLED-NEXT: [[CMP3:%.*]] = icmp ne i32 [[PHI]], 0
; CHECK-DISABLED-NEXT: br i1 [[CMP3]], label [[LOOP]], label [[END]]
; CHECK-DISABLED: end:
; CHECK-DISABLED-NEXT: ret void
;
; CHECK-ENABLED-LABEL: @triangle_phi_loopexit(
; CHECK-ENABLED-NEXT: entry:
; CHECK-ENABLED-NEXT: [[ADD:%.*]] = add i32 [[X:%.*]], 1
; CHECK-ENABLED-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[X]], 0
; CHECK-ENABLED-NEXT: [[CMP2:%.*]] = icmp sgt i32 10, [[ADD]]
; CHECK-ENABLED-NEXT: br i1 [[CMP1]], label [[IF_LICM:%.*]], label [[THEN_LICM:%.*]]
; CHECK-ENABLED: if.licm:
; CHECK-ENABLED-NEXT: br label [[THEN_LICM]]
; CHECK-ENABLED: then.licm:
; CHECK-ENABLED-NEXT: [[PHI:%.*]] = phi i32 [ [[ADD]], [[IF_LICM]] ], [ [[X]], [[ENTRY:%.*]] ]
; CHECK-ENABLED-NEXT: [[CMP3:%.*]] = icmp ne i32 [[PHI]], 0
; CHECK-ENABLED-NEXT: br label [[LOOP:%.*]]
; CHECK-ENABLED: loop:
; CHECK-ENABLED-NEXT: br i1 [[CMP1]], label [[IF:%.*]], label [[THEN:%.*]]
; CHECK-ENABLED: if:
; CHECK-ENABLED-NEXT: br i1 [[CMP2]], label [[THEN]], label [[END:%.*]]
; CHECK-ENABLED: then:
; CHECK-ENABLED-NEXT: store i32 [[PHI]], ptr [[P:%.*]], align 4
; CHECK-ENABLED-NEXT: br i1 [[CMP3]], label [[LOOP]], label [[END]]
; CHECK-ENABLED: end:
; CHECK-ENABLED-NEXT: ret void
;
entry:
br label %loop
Expand Down
40 changes: 27 additions & 13 deletions llvm/test/Transforms/LICM/sinking.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -534,17 +534,24 @@ define i32 @test14(i32 %N, i32 %N2, i1 %C) {
; CHECK-NEXT: Entry:
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: Loop:
; CHECK-NEXT: [[N_ADDR_0_PN:%.*]] = phi i32 [ [[N:%.*]], [[ENTRY:%.*]] ], [ [[DEC:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[N_ADDR_0_PN:%.*]] = phi i32 [ [[DEC:%.*]], [[CONTLOOP:%.*]] ], [ [[N:%.*]], [[ENTRY:%.*]] ]
; CHECK-NEXT: [[DEC]] = add i32 [[N_ADDR_0_PN]], -1
; CHECK-NEXT: br i1 [[C:%.*]], label [[CONTLOOP]], label [[OUT12_SPLIT_LOOP_EXIT1:%.*]]
; CHECK: ContLoop:
; CHECK-NEXT: [[TMP_1:%.*]] = icmp ne i32 [[N_ADDR_0_PN]], 1
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C:%.*]], i1 [[TMP_1]], i1 false
; CHECK-NEXT: br i1 [[OR_COND]], label [[LOOP]], label [[OUT12:%.*]]
; CHECK: Out12:
; CHECK-NEXT: br i1 [[TMP_1]], label [[LOOP]], label [[OUT12_SPLIT_LOOP_EXIT:%.*]]
; CHECK: Out12.split.loop.exit:
; CHECK-NEXT: [[N_ADDR_0_PN_LCSSA4:%.*]] = phi i32 [ [[N_ADDR_0_PN]], [[CONTLOOP]] ]
; CHECK-NEXT: [[SINK_MUL_LE3:%.*]] = mul i32 [[N]], [[N_ADDR_0_PN_LCSSA4]]
; CHECK-NEXT: br label [[OUT12:%.*]]
; CHECK: Out12.split.loop.exit1:
; CHECK-NEXT: [[N_ADDR_0_PN_LCSSA:%.*]] = phi i32 [ [[N_ADDR_0_PN]], [[LOOP]] ]
; CHECK-NEXT: [[SINK_MUL_LE:%.*]] = mul i32 [[N]], [[N_ADDR_0_PN_LCSSA]]
; CHECK-NEXT: [[SINK_SUB_LE:%.*]] = sub i32 [[SINK_MUL_LE]], [[N]]
; CHECK-NEXT: [[TMP_SEL_LE:%.*]] = select i1 [[C]], i32 [[SINK_MUL_LE]], i32 [[SINK_SUB_LE]]
; CHECK-NEXT: ret i32 [[TMP_SEL_LE]]
; CHECK-NEXT: br label [[OUT12]]
; CHECK: Out12:
; CHECK-NEXT: [[TMP:%.*]] = phi i32 [ [[SINK_MUL_LE3]], [[OUT12_SPLIT_LOOP_EXIT]] ], [ [[SINK_SUB_LE]], [[OUT12_SPLIT_LOOP_EXIT1]] ]
; CHECK-NEXT: ret i32 [[TMP]]
;
Entry:
br label %Loop
Expand Down Expand Up @@ -573,18 +580,25 @@ define i32 @test15(i32 %N, i32 %N2, i1 %C) {
; CHECK-NEXT: Entry:
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: Loop:
; CHECK-NEXT: [[N_ADDR_0_PN:%.*]] = phi i32 [ [[N:%.*]], [[ENTRY:%.*]] ], [ [[DEC:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[N_ADDR_0_PN:%.*]] = phi i32 [ [[DEC:%.*]], [[CONTLOOP:%.*]] ], [ [[N:%.*]], [[ENTRY:%.*]] ]
; CHECK-NEXT: [[DEC]] = add i32 [[N_ADDR_0_PN]], -1
; CHECK-NEXT: br i1 [[C:%.*]], label [[CONTLOOP]], label [[OUT12_SPLIT_LOOP_EXIT1:%.*]]
; CHECK: ContLoop:
; CHECK-NEXT: [[TMP_1:%.*]] = icmp ne i32 [[N_ADDR_0_PN]], 1
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C:%.*]], i1 [[TMP_1]], i1 false
; CHECK-NEXT: br i1 [[OR_COND]], label [[LOOP]], label [[OUT12:%.*]]
; CHECK: Out12:
; CHECK-NEXT: br i1 [[TMP_1]], label [[LOOP]], label [[OUT12_SPLIT_LOOP_EXIT:%.*]]
; CHECK: Out12.split.loop.exit:
; CHECK-NEXT: [[N_ADDR_0_PN_LCSSA5:%.*]] = phi i32 [ [[N_ADDR_0_PN]], [[CONTLOOP]] ]
; CHECK-NEXT: [[SINK_MUL_LE4:%.*]] = mul i32 [[N]], [[N_ADDR_0_PN_LCSSA5]]
; CHECK-NEXT: [[SINK_SUB2_LE:%.*]] = sub i32 [[SINK_MUL_LE4]], [[N2:%.*]]
; CHECK-NEXT: br label [[OUT12:%.*]]
; CHECK: Out12.split.loop.exit1:
; CHECK-NEXT: [[N_ADDR_0_PN_LCSSA:%.*]] = phi i32 [ [[N_ADDR_0_PN]], [[LOOP]] ]
; CHECK-NEXT: [[SINK_MUL_LE:%.*]] = mul i32 [[N]], [[N_ADDR_0_PN_LCSSA]]
; CHECK-NEXT: [[SINK_SUB_LE:%.*]] = sub i32 [[SINK_MUL_LE]], [[N]]
; CHECK-NEXT: [[SINK_SUB2_LE:%.*]] = sub i32 [[SINK_MUL_LE]], [[N2:%.*]]
; CHECK-NEXT: [[TMP_SEL_LE:%.*]] = select i1 [[C]], i32 [[SINK_SUB2_LE]], i32 [[SINK_SUB_LE]]
; CHECK-NEXT: ret i32 [[TMP_SEL_LE]]
; CHECK-NEXT: br label [[OUT12]]
; CHECK: Out12:
; CHECK-NEXT: [[TMP:%.*]] = phi i32 [ [[SINK_SUB2_LE]], [[OUT12_SPLIT_LOOP_EXIT]] ], [ [[SINK_SUB_LE]], [[OUT12_SPLIT_LOOP_EXIT1]] ]
; CHECK-NEXT: ret i32 [[TMP]]
;
Entry:
br label %Loop
Expand Down
42 changes: 20 additions & 22 deletions llvm/test/Transforms/LoopStrengthReduce/AArch64/small-constant.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -20,22 +20,21 @@ define float @test1(float* nocapture readonly %arr, i64 %start, float %threshold
; CHECK-NEXT: cbz x1, .LBB0_4
; CHECK-NEXT: // %bb.1: // %for.body.preheader
; CHECK-NEXT: add x8, x0, #28
; CHECK-NEXT: fmov s2, #-7.00000000
; CHECK-NEXT: .LBB0_2: // %for.body
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldr s1, [x8, x1, lsl #2]
; CHECK-NEXT: adds x1, x1, #1
; CHECK-NEXT: cset w9, hs
; CHECK-NEXT: fcmp s1, s0
; CHECK-NEXT: fcsel s1, s1, s2, gt
; CHECK-NEXT: ccmp w9, #0, #0, le
; CHECK-NEXT: b.eq .LBB0_2
; CHECK-NEXT: // %bb.3: // %cleanup2
; CHECK-NEXT: fmov s0, s1
; CHECK-NEXT: ret
; CHECK-NEXT: b.gt .LBB0_5
; CHECK-NEXT: // %bb.3: // %for.cond
; CHECK-NEXT: // in Loop: Header=BB0_2 Depth=1
; CHECK-NEXT: add x1, x1, #1
; CHECK-NEXT: cbnz x1, .LBB0_2
; CHECK-NEXT: .LBB0_4:
; CHECK-NEXT: fmov s0, #-7.00000000
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB0_5: // %cleanup2
; CHECK-NEXT: fmov s0, s1
; CHECK-NEXT: ret
entry:
%cmp11 = icmp eq i64 %start, 0
br i1 %cmp11, label %cleanup2, label %for.body
Expand Down Expand Up @@ -66,24 +65,23 @@ define float @test2(float* nocapture readonly %arr, i64 %start, float %threshold
; CHECK-NEXT: cbz x1, .LBB1_4
; CHECK-NEXT: // %bb.1: // %for.body.preheader
; CHECK-NEXT: add x8, x0, #28
; CHECK-NEXT: fmov s2, #-7.00000000
; CHECK-NEXT: .LBB1_2: // %for.body
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: scvtf s1, x1
; CHECK-NEXT: ldr s3, [x8, x1, lsl #2]
; CHECK-NEXT: adds x1, x1, #1
; CHECK-NEXT: cset w9, hs
; CHECK-NEXT: fadd s1, s1, s0
; CHECK-NEXT: fcmp s3, s1
; CHECK-NEXT: fcsel s1, s3, s2, gt
; CHECK-NEXT: ccmp w9, #0, #0, le
; CHECK-NEXT: b.eq .LBB1_2
; CHECK-NEXT: // %bb.3: // %cleanup4
; CHECK-NEXT: fmov s0, s1
; CHECK-NEXT: ret
; CHECK-NEXT: scvtf s2, x1
; CHECK-NEXT: ldr s1, [x8, x1, lsl #2]
; CHECK-NEXT: fadd s2, s2, s0
; CHECK-NEXT: fcmp s1, s2
; CHECK-NEXT: b.gt .LBB1_5
; CHECK-NEXT: // %bb.3: // %for.cond
; CHECK-NEXT: // in Loop: Header=BB1_2 Depth=1
; CHECK-NEXT: add x1, x1, #1
; CHECK-NEXT: cbnz x1, .LBB1_2
; CHECK-NEXT: .LBB1_4:
; CHECK-NEXT: fmov s0, #-7.00000000
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB1_5: // %cleanup4
; CHECK-NEXT: fmov s0, s1
; CHECK-NEXT: ret
entry:
%cmp14 = icmp eq i64 %start, 0
br i1 %cmp14, label %cleanup4, label %for.body
Expand Down
295 changes: 235 additions & 60 deletions llvm/test/Transforms/LoopUnroll/runtime-loop-multiple-exits.ll
View file

Large diffs are not rendered by default.

16 changes: 9 additions & 7 deletions llvm/test/Transforms/LoopUnroll/scevunroll.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -310,14 +310,16 @@ define void @nsw_latch(i32* %a) nounwind {
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body:
; CHECK-NEXT: [[B_03:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[ADD:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[TOBOOL_NOT:%.*]] = icmp ne i32 [[B_03]], 0
; CHECK-NEXT: [[ADD]] = add nuw nsw i32 [[B_03]], 8
; CHECK-NEXT: [[RETVAL_0_SEL:%.*]] = select i1 [[TOBOOL_NOT]], i32 1, i32 0
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[TOBOOL_NOT]], i1 true, i1 false
; CHECK-NEXT: br i1 [[OR_COND]], label [[RETURN:%.*]], label [[FOR_BODY]]
; CHECK-NEXT: br label [[FOR_COND:%.*]]
; CHECK: for.cond:
; CHECK-NEXT: br i1 false, label [[RETURN:%.*]], label [[FOR_BODY_1:%.*]]
; CHECK: for.body.1:
; CHECK-NEXT: br i1 false, label [[FOR_COND_1:%.*]], label [[RETURN]]
; CHECK: for.cond.1:
; CHECK-NEXT: br label [[RETURN]]
; CHECK: return:
; CHECK-NEXT: [[B_03_LCSSA:%.*]] = phi i32 [ [[B_03]], [[FOR_BODY]] ]
; CHECK-NEXT: [[B_03_LCSSA:%.*]] = phi i32 [ 0, [[FOR_COND]] ], [ 8, [[FOR_BODY_1]] ], [ 0, [[FOR_COND_1]] ]
; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ 0, [[FOR_COND]] ], [ 1, [[FOR_BODY_1]] ], [ 0, [[FOR_COND_1]] ]
; CHECK-NEXT: store i32 [[B_03_LCSSA]], i32* [[A:%.*]], align 4
; CHECK-NEXT: ret void
;
Expand Down
8 changes: 5 additions & 3 deletions llvm/test/Transforms/LoopUnroll/unroll-after-peel.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,10 +8,10 @@ define i64 @hoge(i1 %c) {
; CHECK: bb1.peel.begin:
; CHECK-NEXT: br label [[BB1_PEEL:%.*]]
; CHECK: bb1.peel:
; CHECK-NEXT: br i1 [[C:%.*]], label [[BB2_PEEL:%.*]], label [[BB4:%.*]]
; CHECK: bb2.peel:
; CHECK-NEXT: [[TMP3_PEEL:%.*]] = icmp slt i32 0, 9
; CHECK-NEXT: [[TMP5_SEL_PEEL:%.*]] = select i1 [[C:%.*]], i32 8, i32 0
; CHECK-NEXT: [[OR_COND_PEEL:%.*]] = and i1 [[C]], [[TMP3_PEEL]]
; CHECK-NEXT: br i1 [[OR_COND_PEEL]], label [[BB1_PEEL_NEXT:%.*]], label [[BB4:%.*]]
; CHECK-NEXT: br i1 [[TMP3_PEEL]], label [[BB1_PEEL_NEXT:%.*]], label [[BB4]]
; CHECK: bb1.peel.next:
; CHECK-NEXT: br label [[BB1_PEEL_NEXT1:%.*]]
; CHECK: bb1.peel.next1:
Expand All @@ -21,8 +21,10 @@ define i64 @hoge(i1 %c) {
; CHECK: bb1:
; CHECK-NEXT: br i1 [[C]], label [[BB1]], label [[BB4_LOOPEXIT:%.*]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: bb4.loopexit:
; CHECK-NEXT: [[TMP5_PH:%.*]] = phi i32 [ 8, [[BB1]] ]
; CHECK-NEXT: br label [[BB4]]
; CHECK: bb4:
; CHECK-NEXT: [[TMP5:%.*]] = phi i32 [ 0, [[BB1_PEEL]] ], [ 8, [[BB2_PEEL]] ], [ [[TMP5_PH]], [[BB4_LOOPEXIT]] ]
; CHECK-NEXT: [[TMP6:%.*]] = call i64 (...) @llvm.experimental.deoptimize.i64(i32 10) [ "deopt"() ]
; CHECK-NEXT: ret i64 [[TMP6]]
;
Expand Down
58 changes: 43 additions & 15 deletions llvm/test/Transforms/LoopUnroll/unroll-header-exiting-with-phis-multiple-exiting-blocks.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,25 +8,53 @@ define i16 @full_unroll_multiple_exiting_blocks(i16* %A, i16 %x, i16 %y) {
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[HEADER:%.*]]
; CHECK: header:
; CHECK-NEXT: [[RES:%.*]] = phi i16 [ 123, [[ENTRY:%.*]] ], [ [[RES_NEXT:%.*]], [[LATCH:%.*]] ]
; CHECK-NEXT: [[I_0:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[INC9:%.*]], [[LATCH]] ]
; CHECK-NEXT: [[PTR:%.*]] = getelementptr inbounds i16, i16* [[A:%.*]], i64 [[I_0]]
; CHECK-NEXT: [[LV:%.*]] = load i16, i16* [[PTR]], align 2
; CHECK-NEXT: [[RES_NEXT]] = add i16 [[RES]], [[LV]]
; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp uge i64 [[I_0]], 3
; CHECK-NEXT: [[LV:%.*]] = load i16, i16* [[A:%.*]], align 2
; CHECK-NEXT: [[RES_NEXT:%.*]] = add i16 123, [[LV]]
; CHECK-NEXT: br label [[EXITING_1:%.*]]
; CHECK: exiting.1:
; CHECK-NEXT: [[EC_1:%.*]] = icmp eq i16 [[LV]], [[X:%.*]]
; CHECK-NEXT: [[RES_LCSSA_SEL:%.*]] = select i1 [[CMP_NOT]], i16 [[RES_NEXT]], i16 0
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[CMP_NOT]], i1 true, i1 [[EC_1]]
; CHECK-NEXT: br i1 [[EC_1]], label [[EXIT:%.*]], label [[EXITING_2:%.*]]
; CHECK: exiting.2:
; CHECK-NEXT: [[EC_2:%.*]] = icmp eq i16 [[LV]], [[Y:%.*]]
; CHECK-NEXT: [[RES_LCSSA_SEL1:%.*]] = select i1 [[OR_COND]], i16 [[RES_LCSSA_SEL]], i16 1
; CHECK-NEXT: [[OR_COND2:%.*]] = select i1 [[OR_COND]], i1 true, i1 [[EC_2]]
; CHECK-NEXT: br i1 [[OR_COND2]], label [[EXIT:%.*]], label [[LATCH]]
; CHECK-NEXT: br i1 [[EC_2]], label [[EXIT]], label [[LATCH:%.*]]
; CHECK: latch:
; CHECK-NEXT: [[INC9]] = add i64 [[I_0]], 1
; CHECK-NEXT: br label [[HEADER]]
; CHECK-NEXT: [[PTR_1:%.*]] = getelementptr inbounds i16, i16* [[A]], i64 1
; CHECK-NEXT: [[LV_1:%.*]] = load i16, i16* [[PTR_1]], align 2
; CHECK-NEXT: [[RES_NEXT_1:%.*]] = add i16 [[RES_NEXT]], [[LV_1]]
; CHECK-NEXT: br label [[EXITING_1_1:%.*]]
; CHECK: exiting.1.1:
; CHECK-NEXT: [[EC_1_1:%.*]] = icmp eq i16 [[LV_1]], [[X]]
; CHECK-NEXT: br i1 [[EC_1_1]], label [[EXIT]], label [[EXITING_2_1:%.*]]
; CHECK: exiting.2.1:
; CHECK-NEXT: [[EC_2_1:%.*]] = icmp eq i16 [[LV_1]], [[Y]]
; CHECK-NEXT: br i1 [[EC_2_1]], label [[EXIT]], label [[LATCH_1:%.*]]
; CHECK: latch.1:
; CHECK-NEXT: [[PTR_2:%.*]] = getelementptr inbounds i16, i16* [[A]], i64 2
; CHECK-NEXT: [[LV_2:%.*]] = load i16, i16* [[PTR_2]], align 2
; CHECK-NEXT: [[RES_NEXT_2:%.*]] = add i16 [[RES_NEXT_1]], [[LV_2]]
; CHECK-NEXT: br label [[EXITING_1_2:%.*]]
; CHECK: exiting.1.2:
; CHECK-NEXT: [[EC_1_2:%.*]] = icmp eq i16 [[LV_2]], [[X]]
; CHECK-NEXT: br i1 [[EC_1_2]], label [[EXIT]], label [[EXITING_2_2:%.*]]
; CHECK: exiting.2.2:
; CHECK-NEXT: [[EC_2_2:%.*]] = icmp eq i16 [[LV_2]], [[Y]]
; CHECK-NEXT: br i1 [[EC_2_2]], label [[EXIT]], label [[LATCH_2:%.*]]
; CHECK: latch.2:
; CHECK-NEXT: [[PTR_3:%.*]] = getelementptr inbounds i16, i16* [[A]], i64 3
; CHECK-NEXT: [[LV_3:%.*]] = load i16, i16* [[PTR_3]], align 2
; CHECK-NEXT: [[RES_NEXT_3:%.*]] = add i16 [[RES_NEXT_2]], [[LV_3]]
; CHECK-NEXT: br i1 false, label [[EXITING_1_3:%.*]], label [[EXIT]]
; CHECK: exiting.1.3:
; CHECK-NEXT: [[EC_1_3:%.*]] = icmp eq i16 [[LV_3]], [[X]]
; CHECK-NEXT: br i1 [[EC_1_3]], label [[EXIT]], label [[EXITING_2_3:%.*]]
; CHECK: exiting.2.3:
; CHECK-NEXT: [[EC_2_3:%.*]] = icmp eq i16 [[LV_3]], [[Y]]
; CHECK-NEXT: br i1 [[EC_2_3]], label [[EXIT]], label [[LATCH_3:%.*]]
; CHECK: latch.3:
; CHECK-NEXT: unreachable
; CHECK: exit:
; CHECK-NEXT: [[RES_LCSSA_SEL1_LCSSA:%.*]] = phi i16 [ [[RES_LCSSA_SEL1]], [[HEADER]] ]
; CHECK-NEXT: ret i16 [[RES_LCSSA_SEL1_LCSSA]]
; CHECK-NEXT: [[RES_LCSSA:%.*]] = phi i16 [ 0, [[EXITING_1]] ], [ 1, [[EXITING_2]] ], [ 0, [[EXITING_1_1]] ], [ 1, [[EXITING_2_1]] ], [ 0, [[EXITING_1_2]] ], [ 1, [[EXITING_2_2]] ], [ [[RES_NEXT_3]], [[LATCH_2]] ], [ 0, [[EXITING_1_3]] ], [ 1, [[EXITING_2_3]] ]
; CHECK-NEXT: ret i16 [[RES_LCSSA]]
;
entry:
br label %header
Expand Down
13 changes: 7 additions & 6 deletions llvm/test/Transforms/SimplifyCFG/2008-07-13-InfLoopMiscompile.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,14 +13,15 @@ define i32 @main() nounwind {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[L:%.*]] = load i32, ptr @g_37, align 4
; CHECK-NEXT: [[CMPA:%.*]] = icmp ne i32 [[L]], 0
; CHECK-NEXT: br i1 [[CMPA]], label [[FUNC_1_EXIT:%.*]], label [[MOOSEBLOCK:%.*]]
; CHECK: mooseblock:
; CHECK-NEXT: [[CMPB:%.*]] = icmp eq i1 [[CMPA]], false
; CHECK-NEXT: [[OUTVAL_SEL:%.*]] = select i1 [[CMPA]], i32 1, i32 0
; CHECK-NEXT: [[OR_COND:%.*]] = or i1 [[CMPA]], [[CMPB]]
; CHECK-NEXT: [[BRMERGE:%.*]] = or i1 [[OR_COND]], [[CMPA]]
; CHECK-NEXT: [[OUTVAL_SEL_MUX:%.*]] = select i1 [[OR_COND]], i32 [[OUTVAL_SEL]], i32 2
; CHECK-NEXT: br i1 [[BRMERGE]], label [[FUNC_1_EXIT:%.*]], label [[INFLOOP:%.*]]
; CHECK-NEXT: [[BRMERGE:%.*]] = or i1 [[CMPB]], [[CMPA]]
; CHECK-NEXT: [[DOTMUX:%.*]] = select i1 [[CMPB]], i32 0, i32 2
; CHECK-NEXT: br i1 [[BRMERGE]], label [[FUNC_1_EXIT]], label [[INFLOOP:%.*]]
; CHECK: func_1.exit:
; CHECK-NEXT: [[POUT:%.*]] = tail call i32 (ptr, ...) @printf(ptr noalias @.str, i32 [[OUTVAL_SEL_MUX]]) #[[ATTR0:[0-9]+]]
; CHECK-NEXT: [[OUTVAL:%.*]] = phi i32 [ 1, [[ENTRY:%.*]] ], [ [[DOTMUX]], [[MOOSEBLOCK]] ]
; CHECK-NEXT: [[POUT:%.*]] = tail call i32 (ptr, ...) @printf(ptr noalias @.str, i32 [[OUTVAL]]) #[[ATTR0:[0-9]+]]
; CHECK-NEXT: ret i32 0
; CHECK: infloop:
; CHECK-NEXT: br label [[INFLOOP]]
Expand Down
34 changes: 20 additions & 14 deletions llvm/test/Transforms/SimplifyCFG/X86/SpeculativeExec.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,10 +9,9 @@ define i32 @test1(i32 %a, i32 %b, i32 %c) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[T1:%.*]] = icmp eq i32 [[B:%.*]], 0
; CHECK-NEXT: [[T2:%.*]] = icmp sgt i32 [[C:%.*]], 1
; CHECK-NEXT: [[T4_SEL:%.*]] = select i1 [[T1]], i32 [[A:%.*]], i32 [[B]]
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[T1]], i1 [[T2]], i1 false
; CHECK-NEXT: [[T3:%.*]] = add i32 [[A]], 1
; CHECK-NEXT: [[T4:%.*]] = select i1 [[OR_COND]], i32 [[T3]], i32 [[T4_SEL]]
; CHECK-NEXT: [[T3:%.*]] = add i32 [[A:%.*]], 1
; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[T2]], i32 [[T3]], i32 [[A]]
; CHECK-NEXT: [[T4:%.*]] = select i1 [[T1]], i32 [[SPEC_SELECT]], i32 [[B]]
; CHECK-NEXT: [[T5:%.*]] = sub i32 [[T4]], 1
; CHECK-NEXT: ret i32 [[T5]]
;
Expand All @@ -38,11 +37,15 @@ define float @spec_select_fp1(float %a, float %b, float %c) {
; CHECK-LABEL: @spec_select_fp1(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[T1:%.*]] = fcmp oeq float [[B:%.*]], 0.000000e+00
; CHECK-NEXT: br i1 [[T1]], label [[BB1:%.*]], label [[BB3:%.*]]
; CHECK: bb1:
; CHECK-NEXT: [[T2:%.*]] = fcmp ogt float [[C:%.*]], 1.000000e+00
; CHECK-NEXT: [[T4_SEL:%.*]] = select i1 [[T1]], float [[A:%.*]], float [[B]]
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[T1]], i1 [[T2]], i1 false
; CHECK-NEXT: [[T3:%.*]] = fadd float [[A]], 1.000000e+00
; CHECK-NEXT: [[T4:%.*]] = select ninf i1 [[OR_COND]], float [[T3]], float [[T4_SEL]]
; CHECK-NEXT: br i1 [[T2]], label [[BB2:%.*]], label [[BB3]]
; CHECK: bb2:
; CHECK-NEXT: [[T3:%.*]] = fadd float [[A:%.*]], 1.000000e+00
; CHECK-NEXT: br label [[BB3]]
; CHECK: bb3:
; CHECK-NEXT: [[T4:%.*]] = phi ninf float [ [[B]], [[ENTRY:%.*]] ], [ [[A]], [[BB1]] ], [ [[T3]], [[BB2]] ]
; CHECK-NEXT: [[T5:%.*]] = fsub float [[T4]], 1.000000e+00
; CHECK-NEXT: ret float [[T5]]
;
Expand Down Expand Up @@ -121,10 +124,9 @@ define ptr @test5(i32 %a, i32 %b, i32 %c, ptr dereferenceable(10) %ptr1, ptr der
; CHECK-NEXT: entry:
; CHECK-NEXT: [[T1:%.*]] = icmp eq i32 [[B:%.*]], 0
; CHECK-NEXT: [[T2:%.*]] = icmp sgt i32 [[C:%.*]], 1
; CHECK-NEXT: [[T4_SEL:%.*]] = select i1 [[T1]], ptr [[PTR2:%.*]], ptr [[PTR1:%.*]]
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[T1]], i1 [[T2]], i1 false
; CHECK-NEXT: [[T3:%.*]] = load ptr, ptr [[PTR3:%.*]], align 8
; CHECK-NEXT: [[T4:%.*]] = select i1 [[OR_COND]], ptr [[T3]], ptr [[T4_SEL]]
; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[T2]], ptr [[T3]], ptr [[PTR2:%.*]]
; CHECK-NEXT: [[T4:%.*]] = select i1 [[T1]], ptr [[SPEC_SELECT]], ptr [[PTR1:%.*]]
; CHECK-NEXT: ret ptr [[T4]]
;
entry:
Expand All @@ -148,10 +150,14 @@ define float @spec_select_fp5(float %a, float %b, float %c) {
; CHECK-LABEL: @spec_select_fp5(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[T1:%.*]] = fcmp oeq float [[B:%.*]], 0.000000e+00
; CHECK-NEXT: br i1 [[T1]], label [[BB1:%.*]], label [[BB3:%.*]]
; CHECK: bb1:
; CHECK-NEXT: [[T2:%.*]] = fcmp ogt float [[C:%.*]], 1.000000e+00
; CHECK-NEXT: [[T4_SEL:%.*]] = select i1 [[T1]], float [[B]], float [[A:%.*]]
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[T1]], i1 [[T2]], i1 false
; CHECK-NEXT: [[T4:%.*]] = select nsz i1 [[OR_COND]], float [[C]], float [[T4_SEL]]
; CHECK-NEXT: br i1 [[T2]], label [[BB2:%.*]], label [[BB3]]
; CHECK: bb2:
; CHECK-NEXT: br label [[BB3]]
; CHECK: bb3:
; CHECK-NEXT: [[T4:%.*]] = phi nsz float [ [[A:%.*]], [[ENTRY:%.*]] ], [ [[B]], [[BB1]] ], [ [[C]], [[BB2]] ]
; CHECK-NEXT: ret float [[T4]]
;
entry:
Expand Down
5 changes: 2 additions & 3 deletions llvm/test/Transforms/SimplifyCFG/X86/switch_to_lookup_table.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1434,10 +1434,9 @@ define i32 @no_reuse_cmp2(i32 %x, i32 %y) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[EC:%.*]] = icmp ne i32 [[Y:%.*]], 0
; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[X:%.*]], 4
; CHECK-NEXT: [[R_0_SEL:%.*]] = select i1 [[EC]], i32 0, i32 100
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[EC]], i1 [[TMP0]], i1 false
; CHECK-NEXT: [[SWITCH_OFFSET:%.*]] = add i32 [[X]], 10
; CHECK-NEXT: [[R_0:%.*]] = select i1 [[OR_COND]], i32 [[SWITCH_OFFSET]], i32 [[R_0_SEL]]
; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[TMP0]], i32 [[SWITCH_OFFSET]], i32 0
; CHECK-NEXT: [[R_0:%.*]] = select i1 [[EC]], i32 [[SPEC_SELECT]], i32 100
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[R_0]], 0
; CHECK-NEXT: [[DOTR_0:%.*]] = select i1 [[CMP]], i32 100, i32 [[R_0]]
; CHECK-NEXT: ret i32 [[DOTR_0]]
Expand Down
264 changes: 127 additions & 137 deletions llvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest-phis.ll
View file

Large diffs are not rendered by default.

102 changes: 50 additions & 52 deletions llvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -449,21 +449,21 @@ define void @two_preds_with_extra_op_liveout(i8 %v0, i8 %v1, i8 %v2, i8 %v3) {
; CHECK-NEXT: br i1 [[C0]], label [[PRED0:%.*]], label [[PRED1:%.*]]
; CHECK: pred0:
; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[V1:%.*]], 0
; CHECK-NEXT: [[V3_ADJ_OLD:%.*]] = add i8 [[V1]], [[V2:%.*]]
; CHECK-NEXT: [[C3_OLD:%.*]] = icmp eq i8 [[V3_ADJ_OLD]], 0
; CHECK-NEXT: [[MERGE_LEFT_SEL:%.*]] = select i1 [[C1]], i8 0, i8 [[V3_ADJ_OLD]]
; CHECK-NEXT: [[OR_COND1:%.*]] = select i1 [[C1]], i1 true, i1 [[C3_OLD]]
; CHECK-NEXT: br i1 [[OR_COND1]], label [[FINAL_LEFT:%.*]], label [[FINAL_RIGHT:%.*]]
; CHECK-NEXT: br i1 [[C1]], label [[FINAL_LEFT:%.*]], label [[DISPATCH:%.*]]
; CHECK: pred1:
; CHECK-NEXT: [[C2:%.*]] = icmp eq i8 [[V2]], 0
; CHECK-NEXT: [[C2:%.*]] = icmp eq i8 [[V2:%.*]], 0
; CHECK-NEXT: [[V3_ADJ:%.*]] = add i8 [[V1]], [[V2]]
; CHECK-NEXT: [[C3:%.*]] = icmp eq i8 [[V3_ADJ]], 0
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C2]], i1 [[C3]], i1 false
; CHECK-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT]], label [[FINAL_RIGHT]]
; CHECK-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT]], label [[FINAL_RIGHT:%.*]]
; CHECK: dispatch:
; CHECK-NEXT: [[V3_ADJ_OLD:%.*]] = add i8 [[V1]], [[V2]]
; CHECK-NEXT: [[C3_OLD:%.*]] = icmp eq i8 [[V3_ADJ_OLD]], 0
; CHECK-NEXT: br i1 [[C3_OLD]], label [[FINAL_LEFT]], label [[FINAL_RIGHT]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: final_left:
; CHECK-NEXT: [[MERGE_LEFT:%.*]] = phi i8 [ [[MERGE_LEFT_SEL]], [[PRED0]] ], [ [[V3_ADJ]], [[PRED1]] ]
; CHECK-NEXT: [[MERGE_LEFT:%.*]] = phi i8 [ [[V3_ADJ_OLD]], [[DISPATCH]] ], [ 0, [[PRED0]] ], [ [[V3_ADJ]], [[PRED1]] ]
; CHECK-NEXT: call void @use8(i8 [[MERGE_LEFT]])
; CHECK-NEXT: call void @sideeffect0()
; CHECK-NEXT: br label [[COMMON_RET:%.*]]
Expand Down Expand Up @@ -501,23 +501,22 @@ define void @two_preds_with_extra_op_liveout_multiuse(i8 %v0, i8 %v1, i8 %v2, i8
; CHECK-NEXT: br i1 [[C0]], label [[PRED0:%.*]], label [[PRED1:%.*]]
; CHECK: pred0:
; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[V1:%.*]], 0
; CHECK-NEXT: [[V3_ADJ_OLD:%.*]] = add i8 [[V1]], [[V2:%.*]]
; CHECK-NEXT: [[C3_OLD:%.*]] = icmp eq i8 [[V3_ADJ_OLD]], 0
; CHECK-NEXT: [[MERGE_LEFT_SEL:%.*]] = select i1 [[C1]], i8 0, i8 [[V3_ADJ_OLD]]
; CHECK-NEXT: [[MERGE_LEFT_2_SEL:%.*]] = select i1 [[C1]], i8 42, i8 [[V3_ADJ_OLD]]
; CHECK-NEXT: [[OR_COND1:%.*]] = select i1 [[C1]], i1 true, i1 [[C3_OLD]]
; CHECK-NEXT: br i1 [[OR_COND1]], label [[FINAL_LEFT:%.*]], label [[FINAL_RIGHT:%.*]]
; CHECK-NEXT: br i1 [[C1]], label [[FINAL_LEFT:%.*]], label [[DISPATCH:%.*]]
; CHECK: pred1:
; CHECK-NEXT: [[C2:%.*]] = icmp eq i8 [[V2]], 0
; CHECK-NEXT: [[C2:%.*]] = icmp eq i8 [[V2:%.*]], 0
; CHECK-NEXT: [[V3_ADJ:%.*]] = add i8 [[V1]], [[V2]]
; CHECK-NEXT: [[C3:%.*]] = icmp eq i8 [[V3_ADJ]], 0
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C2]], i1 [[C3]], i1 false
; CHECK-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT]], label [[FINAL_RIGHT]]
; CHECK-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT]], label [[FINAL_RIGHT:%.*]]
; CHECK: dispatch:
; CHECK-NEXT: [[V3_ADJ_OLD:%.*]] = add i8 [[V1]], [[V2]]
; CHECK-NEXT: [[C3_OLD:%.*]] = icmp eq i8 [[V3_ADJ_OLD]], 0
; CHECK-NEXT: br i1 [[C3_OLD]], label [[FINAL_LEFT]], label [[FINAL_RIGHT]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: final_left:
; CHECK-NEXT: [[MERGE_LEFT:%.*]] = phi i8 [ [[MERGE_LEFT_SEL]], [[PRED0]] ], [ [[V3_ADJ]], [[PRED1]] ]
; CHECK-NEXT: [[MERGE_LEFT_2:%.*]] = phi i8 [ [[MERGE_LEFT_2_SEL]], [[PRED0]] ], [ [[V3_ADJ]], [[PRED1]] ]
; CHECK-NEXT: [[MERGE_LEFT:%.*]] = phi i8 [ [[V3_ADJ_OLD]], [[DISPATCH]] ], [ 0, [[PRED0]] ], [ [[V3_ADJ]], [[PRED1]] ]
; CHECK-NEXT: [[MERGE_LEFT_2:%.*]] = phi i8 [ [[V3_ADJ_OLD]], [[DISPATCH]] ], [ 42, [[PRED0]] ], [ [[V3_ADJ]], [[PRED1]] ]
; CHECK-NEXT: call void @use8(i8 [[MERGE_LEFT]])
; CHECK-NEXT: call void @use8(i8 [[MERGE_LEFT_2]])
; CHECK-NEXT: call void @sideeffect0()
Expand Down Expand Up @@ -632,21 +631,21 @@ define void @two_preds_with_extra_op_externally_used_only(i8 %v0, i8 %v1, i8 %v2
; CHECK-NEXT: br i1 [[C0]], label [[PRED0:%.*]], label [[PRED1:%.*]]
; CHECK: pred0:
; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[V1:%.*]], 0
; CHECK-NEXT: [[V3_ADJ_OLD:%.*]] = add i8 [[V1]], [[V2:%.*]]
; CHECK-NEXT: [[C3_OLD:%.*]] = icmp eq i8 [[V3:%.*]], 0
; CHECK-NEXT: [[MERGE_LEFT_SEL:%.*]] = select i1 [[C1]], i8 0, i8 [[V3_ADJ_OLD]]
; CHECK-NEXT: [[OR_COND1:%.*]] = select i1 [[C1]], i1 true, i1 [[C3_OLD]]
; CHECK-NEXT: br i1 [[OR_COND1]], label [[FINAL_LEFT:%.*]], label [[FINAL_RIGHT:%.*]]
; CHECK-NEXT: br i1 [[C1]], label [[FINAL_LEFT:%.*]], label [[DISPATCH:%.*]]
; CHECK: pred1:
; CHECK-NEXT: [[C2:%.*]] = icmp eq i8 [[V2]], 0
; CHECK-NEXT: [[C2:%.*]] = icmp eq i8 [[V2:%.*]], 0
; CHECK-NEXT: [[V3_ADJ:%.*]] = add i8 [[V1]], [[V2]]
; CHECK-NEXT: [[C3:%.*]] = icmp eq i8 [[V3]], 0
; CHECK-NEXT: [[C3:%.*]] = icmp eq i8 [[V3:%.*]], 0
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C2]], i1 [[C3]], i1 false
; CHECK-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT]], label [[FINAL_RIGHT]]
; CHECK-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT]], label [[FINAL_RIGHT:%.*]]
; CHECK: dispatch:
; CHECK-NEXT: [[V3_ADJ_OLD:%.*]] = add i8 [[V1]], [[V2]]
; CHECK-NEXT: [[C3_OLD:%.*]] = icmp eq i8 [[V3]], 0
; CHECK-NEXT: br i1 [[C3_OLD]], label [[FINAL_LEFT]], label [[FINAL_RIGHT]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: final_left:
; CHECK-NEXT: [[MERGE_LEFT:%.*]] = phi i8 [ [[MERGE_LEFT_SEL]], [[PRED0]] ], [ [[V3_ADJ]], [[PRED1]] ]
; CHECK-NEXT: [[MERGE_LEFT:%.*]] = phi i8 [ [[V3_ADJ_OLD]], [[DISPATCH]] ], [ 0, [[PRED0]] ], [ [[V3_ADJ]], [[PRED1]] ]
; CHECK-NEXT: call void @use8(i8 [[MERGE_LEFT]])
; CHECK-NEXT: call void @sideeffect0()
; CHECK-NEXT: br label [[COMMON_RET:%.*]]
Expand Down Expand Up @@ -684,23 +683,22 @@ define void @two_preds_with_extra_op_externally_used_only_multiuse(i8 %v0, i8 %v
; CHECK-NEXT: br i1 [[C0]], label [[PRED0:%.*]], label [[PRED1:%.*]]
; CHECK: pred0:
; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[V1:%.*]], 0
; CHECK-NEXT: [[V3_ADJ_OLD:%.*]] = add i8 [[V1]], [[V2:%.*]]
; CHECK-NEXT: [[C3_OLD:%.*]] = icmp eq i8 [[V3:%.*]], 0
; CHECK-NEXT: [[MERGE_LEFT_SEL:%.*]] = select i1 [[C1]], i8 0, i8 [[V3_ADJ_OLD]]
; CHECK-NEXT: [[MERGE_LEFT_2_SEL:%.*]] = select i1 [[C1]], i8 42, i8 [[V3_ADJ_OLD]]
; CHECK-NEXT: [[OR_COND1:%.*]] = select i1 [[C1]], i1 true, i1 [[C3_OLD]]
; CHECK-NEXT: br i1 [[OR_COND1]], label [[FINAL_LEFT:%.*]], label [[FINAL_RIGHT:%.*]]
; CHECK-NEXT: br i1 [[C1]], label [[FINAL_LEFT:%.*]], label [[DISPATCH:%.*]]
; CHECK: pred1:
; CHECK-NEXT: [[C2:%.*]] = icmp eq i8 [[V2]], 0
; CHECK-NEXT: [[C2:%.*]] = icmp eq i8 [[V2:%.*]], 0
; CHECK-NEXT: [[V3_ADJ:%.*]] = add i8 [[V1]], [[V2]]
; CHECK-NEXT: [[C3:%.*]] = icmp eq i8 [[V3]], 0
; CHECK-NEXT: [[C3:%.*]] = icmp eq i8 [[V3:%.*]], 0
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C2]], i1 [[C3]], i1 false
; CHECK-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT]], label [[FINAL_RIGHT]]
; CHECK-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT]], label [[FINAL_RIGHT:%.*]]
; CHECK: dispatch:
; CHECK-NEXT: [[V3_ADJ_OLD:%.*]] = add i8 [[V1]], [[V2]]
; CHECK-NEXT: [[C3_OLD:%.*]] = icmp eq i8 [[V3]], 0
; CHECK-NEXT: br i1 [[C3_OLD]], label [[FINAL_LEFT]], label [[FINAL_RIGHT]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: final_left:
; CHECK-NEXT: [[MERGE_LEFT:%.*]] = phi i8 [ [[MERGE_LEFT_SEL]], [[PRED0]] ], [ [[V3_ADJ]], [[PRED1]] ]
; CHECK-NEXT: [[MERGE_LEFT_2:%.*]] = phi i8 [ [[MERGE_LEFT_2_SEL]], [[PRED0]] ], [ [[V3_ADJ]], [[PRED1]] ]
; CHECK-NEXT: [[MERGE_LEFT:%.*]] = phi i8 [ [[V3_ADJ_OLD]], [[DISPATCH]] ], [ 0, [[PRED0]] ], [ [[V3_ADJ]], [[PRED1]] ]
; CHECK-NEXT: [[MERGE_LEFT_2:%.*]] = phi i8 [ [[V3_ADJ_OLD]], [[DISPATCH]] ], [ 42, [[PRED0]] ], [ [[V3_ADJ]], [[PRED1]] ]
; CHECK-NEXT: call void @use8(i8 [[MERGE_LEFT]])
; CHECK-NEXT: call void @use8(i8 [[MERGE_LEFT_2]])
; CHECK-NEXT: call void @sideeffect0()
Expand Down Expand Up @@ -792,21 +790,21 @@ define void @two_preds_with_extra_op_externally_used_only_after_cond(i8 %v0, i8
; CHECK-NEXT: br i1 [[C0]], label [[PRED0:%.*]], label [[PRED1:%.*]]
; CHECK: pred0:
; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[V1:%.*]], 0
; CHECK-NEXT: [[C3_OLD:%.*]] = icmp eq i8 [[V3:%.*]], 0
; CHECK-NEXT: [[V3_ADJ_OLD:%.*]] = add i8 [[V4:%.*]], [[V5:%.*]]
; CHECK-NEXT: [[MERGE_LEFT_SEL:%.*]] = select i1 [[C1]], i8 0, i8 [[V3_ADJ_OLD]]
; CHECK-NEXT: [[OR_COND1:%.*]] = select i1 [[C1]], i1 true, i1 [[C3_OLD]]
; CHECK-NEXT: br i1 [[OR_COND1]], label [[FINAL_LEFT:%.*]], label [[FINAL_RIGHT:%.*]]
; CHECK-NEXT: br i1 [[C1]], label [[FINAL_LEFT:%.*]], label [[DISPATCH:%.*]]
; CHECK: pred1:
; CHECK-NEXT: [[C2:%.*]] = icmp eq i8 [[V2:%.*]], 0
; CHECK-NEXT: [[C3:%.*]] = icmp eq i8 [[V3]], 0
; CHECK-NEXT: [[V3_ADJ:%.*]] = add i8 [[V4]], [[V5]]
; CHECK-NEXT: [[C3:%.*]] = icmp eq i8 [[V3:%.*]], 0
; CHECK-NEXT: [[V3_ADJ:%.*]] = add i8 [[V4:%.*]], [[V5:%.*]]
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C2]], i1 [[C3]], i1 false
; CHECK-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT]], label [[FINAL_RIGHT]]
; CHECK-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT]], label [[FINAL_RIGHT:%.*]]
; CHECK: dispatch:
; CHECK-NEXT: [[C3_OLD:%.*]] = icmp eq i8 [[V3]], 0
; CHECK-NEXT: [[V3_ADJ_OLD:%.*]] = add i8 [[V4]], [[V5]]
; CHECK-NEXT: br i1 [[C3_OLD]], label [[FINAL_LEFT]], label [[FINAL_RIGHT]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: final_left:
; CHECK-NEXT: [[MERGE_LEFT:%.*]] = phi i8 [ [[MERGE_LEFT_SEL]], [[PRED0]] ], [ [[V3_ADJ]], [[PRED1]] ]
; CHECK-NEXT: [[MERGE_LEFT:%.*]] = phi i8 [ [[V3_ADJ_OLD]], [[DISPATCH]] ], [ 0, [[PRED0]] ], [ [[V3_ADJ]], [[PRED1]] ]
; CHECK-NEXT: call void @use8(i8 [[MERGE_LEFT]])
; CHECK-NEXT: call void @sideeffect0()
; CHECK-NEXT: br label [[COMMON_RET:%.*]]
Expand Down Expand Up @@ -1123,13 +1121,13 @@ define i32 @test_builtin_fpclassify(float %x) {
; CHECK-LABEL: @test_builtin_fpclassify(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[ISZERO:%.*]] = fcmp oeq float [[X:%.*]], 0.000000e+00
; CHECK-NEXT: [[CMP:%.*]] = fcmp uno float [[X]], 0.000000e+00
; CHECK-NEXT: [[FPCLASSIFY_RESULT_SEL:%.*]] = select i1 [[ISZERO]], i32 2, i32 0
; CHECK-NEXT: [[OR_COND:%.*]] = or i1 [[ISZERO]], [[CMP]]
; CHECK-NEXT: br i1 [[OR_COND]], label [[FPCLASSIFY_END:%.*]], label [[FPCLASSIFY_NOT_NAN:%.*]]
; CHECK-NEXT: br i1 [[ISZERO]], label [[FPCLASSIFY_END:%.*]], label [[FPCLASSIFY_NOT_ZERO:%.*]]
; CHECK: fpclassify_end:
; CHECK-NEXT: [[FPCLASSIFY_RESULT:%.*]] = phi i32 [ [[FPCLASSIFY_RESULT_SEL]], [[ENTRY:%.*]] ], [ 1, [[FPCLASSIFY_NOT_NAN]] ], [ [[NORMAL_OR_SUBNORMAL:%.*]], [[FPCLASSIFY_NOT_INF:%.*]] ]
; CHECK-NEXT: [[FPCLASSIFY_RESULT:%.*]] = phi i32 [ 2, [[ENTRY:%.*]] ], [ 0, [[FPCLASSIFY_NOT_ZERO]] ], [ 1, [[FPCLASSIFY_NOT_NAN:%.*]] ], [ [[NORMAL_OR_SUBNORMAL:%.*]], [[FPCLASSIFY_NOT_INF:%.*]] ]
; CHECK-NEXT: ret i32 [[FPCLASSIFY_RESULT]]
; CHECK: fpclassify_not_zero:
; CHECK-NEXT: [[CMP:%.*]] = fcmp uno float [[X]], 0.000000e+00
; CHECK-NEXT: br i1 [[CMP]], label [[FPCLASSIFY_END]], label [[FPCLASSIFY_NOT_NAN]]
; CHECK: fpclassify_not_nan:
; CHECK-NEXT: [[X_ABS:%.*]] = tail call float @llvm.fabs.f32(float [[X]])
; CHECK-NEXT: [[ISINF:%.*]] = fcmp oeq float [[X_ABS]], 0x7FF0000000000000
Expand Down
16 changes: 7 additions & 9 deletions llvm/test/Transforms/SimplifyCFG/hoist-dbgvalue.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -71,16 +71,14 @@ exit:
define i16 @hoist_with_debug3_pr49982(i32 %x, i1 %c.2) !dbg !26 {
; CHECK-LABEL: @hoist_with_debug3_pr49982(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[C_0_OLD:%.*]] = icmp sgt i32 [[X:%.*]], 0
; CHECK-NEXT: br i1 [[C_0_OLD]], label [[COMMON_RET:%.*]], label [[LATCH:%.*]]
; CHECK: latch:
; CHECK-NEXT: [[C_0:%.*]] = icmp sgt i32 [[X]], 0
; CHECK-NEXT: [[COMMON_RET_OP_SEL:%.*]] = select i1 [[C_2:%.*]], i16 20, i16 0
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C_2]], i1 true, i1 [[C_0]]
; CHECK-NEXT: br i1 [[OR_COND]], label [[COMMON_RET]], label [[LATCH]]
; CHECK-NEXT: br label [[FOR_COND:%.*]]
; CHECK: for.cond:
; CHECK-NEXT: [[C_0:%.*]] = icmp sgt i32 [[X:%.*]], 0
; CHECK-NEXT: [[BRMERGE:%.*]] = select i1 [[C_0]], i1 true, i1 [[C_2:%.*]]
; CHECK-NEXT: [[DOTMUX:%.*]] = select i1 [[C_0]], i16 0, i16 20
; CHECK-NEXT: br i1 [[BRMERGE]], label [[COMMON_RET:%.*]], label [[FOR_COND]]
; CHECK: common.ret:
; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i16 [ [[COMMON_RET_OP_SEL]], [[LATCH]] ], [ 0, [[ENTRY:%.*]] ]
; CHECK-NEXT: ret i16 [[COMMON_RET_OP]]
; CHECK-NEXT: ret i16 [[DOTMUX]]
;
entry:
br label %for.cond
Expand Down
18 changes: 9 additions & 9 deletions llvm/test/Transforms/SimplifyCFG/switch-on-const-select.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,18 +5,19 @@
define i32 @foo(i64 %x, i64 %y) nounwind {
; CHECK-LABEL: @foo(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[EQ_NOT:%.*]] = icmp ne i64 [[X:%.*]], [[Y:%.*]]
; CHECK-NEXT: [[EQ:%.*]] = icmp eq i64 [[X:%.*]], [[Y:%.*]]
; CHECK-NEXT: br i1 [[EQ]], label [[B:%.*]], label [[SWITCH:%.*]]
; CHECK: switch:
; CHECK-NEXT: [[LT:%.*]] = icmp slt i64 [[X]], [[Y]]
; CHECK-NEXT: [[RETVAL_SEL:%.*]] = select i1 [[EQ_NOT]], i32 0, i32 2
; CHECK-NEXT: [[OR_COND:%.*]] = and i1 [[EQ_NOT]], [[LT]]
; CHECK-NEXT: br i1 [[OR_COND]], label [[A:%.*]], label [[B:%.*]]
; CHECK-NEXT: br i1 [[LT]], label [[A:%.*]], label [[B]]
; CHECK: common.ret:
; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i32 [ 1, [[A]] ], [ [[RETVAL_SEL]], [[B]] ]
; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i32 [ 1, [[A]] ], [ [[RETVAL:%.*]], [[B]] ]
; CHECK-NEXT: ret i32 [[COMMON_RET_OP]]
; CHECK: a:
; CHECK-NEXT: tail call void @bees.a() #[[ATTR0:[0-9]+]]
; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: b:
; CHECK-NEXT: [[RETVAL]] = phi i32 [ 0, [[SWITCH]] ], [ 2, [[ENTRY:%.*]] ]
; CHECK-NEXT: tail call void @bees.b() #[[ATTR0]]
; CHECK-NEXT: br label [[COMMON_RET]]
;
Expand Down Expand Up @@ -126,11 +127,10 @@ bees:
define i32 @xyzzy(i64 %x, i64 %y) {
; CHECK-LABEL: @xyzzy(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[EQ_NOT:%.*]] = icmp ne i64 [[X:%.*]], [[Y:%.*]]
; CHECK-NEXT: [[EQ:%.*]] = icmp eq i64 [[X:%.*]], [[Y:%.*]]
; CHECK-NEXT: [[LT:%.*]] = icmp slt i64 [[X]], [[Y]]
; CHECK-NEXT: [[VAL_SEL:%.*]] = select i1 [[EQ_NOT]], i32 1, i32 0
; CHECK-NEXT: [[OR_COND:%.*]] = and i1 [[EQ_NOT]], [[LT]]
; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = select i1 [[OR_COND]], i32 -1, i32 [[VAL_SEL]]
; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[LT]], i32 -1, i32 1
; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = select i1 [[EQ]], i32 0, i32 [[SPEC_SELECT]]
; CHECK-NEXT: ret i32 [[COMMON_RET_OP]]
;
entry:
Expand Down