57 changes: 57 additions & 0 deletions llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
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//===-- AMDGPUDisassembler.hpp - Disassembler for AMDGPU ISA ---*- C++ -*--===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
/// \file
///
/// This file contains declaration for AMDGPU ISA disassembler
//
//===----------------------------------------------------------------------===//

#ifndef LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
#define LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H

#include "llvm/MC/MCDisassembler/MCDisassembler.h"

namespace llvm {

class MCContext;
class MCInst;
class MCSubtargetInfo;

class AMDGPUDisassembler : public MCDisassembler {
public:
AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
MCDisassembler(STI, Ctx) {}

~AMDGPUDisassembler() {}

DecodeStatus getInstruction(MCInst &MI, uint64_t &Size,
ArrayRef<uint8_t> Bytes, uint64_t Address,
raw_ostream &WS, raw_ostream &CS) const override;

/// Decode inline float value in VSrc field
DecodeStatus DecodeLitFloat(unsigned Imm, uint32_t& F) const;
/// Decode inline integer value in VSrc field
DecodeStatus DecodeLitInteger(unsigned Imm, int64_t& I) const;
/// Decode VGPR register
DecodeStatus DecodeVgprRegister(unsigned Val, unsigned& RegID) const;
/// Decode SGPR register
DecodeStatus DecodeSgprRegister(unsigned Val, unsigned& RegID) const;
/// Decode register in VSrc field
DecodeStatus DecodeSrcRegister(unsigned Val, unsigned& RegID) const;

DecodeStatus DecodeVS_32RegisterClass(MCInst &Inst, unsigned Imm,
uint64_t Addr) const;

DecodeStatus DecodeVGPR_32RegisterClass(MCInst &Inst, unsigned Imm,
uint64_t Addr) const;
};
} // namespace llvm

#endif //LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
7 changes: 7 additions & 0 deletions llvm/lib/Target/AMDGPU/Disassembler/CMakeLists.txt
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include_directories( ${CMAKE_CURRENT_BINARY_DIR}/.. ${CMAKE_CURRENT_SOURCE_DIR}/.. )

add_llvm_library(LLVMAMDGPUDisassembler
AMDGPUDisassembler.cpp
)

add_dependencies(LLVMAMDGPUDisassembler AMDGPUCommonTableGen)
23 changes: 23 additions & 0 deletions llvm/lib/Target/AMDGPU/Disassembler/LLVMBuild.txt
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;===- ./lib/Target/AMDGPU/Disassembler/LLVMBuild.txt ------------*- Conf -*--===;
;
; The LLVM Compiler Infrastructure
;
; This file is distributed under the University of Illinois Open Source
; License. See LICENSE.TXT for details.
;
;===------------------------------------------------------------------------===;
;
; This is an LLVMBuild description file for the components in this subdirectory.
;
; For more information on the LLVMBuild system, please see:
;
; http://llvm.org/docs/LLVMBuild.html
;
;===------------------------------------------------------------------------===;

[component_0]
type = Library
name = AMDGPUDisassembler
parent = AMDGPU
required_libraries = AMDGPUDesc AMDGPUInfo AMDGPUUtils MC MCDisassembler Support
add_to_library_groups = AMDGPU
3 changes: 2 additions & 1 deletion llvm/lib/Target/AMDGPU/LLVMBuild.txt
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Expand Up @@ -16,14 +16,15 @@
;===------------------------------------------------------------------------===;

[common]
subdirectories = AsmParser InstPrinter MCTargetDesc TargetInfo Utils
subdirectories = AsmParser Disassembler InstPrinter MCTargetDesc TargetInfo Utils

[component_0]
type = TargetGroup
name = AMDGPU
parent = Target
has_asmparser = 1
has_asmprinter = 1
has_disassembler = 1

[component_1]
type = Library
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6 changes: 6 additions & 0 deletions llvm/lib/Target/AMDGPU/SIInstrFormats.td
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Expand Up @@ -75,6 +75,12 @@ class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
let TSFlags{22} = VOPAsmPrefer32Bit;

let SchedRW = [Write32Bit];

field bits<1> DisableSIDecoder = 0;
field bits<1> DisableVIDecoder = 0;
field bits<1> DisableDecoder = 0;

let isAsmParserOnly = !if(!eq(DisableDecoder{0}, {0}), 0, 1);
}

class Enc32 {
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171 changes: 129 additions & 42 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.td
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Large diffs are not rendered by default.

11 changes: 7 additions & 4 deletions llvm/lib/Target/AMDGPU/SIInstructions.td
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Expand Up @@ -1034,7 +1034,7 @@ defm BUFFER_ATOMIC_XOR : MUBUF_Atomic <
//def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 <mubuf<0x5f>, "buffer_atomic_fmin_x2", []>; // isn't on VI
//def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <mubuf<0x60>, "buffer_atomic_fmax_x2", []>; // isn't on VI

let SubtargetPredicate = isSI in {
let SubtargetPredicate = isSI, DisableVIDecoder = 1 in {
defm BUFFER_WBINVL1_SC : MUBUF_Invalidate <mubuf<0x70>, "buffer_wbinvl1_sc", int_amdgcn_buffer_wbinvl1_sc>; // isn't on CI & VI
}

Expand Down Expand Up @@ -1396,11 +1396,11 @@ defm V_INTERP_P1_F32 : V_INTERP_P1_F32_m;

} // End OtherPredicates = [has32BankLDS]

let OtherPredicates = [has16BankLDS], Constraints = "@earlyclobber $dst" in {
let OtherPredicates = [has16BankLDS], Constraints = "@earlyclobber $dst", isAsmParserOnly=1 in {

defm V_INTERP_P1_F32_16bank : V_INTERP_P1_F32_m;

} // End OtherPredicates = [has32BankLDS], Constraints = "@earlyclobber $dst"
} // End OtherPredicates = [has32BankLDS], Constraints = "@earlyclobber $dst", isAsmParserOnly=1

let DisableEncoding = "$src0", Constraints = "$src0 = $dst" in {

Expand Down Expand Up @@ -1759,9 +1759,12 @@ defm V_MUL_HI_U32 : VOP3Inst <vop3<0x16a, 0x286>, "v_mul_hi_u32",
VOP_I32_I32_I32, mulhu
>;

let DisableVIDecoder=1 in { // removed from VI as identical to V_MUL_LO_U32
defm V_MUL_LO_I32 : VOP3Inst <vop3<0x16b, 0x285>, "v_mul_lo_i32",
VOP_I32_I32_I32
>;
}

defm V_MUL_HI_I32 : VOP3Inst <vop3<0x16c, 0x287>, "v_mul_hi_i32",
VOP_I32_I32_I32, mulhs
>;
Expand Down Expand Up @@ -1830,7 +1833,7 @@ defm V_MULLIT_F32 : VOP3Inst <vop3<0x150>, "v_mullit_f32",

} // End SubtargetPredicate = isSICI

let SubtargetPredicate = isVI in {
let SubtargetPredicate = isVI, DisableSIDecoder = 1 in {

defm V_LSHLREV_B64 : VOP3Inst <vop3<0, 0x28f>, "v_lshlrev_b64",
VOP_I64_I32_I64
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4 changes: 4 additions & 0 deletions llvm/lib/Target/AMDGPU/VIInstructions.td
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Expand Up @@ -11,6 +11,8 @@

let SIAssemblerPredicate = DisableInst, SubtargetPredicate = isVI in {

let DisableSIDecoder = 1 in {

//===----------------------------------------------------------------------===//
// VOP1 Instructions
//===----------------------------------------------------------------------===//
Expand Down Expand Up @@ -73,6 +75,8 @@ defm V_MIN_I16 : VOP2Inst <vop2<0,0x32>, "v_min_i16", VOP_I16_I16_I16>;
} // End isCommutable = 1
defm V_LDEXP_F16 : VOP2Inst <vop2<0,0x33>, "v_ldexp_f16", VOP_F16_F16_I16>;

} // let DisableSIDecoder = 1

// Aliases to simplify matching of floating-point instructions that
// are VOP2 on SI and VOP3 on VI.

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2 changes: 2 additions & 0 deletions llvm/test/MC/Disassembler/AMDGPU/lit.local.cfg
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if not 'AMDGPU' in config.root.targets:
config.unsupported = True
31 changes: 31 additions & 0 deletions llvm/test/MC/Disassembler/AMDGPU/mov.txt
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# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s

# CHECK: v_mov_b32_e32 v2, v1 ; encoding: [0x01,0x03,0x04,0x7e]
0x01 0x03 0x04 0x7e

# CHECK: v_mov_b32_e32 v1, 0.5 ; encoding: [0xf0,0x02,0x02,0x7e]
0xf0 0x02 0x02 0x7e

# CHECK: v_mov_b32_e32 v15, s100 ; encoding: [0x64,0x02,0x1e,0x7e]
0x64 0x02 0x1e 0x7e

# CHECK: v_mov_b32_e32 v90, flat_scratch_lo ; encoding: [0x66,0x02,0xb4,0x7e]
0x66 0x02 0xb4 0x7e

# CHECK: v_mov_b32_e32 v150, vcc_lo ; encoding: [0x6a,0x02,0x2c,0x7f]
0x6a 0x02 0x2c 0x7f

# CHECK: v_mov_b32_e32 v199, exec_lo ; encoding: [0x7e,0x02,0x8e,0x7f]
0x7e 0x02 0x8e 0x7f

# CHECK: v_mov_b32_e32 v222, m0 ; encoding: [0x7c,0x02,0xbc,0x7f]
0x7c 0x02 0xbc 0x7f

# CHECK: v_mov_b32_e32 v255, -13 ; encoding: [0xcd,0x02,0xfe,0x7f]
0xcd 0x02 0xfe 0x7f

# CHECK: v_cvt_f32_i32_e32 v153, s98 ; encoding: [0x62,0x0a,0x32,0x7f]
0x62 0x0a 0x32 0x7f

# CHECK: v_cvt_f32_u32_e32 v33, -4.0 ; encoding: [0xf7,0x0c,0x42,0x7e]
0xf7 0x0c 0x42 0x7e
4 changes: 4 additions & 0 deletions llvm/test/MC/Disassembler/AMDGPU/nop.txt
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# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s

# CHECK: v_nop ; encoding: [0x00,0x00,0x00,0x7e]
0x00 0x00 0x00 0x7e