12 changes: 6 additions & 6 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,7 @@ define i64 @v_udiv_i64(i64 %num, i64 %den) {
; CHECK-NEXT: ; implicit-def: $vgpr4_vgpr5
; CHECK-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
; CHECK-NEXT: s_cbranch_execnz BB0_2
; CHECK-NEXT: s_cbranch_execz BB0_2
; CHECK-NEXT: ; %bb.1:
; CHECK-NEXT: v_cvt_f32_u32_e32 v4, v2
; CHECK-NEXT: v_cvt_f32_u32_e32 v5, v3
Expand Down Expand Up @@ -646,7 +646,7 @@ define <2 x i64> @v_udiv_v2i64(<2 x i64> %num, <2 x i64> %den) {
; CGP-NEXT: ; implicit-def: $vgpr0_vgpr1
; CGP-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
; CGP-NEXT: s_cbranch_execnz BB2_2
; CGP-NEXT: s_cbranch_execz BB2_2
; CGP-NEXT: ; %bb.1:
; CGP-NEXT: v_cvt_f32_u32_e32 v0, v4
; CGP-NEXT: v_cvt_f32_u32_e32 v1, v5
Expand Down Expand Up @@ -814,7 +814,7 @@ define <2 x i64> @v_udiv_v2i64(<2 x i64> %num, <2 x i64> %den) {
; CGP-NEXT: ; implicit-def: $vgpr4_vgpr5
; CGP-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
; CGP-NEXT: s_cbranch_execnz BB2_6
; CGP-NEXT: s_cbranch_execz BB2_6
; CGP-NEXT: ; %bb.5:
; CGP-NEXT: v_cvt_f32_u32_e32 v4, v6
; CGP-NEXT: v_cvt_f32_u32_e32 v5, v7
Expand Down Expand Up @@ -2318,7 +2318,7 @@ define i64 @v_udiv_i64_pow2_shl_denom(i64 %x, i64 %y) {
; CHECK-NEXT: ; implicit-def: $vgpr2_vgpr3
; CHECK-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
; CHECK-NEXT: s_cbranch_execnz BB7_2
; CHECK-NEXT: s_cbranch_execz BB7_2
; CHECK-NEXT: ; %bb.1:
; CHECK-NEXT: v_cvt_f32_u32_e32 v2, v4
; CHECK-NEXT: v_cvt_f32_u32_e32 v3, v5
Expand Down Expand Up @@ -2767,7 +2767,7 @@ define <2 x i64> @v_udiv_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
; CGP-NEXT: ; implicit-def: $vgpr0_vgpr1
; CGP-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
; CGP-NEXT: s_cbranch_execnz BB8_2
; CGP-NEXT: s_cbranch_execz BB8_2
; CGP-NEXT: ; %bb.1:
; CGP-NEXT: v_cvt_f32_u32_e32 v0, v10
; CGP-NEXT: v_cvt_f32_u32_e32 v1, v11
Expand Down Expand Up @@ -2935,7 +2935,7 @@ define <2 x i64> @v_udiv_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
; CGP-NEXT: ; implicit-def: $vgpr4_vgpr5
; CGP-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
; CGP-NEXT: s_cbranch_execnz BB8_6
; CGP-NEXT: s_cbranch_execz BB8_6
; CGP-NEXT: ; %bb.5:
; CGP-NEXT: v_cvt_f32_u32_e32 v4, v8
; CGP-NEXT: v_cvt_f32_u32_e32 v5, v9
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,7 @@ define i64 @v_urem_i64(i64 %num, i64 %den) {
; CHECK-NEXT: ; implicit-def: $vgpr4_vgpr5
; CHECK-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
; CHECK-NEXT: s_cbranch_execnz BB0_2
; CHECK-NEXT: s_cbranch_execz BB0_2
; CHECK-NEXT: ; %bb.1:
; CHECK-NEXT: v_cvt_f32_u32_e32 v4, v2
; CHECK-NEXT: v_cvt_f32_u32_e32 v5, v3
Expand Down Expand Up @@ -642,7 +642,7 @@ define <2 x i64> @v_urem_v2i64(<2 x i64> %num, <2 x i64> %den) {
; CGP-NEXT: ; implicit-def: $vgpr0_vgpr1
; CGP-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
; CGP-NEXT: s_cbranch_execnz BB2_2
; CGP-NEXT: s_cbranch_execz BB2_2
; CGP-NEXT: ; %bb.1:
; CGP-NEXT: v_cvt_f32_u32_e32 v0, v4
; CGP-NEXT: v_cvt_f32_u32_e32 v1, v5
Expand Down Expand Up @@ -809,7 +809,7 @@ define <2 x i64> @v_urem_v2i64(<2 x i64> %num, <2 x i64> %den) {
; CGP-NEXT: ; implicit-def: $vgpr4_vgpr5
; CGP-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
; CGP-NEXT: s_cbranch_execnz BB2_6
; CGP-NEXT: s_cbranch_execz BB2_6
; CGP-NEXT: ; %bb.5:
; CGP-NEXT: v_cvt_f32_u32_e32 v4, v6
; CGP-NEXT: v_cvt_f32_u32_e32 v5, v7
Expand Down Expand Up @@ -2292,7 +2292,7 @@ define i64 @v_urem_i64_pow2_shl_denom(i64 %x, i64 %y) {
; CHECK-NEXT: ; implicit-def: $vgpr2_vgpr3
; CHECK-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
; CHECK-NEXT: s_cbranch_execnz BB7_2
; CHECK-NEXT: s_cbranch_execz BB7_2
; CHECK-NEXT: ; %bb.1:
; CHECK-NEXT: v_cvt_f32_u32_e32 v2, v4
; CHECK-NEXT: v_cvt_f32_u32_e32 v3, v5
Expand Down Expand Up @@ -2738,7 +2738,7 @@ define <2 x i64> @v_urem_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
; CGP-NEXT: ; implicit-def: $vgpr0_vgpr1
; CGP-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
; CGP-NEXT: s_cbranch_execnz BB8_2
; CGP-NEXT: s_cbranch_execz BB8_2
; CGP-NEXT: ; %bb.1:
; CGP-NEXT: v_cvt_f32_u32_e32 v0, v10
; CGP-NEXT: v_cvt_f32_u32_e32 v1, v11
Expand Down Expand Up @@ -2905,7 +2905,7 @@ define <2 x i64> @v_urem_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
; CGP-NEXT: ; implicit-def: $vgpr4_vgpr5
; CGP-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
; CGP-NEXT: s_cbranch_execnz BB8_6
; CGP-NEXT: s_cbranch_execz BB8_6
; CGP-NEXT: ; %bb.5:
; CGP-NEXT: v_cvt_f32_u32_e32 v4, v8
; CGP-NEXT: v_cvt_f32_u32_e32 v5, v9
Expand Down