diff --git a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
diff --git a/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp b/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
@@ -495,7 +495,8 @@ static bool hasPCRelativeForm(MachineInstr &Use) {
             }
           }
           MachineInstr *DefMIToErase = nullptr;
-          if (TII->convertToImmediateForm(MI, &DefMIToErase)) {
+          SmallSet<Register, 4> UpdatedRegs;
+          if (TII->convertToImmediateForm(MI, UpdatedRegs, &DefMIToErase)) {
             Changed = true;
             NumRRConvertedInPreEmit++;
             LLVM_DEBUG(dbgs() << "Converted instruction to imm form: ");

diff --git a/llvm/test/CodeGen/PowerPC/O3-pipeline.ll b/llvm/test/CodeGen/PowerPC/O3-pipeline.ll
@@ -127,6 +127,8 @@
 ; CHECK-NEXT:       Remove dead machine instructions
 ; CHECK-NEXT:       MachineDominator Tree Construction
 ; CHECK-NEXT:       PowerPC Reduce CR logical Operation
+; CHECK-NEXT:       Remove unreachable machine basic blocks
+; CHECK-NEXT:       Live Variable Analysis
 ; CHECK-NEXT:       MachineDominator Tree Construction
 ; CHECK-NEXT:       MachinePostDominator Tree Construction
 ; CHECK-NEXT:       Machine Natural Loop Construction

diff --git a/llvm/test/CodeGen/PowerPC/combine-sext-and-shl-after-isel.ll b/llvm/test/CodeGen/PowerPC/combine-sext-and-shl-after-isel.ll
@@ -200,3 +200,212 @@ true:
 false:
   ret i64 %iconv
 }
+
+define hidden void @testCaller(i1 %incond) local_unnamed_addr align 2 nounwind {
+; CHECK-LABEL: testCaller:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mfocrf r12, 32
+; CHECK-NEXT:    stw r12, 8(r1)
+; CHECK-NEXT:    mflr r0
+; CHECK-NEXT:    stdu r1, -64(r1)
+; CHECK-NEXT:    std r0, 80(r1)
+; CHECK-NEXT:    std r30, 48(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    andi. r3, r3, 1
+; CHECK-NEXT:    li r3, -1
+; CHECK-NEXT:    li r30, 0
+; CHECK-NEXT:    crmove 4*cr2+lt, gt
+; CHECK-NEXT:    std r29, 40(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    b .LBB3_2
+; CHECK-NEXT:    .p2align 4
+; CHECK-NEXT:  .LBB3_1: # %if.end116
+; CHECK-NEXT:    #
+; CHECK-NEXT:    bl callee
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    mr r3, r29
+; CHECK-NEXT:  .LBB3_2: # %cond.end.i.i
+; CHECK-NEXT:    # =>This Loop Header: Depth=1
+; CHECK-NEXT:    # Child Loop BB3_3 Depth 2
+; CHECK-NEXT:    lwz r29, 0(r3)
+; CHECK-NEXT:    li r5, 0
+; CHECK-NEXT:    extsw r4, r29
+; CHECK-NEXT:    .p2align 5
+; CHECK-NEXT:  .LBB3_3: # %while.body5.i
+; CHECK-NEXT:    # Parent Loop BB3_2 Depth=1
+; CHECK-NEXT:    # => This Inner Loop Header: Depth=2
+; CHECK-NEXT:    addi r5, r5, -1
+; CHECK-NEXT:    cmpwi r5, 0
+; CHECK-NEXT:    bgt cr0, .LBB3_3
+; CHECK-NEXT:  # %bb.4: # %while.cond12.preheader.i
+; CHECK-NEXT:    #
+; CHECK-NEXT:    bc 12, 4*cr2+lt, .LBB3_1
+; CHECK-NEXT:  # %bb.5: # %for.cond99.preheader
+; CHECK-NEXT:    #
+; CHECK-NEXT:    ld r5, 0(r3)
+; CHECK-NEXT:    sldi r4, r4, 2
+; CHECK-NEXT:    stw r3, 0(r3)
+; CHECK-NEXT:    stwx r30, r5, r4
+; CHECK-NEXT:    b .LBB3_1
+;
+; CHECK-BE-LABEL: testCaller:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    mfcr r12
+; CHECK-BE-NEXT:    stw r12, 8(r1)
+; CHECK-BE-NEXT:    mflr r0
+; CHECK-BE-NEXT:    stdu r1, -80(r1)
+; CHECK-BE-NEXT:    std r0, 96(r1)
+; CHECK-BE-NEXT:    std r30, 64(r1) # 8-byte Folded Spill
+; CHECK-BE-NEXT:    andi. r3, r3, 1
+; CHECK-BE-NEXT:    li r3, -1
+; CHECK-BE-NEXT:    li r30, 0
+; CHECK-BE-NEXT:    crmove 4*cr2+lt, gt
+; CHECK-BE-NEXT:    std r29, 56(r1) # 8-byte Folded Spill
+; CHECK-BE-NEXT:    b .LBB3_2
+; CHECK-BE-NEXT:    .p2align 4
+; CHECK-BE-NEXT:  .LBB3_1: # %if.end116
+; CHECK-BE-NEXT:    #
+; CHECK-BE-NEXT:    bl callee
+; CHECK-BE-NEXT:    nop
+; CHECK-BE-NEXT:    mr r3, r29
+; CHECK-BE-NEXT:  .LBB3_2: # %cond.end.i.i
+; CHECK-BE-NEXT:    # =>This Loop Header: Depth=1
+; CHECK-BE-NEXT:    # Child Loop BB3_3 Depth 2
+; CHECK-BE-NEXT:    lwz r29, 0(r3)
+; CHECK-BE-NEXT:    li r5, 0
+; CHECK-BE-NEXT:    extsw r4, r29
+; CHECK-BE-NEXT:    .p2align 5
+; CHECK-BE-NEXT:  .LBB3_3: # %while.body5.i
+; CHECK-BE-NEXT:    # Parent Loop BB3_2 Depth=1
+; CHECK-BE-NEXT:    # => This Inner Loop Header: Depth=2
+; CHECK-BE-NEXT:    addi r5, r5, -1
+; CHECK-BE-NEXT:    cmpwi r5, 0
+; CHECK-BE-NEXT:    bgt cr0, .LBB3_3
+; CHECK-BE-NEXT:  # %bb.4: # %while.cond12.preheader.i
+; CHECK-BE-NEXT:    #
+; CHECK-BE-NEXT:    bc 12, 4*cr2+lt, .LBB3_1
+; CHECK-BE-NEXT:  # %bb.5: # %for.cond99.preheader
+; CHECK-BE-NEXT:    #
+; CHECK-BE-NEXT:    ld r5, 0(r3)
+; CHECK-BE-NEXT:    sldi r4, r4, 2
+; CHECK-BE-NEXT:    stw r3, 0(r3)
+; CHECK-BE-NEXT:    stwx r30, r5, r4
+; CHECK-BE-NEXT:    b .LBB3_1
+;
+; CHECK-P9-LABEL: testCaller:
+; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    mfocrf r12, 32
+; CHECK-P9-NEXT:    mflr r0
+; CHECK-P9-NEXT:    stw r12, 8(r1)
+; CHECK-P9-NEXT:    stdu r1, -64(r1)
+; CHECK-P9-NEXT:    andi. r3, r3, 1
+; CHECK-P9-NEXT:    std r0, 80(r1)
+; CHECK-P9-NEXT:    std r30, 48(r1) # 8-byte Folded Spill
+; CHECK-P9-NEXT:    li r3, -1
+; CHECK-P9-NEXT:    li r30, 0
+; CHECK-P9-NEXT:    std r29, 40(r1) # 8-byte Folded Spill
+; CHECK-P9-NEXT:    crmove 4*cr2+lt, gt
+; CHECK-P9-NEXT:    b .LBB3_2
+; CHECK-P9-NEXT:    .p2align 4
+; CHECK-P9-NEXT:  .LBB3_1: # %if.end116
+; CHECK-P9-NEXT:    #
+; CHECK-P9-NEXT:    bl callee
+; CHECK-P9-NEXT:    nop
+; CHECK-P9-NEXT:    mr r3, r29
+; CHECK-P9-NEXT:  .LBB3_2: # %cond.end.i.i
+; CHECK-P9-NEXT:    # =>This Loop Header: Depth=1
+; CHECK-P9-NEXT:    # Child Loop BB3_3 Depth 2
+; CHECK-P9-NEXT:    lwz r29, 0(r3)
+; CHECK-P9-NEXT:    li r4, 0
+; CHECK-P9-NEXT:    .p2align 5
+; CHECK-P9-NEXT:  .LBB3_3: # %while.body5.i
+; CHECK-P9-NEXT:    # Parent Loop BB3_2 Depth=1
+; CHECK-P9-NEXT:    # => This Inner Loop Header: Depth=2
+; CHECK-P9-NEXT:    addi r4, r4, -1
+; CHECK-P9-NEXT:    cmpwi r4, 0
+; CHECK-P9-NEXT:    bgt cr0, .LBB3_3
+; CHECK-P9-NEXT:  # %bb.4: # %while.cond12.preheader.i
+; CHECK-P9-NEXT:    #
+; CHECK-P9-NEXT:    bc 12, 4*cr2+lt, .LBB3_1
+; CHECK-P9-NEXT:  # %bb.5: # %for.cond99.preheader
+; CHECK-P9-NEXT:    #
+; CHECK-P9-NEXT:    ld r4, 0(r3)
+; CHECK-P9-NEXT:    extswsli r5, r29, 2
+; CHECK-P9-NEXT:    stw r3, 0(r3)
+; CHECK-P9-NEXT:    stwx r30, r4, r5
+; CHECK-P9-NEXT:    b .LBB3_1
+;
+; CHECK-P9-BE-LABEL: testCaller:
+; CHECK-P9-BE:       # %bb.0: # %entry
+; CHECK-P9-BE-NEXT:    mfcr r12
+; CHECK-P9-BE-NEXT:    mflr r0
+; CHECK-P9-BE-NEXT:    stw r12, 8(r1)
+; CHECK-P9-BE-NEXT:    stdu r1, -80(r1)
+; CHECK-P9-BE-NEXT:    andi. r3, r3, 1
+; CHECK-P9-BE-NEXT:    std r0, 96(r1)
+; CHECK-P9-BE-NEXT:    std r30, 64(r1) # 8-byte Folded Spill
+; CHECK-P9-BE-NEXT:    li r3, -1
+; CHECK-P9-BE-NEXT:    li r30, 0
+; CHECK-P9-BE-NEXT:    std r29, 56(r1) # 8-byte Folded Spill
+; CHECK-P9-BE-NEXT:    crmove 4*cr2+lt, gt
+; CHECK-P9-BE-NEXT:    b .LBB3_2
+; CHECK-P9-BE-NEXT:    .p2align 4
+; CHECK-P9-BE-NEXT:  .LBB3_1: # %if.end116
+; CHECK-P9-BE-NEXT:    #
+; CHECK-P9-BE-NEXT:    bl callee
+; CHECK-P9-BE-NEXT:    nop
+; CHECK-P9-BE-NEXT:    mr r3, r29
+; CHECK-P9-BE-NEXT:  .LBB3_2: # %cond.end.i.i
+; CHECK-P9-BE-NEXT:    # =>This Loop Header: Depth=1
+; CHECK-P9-BE-NEXT:    # Child Loop BB3_3 Depth 2
+; CHECK-P9-BE-NEXT:    lwz r29, 0(r3)
+; CHECK-P9-BE-NEXT:    li r4, 0
+; CHECK-P9-BE-NEXT:    .p2align 5
+; CHECK-P9-BE-NEXT:  .LBB3_3: # %while.body5.i
+; CHECK-P9-BE-NEXT:    # Parent Loop BB3_2 Depth=1
+; CHECK-P9-BE-NEXT:    # => This Inner Loop Header: Depth=2
+; CHECK-P9-BE-NEXT:    addi r4, r4, -1
+; CHECK-P9-BE-NEXT:    cmpwi r4, 0
+; CHECK-P9-BE-NEXT:    bgt cr0, .LBB3_3
+; CHECK-P9-BE-NEXT:  # %bb.4: # %while.cond12.preheader.i
+; CHECK-P9-BE-NEXT:    #
+; CHECK-P9-BE-NEXT:    bc 12, 4*cr2+lt, .LBB3_1
+; CHECK-P9-BE-NEXT:  # %bb.5: # %for.cond99.preheader
+; CHECK-P9-BE-NEXT:    #
+; CHECK-P9-BE-NEXT:    ld r4, 0(r3)
+; CHECK-P9-BE-NEXT:    extswsli r5, r29, 2
+; CHECK-P9-BE-NEXT:    stw r3, 0(r3)
+; CHECK-P9-BE-NEXT:    stwx r30, r4, r5
+; CHECK-P9-BE-NEXT:    b .LBB3_1
+entry:
+  br label %exit
+
+exit: ; preds = %entry
+  br label %cond.end.i.i
+
+cond.end.i.i:                                     ; preds = %if.end116, %exit
+  %CurrentState.0566 = phi i32 [ %CurrentState.2, %if.end116 ], [ -1, %exit ]
+  %0 = load i32, ptr poison, align 8
+  br label %while.body5.i
+
+while.cond12.preheader.i:                         ; preds = %while.body5.i
+  br i1 %incond, label %if.end116, label %for.cond99.preheader
+
+while.body5.i:                                    ; preds = %while.body5.i, %cond.end.i.i
+  %Test.012.i = phi i32 [ 0, %cond.end.i.i ], [ %dec10.i, %while.body5.i ]
+  %dec10.i = add nsw i32 %Test.012.i, -1
+  %cmp4.i = icmp slt i32 0, %dec10.i
+  br i1 %cmp4.i, label %while.body5.i, label %while.cond12.preheader.i
+
+for.cond99.preheader:                             ; preds = %while.cond12.preheader.i
+  %1 = load ptr, ptr poison, align 8
+  %conv103 = sext i32 %0 to i64
+  %arrayidx.i426 = getelementptr inbounds i32, ptr %1, i64 %conv103
+  store i32 0, ptr %arrayidx.i426, align 4
+  store i32 %CurrentState.0566, ptr poison, align 8
+  br label %if.end116
+
+if.end116:                                        ; preds = %for.cond99.preheader, %while.cond12.preheader.i
+  %CurrentState.2 = phi i32 [ %0, %while.cond12.preheader.i ], [ poison, %for.cond99.preheader ]
+  call fastcc void @callee()
+  br label %cond.end.i.i
+}
+declare dso_local fastcc void @callee() unnamed_addr align 2
diff --git a/llvm/test/CodeGen/PowerPC/convert-ri-addi-to-ri.mir b/llvm/test/CodeGen/PowerPC/convert-ri-addi-to-ri.mir
@@ -12,7 +12,7 @@ body:             |
     %0:g8rc_and_g8rc_nox0 = COPY $x3
     %1:g8rc_and_g8rc_nox0 = ADDI8 %0:g8rc_and_g8rc_nox0, 144
     %2:g8rc = LI8 0
-    ; CHECK: STD killed %2, 160, %0
+    ; CHECK: STD killed %2, 160, killed %0
     STD killed %2:g8rc, 16, %1:g8rc_and_g8rc_nox0
     BLR8 implicit $lr8, implicit $rm
 ...
@@ -27,7 +27,7 @@ body:             |
     %0:g8rc_and_g8rc_nox0 = COPY $x3
     %1:g8rc_and_g8rc_nox0 = ADDI8 %0:g8rc_and_g8rc_nox0, 141
     %2:g8rc = LI8 0
-    ; CHECK: STD killed %2, 16, %1
+    ; CHECK: STD killed %2, 16, killed %1
     STD killed %2:g8rc, 16, %1:g8rc_and_g8rc_nox0
     BLR8 implicit $lr8, implicit $rm
 ...
@@ -42,7 +42,7 @@ body:             |
     %0:g8rc_and_g8rc_nox0 = COPY $x3
     %1:g8rc_and_g8rc_nox0 = ADDI8 %0:g8rc_and_g8rc_nox0, 144
     %2:g8rc = LI8 0
-    ; CHECK: STD %1, 0, %0
+    ; CHECK: STD killed %1, 0, %0
     STD %1:g8rc_and_g8rc_nox0, 0, killed %0:g8rc_and_g8rc_nox0
     ; CHECK: STD killed %2, 160, killed %0
     STD killed %2:g8rc, 16, %1:g8rc_and_g8rc_nox0

diff --git a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-kill-flag.mir b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-kill-flag.mir
@@ -47,7 +47,7 @@ body: |
     STFSX killed $f1, killed $x3, $x5
     ; CHECK: STFS killed $f1, 100, $x5
     STD killed $x5, $x5, 100
-    ; CHECK: STD killed $x5, $x5, 100
+    ; CHECK: STD killed $x5, killed $x5, 100
     BLR8 implicit $lr8, implicit $rm
 
 ...
@@ -100,7 +100,7 @@ body: |
     STFSX killed $f1, $zero8, killed $x3
     ; CHECK: STFS killed $f1, 100, $x5
     STD killed $x5, $x5, 100
-    ; CHECK: STD killed $x5, $x5, 100
+    ; CHECK: STD killed $x5, killed $x5, 100
     BLR8 implicit $lr8, implicit $rm
 
 ...
@@ -119,7 +119,7 @@ body: |
     STFSX killed $f1, $zero8, $x3
     ; CHECK: STFS killed $f1, 100, killed $x5
     STD killed $x3, $x3, 100
-    ; CHECK: STD killed $x3, $x3, 100
+    ; CHECK: STD killed $x3, killed $x3, 100
     BLR8 implicit $lr8, implicit $rm
 
 ...
@@ -154,9 +154,9 @@ body: |
     $x3 = LDX $zero8, killed $x3
     ; CHECK: $x3 = LD 100, $x5
     STD killed $x5, $x5, 100
-    ; CHECK: STD killed $x5, $x5, 100
+    ; CHECK: STD killed $x5, killed $x5, 100
     STD killed $x3, $x3, 200
-    ; CHECK: STD killed $x3, $x3, 200
+    ; CHECK: STD killed $x3, killed $x3, 200
     BLR8 implicit $lr8, implicit $rm
 
 ...
@@ -175,7 +175,7 @@ body: |
     STD killed $x5, $x5, 100
     ; CHECK: STD $x5, $x5, 100
     STD $x3, $x3, 200
-    ; CHECK: STD killed $x3, $x3, 200
+    ; CHECK: STD killed $x3, killed $x3, 200
     STFSX killed $f1, $zero8, killed $x3
     ; CHECK: STFS killed $f1, 100, killed $x5
     BLR8 implicit $lr8, implicit $rm

diff --git a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir
@@ -304,7 +304,7 @@ body:             |
     %0 = LI8 234
     %1 = COPY $x3
     %2 = RLWNM8 %1, %0, 20, 27
-    ; CHECK: RLWINM8 %1, 10, 20, 27
+    ; CHECK: RLWINM8 killed %1, 10, 20, 27
     ; CHECK-LATE: rlwinm 3, 3, 10, 20, 27
     $x3 = COPY %2
     BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -835,7 +835,7 @@ body:             |
     %2 = COPY %1.sub_32
     %3 = LI 140
     %4 = RLDCL %0, killed %3, 0
-    ; CHECK: RLDICL %0, 12, 0
+    ; CHECK: RLDICL killed %0, 12, 0
     ; CHECK-LATE: rotldi 3, 3, 12
     $x3 = COPY %4
     BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -945,7 +945,7 @@ body:             |
     %2 = COPY %1.sub_32
     %3 = LI 300
     %4 = RLDCR %0, killed %3, 0
-    ; CHECK: RLDICR %0, 44, 0
+    ; CHECK: RLDICR killed %0, 44, 0
     ; CHECK-LATE: rldicr 3, 3, 44, 0
     $x3 = COPY %4
     BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -1159,7 +1159,7 @@ body:             |
     %0 = COPY $x3
     %2 = LI 400
     %3 = SRD %0, killed %2
-    ; CHECK: RLDICL %0, 48, 16
+    ; CHECK: RLDICL killed %0, 48, 16
     ; CHECK-LATE: rldicl 3, 3, 48, 16
     $x3 = COPY %3
     BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -1265,7 +1265,7 @@ body:             |
     %0 = COPY $x3
     %2 = LI -44
     %3 = SRAD %0, killed %2, implicit-def dead $carry
-    ; CHECK: SRAD %0, killed %2, implicit-def dead $carry
+    ; CHECK: SRAD killed %0, killed %2, implicit-def dead $carry
     ; CHECK-LATE: srad 3, 3, 4
     $x3 = COPY %3
     BLR8 implicit $lr8, implicit $rm, implicit $x3
@@ -1318,7 +1318,7 @@ body:             |
     %0 = COPY $x3
     %2 = LI 68
     %3 = SRAD_rec %0, killed %2, implicit-def dead $carry, implicit-def $cr0
-    ; CHECK: SRAD_rec %0, killed %2, implicit-def dead $carry, implicit-def $cr0
+    ; CHECK: SRAD_rec killed %0, killed %2, implicit-def dead $carry, implicit-def $cr0
     ; CHECK-LATE: srad. 3, 3, 5
     %4 = COPY killed $cr0
     %5 = ISEL8 %1, %3, %4.sub_eq

diff --git a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
diff --git a/llvm/test/CodeGen/PowerPC/fixup-kill-dead-flag-crash.mir b/llvm/test/CodeGen/PowerPC/fixup-kill-dead-flag-crash.mir
@@ -28,11 +28,11 @@ body: |
     liveins: $r3
     %0:gprc = COPY $r3
     %1:gprc_and_gprc_nor0 = LI 0
-    ; CHECK: dead %2:gprc = COPY %1
+    ; CHECK-NOT: COPY %1
     %2:gprc = COPY %1:gprc_and_gprc_nor0
     ; CHECK: %3:gprc = LI 1
     %3:gprc = ORI killed %2:gprc, 1
-    ; CHECK: STW killed %3, %0, 100
+    ; CHECK: STW killed %3, killed %0, 100
     STW killed %3:gprc, %0:gprc, 100
     BLR8 implicit $lr8, implicit $rm
 ...
diff --git a/llvm/test/CodeGen/PowerPC/fold-rlwinm.mir b/llvm/test/CodeGen/PowerPC/fold-rlwinm.mir
@@ -13,7 +13,7 @@ body: |
     %2:gprc = RLWINM %1:gprc, 27, 5, 31
     ; CHECK-NOT: %2:gprc = RLWINM %1, 27, 5, 31
     %3:gprc = RLWINM %2:gprc, 19, 0, 12
-    ; CHECK: %3:gprc = RLWINM %1, 14, 0, 12
+    ; CHECK: %3:gprc = RLWINM killed %1, 14, 0, 12
     BLR8 implicit $lr8, implicit $rm
 ...
 ---
@@ -28,7 +28,7 @@ body: |
     %2:gprc = RLWINM %1:gprc, 27, 0, 31
     ; CHECK-NOT: %2:gprc = RLWINM %1, 27, 0, 31
     %3:gprc = RLWINM %2:gprc, 19, 0, 12
-    ; CHECK: %3:gprc = RLWINM %1, 14, 0, 12
+    ; CHECK: %3:gprc = RLWINM killed %1, 14, 0, 12
     BLR8 implicit $lr8, implicit $rm
 ...
 ---
@@ -43,7 +43,7 @@ body: |
     %2:gprc = RLWINM %1:gprc, 27, 10, 9 
     ; CHECK-NOT: %2:gprc = RLWINM %1, 27, 10, 9
     %3:gprc = RLWINM %2:gprc, 19, 10, 1
-    ; CHECK: %3:gprc = RLWINM %1, 14, 10, 1
+    ; CHECK: %3:gprc = RLWINM killed %1, 14, 10, 1
     BLR8 implicit $lr8, implicit $rm
 ...
 ---
@@ -58,7 +58,7 @@ body: |
     %2:gprc = RLWINM %1:gprc, 27, 30, 10
     ; CHECK-NOT: %2:gprc = RLWINM %1, 27, 30, 10 
     %3:gprc = RLWINM %2:gprc, 19, 0, 12
-    ; CHECK: %3:gprc = RLWINM %1, 14, 11, 12
+    ; CHECK: %3:gprc = RLWINM killed %1, 14, 11, 12
     BLR8 implicit $lr8, implicit $rm
 ...
 ---
@@ -71,9 +71,9 @@ body: |
     %0:g8rc = COPY $x3
     %1:gprc = COPY %0.sub_32:g8rc
     %2:gprc = RLWINM %1:gprc, 10, 5, 31
-    ; CHECK: %2:gprc = RLWINM %1, 10, 5, 31
+    ; CHECK: %2:gprc = RLWINM killed %1, 10, 5, 31
     %3:gprc = RLWINM %2:gprc, 10, 30, 5
-    ; CHECK: %3:gprc = RLWINM %2, 10, 30, 5
+    ; CHECK: %3:gprc = RLWINM killed %2, 10, 30, 5
     BLR8 implicit $lr8, implicit $rm
 ...
 ---
@@ -85,10 +85,10 @@ body: |
     liveins: $x3
     %0:g8rc = COPY $x3
     %1:gprc = COPY %0.sub_32:g8rc
-    %2:gprc = RLWINM %1:gprc, 10, 20, 10
-    ; CHECK: %2:gprc = RLWINM %1, 10, 20, 10
-    %3:gprc = RLWINM %2:gprc, 10, 0, 31
-    ; CHECK: %3:gprc = RLWINM %2, 10, 0, 31
+    %2:gprc = RLWINM killed %1:gprc, 10, 20, 10
+    ; CHECK: %2:gprc = RLWINM killed %1, 10, 20, 10
+    %3:gprc = RLWINM killed %2:gprc, 10, 0, 31
+    ; CHECK: %3:gprc = RLWINM killed %2, 10, 0, 31
     BLR8 implicit $lr8, implicit $rm
 ...
 ---
@@ -105,7 +105,7 @@ body: |
     %3:gprc = RLWINM %2:gprc, 19, 0, 12
     ; CHECK: %3:gprc = RLWINM killed %1, 14, 0, 12
     STW %3:gprc, %2:gprc, 100 
-    ; CHECK: STW %3, %2, 100
+    ; CHECK: STW killed %3, killed %2, 100
     BLR8 implicit $lr8, implicit $rm
 ...
 ---
@@ -135,7 +135,7 @@ body: |
     %2:gprc = RLWINM %1:gprc, 27, 5, 10
     ; CHECK-NOT: RLWINM %1,
     %3:gprc = RLWINM_rec %2:gprc, 8, 5, 10, implicit-def $cr0
-    ; CHECK: %3:gprc = ANDI_rec %1, 0, implicit-def $cr0
+    ; CHECK: %3:gprc = ANDI_rec killed %1, 0, implicit-def dead $cr0
     BLR8 implicit $lr8, implicit $rm
 ...
 ---
@@ -147,10 +147,10 @@ body: |
     liveins: $x3
     %0:g8rc = COPY $x3
     %1:gprc = COPY %0.sub_32:g8rc
-    %2:gprc = RLWINM_rec %1:gprc, 27, 5, 10, implicit-def $cr0
-    ; CHECK: %2:gprc = RLWINM_rec %1, 27, 5, 10, implicit-def $cr0
-    %3:gprc = RLWINM_rec %2:gprc, 8, 5, 10, implicit-def $cr0
-    ; CHECK: %3:gprc = ANDI_rec %1, 0, implicit-def $cr0
+    %2:gprc = RLWINM_rec killed %1:gprc, 27, 5, 10, implicit-def $cr0
+    ; CHECK: %2:gprc = RLWINM_rec %1, 27, 5, 10, implicit-def dead $cr0
+    %3:gprc = RLWINM_rec killed %2:gprc, 8, 5, 10, implicit-def $cr0
+    ; CHECK: %3:gprc = ANDI_rec killed %1, 0, implicit-def dead $cr0
     BLR8 implicit $lr8, implicit $rm
 ...
 ---
@@ -163,9 +163,9 @@ body: |
     %0:g8rc = COPY $x3
     %1:gprc = COPY %0.sub_32:g8rc
     %2:gprc = RLWINM %1:gprc, 20, 5, 31
-    ; CHECK: %2:gprc = RLWINM %1, 20, 5, 31
+    ; CHECK: %2:gprc = RLWINM killed %1, 20, 5, 31
     %3:gprc = RLWINM %2:gprc, 19, 10, 20
-    ; CHECK: %3:gprc = RLWINM %2, 19, 10, 20
+    ; CHECK: %3:gprc = RLWINM killed %2, 19, 10, 20
     BLR8 implicit $lr8, implicit $rm
 ...
 ---
@@ -190,10 +190,10 @@ body: |
     liveins: $x3
     ; CHECK-LABEL: name: testFoldRLWINMAndANDI
     ; CHECK: liveins: $x3
-    ; CHECK: [[COPY:%[0-9]+]]:g8rc = COPY $x3
-    ; CHECK: [[COPY1:%[0-9]+]]:gprc = COPY [[COPY]].sub_32
-    ; CHECK: [[RLWINM:%[0-9]+]]:gprc = RLWINM [[COPY1]], 4, 28, 31
-    ; CHECK: [[ANDI_rec:%[0-9]+]]:gprc = ANDI_rec [[RLWINM]], 4, implicit-def $cr0
+    ; CHECK: [[COPY:%[0-9]+]]:g8rc = COPY killed $x3
+    ; CHECK: [[COPY1:%[0-9]+]]:gprc = COPY killed [[COPY]].sub_32
+    ; CHECK: [[RLWINM:%[0-9]+]]:gprc = RLWINM killed [[COPY1]], 4, 28, 31
+    ; CHECK: [[ANDI_rec:%[0-9]+]]:gprc = ANDI_rec killed [[RLWINM]], 4, implicit-def dead $cr0
     ; CHECK: BLR8 implicit $lr8, implicit $rm
     %0:g8rc = COPY $x3
     %1:gprc = COPY %0.sub_32:g8rc

diff --git a/llvm/test/CodeGen/PowerPC/mi-peephole.mir b/llvm/test/CodeGen/PowerPC/mi-peephole.mir
@@ -28,9 +28,9 @@ body:             |
 
   ; CHECK-LABEL: testRLDIC
   ; CHECK: bb.0.entry:
-  ; CHECK:   %1:g8rc = COPY $x4
-  ; CHECK:   %0:g8rc = COPY $x3
+  ; CHECK:   %1:g8rc = COPY killed $x4
+  ; CHECK:   %0:g8rc = COPY killed $x3
   ; CHECK:   %3:g8rc = RLDIC killed %1, 2, 30
-  ; CHECK:   $x3 = COPY %3
-  ; CHECK:   BLR8 implicit $lr8, implicit $rm, implicit $x3
+  ; CHECK:   $x3 = COPY killed %3
+  ; CHECK:   BLR8 implicit $lr8, implicit $rm, implicit killed $x3
 ...
diff --git a/llvm/test/CodeGen/PowerPC/opt-cmp-rec-postra.mir b/llvm/test/CodeGen/PowerPC/opt-cmp-rec-postra.mir
@@ -11,7 +11,7 @@ body:             |
     renamable $x3 = OR8 killed renamable $x3, killed renamable $x4
     renamable $cr0 = CMPDI renamable $x3, 0, implicit killed $x3
     ; CHECK-LABEL: name: test1
-    ; CHECK: renamable $x3 = OR8_rec renamable $x3, killed renamable $x4, implicit-def $cr0
+    ; CHECK: renamable $x3 = OR8_rec killed renamable $x3, killed renamable $x4, implicit-def $cr0
     ; CHECK-NOT: CMPDI
     BCC 68, killed renamable $cr0, %bb.2
 

diff --git a/llvm/test/CodeGen/PowerPC/peephole-miscompile-extswsli.mir b/llvm/test/CodeGen/PowerPC/peephole-miscompile-extswsli.mir
@@ -8,31 +8,35 @@ tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: poc
   ; CHECK: bb.0.entry:
-  ; CHECK:   successors: %bb.1, %bb.2
-  ; CHECK:   liveins: $x3, $x4, $x5, $x6
-  ; CHECK:   [[COPY:%[0-9]+]]:g8rc = COPY $x6
-  ; CHECK:   [[COPY1:%[0-9]+]]:g8rc = COPY $x5
-  ; CHECK:   [[COPY2:%[0-9]+]]:g8rc = COPY $x4
-  ; CHECK:   [[COPY3:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x3
-  ; CHECK:   [[ANDI8_rec_:%[0-9]+]]:g8rc = ANDI8_rec [[COPY1]], 1, implicit-def $cr0
-  ; CHECK:   [[COPY4:%[0-9]+]]:crbitrc = COPY $cr0gt
-  ; CHECK:   BCn killed [[COPY4]], %bb.2
-  ; CHECK:   B %bb.1
-  ; CHECK: bb.1:
-  ; CHECK:   liveins: $x3
-  ; CHECK:   [[EXTSW:%[0-9]+]]:g8rc = EXTSW $x3
-  ; CHECK:   [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[ANDI8_rec_]], 2, 61
-  ; CHECK:   $x3 = COPY [[RLDICR]]
-  ; CHECK:   [[RLDICR1:%[0-9]+]]:g8rc = RLDICR [[EXTSW]], 2, 61
-  ; CHECK:   [[ADD8_:%[0-9]+]]:g8rc = ADD8 [[COPY3]], [[RLDICR1]]
-  ; CHECK:   $x3 = COPY [[ADD8_]]
-  ; CHECK:   BLR8 implicit $lr8, implicit $rm, implicit $x3
-  ; CHECK: bb.2:
-  ; CHECK:   [[COPY5:%[0-9]+]]:gprc = COPY [[COPY]].sub_32
-  ; CHECK:   [[DEF:%[0-9]+]]:g8rc = IMPLICIT_DEF
-  ; CHECK:   [[INSERT_SUBREG:%[0-9]+]]:g8rc = INSERT_SUBREG [[DEF]], [[COPY5]], %subreg.sub_32
-  ; CHECK:   $x3 = COPY [[INSERT_SUBREG]]
-  ; CHECK:   BLR8 implicit $lr8, implicit $rm, implicit $x3
+  ; CHECK-NEXT:   successors: %bb.1, %bb.2
+  ; CHECK-NEXT:   liveins: $x3, $x4, $x5, $x6
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:g8rc = COPY killed $x6
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:g8rc = COPY killed $x5
+  ; CHECK-NEXT:   dead %2:g8rc = COPY killed $x4
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY killed $x3
+  ; CHECK-NEXT:   [[ANDI8_rec:%[0-9]+]]:g8rc = ANDI8_rec killed [[COPY1]], 1, implicit-def dead $cr0, implicit-def $cr0gt
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:crbitrc = COPY killed $cr0gt
+  ; CHECK-NEXT:   BCn killed [[COPY3]], %bb.2
+  ; CHECK-NEXT:   B %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   liveins: $x3
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[EXTSW:%[0-9]+]]:g8rc = EXTSW killed $x3
+  ; CHECK-NEXT:   [[RLDICR:%[0-9]+]]:g8rc = RLDICR killed [[ANDI8_rec]], 2, 61
+  ; CHECK-NEXT:   dead $x3 = COPY killed [[RLDICR]]
+  ; CHECK-NEXT:   [[RLDICR1:%[0-9]+]]:g8rc = RLDICR killed [[EXTSW]], 2, 61
+  ; CHECK-NEXT:   [[ADD8_:%[0-9]+]]:g8rc = ADD8 killed [[COPY2]], killed [[RLDICR1]]
+  ; CHECK-NEXT:   $x3 = COPY killed [[ADD8_]]
+  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm, implicit killed $x3
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2:
+  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:gprc = COPY killed [[COPY]].sub_32
+  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:g8rc = IMPLICIT_DEF
+  ; CHECK-NEXT:   [[INSERT_SUBREG:%[0-9]+]]:g8rc = INSERT_SUBREG killed [[DEF]], killed [[COPY4]], %subreg.sub_32
+  ; CHECK-NEXT:   $x3 = COPY killed [[INSERT_SUBREG]]
+  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm, implicit killed $x3
   bb.0.entry:
     successors: %bb.1, %bb.2
     liveins: $x3, $x4, $x5, $x6

diff --git a/llvm/test/CodeGen/PowerPC/peephole-phi-acc.mir b/llvm/test/CodeGen/PowerPC/peephole-phi-acc.mir
@@ -674,6 +674,7 @@ registers:
   - { id: 52, class: vsrprc, preferred-register: '' }
   - { id: 53, class: vsrc, preferred-register: '' }
   - { id: 54, class: vsrprc, preferred-register: '' }
+  - { id: 55, class: crrc, preferred-register: '' }
 liveins:
   - { reg: '$x3', virtual-reg: '%7' }
   - { reg: '$v2', virtual-reg: '%8' }
@@ -767,22 +768,24 @@ body:             |
     %37:g8rc_and_g8rc_nox0 = RLDICL killed %35, 0, 32
     %38:g8rc = nuw nsw ADDI8 killed %37, 1
     MTCTR8loop killed %38, implicit-def dead $ctr8
+    B %bb.5
 
   bb.5.for.body.epil:
     successors: %bb.3(0x40000000), %bb.5(0x7c000000)
-    ; We check that no phi node is inserted in the block.
+    ; We check that no [u]acc phi node is inserted in the block.
     ; CHECK-LABEL: bb.{{[0-9]}}.for.body.epil:
     ; CHECK-NEXT: successors: %bb.{{[0-9]}}(0x{{[0-9a-f]+}}), %bb.{{[0-9]}}(0x{{[0-9a-f]+}})
-    ; CHECK-NEXT: {{ }}
-    ; CHECK-NEXT: %2:uaccrc = PHI
+    ; CHECK-NOT: uaccrc = PHI
+    ; CHECK-NOT: accrc = PHI
+    ; CHECK: %2:uaccrc = PHI
     ; CHECK-NEXT: %39:vsrc
     %2:uaccrc = PHI %1, %bb.4, %3, %bb.5
     %39:vsrc = COPY %8
     %41:accrc = COPY %2
     %40:accrc = XVF32GERPP %41, %39, %39
     %3:uaccrc = COPY %40
-    %15:crrc = CMPLWI %14, 7
-    BCC 12, killed %15, %bb.5
+    %55:crrc = CMPLWI %14, 7
+    BCC 12, killed %55, %bb.5
     B %bb.3
 
   bb.6.for.cond.cleanup:

diff --git a/llvm/test/CodeGen/PowerPC/remove-redundant-li-implicit-reg.mir b/llvm/test/CodeGen/PowerPC/remove-redundant-li-implicit-reg.mir
@@ -18,5 +18,5 @@ body: |
   ; CHECK: bb.0.entry:
   ; CHECK:   STW killed $r3, killed $x5, 100
   ; CHECK:   renamable $x4 = exact RLDICL killed renamable $x4, 62, 2
-  ; CHECK:   STD killed $x4, $x4, 100
+  ; CHECK:   STD killed $x4, killed $x4, 100
   ; CHECK:   BLR8 implicit $lr8, implicit $rm
diff --git a/llvm/test/CodeGen/PowerPC/rlwinm_rldicl_to_andi.mir b/llvm/test/CodeGen/PowerPC/rlwinm_rldicl_to_andi.mir
@@ -122,7 +122,7 @@ body:             |
     %3:gprc = LI -11
     %4:gprc_and_gprc_nor0 = RLWINM_rec %3, 2, 20, 31, implicit-def $cr0
     ; CHECK: LI 4055
-    ; CHECK: ANDI_rec %3, 4055
+    ; CHECK: ANDI_rec killed %3, 4055
     ; CHECK-LATE-NOT: andi.
     ; CHECK-LATE: rlwinm.
     %5:crrc = COPY killed $cr0
@@ -297,7 +297,7 @@ body:             |
     %0:g8rc = LI8 -11
     %2:g8rc_and_g8rc_nox0  = RLDICL_rec %0, 2, 49, implicit-def $cr0
     ; CHECK: LI8 32727
-    ; CHECK: ANDI8_rec %0, 32727
+    ; CHECK: ANDI8_rec killed %0, 32727
     ; CHECK-LATE-NOT: andi.
     ; CHECK-LATE: rldicl.
     %3:crrc = COPY killed $cr0

diff --git a/llvm/test/CodeGen/PowerPC/sext_elimination.mir b/llvm/test/CodeGen/PowerPC/sext_elimination.mir
@@ -38,12 +38,12 @@ body:             |
     liveins: $x3
 
     ; CHECK-LABEL: bb.0.entry:
-    ; CHECK: %4:g8rc = EXTSW_32_64 %3
+    ; CHECK: %4:g8rc = EXTSW_32_64 killed %3
     ; CHECK: %5:g8rc = INSERT_SUBREG %15, %1, %subreg.sub_32
-    ; CHECK: %7:g8rc = EXTSW_32_64 %6
+    ; CHECK: %7:g8rc = EXTSW_32_64 killed %6
     ; CHECK: %9:g8rc = INSERT_SUBREG %16, %8, %subreg.sub_32
     ; CHECK: %11:g8rc = INSERT_SUBREG %17, %10, %subreg.sub_32
-    ; CHECK: %14:g8rc = COPY %1
+    ; CHECK: %14:g8rc = COPY killed %13
 
     %0:g8rc_nox0 = COPY $x3
     %1:gprc, %2:g8rc_nox0 = LBZU 0, %0:g8rc_nox0