1,157 changes: 1,141 additions & 16 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
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350 changes: 346 additions & 4 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
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Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+experimental-zvfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8
; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+experimental-zvfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8
; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+experimental-zvfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+experimental-zvfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+experimental-zvfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8,LMULMAX8RV32
; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+experimental-zvfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8,LMULMAX8RV64
; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+experimental-zvfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1,LMULMAX1RV32
; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+experimental-zvfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1,LMULMAX1RV64

define void @fp2si_v2f32_v2i32(ptr %x, ptr %y) {
; CHECK-LABEL: fp2si_v2f32_v2i32:
Expand Down Expand Up @@ -78,6 +78,348 @@ define <2 x i1> @fp2ui_v2f32_v2i1(<2 x float> %x) {
ret <2 x i1> %z
}

define void @fp2si_v3f32_v3i32(ptr %x, ptr %y) {
; LMULMAX8RV32-LABEL: fp2si_v3f32_v3i32:
; LMULMAX8RV32: # %bb.0:
; LMULMAX8RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX8RV32-NEXT: vle32.v v8, (a0)
; LMULMAX8RV32-NEXT: vfcvt.rtz.x.f.v v8, v8
; LMULMAX8RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX8RV32-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX8RV32-NEXT: addi a0, a1, 8
; LMULMAX8RV32-NEXT: vse32.v v9, (a0)
; LMULMAX8RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX8RV32-NEXT: vse32.v v8, (a1)
; LMULMAX8RV32-NEXT: ret
;
; LMULMAX8RV64-LABEL: fp2si_v3f32_v3i32:
; LMULMAX8RV64: # %bb.0:
; LMULMAX8RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX8RV64-NEXT: vle32.v v8, (a0)
; LMULMAX8RV64-NEXT: vfcvt.rtz.x.f.v v8, v8
; LMULMAX8RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX8RV64-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX8RV64-NEXT: addi a0, a1, 8
; LMULMAX8RV64-NEXT: vse32.v v9, (a0)
; LMULMAX8RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX8RV64-NEXT: vse64.v v8, (a1)
; LMULMAX8RV64-NEXT: ret
;
; LMULMAX1RV32-LABEL: fp2si_v3f32_v3i32:
; LMULMAX1RV32: # %bb.0:
; LMULMAX1RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1RV32-NEXT: vle32.v v8, (a0)
; LMULMAX1RV32-NEXT: vfcvt.rtz.x.f.v v8, v8
; LMULMAX1RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1RV32-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX1RV32-NEXT: addi a0, a1, 8
; LMULMAX1RV32-NEXT: vse32.v v9, (a0)
; LMULMAX1RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX1RV32-NEXT: vse32.v v8, (a1)
; LMULMAX1RV32-NEXT: ret
;
; LMULMAX1RV64-LABEL: fp2si_v3f32_v3i32:
; LMULMAX1RV64: # %bb.0:
; LMULMAX1RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1RV64-NEXT: vle32.v v8, (a0)
; LMULMAX1RV64-NEXT: vfcvt.rtz.x.f.v v8, v8
; LMULMAX1RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1RV64-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX1RV64-NEXT: addi a0, a1, 8
; LMULMAX1RV64-NEXT: vse32.v v9, (a0)
; LMULMAX1RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX1RV64-NEXT: vse64.v v8, (a1)
; LMULMAX1RV64-NEXT: ret
%a = load <3 x float>, ptr %x
%d = fptosi <3 x float> %a to <3 x i32>
store <3 x i32> %d, ptr %y
ret void
}

define void @fp2ui_v3f32_v3i32(ptr %x, ptr %y) {
; LMULMAX8RV32-LABEL: fp2ui_v3f32_v3i32:
; LMULMAX8RV32: # %bb.0:
; LMULMAX8RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX8RV32-NEXT: vle32.v v8, (a0)
; LMULMAX8RV32-NEXT: vfcvt.rtz.xu.f.v v8, v8
; LMULMAX8RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX8RV32-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX8RV32-NEXT: addi a0, a1, 8
; LMULMAX8RV32-NEXT: vse32.v v9, (a0)
; LMULMAX8RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX8RV32-NEXT: vse32.v v8, (a1)
; LMULMAX8RV32-NEXT: ret
;
; LMULMAX8RV64-LABEL: fp2ui_v3f32_v3i32:
; LMULMAX8RV64: # %bb.0:
; LMULMAX8RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX8RV64-NEXT: vle32.v v8, (a0)
; LMULMAX8RV64-NEXT: vfcvt.rtz.xu.f.v v8, v8
; LMULMAX8RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX8RV64-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX8RV64-NEXT: addi a0, a1, 8
; LMULMAX8RV64-NEXT: vse32.v v9, (a0)
; LMULMAX8RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX8RV64-NEXT: vse64.v v8, (a1)
; LMULMAX8RV64-NEXT: ret
;
; LMULMAX1RV32-LABEL: fp2ui_v3f32_v3i32:
; LMULMAX1RV32: # %bb.0:
; LMULMAX1RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1RV32-NEXT: vle32.v v8, (a0)
; LMULMAX1RV32-NEXT: vfcvt.rtz.xu.f.v v8, v8
; LMULMAX1RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1RV32-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX1RV32-NEXT: addi a0, a1, 8
; LMULMAX1RV32-NEXT: vse32.v v9, (a0)
; LMULMAX1RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX1RV32-NEXT: vse32.v v8, (a1)
; LMULMAX1RV32-NEXT: ret
;
; LMULMAX1RV64-LABEL: fp2ui_v3f32_v3i32:
; LMULMAX1RV64: # %bb.0:
; LMULMAX1RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1RV64-NEXT: vle32.v v8, (a0)
; LMULMAX1RV64-NEXT: vfcvt.rtz.xu.f.v v8, v8
; LMULMAX1RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1RV64-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX1RV64-NEXT: addi a0, a1, 8
; LMULMAX1RV64-NEXT: vse32.v v9, (a0)
; LMULMAX1RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX1RV64-NEXT: vse64.v v8, (a1)
; LMULMAX1RV64-NEXT: ret
%a = load <3 x float>, ptr %x
%d = fptoui <3 x float> %a to <3 x i32>
store <3 x i32> %d, ptr %y
ret void
}

define <3 x i1> @fp2si_v3f32_v3i1(<3 x float> %x) {
; CHECK-LABEL: fp2si_v3f32_v3i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
; CHECK-NEXT: vand.vi v8, v9, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%z = fptosi <3 x float> %x to <3 x i1>
ret <3 x i1> %z
}

; FIXME: This is expanded when they could be widened + promoted
define <3 x i15> @fp2si_v3f32_v3i15(<3 x float> %x) {
; LMULMAX8RV32-LABEL: fp2si_v3f32_v3i15:
; LMULMAX8RV32: # %bb.0:
; LMULMAX8RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; LMULMAX8RV32-NEXT: vfncvt.rtz.x.f.w v9, v8
; LMULMAX8RV32-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; LMULMAX8RV32-NEXT: vslidedown.vi v8, v9, 2
; LMULMAX8RV32-NEXT: vmv.x.s a1, v8
; LMULMAX8RV32-NEXT: slli a2, a1, 17
; LMULMAX8RV32-NEXT: srli a2, a2, 19
; LMULMAX8RV32-NEXT: sh a2, 4(a0)
; LMULMAX8RV32-NEXT: vmv.x.s a2, v9
; LMULMAX8RV32-NEXT: lui a3, 8
; LMULMAX8RV32-NEXT: addi a3, a3, -1
; LMULMAX8RV32-NEXT: and a2, a2, a3
; LMULMAX8RV32-NEXT: vslidedown.vi v8, v9, 1
; LMULMAX8RV32-NEXT: vmv.x.s a4, v8
; LMULMAX8RV32-NEXT: and a3, a4, a3
; LMULMAX8RV32-NEXT: slli a3, a3, 15
; LMULMAX8RV32-NEXT: slli a1, a1, 30
; LMULMAX8RV32-NEXT: or a1, a2, a1
; LMULMAX8RV32-NEXT: or a1, a1, a3
; LMULMAX8RV32-NEXT: sw a1, 0(a0)
; LMULMAX8RV32-NEXT: ret
;
; LMULMAX8RV64-LABEL: fp2si_v3f32_v3i15:
; LMULMAX8RV64: # %bb.0:
; LMULMAX8RV64-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; LMULMAX8RV64-NEXT: vfncvt.rtz.x.f.w v9, v8
; LMULMAX8RV64-NEXT: vmv.x.s a1, v9
; LMULMAX8RV64-NEXT: lui a2, 8
; LMULMAX8RV64-NEXT: addiw a2, a2, -1
; LMULMAX8RV64-NEXT: and a1, a1, a2
; LMULMAX8RV64-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; LMULMAX8RV64-NEXT: vslidedown.vi v8, v9, 1
; LMULMAX8RV64-NEXT: vmv.x.s a3, v8
; LMULMAX8RV64-NEXT: and a2, a3, a2
; LMULMAX8RV64-NEXT: slli a2, a2, 15
; LMULMAX8RV64-NEXT: vslidedown.vi v8, v9, 2
; LMULMAX8RV64-NEXT: vmv.x.s a3, v8
; LMULMAX8RV64-NEXT: slli a3, a3, 30
; LMULMAX8RV64-NEXT: or a1, a1, a3
; LMULMAX8RV64-NEXT: or a1, a1, a2
; LMULMAX8RV64-NEXT: sw a1, 0(a0)
; LMULMAX8RV64-NEXT: slli a1, a1, 19
; LMULMAX8RV64-NEXT: srli a1, a1, 51
; LMULMAX8RV64-NEXT: sh a1, 4(a0)
; LMULMAX8RV64-NEXT: ret
;
; LMULMAX1RV32-LABEL: fp2si_v3f32_v3i15:
; LMULMAX1RV32: # %bb.0:
; LMULMAX1RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; LMULMAX1RV32-NEXT: vfncvt.rtz.x.f.w v9, v8
; LMULMAX1RV32-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; LMULMAX1RV32-NEXT: vslidedown.vi v8, v9, 2
; LMULMAX1RV32-NEXT: vmv.x.s a1, v8
; LMULMAX1RV32-NEXT: slli a2, a1, 17
; LMULMAX1RV32-NEXT: srli a2, a2, 19
; LMULMAX1RV32-NEXT: sh a2, 4(a0)
; LMULMAX1RV32-NEXT: vmv.x.s a2, v9
; LMULMAX1RV32-NEXT: lui a3, 8
; LMULMAX1RV32-NEXT: addi a3, a3, -1
; LMULMAX1RV32-NEXT: and a2, a2, a3
; LMULMAX1RV32-NEXT: vslidedown.vi v8, v9, 1
; LMULMAX1RV32-NEXT: vmv.x.s a4, v8
; LMULMAX1RV32-NEXT: and a3, a4, a3
; LMULMAX1RV32-NEXT: slli a3, a3, 15
; LMULMAX1RV32-NEXT: slli a1, a1, 30
; LMULMAX1RV32-NEXT: or a1, a2, a1
; LMULMAX1RV32-NEXT: or a1, a1, a3
; LMULMAX1RV32-NEXT: sw a1, 0(a0)
; LMULMAX1RV32-NEXT: ret
;
; LMULMAX1RV64-LABEL: fp2si_v3f32_v3i15:
; LMULMAX1RV64: # %bb.0:
; LMULMAX1RV64-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; LMULMAX1RV64-NEXT: vfncvt.rtz.x.f.w v9, v8
; LMULMAX1RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1RV64-NEXT: lui a2, 8
; LMULMAX1RV64-NEXT: addiw a2, a2, -1
; LMULMAX1RV64-NEXT: and a1, a1, a2
; LMULMAX1RV64-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; LMULMAX1RV64-NEXT: vslidedown.vi v8, v9, 1
; LMULMAX1RV64-NEXT: vmv.x.s a3, v8
; LMULMAX1RV64-NEXT: and a2, a3, a2
; LMULMAX1RV64-NEXT: slli a2, a2, 15
; LMULMAX1RV64-NEXT: vslidedown.vi v8, v9, 2
; LMULMAX1RV64-NEXT: vmv.x.s a3, v8
; LMULMAX1RV64-NEXT: slli a3, a3, 30
; LMULMAX1RV64-NEXT: or a1, a1, a3
; LMULMAX1RV64-NEXT: or a1, a1, a2
; LMULMAX1RV64-NEXT: sw a1, 0(a0)
; LMULMAX1RV64-NEXT: slli a1, a1, 19
; LMULMAX1RV64-NEXT: srli a1, a1, 51
; LMULMAX1RV64-NEXT: sh a1, 4(a0)
; LMULMAX1RV64-NEXT: ret
%z = fptosi <3 x float> %x to <3 x i15>
ret <3 x i15> %z
}

; FIXME: This is expanded when they could be widened + promoted
define <3 x i15> @fp2ui_v3f32_v3i15(<3 x float> %x) {
; LMULMAX8RV32-LABEL: fp2ui_v3f32_v3i15:
; LMULMAX8RV32: # %bb.0:
; LMULMAX8RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; LMULMAX8RV32-NEXT: vfncvt.rtz.x.f.w v9, v8
; LMULMAX8RV32-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; LMULMAX8RV32-NEXT: vslidedown.vi v8, v9, 2
; LMULMAX8RV32-NEXT: vmv.x.s a1, v8
; LMULMAX8RV32-NEXT: slli a2, a1, 17
; LMULMAX8RV32-NEXT: srli a2, a2, 19
; LMULMAX8RV32-NEXT: sh a2, 4(a0)
; LMULMAX8RV32-NEXT: vmv.x.s a2, v9
; LMULMAX8RV32-NEXT: lui a3, 16
; LMULMAX8RV32-NEXT: addi a3, a3, -1
; LMULMAX8RV32-NEXT: and a2, a2, a3
; LMULMAX8RV32-NEXT: vslidedown.vi v8, v9, 1
; LMULMAX8RV32-NEXT: vmv.x.s a4, v8
; LMULMAX8RV32-NEXT: and a3, a4, a3
; LMULMAX8RV32-NEXT: slli a3, a3, 15
; LMULMAX8RV32-NEXT: slli a1, a1, 30
; LMULMAX8RV32-NEXT: or a1, a2, a1
; LMULMAX8RV32-NEXT: or a1, a1, a3
; LMULMAX8RV32-NEXT: sw a1, 0(a0)
; LMULMAX8RV32-NEXT: ret
;
; LMULMAX8RV64-LABEL: fp2ui_v3f32_v3i15:
; LMULMAX8RV64: # %bb.0:
; LMULMAX8RV64-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; LMULMAX8RV64-NEXT: vfncvt.rtz.x.f.w v9, v8
; LMULMAX8RV64-NEXT: vmv.x.s a1, v9
; LMULMAX8RV64-NEXT: lui a2, 16
; LMULMAX8RV64-NEXT: addiw a2, a2, -1
; LMULMAX8RV64-NEXT: and a1, a1, a2
; LMULMAX8RV64-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; LMULMAX8RV64-NEXT: vslidedown.vi v8, v9, 1
; LMULMAX8RV64-NEXT: vmv.x.s a3, v8
; LMULMAX8RV64-NEXT: and a2, a3, a2
; LMULMAX8RV64-NEXT: slli a2, a2, 15
; LMULMAX8RV64-NEXT: vslidedown.vi v8, v9, 2
; LMULMAX8RV64-NEXT: vmv.x.s a3, v8
; LMULMAX8RV64-NEXT: slli a3, a3, 30
; LMULMAX8RV64-NEXT: or a1, a1, a3
; LMULMAX8RV64-NEXT: or a1, a1, a2
; LMULMAX8RV64-NEXT: sw a1, 0(a0)
; LMULMAX8RV64-NEXT: slli a1, a1, 19
; LMULMAX8RV64-NEXT: srli a1, a1, 51
; LMULMAX8RV64-NEXT: sh a1, 4(a0)
; LMULMAX8RV64-NEXT: ret
;
; LMULMAX1RV32-LABEL: fp2ui_v3f32_v3i15:
; LMULMAX1RV32: # %bb.0:
; LMULMAX1RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; LMULMAX1RV32-NEXT: vfncvt.rtz.x.f.w v9, v8
; LMULMAX1RV32-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; LMULMAX1RV32-NEXT: vslidedown.vi v8, v9, 2
; LMULMAX1RV32-NEXT: vmv.x.s a1, v8
; LMULMAX1RV32-NEXT: slli a2, a1, 17
; LMULMAX1RV32-NEXT: srli a2, a2, 19
; LMULMAX1RV32-NEXT: sh a2, 4(a0)
; LMULMAX1RV32-NEXT: vmv.x.s a2, v9
; LMULMAX1RV32-NEXT: lui a3, 16
; LMULMAX1RV32-NEXT: addi a3, a3, -1
; LMULMAX1RV32-NEXT: and a2, a2, a3
; LMULMAX1RV32-NEXT: vslidedown.vi v8, v9, 1
; LMULMAX1RV32-NEXT: vmv.x.s a4, v8
; LMULMAX1RV32-NEXT: and a3, a4, a3
; LMULMAX1RV32-NEXT: slli a3, a3, 15
; LMULMAX1RV32-NEXT: slli a1, a1, 30
; LMULMAX1RV32-NEXT: or a1, a2, a1
; LMULMAX1RV32-NEXT: or a1, a1, a3
; LMULMAX1RV32-NEXT: sw a1, 0(a0)
; LMULMAX1RV32-NEXT: ret
;
; LMULMAX1RV64-LABEL: fp2ui_v3f32_v3i15:
; LMULMAX1RV64: # %bb.0:
; LMULMAX1RV64-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; LMULMAX1RV64-NEXT: vfncvt.rtz.x.f.w v9, v8
; LMULMAX1RV64-NEXT: vmv.x.s a1, v9
; LMULMAX1RV64-NEXT: lui a2, 16
; LMULMAX1RV64-NEXT: addiw a2, a2, -1
; LMULMAX1RV64-NEXT: and a1, a1, a2
; LMULMAX1RV64-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; LMULMAX1RV64-NEXT: vslidedown.vi v8, v9, 1
; LMULMAX1RV64-NEXT: vmv.x.s a3, v8
; LMULMAX1RV64-NEXT: and a2, a3, a2
; LMULMAX1RV64-NEXT: slli a2, a2, 15
; LMULMAX1RV64-NEXT: vslidedown.vi v8, v9, 2
; LMULMAX1RV64-NEXT: vmv.x.s a3, v8
; LMULMAX1RV64-NEXT: slli a3, a3, 30
; LMULMAX1RV64-NEXT: or a1, a1, a3
; LMULMAX1RV64-NEXT: or a1, a1, a2
; LMULMAX1RV64-NEXT: sw a1, 0(a0)
; LMULMAX1RV64-NEXT: slli a1, a1, 19
; LMULMAX1RV64-NEXT: srli a1, a1, 51
; LMULMAX1RV64-NEXT: sh a1, 4(a0)
; LMULMAX1RV64-NEXT: ret
%z = fptoui <3 x float> %x to <3 x i15>
ret <3 x i15> %z
}

define <3 x i1> @fp2ui_v3f32_v3i1(<3 x float> %x) {
; CHECK-LABEL: fp2ui_v3f32_v3i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
; CHECK-NEXT: vand.vi v8, v9, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
%z = fptoui <3 x float> %x to <3 x i1>
ret <3 x i1> %z
}

define void @fp2si_v8f32_v8i32(ptr %x, ptr %y) {
; LMULMAX8-LABEL: fp2si_v8f32_v8i32:
; LMULMAX8: # %bb.0:
Expand Down
326 changes: 322 additions & 4 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
View file
Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+experimental-zvfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8
; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+experimental-zvfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8
; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+experimental-zvfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+experimental-zvfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+experimental-zvfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8,LMULMAX8RV32
; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+experimental-zvfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8,LMULMAX8RV64
; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+experimental-zvfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1,LMULMAX1RV32
; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+experimental-zvfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1,LMULMAX1RV64

define void @si2fp_v2i32_v2f32(ptr %x, ptr %y) {
; CHECK-LABEL: si2fp_v2i32_v2f32:
Expand Down Expand Up @@ -84,6 +84,324 @@ define <2 x float> @ui2fp_v2i1_v2f32(<2 x i1> %x) {
ret <2 x float> %z
}

define void @si2fp_v3i32_v3f32(ptr %x, ptr %y) {
; LMULMAX8RV32-LABEL: si2fp_v3i32_v3f32:
; LMULMAX8RV32: # %bb.0:
; LMULMAX8RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX8RV32-NEXT: vle32.v v8, (a0)
; LMULMAX8RV32-NEXT: vfcvt.f.x.v v8, v8
; LMULMAX8RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX8RV32-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX8RV32-NEXT: addi a0, a1, 8
; LMULMAX8RV32-NEXT: vse32.v v9, (a0)
; LMULMAX8RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX8RV32-NEXT: vse32.v v8, (a1)
; LMULMAX8RV32-NEXT: ret
;
; LMULMAX8RV64-LABEL: si2fp_v3i32_v3f32:
; LMULMAX8RV64: # %bb.0:
; LMULMAX8RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX8RV64-NEXT: vle32.v v8, (a0)
; LMULMAX8RV64-NEXT: vfcvt.f.x.v v8, v8
; LMULMAX8RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX8RV64-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX8RV64-NEXT: addi a0, a1, 8
; LMULMAX8RV64-NEXT: vse32.v v9, (a0)
; LMULMAX8RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX8RV64-NEXT: vse64.v v8, (a1)
; LMULMAX8RV64-NEXT: ret
;
; LMULMAX1RV32-LABEL: si2fp_v3i32_v3f32:
; LMULMAX1RV32: # %bb.0:
; LMULMAX1RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1RV32-NEXT: vle32.v v8, (a0)
; LMULMAX1RV32-NEXT: vfcvt.f.x.v v8, v8
; LMULMAX1RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1RV32-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX1RV32-NEXT: addi a0, a1, 8
; LMULMAX1RV32-NEXT: vse32.v v9, (a0)
; LMULMAX1RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX1RV32-NEXT: vse32.v v8, (a1)
; LMULMAX1RV32-NEXT: ret
;
; LMULMAX1RV64-LABEL: si2fp_v3i32_v3f32:
; LMULMAX1RV64: # %bb.0:
; LMULMAX1RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1RV64-NEXT: vle32.v v8, (a0)
; LMULMAX1RV64-NEXT: vfcvt.f.x.v v8, v8
; LMULMAX1RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1RV64-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX1RV64-NEXT: addi a0, a1, 8
; LMULMAX1RV64-NEXT: vse32.v v9, (a0)
; LMULMAX1RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX1RV64-NEXT: vse64.v v8, (a1)
; LMULMAX1RV64-NEXT: ret
%a = load <3 x i32>, ptr %x
%d = sitofp <3 x i32> %a to <3 x float>
store <3 x float> %d, ptr %y
ret void
}

define void @ui2fp_v3i32_v3f32(ptr %x, ptr %y) {
; LMULMAX8RV32-LABEL: ui2fp_v3i32_v3f32:
; LMULMAX8RV32: # %bb.0:
; LMULMAX8RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX8RV32-NEXT: vle32.v v8, (a0)
; LMULMAX8RV32-NEXT: vfcvt.f.xu.v v8, v8
; LMULMAX8RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX8RV32-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX8RV32-NEXT: addi a0, a1, 8
; LMULMAX8RV32-NEXT: vse32.v v9, (a0)
; LMULMAX8RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX8RV32-NEXT: vse32.v v8, (a1)
; LMULMAX8RV32-NEXT: ret
;
; LMULMAX8RV64-LABEL: ui2fp_v3i32_v3f32:
; LMULMAX8RV64: # %bb.0:
; LMULMAX8RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX8RV64-NEXT: vle32.v v8, (a0)
; LMULMAX8RV64-NEXT: vfcvt.f.xu.v v8, v8
; LMULMAX8RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX8RV64-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX8RV64-NEXT: addi a0, a1, 8
; LMULMAX8RV64-NEXT: vse32.v v9, (a0)
; LMULMAX8RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX8RV64-NEXT: vse64.v v8, (a1)
; LMULMAX8RV64-NEXT: ret
;
; LMULMAX1RV32-LABEL: ui2fp_v3i32_v3f32:
; LMULMAX1RV32: # %bb.0:
; LMULMAX1RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1RV32-NEXT: vle32.v v8, (a0)
; LMULMAX1RV32-NEXT: vfcvt.f.xu.v v8, v8
; LMULMAX1RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1RV32-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX1RV32-NEXT: addi a0, a1, 8
; LMULMAX1RV32-NEXT: vse32.v v9, (a0)
; LMULMAX1RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX1RV32-NEXT: vse32.v v8, (a1)
; LMULMAX1RV32-NEXT: ret
;
; LMULMAX1RV64-LABEL: ui2fp_v3i32_v3f32:
; LMULMAX1RV64: # %bb.0:
; LMULMAX1RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1RV64-NEXT: vle32.v v8, (a0)
; LMULMAX1RV64-NEXT: vfcvt.f.xu.v v8, v8
; LMULMAX1RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1RV64-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX1RV64-NEXT: addi a0, a1, 8
; LMULMAX1RV64-NEXT: vse32.v v9, (a0)
; LMULMAX1RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX1RV64-NEXT: vse64.v v8, (a1)
; LMULMAX1RV64-NEXT: ret
%a = load <3 x i32>, ptr %x
%d = uitofp <3 x i32> %a to <3 x float>
store <3 x float> %d, ptr %y
ret void
}

define <3 x float> @si2fp_v3i1_v3f32(<3 x i1> %x) {
; CHECK-LABEL: si2fp_v3i1_v3f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v9, v8, -1, v0
; CHECK-NEXT: vfwcvt.f.x.v v8, v9
; CHECK-NEXT: ret
%z = sitofp <3 x i1> %x to <3 x float>
ret <3 x float> %z
}

; FIXME: This gets expanded instead of widened + promoted
define <3 x float> @si2fp_v3i7_v3f32(<3 x i7> %x) {
; LMULMAX8RV32-LABEL: si2fp_v3i7_v3f32:
; LMULMAX8RV32: # %bb.0:
; LMULMAX8RV32-NEXT: addi sp, sp, -16
; LMULMAX8RV32-NEXT: .cfi_def_cfa_offset 16
; LMULMAX8RV32-NEXT: lw a1, 8(a0)
; LMULMAX8RV32-NEXT: sb a1, 14(sp)
; LMULMAX8RV32-NEXT: lw a1, 4(a0)
; LMULMAX8RV32-NEXT: sb a1, 13(sp)
; LMULMAX8RV32-NEXT: lw a0, 0(a0)
; LMULMAX8RV32-NEXT: sb a0, 12(sp)
; LMULMAX8RV32-NEXT: addi a0, sp, 12
; LMULMAX8RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; LMULMAX8RV32-NEXT: vle8.v v8, (a0)
; LMULMAX8RV32-NEXT: vadd.vv v8, v8, v8
; LMULMAX8RV32-NEXT: vsra.vi v8, v8, 1
; LMULMAX8RV32-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; LMULMAX8RV32-NEXT: vsext.vf2 v9, v8
; LMULMAX8RV32-NEXT: vfwcvt.f.x.v v8, v9
; LMULMAX8RV32-NEXT: addi sp, sp, 16
; LMULMAX8RV32-NEXT: ret
;
; LMULMAX8RV64-LABEL: si2fp_v3i7_v3f32:
; LMULMAX8RV64: # %bb.0:
; LMULMAX8RV64-NEXT: addi sp, sp, -16
; LMULMAX8RV64-NEXT: .cfi_def_cfa_offset 16
; LMULMAX8RV64-NEXT: ld a1, 16(a0)
; LMULMAX8RV64-NEXT: sb a1, 14(sp)
; LMULMAX8RV64-NEXT: ld a1, 8(a0)
; LMULMAX8RV64-NEXT: sb a1, 13(sp)
; LMULMAX8RV64-NEXT: ld a0, 0(a0)
; LMULMAX8RV64-NEXT: sb a0, 12(sp)
; LMULMAX8RV64-NEXT: addi a0, sp, 12
; LMULMAX8RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; LMULMAX8RV64-NEXT: vle8.v v8, (a0)
; LMULMAX8RV64-NEXT: vadd.vv v8, v8, v8
; LMULMAX8RV64-NEXT: vsra.vi v8, v8, 1
; LMULMAX8RV64-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; LMULMAX8RV64-NEXT: vsext.vf2 v9, v8
; LMULMAX8RV64-NEXT: vfwcvt.f.x.v v8, v9
; LMULMAX8RV64-NEXT: addi sp, sp, 16
; LMULMAX8RV64-NEXT: ret
;
; LMULMAX1RV32-LABEL: si2fp_v3i7_v3f32:
; LMULMAX1RV32: # %bb.0:
; LMULMAX1RV32-NEXT: addi sp, sp, -16
; LMULMAX1RV32-NEXT: .cfi_def_cfa_offset 16
; LMULMAX1RV32-NEXT: lw a1, 8(a0)
; LMULMAX1RV32-NEXT: sb a1, 14(sp)
; LMULMAX1RV32-NEXT: lw a1, 4(a0)
; LMULMAX1RV32-NEXT: sb a1, 13(sp)
; LMULMAX1RV32-NEXT: lw a0, 0(a0)
; LMULMAX1RV32-NEXT: sb a0, 12(sp)
; LMULMAX1RV32-NEXT: addi a0, sp, 12
; LMULMAX1RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; LMULMAX1RV32-NEXT: vle8.v v8, (a0)
; LMULMAX1RV32-NEXT: vadd.vv v8, v8, v8
; LMULMAX1RV32-NEXT: vsra.vi v8, v8, 1
; LMULMAX1RV32-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; LMULMAX1RV32-NEXT: vsext.vf2 v9, v8
; LMULMAX1RV32-NEXT: vfwcvt.f.x.v v8, v9
; LMULMAX1RV32-NEXT: addi sp, sp, 16
; LMULMAX1RV32-NEXT: ret
;
; LMULMAX1RV64-LABEL: si2fp_v3i7_v3f32:
; LMULMAX1RV64: # %bb.0:
; LMULMAX1RV64-NEXT: addi sp, sp, -16
; LMULMAX1RV64-NEXT: .cfi_def_cfa_offset 16
; LMULMAX1RV64-NEXT: ld a1, 16(a0)
; LMULMAX1RV64-NEXT: sb a1, 14(sp)
; LMULMAX1RV64-NEXT: ld a1, 8(a0)
; LMULMAX1RV64-NEXT: sb a1, 13(sp)
; LMULMAX1RV64-NEXT: ld a0, 0(a0)
; LMULMAX1RV64-NEXT: sb a0, 12(sp)
; LMULMAX1RV64-NEXT: addi a0, sp, 12
; LMULMAX1RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; LMULMAX1RV64-NEXT: vle8.v v8, (a0)
; LMULMAX1RV64-NEXT: vadd.vv v8, v8, v8
; LMULMAX1RV64-NEXT: vsra.vi v8, v8, 1
; LMULMAX1RV64-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; LMULMAX1RV64-NEXT: vsext.vf2 v9, v8
; LMULMAX1RV64-NEXT: vfwcvt.f.x.v v8, v9
; LMULMAX1RV64-NEXT: addi sp, sp, 16
; LMULMAX1RV64-NEXT: ret
%z = sitofp <3 x i7> %x to <3 x float>
ret <3 x float> %z
}

; FIXME: This gets expanded instead of widened + promoted
define <3 x float> @ui2fp_v3i7_v3f32(<3 x i7> %x) {
; LMULMAX8RV32-LABEL: ui2fp_v3i7_v3f32:
; LMULMAX8RV32: # %bb.0:
; LMULMAX8RV32-NEXT: addi sp, sp, -16
; LMULMAX8RV32-NEXT: .cfi_def_cfa_offset 16
; LMULMAX8RV32-NEXT: lw a1, 8(a0)
; LMULMAX8RV32-NEXT: sb a1, 14(sp)
; LMULMAX8RV32-NEXT: lw a1, 4(a0)
; LMULMAX8RV32-NEXT: sb a1, 13(sp)
; LMULMAX8RV32-NEXT: lw a0, 0(a0)
; LMULMAX8RV32-NEXT: sb a0, 12(sp)
; LMULMAX8RV32-NEXT: addi a0, sp, 12
; LMULMAX8RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; LMULMAX8RV32-NEXT: vle8.v v8, (a0)
; LMULMAX8RV32-NEXT: li a0, 127
; LMULMAX8RV32-NEXT: vand.vx v8, v8, a0
; LMULMAX8RV32-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; LMULMAX8RV32-NEXT: vzext.vf2 v9, v8
; LMULMAX8RV32-NEXT: vfwcvt.f.xu.v v8, v9
; LMULMAX8RV32-NEXT: addi sp, sp, 16
; LMULMAX8RV32-NEXT: ret
;
; LMULMAX8RV64-LABEL: ui2fp_v3i7_v3f32:
; LMULMAX8RV64: # %bb.0:
; LMULMAX8RV64-NEXT: addi sp, sp, -16
; LMULMAX8RV64-NEXT: .cfi_def_cfa_offset 16
; LMULMAX8RV64-NEXT: ld a1, 16(a0)
; LMULMAX8RV64-NEXT: sb a1, 14(sp)
; LMULMAX8RV64-NEXT: ld a1, 8(a0)
; LMULMAX8RV64-NEXT: sb a1, 13(sp)
; LMULMAX8RV64-NEXT: ld a0, 0(a0)
; LMULMAX8RV64-NEXT: sb a0, 12(sp)
; LMULMAX8RV64-NEXT: addi a0, sp, 12
; LMULMAX8RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; LMULMAX8RV64-NEXT: vle8.v v8, (a0)
; LMULMAX8RV64-NEXT: li a0, 127
; LMULMAX8RV64-NEXT: vand.vx v8, v8, a0
; LMULMAX8RV64-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; LMULMAX8RV64-NEXT: vzext.vf2 v9, v8
; LMULMAX8RV64-NEXT: vfwcvt.f.xu.v v8, v9
; LMULMAX8RV64-NEXT: addi sp, sp, 16
; LMULMAX8RV64-NEXT: ret
;
; LMULMAX1RV32-LABEL: ui2fp_v3i7_v3f32:
; LMULMAX1RV32: # %bb.0:
; LMULMAX1RV32-NEXT: addi sp, sp, -16
; LMULMAX1RV32-NEXT: .cfi_def_cfa_offset 16
; LMULMAX1RV32-NEXT: lw a1, 8(a0)
; LMULMAX1RV32-NEXT: sb a1, 14(sp)
; LMULMAX1RV32-NEXT: lw a1, 4(a0)
; LMULMAX1RV32-NEXT: sb a1, 13(sp)
; LMULMAX1RV32-NEXT: lw a0, 0(a0)
; LMULMAX1RV32-NEXT: sb a0, 12(sp)
; LMULMAX1RV32-NEXT: addi a0, sp, 12
; LMULMAX1RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; LMULMAX1RV32-NEXT: vle8.v v8, (a0)
; LMULMAX1RV32-NEXT: li a0, 127
; LMULMAX1RV32-NEXT: vand.vx v8, v8, a0
; LMULMAX1RV32-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; LMULMAX1RV32-NEXT: vzext.vf2 v9, v8
; LMULMAX1RV32-NEXT: vfwcvt.f.xu.v v8, v9
; LMULMAX1RV32-NEXT: addi sp, sp, 16
; LMULMAX1RV32-NEXT: ret
;
; LMULMAX1RV64-LABEL: ui2fp_v3i7_v3f32:
; LMULMAX1RV64: # %bb.0:
; LMULMAX1RV64-NEXT: addi sp, sp, -16
; LMULMAX1RV64-NEXT: .cfi_def_cfa_offset 16
; LMULMAX1RV64-NEXT: ld a1, 16(a0)
; LMULMAX1RV64-NEXT: sb a1, 14(sp)
; LMULMAX1RV64-NEXT: ld a1, 8(a0)
; LMULMAX1RV64-NEXT: sb a1, 13(sp)
; LMULMAX1RV64-NEXT: ld a0, 0(a0)
; LMULMAX1RV64-NEXT: sb a0, 12(sp)
; LMULMAX1RV64-NEXT: addi a0, sp, 12
; LMULMAX1RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; LMULMAX1RV64-NEXT: vle8.v v8, (a0)
; LMULMAX1RV64-NEXT: li a0, 127
; LMULMAX1RV64-NEXT: vand.vx v8, v8, a0
; LMULMAX1RV64-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; LMULMAX1RV64-NEXT: vzext.vf2 v9, v8
; LMULMAX1RV64-NEXT: vfwcvt.f.xu.v v8, v9
; LMULMAX1RV64-NEXT: addi sp, sp, 16
; LMULMAX1RV64-NEXT: ret
%z = uitofp <3 x i7> %x to <3 x float>
ret <3 x float> %z
}

define <3 x float> @ui2fp_v3i1_v3f32(<3 x i1> %x) {
; CHECK-LABEL: ui2fp_v3i1_v3f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v9, v8, 1, v0
; CHECK-NEXT: vfwcvt.f.xu.v v8, v9
; CHECK-NEXT: ret
%z = uitofp <3 x i1> %x to <3 x float>
ret <3 x float> %z
}

define void @si2fp_v8i32_v8f32(ptr %x, ptr %y) {
; LMULMAX8-LABEL: si2fp_v8i32_v8f32:
; LMULMAX8: # %bb.0:
Expand Down
1,273 changes: 1,197 additions & 76 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
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519 changes: 517 additions & 2 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
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