70 changes: 70 additions & 0 deletions llvm/lib/Target/SystemZ/SystemZInstrVector.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -938,6 +938,7 @@ let Predicates = [FeatureVector] in {
let Predicates = [FeatureVectorEnhancements1] in {
def VFASB : BinaryVRRc<"vfasb", 0xE7E3, fadd, v128sb, v128sb, 2, 0>;
def WFASB : BinaryVRRc<"wfasb", 0xE7E3, fadd, v32sb, v32sb, 2, 8>;
def WFAXB : BinaryVRRc<"wfaxb", 0xE7E3, fadd, v128xb, v128xb, 4, 8>;
}

// Convert from fixed 64-bit.
Expand Down Expand Up @@ -973,6 +974,7 @@ let Predicates = [FeatureVector] in {
let Predicates = [FeatureVectorEnhancements1] in {
def VFDSB : BinaryVRRc<"vfdsb", 0xE7E5, fdiv, v128sb, v128sb, 2, 0>;
def WFDSB : BinaryVRRc<"wfdsb", 0xE7E5, fdiv, v32sb, v32sb, 2, 8>;
def WFDXB : BinaryVRRc<"wfdxb", 0xE7E5, fdiv, v128xb, v128xb, 4, 8>;
}

// Load FP integer.
Expand All @@ -984,8 +986,10 @@ let Predicates = [FeatureVector] in {
let Predicates = [FeatureVectorEnhancements1] in {
def VFISB : TernaryVRRa<"vfisb", 0xE7C7, int_s390_vfisb, v128sb, v128sb, 2, 0>;
def WFISB : TernaryVRRa<"wfisb", 0xE7C7, null_frag, v32sb, v32sb, 2, 8>;
def WFIXB : TernaryVRRa<"wfixb", 0xE7C7, null_frag, v128xb, v128xb, 4, 8>;
defm : VectorRounding<VFISB, v128sb>;
defm : VectorRounding<WFISB, v32sb>;
defm : VectorRounding<WFIXB, v128xb>;
}

// Load lengthened.
Expand All @@ -998,6 +1002,9 @@ let Predicates = [FeatureVector] in {
def VFLLS : UnaryVRRa<"vflls", 0xE7C4, null_frag, v128db, v128sb, 2, 0>;
def WFLLS : UnaryVRRa<"wflls", 0xE7C4, null_frag, v64db, v32sb, 2, 8>;
}
def WFLLD : UnaryVRRa<"wflld", 0xE7C4, fpextend, v128xb, v64db, 3, 8>;
def : Pat<(f128 (fpextend (f32 VR32:$src))),
(WFLLD (WLDEB VR32:$src))>;
}

// Load rounded.
Expand All @@ -1012,6 +1019,10 @@ let Predicates = [FeatureVector] in {
def VFLRD : TernaryVRRa<"vflrd", 0xE7C5, null_frag, v128sb, v128db, 3, 0>;
def WFLRD : TernaryVRRa<"wflrd", 0xE7C5, null_frag, v32sb, v64db, 3, 8>;
}
def WFLRX : TernaryVRRa<"wflrx", 0xE7C5, null_frag, v64db, v128xb, 4, 8>;
def : FPConversion<WFLRX, fpround, v64db, v128xb, 0, 0>;
def : Pat<(f32 (fpround (f128 VR128:$src))),
(WLEDB (WFLRX VR128:$src, 0, 3), 0, 0)>;
}

// Maximum.
Expand All @@ -1029,10 +1040,13 @@ let Predicates = [FeatureVector] in {
v128sb, v128sb, 2, 0>;
def WFMAXSB : TernaryVRRcFloat<"wfmaxsb", 0xE7EF, null_frag,
v32sb, v32sb, 2, 8>;
def WFMAXXB : TernaryVRRcFloat<"wfmaxxb", 0xE7EF, null_frag,
v128xb, v128xb, 4, 8>;
defm : VectorMax<VFMAXDB, v128db>;
defm : VectorMax<WFMAXDB, v64db>;
defm : VectorMax<VFMAXSB, v128sb>;
defm : VectorMax<WFMAXSB, v32sb>;
defm : VectorMax<WFMAXXB, v128xb>;
}

// Minimum.
Expand All @@ -1050,10 +1064,13 @@ let Predicates = [FeatureVector] in {
v128sb, v128sb, 2, 0>;
def WFMINSB : TernaryVRRcFloat<"wfminsb", 0xE7EE, null_frag,
v32sb, v32sb, 2, 8>;
def WFMINXB : TernaryVRRcFloat<"wfminxb", 0xE7EE, null_frag,
v128xb, v128xb, 4, 8>;
defm : VectorMin<VFMINDB, v128db>;
defm : VectorMin<WFMINDB, v64db>;
defm : VectorMin<VFMINSB, v128sb>;
defm : VectorMin<WFMINSB, v32sb>;
defm : VectorMin<WFMINXB, v128xb>;
}

// Multiply.
Expand All @@ -1063,6 +1080,7 @@ let Predicates = [FeatureVector] in {
let Predicates = [FeatureVectorEnhancements1] in {
def VFMSB : BinaryVRRc<"vfmsb", 0xE7E7, fmul, v128sb, v128sb, 2, 0>;
def WFMSB : BinaryVRRc<"wfmsb", 0xE7E7, fmul, v32sb, v32sb, 2, 8>;
def WFMXB : BinaryVRRc<"wfmxb", 0xE7E7, fmul, v128xb, v128xb, 4, 8>;
}

// Multiply and add.
Expand All @@ -1072,6 +1090,7 @@ let Predicates = [FeatureVector] in {
let Predicates = [FeatureVectorEnhancements1] in {
def VFMASB : TernaryVRRe<"vfmasb", 0xE78F, fma, v128sb, v128sb, 0, 2>;
def WFMASB : TernaryVRRe<"wfmasb", 0xE78F, fma, v32sb, v32sb, 8, 2>;
def WFMAXB : TernaryVRRe<"wfmaxb", 0xE78F, fma, v128xb, v128xb, 8, 4>;
}

// Multiply and subtract.
Expand All @@ -1081,6 +1100,7 @@ let Predicates = [FeatureVector] in {
let Predicates = [FeatureVectorEnhancements1] in {
def VFMSSB : TernaryVRRe<"vfmssb", 0xE78E, fms, v128sb, v128sb, 0, 2>;
def WFMSSB : TernaryVRRe<"wfmssb", 0xE78E, fms, v32sb, v32sb, 8, 2>;
def WFMSXB : TernaryVRRe<"wfmsxb", 0xE78E, fms, v128xb, v128xb, 8, 4>;
}

// Negative multiply and add.
Expand All @@ -1090,6 +1110,7 @@ let Predicates = [FeatureVector] in {
def WFNMADB : TernaryVRRe<"wfnmadb", 0xE79F, fnma, v64db, v64db, 8, 3>;
def VFNMASB : TernaryVRRe<"vfnmasb", 0xE79F, fnma, v128sb, v128sb, 0, 2>;
def WFNMASB : TernaryVRRe<"wfnmasb", 0xE79F, fnma, v32sb, v32sb, 8, 2>;
def WFNMAXB : TernaryVRRe<"wfnmaxb", 0xE79F, fnma, v128xb, v128xb, 8, 4>;
}

// Negative multiply and subtract.
Expand All @@ -1099,6 +1120,7 @@ let Predicates = [FeatureVector] in {
def WFNMSDB : TernaryVRRe<"wfnmsdb", 0xE79E, fnms, v64db, v64db, 8, 3>;
def VFNMSSB : TernaryVRRe<"vfnmssb", 0xE79E, fnms, v128sb, v128sb, 0, 2>;
def WFNMSSB : TernaryVRRe<"wfnmssb", 0xE79E, fnms, v32sb, v32sb, 8, 2>;
def WFNMSXB : TernaryVRRe<"wfnmsxb", 0xE79E, fnms, v128xb, v128xb, 8, 4>;
}

// Perform sign operation.
Expand All @@ -1108,6 +1130,7 @@ let Predicates = [FeatureVector] in {
let Predicates = [FeatureVectorEnhancements1] in {
def VFPSOSB : BinaryVRRa<"vfpsosb", 0xE7CC, null_frag, v128sb, v128sb, 2, 0>;
def WFPSOSB : BinaryVRRa<"wfpsosb", 0xE7CC, null_frag, v32sb, v32sb, 2, 8>;
def WFPSOXB : BinaryVRRa<"wfpsoxb", 0xE7CC, null_frag, v128xb, v128xb, 4, 8>;
}

// Load complement.
Expand All @@ -1116,6 +1139,7 @@ let Predicates = [FeatureVector] in {
let Predicates = [FeatureVectorEnhancements1] in {
def VFLCSB : UnaryVRRa<"vflcsb", 0xE7CC, fneg, v128sb, v128sb, 2, 0, 0>;
def WFLCSB : UnaryVRRa<"wflcsb", 0xE7CC, fneg, v32sb, v32sb, 2, 8, 0>;
def WFLCXB : UnaryVRRa<"wflcxb", 0xE7CC, fneg, v128xb, v128xb, 4, 8, 0>;
}

// Load negative.
Expand All @@ -1124,6 +1148,7 @@ let Predicates = [FeatureVector] in {
let Predicates = [FeatureVectorEnhancements1] in {
def VFLNSB : UnaryVRRa<"vflnsb", 0xE7CC, fnabs, v128sb, v128sb, 2, 0, 1>;
def WFLNSB : UnaryVRRa<"wflnsb", 0xE7CC, fnabs, v32sb, v32sb, 2, 8, 1>;
def WFLNXB : UnaryVRRa<"wflnxb", 0xE7CC, fnabs, v128xb, v128xb, 4, 8, 1>;
}

// Load positive.
Expand All @@ -1132,6 +1157,7 @@ let Predicates = [FeatureVector] in {
let Predicates = [FeatureVectorEnhancements1] in {
def VFLPSB : UnaryVRRa<"vflpsb", 0xE7CC, fabs, v128sb, v128sb, 2, 0, 2>;
def WFLPSB : UnaryVRRa<"wflpsb", 0xE7CC, fabs, v32sb, v32sb, 2, 8, 2>;
def WFLPXB : UnaryVRRa<"wflpxb", 0xE7CC, fabs, v128xb, v128xb, 4, 8, 2>;
}

// Square root.
Expand All @@ -1141,6 +1167,7 @@ let Predicates = [FeatureVector] in {
let Predicates = [FeatureVectorEnhancements1] in {
def VFSQSB : UnaryVRRa<"vfsqsb", 0xE7CE, fsqrt, v128sb, v128sb, 2, 0>;
def WFSQSB : UnaryVRRa<"wfsqsb", 0xE7CE, fsqrt, v32sb, v32sb, 2, 8>;
def WFSQXB : UnaryVRRa<"wfsqxb", 0xE7CE, fsqrt, v128xb, v128xb, 4, 8>;
}

// Subtract.
Expand All @@ -1150,6 +1177,7 @@ let Predicates = [FeatureVector] in {
let Predicates = [FeatureVectorEnhancements1] in {
def VFSSB : BinaryVRRc<"vfssb", 0xE7E2, fsub, v128sb, v128sb, 2, 0>;
def WFSSB : BinaryVRRc<"wfssb", 0xE7E2, fsub, v32sb, v32sb, 2, 8>;
def WFSXB : BinaryVRRc<"wfsxb", 0xE7E2, fsub, v128xb, v128xb, 4, 8>;
}

// Test data class immediate.
Expand All @@ -1160,6 +1188,7 @@ let Predicates = [FeatureVector] in {
let Predicates = [FeatureVectorEnhancements1] in {
def VFTCISB : BinaryVRIe<"vftcisb", 0xE74A, z_vftci, v128f, v128sb, 2, 0>;
def WFTCISB : BinaryVRIe<"wftcisb", 0xE74A, null_frag, v32f, v32sb, 2, 8>;
def WFTCIXB : BinaryVRIe<"wftcixb", 0xE74A, null_frag, v128q, v128xb, 4, 8>;
}
}
}
Expand All @@ -1175,6 +1204,7 @@ let Predicates = [FeatureVector] in {
def WFCDB : CompareVRRa<"wfcdb", 0xE7CB, z_fcmp, v64db, 3>;
let Predicates = [FeatureVectorEnhancements1] in {
def WFCSB : CompareVRRa<"wfcsb", 0xE7CB, z_fcmp, v32sb, 2>;
def WFCXB : CompareVRRa<"wfcxb", 0xE7CB, z_fcmp, v128xb, 4>;
}
}

Expand All @@ -1184,6 +1214,7 @@ let Predicates = [FeatureVector] in {
def WFKDB : CompareVRRa<"wfkdb", 0xE7CA, null_frag, v64db, 3>;
let Predicates = [FeatureVectorEnhancements1] in {
def WFKSB : CompareVRRa<"wfksb", 0xE7CA, null_frag, v32sb, 2>;
def WFKXB : CompareVRRa<"wfkxb", 0xE7CA, null_frag, v128xb, 4>;
}
}

Expand All @@ -1198,6 +1229,8 @@ let Predicates = [FeatureVector] in {
v128f, v128sb, 2, 0>;
defm WFCESB : BinaryVRRcSPair<"wfcesb", 0xE7E8, null_frag, null_frag,
v32f, v32sb, 2, 8>;
defm WFCEXB : BinaryVRRcSPair<"wfcexb", 0xE7E8, null_frag, null_frag,
v128q, v128xb, 4, 8>;
}

// Compare and signal equal.
Expand All @@ -1210,6 +1243,8 @@ let Predicates = [FeatureVector] in {
v128f, v128sb, 2, 4>;
defm WFKESB : BinaryVRRcSPair<"wfkesb", 0xE7E8, null_frag, null_frag,
v32f, v32sb, 2, 12>;
defm WFKEXB : BinaryVRRcSPair<"wfkexb", 0xE7E8, null_frag, null_frag,
v128q, v128xb, 4, 12>;
}

// Compare high.
Expand All @@ -1223,6 +1258,8 @@ let Predicates = [FeatureVector] in {
v128f, v128sb, 2, 0>;
defm WFCHSB : BinaryVRRcSPair<"wfchsb", 0xE7EB, null_frag, null_frag,
v32f, v32sb, 2, 8>;
defm WFCHXB : BinaryVRRcSPair<"wfchxb", 0xE7EB, null_frag, null_frag,
v128q, v128xb, 4, 8>;
}

// Compare and signal high.
Expand All @@ -1235,6 +1272,8 @@ let Predicates = [FeatureVector] in {
v128f, v128sb, 2, 4>;
defm WFKHSB : BinaryVRRcSPair<"wfkhsb", 0xE7EB, null_frag, null_frag,
v32f, v32sb, 2, 12>;
defm WFKHXB : BinaryVRRcSPair<"wfkhxb", 0xE7EB, null_frag, null_frag,
v128q, v128xb, 4, 12>;
}

// Compare high or equal.
Expand All @@ -1248,6 +1287,8 @@ let Predicates = [FeatureVector] in {
v128f, v128sb, 2, 0>;
defm WFCHESB : BinaryVRRcSPair<"wfchesb", 0xE7EA, null_frag, null_frag,
v32f, v32sb, 2, 8>;
defm WFCHEXB : BinaryVRRcSPair<"wfchexb", 0xE7EA, null_frag, null_frag,
v128q, v128xb, 4, 8>;
}

// Compare and signal high or equal.
Expand All @@ -1260,6 +1301,8 @@ let Predicates = [FeatureVector] in {
v128f, v128sb, 2, 4>;
defm WFKHESB : BinaryVRRcSPair<"wfkhesb", 0xE7EA, null_frag, null_frag,
v32f, v32sb, 2, 12>;
defm WFKHEXB : BinaryVRRcSPair<"wfkhexb", 0xE7EA, null_frag, null_frag,
v128q, v128xb, 4, 12>;
}
}

Expand All @@ -1272,36 +1315,49 @@ def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
def : Pat<(v16i8 (bitconvert (f128 VR128:$src))), (v16i8 VR128:$src)>;

def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
def : Pat<(v8i16 (bitconvert (f128 VR128:$src))), (v8i16 VR128:$src)>;

def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
def : Pat<(v4i32 (bitconvert (f128 VR128:$src))), (v4i32 VR128:$src)>;

def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
def : Pat<(v2i64 (bitconvert (f128 VR128:$src))), (v2i64 VR128:$src)>;

def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
def : Pat<(v4f32 (bitconvert (f128 VR128:$src))), (v4f32 VR128:$src)>;

def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
def : Pat<(v2f64 (bitconvert (f128 VR128:$src))), (v2f64 VR128:$src)>;

def : Pat<(f128 (bitconvert (v16i8 VR128:$src))), (f128 VR128:$src)>;
def : Pat<(f128 (bitconvert (v8i16 VR128:$src))), (f128 VR128:$src)>;
def : Pat<(f128 (bitconvert (v4i32 VR128:$src))), (f128 VR128:$src)>;
def : Pat<(f128 (bitconvert (v2i64 VR128:$src))), (f128 VR128:$src)>;
def : Pat<(f128 (bitconvert (v4f32 VR128:$src))), (f128 VR128:$src)>;
def : Pat<(f128 (bitconvert (v2f64 VR128:$src))), (f128 VR128:$src)>;

//===----------------------------------------------------------------------===//
// Replicating scalars
Expand Down Expand Up @@ -1377,6 +1433,20 @@ let AddedComplexity = 4 in {
(EXTRACT_SUBREG (VREPG VR128:$vec, imm32zx1:$index), subreg_r64)>;
}

//===----------------------------------------------------------------------===//
// Support for 128-bit floating-point values in vector registers
//===----------------------------------------------------------------------===//

let Predicates = [FeatureVectorEnhancements1] in {
def : Pat<(f128 (load bdxaddr12only:$addr)),
(VL bdxaddr12only:$addr)>;
def : Pat<(store (f128 VR128:$src), bdxaddr12only:$addr),
(VST VR128:$src, bdxaddr12only:$addr)>;

def : Pat<(f128 fpimm0), (VZERO)>;
def : Pat<(f128 fpimmneg0), (WFLNXB (VZERO))>;
}

//===----------------------------------------------------------------------===//
// String instructions
//===----------------------------------------------------------------------===//
Expand Down
9 changes: 5 additions & 4 deletions llvm/lib/Target/SystemZ/SystemZRegisterInfo.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -260,10 +260,10 @@ defm VF128 : SystemZRegClass<"VF128",

// All vector registers.
defm VR128 : SystemZRegClass<"VR128",
[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 128,
(add (sequence "V%u", 0, 7),
(sequence "V%u", 16, 31),
(sequence "V%u", 8, 15))>;
[f128, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
128, (add (sequence "V%u", 0, 7),
(sequence "V%u", 16, 31),
(sequence "V%u", 8, 15))>;

// Attaches a ValueType to a register operand, to make the instruction
// definitions easier.
Expand All @@ -283,6 +283,7 @@ def v128g : TypedReg<v2i64, VR128>;
def v128q : TypedReg<v16i8, VR128>;
def v128sb : TypedReg<v4f32, VR128>;
def v128db : TypedReg<v2f64, VR128>;
def v128xb : TypedReg<f128, VR128>;
def v128any : TypedReg<untyped, VR128>;

//===----------------------------------------------------------------------===//
Expand Down
17 changes: 16 additions & 1 deletion llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -753,7 +753,7 @@ def : InstRW<[], (instregex "Insn.*")>;
// FP: Select instructions
//===----------------------------------------------------------------------===//

def : InstRW<[FXa], (instregex "SelectF(32|64|128)$")>;
def : InstRW<[FXa], (instregex "Select(F32|F64|F128|VR128)$")>;
def : InstRW<[FXa], (instregex "CondStoreF32(Inv)?$")>;
def : InstRW<[FXa], (instregex "CondStoreF64(Inv)?$")>;

Expand Down Expand Up @@ -1319,57 +1319,69 @@ def : InstRW<[VecBF], (instregex "WL(DE|ED)B$")>;
def : InstRW<[VecBF], (instregex "VFL(L|R)$")>;
def : InstRW<[VecBF], (instregex "VFL(LS|RD)$")>;
def : InstRW<[VecBF], (instregex "WFL(LS|RD)$")>;
def : InstRW<[VecBF2], (instregex "WFLLD$")>;
def : InstRW<[VecDF2, Lat10], (instregex "WFLRX$")>;
def : InstRW<[VecBF2], (instregex "VFI$")>;
def : InstRW<[VecBF], (instregex "VFIDB$")>;
def : InstRW<[VecBF], (instregex "WFIDB$")>;
def : InstRW<[VecBF2], (instregex "VFISB$")>;
def : InstRW<[VecBF], (instregex "WFISB$")>;
def : InstRW<[VecDF2, Lat10], (instregex "WFIXB$")>;

// Sign operations
def : InstRW<[VecXsPm], (instregex "VFPSO$")>;
def : InstRW<[VecXsPm], (instregex "(V|W)FPSODB$")>;
def : InstRW<[VecXsPm], (instregex "(V|W)FPSOSB$")>;
def : InstRW<[VecXsPm], (instregex "WFPSOXB$")>;
def : InstRW<[VecXsPm], (instregex "(V|W)FL(C|N|P)DB$")>;
def : InstRW<[VecXsPm], (instregex "(V|W)FL(C|N|P)SB$")>;
def : InstRW<[VecXsPm], (instregex "WFL(C|N|P)XB$")>;

// Minimum / maximum
def : InstRW<[VecXsPm], (instregex "VF(MAX|MIN)$")>;
def : InstRW<[VecXsPm], (instregex "VF(MAX|MIN)DB$")>;
def : InstRW<[VecXsPm], (instregex "WF(MAX|MIN)DB$")>;
def : InstRW<[VecXsPm], (instregex "VF(MAX|MIN)SB$")>;
def : InstRW<[VecXsPm], (instregex "WF(MAX|MIN)SB$")>;
def : InstRW<[VecDFX], (instregex "WF(MAX|MIN)XB$")>;

// Test data class
def : InstRW<[VecXsPm, Lat4], (instregex "VFTCI$")>;
def : InstRW<[VecXsPm, Lat4], (instregex "(V|W)FTCIDB$")>;
def : InstRW<[VecXsPm, Lat4], (instregex "(V|W)FTCISB$")>;
def : InstRW<[VecDFX, Lat4], (instregex "WFTCIXB$")>;

// Add / subtract
def : InstRW<[VecBF2], (instregex "VF(A|S)$")>;
def : InstRW<[VecBF], (instregex "VF(A|S)DB$")>;
def : InstRW<[VecBF], (instregex "WF(A|S)DB$")>;
def : InstRW<[VecBF2], (instregex "VF(A|S)SB$")>;
def : InstRW<[VecBF], (instregex "WF(A|S)SB$")>;
def : InstRW<[VecDF2, Lat10], (instregex "WF(A|S)XB$")>;

// Multiply / multiply-and-add/subtract
def : InstRW<[VecBF2], (instregex "VFM$")>;
def : InstRW<[VecBF], (instregex "VFMDB$")>;
def : InstRW<[VecBF], (instregex "WFMDB$")>;
def : InstRW<[VecBF2], (instregex "VFMSB$")>;
def : InstRW<[VecBF], (instregex "WFMSB$")>;
def : InstRW<[VecDF2, Lat20], (instregex "WFMXB$")>;
def : InstRW<[VecBF2], (instregex "VF(N)?M(A|S)$")>;
def : InstRW<[VecBF], (instregex "VF(N)?M(A|S)DB$")>;
def : InstRW<[VecBF], (instregex "WF(N)?M(A|S)DB$")>;
def : InstRW<[VecBF2], (instregex "VF(N)?M(A|S)SB$")>;
def : InstRW<[VecBF], (instregex "WF(N)?M(A|S)SB$")>;
def : InstRW<[VecDF2, Lat20], (instregex "WF(N)?M(A|S)XB$")>;

// Divide / square root
def : InstRW<[VecFPd], (instregex "VFD$")>;
def : InstRW<[VecFPd], (instregex "(V|W)FDDB$")>;
def : InstRW<[VecFPd], (instregex "(V|W)FDSB$")>;
def : InstRW<[VecFPd], (instregex "WFDXB$")>;
def : InstRW<[VecFPd], (instregex "VFSQ$")>;
def : InstRW<[VecFPd], (instregex "(V|W)FSQDB$")>;
def : InstRW<[VecFPd], (instregex "(V|W)FSQSB$")>;
def : InstRW<[VecFPd], (instregex "WFSQXB$")>;

//===----------------------------------------------------------------------===//
// Vector: Floating-point comparison
Expand All @@ -1380,13 +1392,16 @@ def : InstRW<[VecXsPm], (instregex "VF(C|K)(E|H|HE)DB$")>;
def : InstRW<[VecXsPm], (instregex "WF(C|K)(E|H|HE)DB$")>;
def : InstRW<[VecXsPm], (instregex "VF(C|K)(E|H|HE)SB$")>;
def : InstRW<[VecXsPm], (instregex "WF(C|K)(E|H|HE)SB$")>;
def : InstRW<[VecDFX], (instregex "WF(C|K)(E|H|HE)XB$")>;
def : InstRW<[VecXsPm, Lat4], (instregex "VF(C|K)(E|H|HE)DBS$")>;
def : InstRW<[VecXsPm, Lat4], (instregex "WF(C|K)(E|H|HE)DBS$")>;
def : InstRW<[VecXsPm, Lat4], (instregex "VF(C|K)(E|H|HE)SBS$")>;
def : InstRW<[VecXsPm, Lat4], (instregex "WF(C|K)(E|H|HE)SBS$")>;
def : InstRW<[VecDFX, Lat4], (instregex "WF(C|K)(E|H|HE)XBS$")>;
def : InstRW<[VecXsPm, Lat4], (instregex "WF(C|K)$")>;
def : InstRW<[VecXsPm, Lat4], (instregex "WF(C|K)DB$")>;
def : InstRW<[VecXsPm, Lat4], (instregex "WF(C|K)SB$")>;
def : InstRW<[VecDFX, Lat4], (instregex "WF(C|K)XB$")>;

//===----------------------------------------------------------------------===//
// Vector: Floating-point insertion and extraction
Expand Down
7 changes: 5 additions & 2 deletions llvm/test/CodeGen/SystemZ/fp-abs-03.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -28,8 +28,11 @@ define double @f2(double %f) {
declare fp128 @llvm.fabs.f128(fp128 %f)
define void @f3(fp128 *%ptr, fp128 *%ptr2) {
; CHECK-LABEL: f3:
; CHECK: lpxbr
; CHECK: dxbr
; CHECK-DAG: vl [[REG1:%v[0-9]+]], 0(%r2)
; CHECK-DAG: vl [[REG2:%v[0-9]+]], 0(%r3)
; CHECK-DAG: wflpxb [[POSREG1:%v[0-9]+]], [[REG1]]
; CHECK: wfdxb [[RES:%v[0-9]+]], [[POSREG1]], [[REG2]]
; CHECK: vst [[RES]], 0(%r2)
; CHECK: br %r14
%orig = load fp128 , fp128 *%ptr
%abs = call fp128 @llvm.fabs.f128(fp128 %orig)
Expand Down
7 changes: 5 additions & 2 deletions llvm/test/CodeGen/SystemZ/fp-abs-04.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -30,8 +30,11 @@ define double @f2(double %f) {
declare fp128 @llvm.fabs.f128(fp128 %f)
define void @f3(fp128 *%ptr, fp128 *%ptr2) {
; CHECK-LABEL: f3:
; CHECK: lnxbr
; CHECK: dxbr
; CHECK-DAG: vl [[REG1:%v[0-9]+]], 0(%r2)
; CHECK-DAG: vl [[REG2:%v[0-9]+]], 0(%r3)
; CHECK-DAG: wflnxb [[NEGREG1:%v[0-9]+]], [[REG1]]
; CHECK: wfdxb [[RES:%v[0-9]+]], [[NEGREG1]], [[REG2]]
; CHECK: vst [[RES]], 0(%r2)
; CHECK: br %r14
%orig = load fp128 , fp128 *%ptr
%abs = call fp128 @llvm.fabs.f128(fp128 %orig)
Expand Down
17 changes: 17 additions & 0 deletions llvm/test/CodeGen/SystemZ/fp-add-04.ll
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Original file line number Diff line number Diff line change
@@ -0,0 +1,17 @@
; Test 128-bit floating-point addition on z14.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s

define void @f1(fp128 *%ptr1, fp128 *%ptr2) {
; CHECK-LABEL: f1:
; CHECK-DAG: vl [[REG1:%v[0-9]+]], 0(%r2)
; CHECK-DAG: vl [[REG2:%v[0-9]+]], 0(%r3)
; CHECK: wfaxb [[RES:%v[0-9]+]], [[REG1]], [[REG2]]
; CHECK: vst [[RES]], 0(%r2)
; CHECK: br %r14
%f1 = load fp128, fp128 *%ptr1
%f2 = load fp128, fp128 *%ptr2
%sum = fadd fp128 %f1, %f2
store fp128 %sum, fp128 *%ptr1
ret void
}
33 changes: 33 additions & 0 deletions llvm/test/CodeGen/SystemZ/fp-cmp-06.ll
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Original file line number Diff line number Diff line change
@@ -0,0 +1,33 @@
; Test f128 comparisons on z14.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s

; There is no memory form of 128-bit comparison.
define i64 @f1(i64 %a, i64 %b, fp128 *%ptr1, fp128 *%ptr2) {
; CHECK-LABEL: f1:
; CHECK-DAG: vl [[REG1:%v[0-9]+]], 0(%r4)
; CHECK-DAG: vl [[REG2:%v[0-9]+]], 0(%r5)
; CHECK: wfcxb [[REG1]], [[REG2]]
; CHECK-NEXT: locgrne %r2, %r3
; CHECK: br %r14
%f1 = load fp128, fp128 *%ptr1
%f2 = load fp128, fp128 *%ptr2
%cond = fcmp oeq fp128 %f1, %f2
%res = select i1 %cond, i64 %a, i64 %b
ret i64 %res
}

; Check comparison with zero -- it is not worthwhile to copy to
; FP pairs just so we can use LTXBR, so simply load up a zero.
define i64 @f2(i64 %a, i64 %b, fp128 *%ptr) {
; CHECK-LABEL: f2:
; CHECK-DAG: vl [[REG1:%v[0-9]+]], 0(%r4)
; CHECK-DAG: vzero [[REG2:%v[0-9]+]]
; CHECK: wfcxb [[REG1]], [[REG2]]
; CHECK-NEXT: locgrne %r2, %r3
; CHECK: br %r14
%f = load fp128, fp128 *%ptr
%cond = fcmp oeq fp128 %f, 0xL00000000000000000000000000000000
%res = select i1 %cond, i64 %a, i64 %b
ret i64 %res
}
40 changes: 40 additions & 0 deletions llvm/test/CodeGen/SystemZ/fp-const-11.ll
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Original file line number Diff line number Diff line change
@@ -0,0 +1,40 @@
; Test loads of f128 floating-point constants on z14.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s -check-prefix=CONST

; Test loading zero.
define void @f1(fp128 *%x) {
; CHECK-LABEL: f1:
; CHECK: vzero [[REG:%v[0-9]+]]
; CHECK: vst [[REG]], 0(%r2)
; CHECK: br %r14
store fp128 0xL00000000000000000000000000000000, fp128 *%x
ret void
}

; Test loading of negative floating-point zero.
define void @f2(fp128 *%x) {
; CHECK-LABEL: f2:
; CHECK: vzero [[REG:%v[0-9]+]]
; CHECK: wflnxb [[REG]], [[REG]]
; CHECK: vst [[REG]], 0(%r2)
; CHECK: br %r14
store fp128 0xL00000000000000008000000000000000, fp128 *%x
ret void
}

; Test loading of a 128-bit floating-point constant. This value would
; actually fit within the 32-bit format, but we don't have extending
; loads into vector registers.
define void @f3(fp128 *%x) {
; CHECK-LABEL: f3:
; CHECK: larl [[REGISTER:%r[1-5]+]], {{.*}}
; CHECK: vl [[REG:%v[0-9]+]], 0([[REGISTER]])
; CHECK: vst [[REG]], 0(%r2)
; CHECK: br %r14
; CONST: .quad 4611404543484231680
; CONST: .quad 0
store fp128 0xL00000000000000003fff000002000000, fp128 *%x
ret void
}
50 changes: 50 additions & 0 deletions llvm/test/CodeGen/SystemZ/fp-conv-15.ll
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Original file line number Diff line number Diff line change
@@ -0,0 +1,50 @@
; Test f128 floating-point truncations/extensions on z14.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s

; Test f128->f64.
define double @f1(fp128 *%ptr) {
; CHECK-LABEL: f1:
; CHECK: vl [[REG:%v[0-9]+]], 0(%r2)
; CHECK: wflrx %f0, [[REG]], 0, 0
; CHECK: br %r14
%val = load fp128, fp128 *%ptr
%res = fptrunc fp128 %val to double
ret double %res
}

; Test f128->f32.
define float @f2(fp128 *%ptr) {
; CHECK-LABEL: f2:
; CHECK: vl [[REG:%v[0-9]+]], 0(%r2)
; CHECK: wflrx %f0, [[REG]], 0, 3
; CHECK: ledbra %f0, 0, %f0, 0
; CHECK: br %r14
%val = load fp128, fp128 *%ptr
%res = fptrunc fp128 %val to float
ret float %res
}

; Test f64->f128.
define void @f3(fp128 *%dst, double %val) {
; CHECK-LABEL: f3:
; CHECK: wflld [[RES:%v[0-9]+]], %f0
; CHECK: vst [[RES]], 0(%r2)
; CHECK: br %r14
%res = fpext double %val to fp128
store fp128 %res, fp128 *%dst
ret void
}

; Test f32->f128.
define void @f4(fp128 *%dst, float %val) {
; CHECK-LABEL: f4:
; CHECK: ldebr %f0, %f0
; CHECK: wflld [[RES:%v[0-9]+]], %f0
; CHECK: vst [[RES]], 0(%r2)
; CHECK: br %r14
%res = fpext float %val to fp128
store fp128 %res, fp128 *%dst
ret void
}

99 changes: 99 additions & 0 deletions llvm/test/CodeGen/SystemZ/fp-conv-16.ll
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Original file line number Diff line number Diff line change
@@ -0,0 +1,99 @@
; Test f128 floating-point conversion to/from integers on z14.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s

; Test signed i32->f128.
define void @f1(i32 %i, fp128 *%dst) {
; CHECK-LABEL: f1:
; CHECK: cxfbr %f0, %r2
; CHECK: vmrhg %v0, %v0, %v2
; CHECK: vst %v0, 0(%r3)
; CHECK: br %r14
%conv = sitofp i32 %i to fp128
store fp128 %conv, fp128 *%dst
ret void
}

; Test signed i64->f128.
define void @f2(i64 %i, fp128 *%dst) {
; CHECK-LABEL: f2:
; CHECK: cxgbr %f0, %r2
; CHECK: vmrhg %v0, %v0, %v2
; CHECK: vst %v0, 0(%r3)
; CHECK: br %r14
%conv = sitofp i64 %i to fp128
store fp128 %conv, fp128 *%dst
ret void
}

; Test unsigned i32->f128.
define void @f3(i32 %i, fp128 *%dst) {
; CHECK-LABEL: f3:
; CHECK: cxlfbr %f0, 0, %r2, 0
; CHECK: vmrhg %v0, %v0, %v2
; CHECK: vst %v0, 0(%r3)
; CHECK: br %r14
%conv = uitofp i32 %i to fp128
store fp128 %conv, fp128 *%dst
ret void
}

; Test unsigned i64->f128.
define void @f4(i64 %i, fp128 *%dst) {
; CHECK-LABEL: f4:
; CHECK: cxlgbr %f0, 0, %r2, 0
; CHECK: vmrhg %v0, %v0, %v2
; CHECK: vst %v0, 0(%r3)
; CHECK: br %r14
%conv = uitofp i64 %i to fp128
store fp128 %conv, fp128 *%dst
ret void
}

; Test signed f128->i32.
define i32 @f5(fp128 *%src) {
; CHECK-LABEL: f5:
; CHECK: vl %v0, 0(%r2)
; CHECK: vrepg %v2, %v0, 1
; CHECK: cfxbr %r2, 5, %f0
; CHECK: br %r14
%f = load fp128, fp128 *%src
%conv = fptosi fp128 %f to i32
ret i32 %conv
}

; Test signed f128->i64.
define i64 @f6(fp128 *%src) {
; CHECK-LABEL: f6:
; CHECK: vl %v0, 0(%r2)
; CHECK: vrepg %v2, %v0, 1
; CHECK: cgxbr %r2, 5, %f0
; CHECK: br %r14
%f = load fp128, fp128 *%src
%conv = fptosi fp128 %f to i64
ret i64 %conv
}

; Test unsigned f128->i32.
define i32 @f7(fp128 *%src) {
; CHECK-LABEL: f7:
; CHECK: vl %v0, 0(%r2)
; CHECK: vrepg %v2, %v0, 1
; CHECK: clfxbr %r2, 5, %f0, 0
; CHECK: br %r14
%f = load fp128 , fp128 *%src
%conv = fptoui fp128 %f to i32
ret i32 %conv
}

; Test unsigned f128->i64.
define i64 @f8(fp128 *%src) {
; CHECK-LABEL: f8:
; CHECK: vl %v0, 0(%r2)
; CHECK: vrepg %v2, %v0, 1
; CHECK: clgxbr %r2, 5, %f0, 0
; CHECK: br %r14
%f = load fp128 , fp128 *%src
%conv = fptoui fp128 %f to i64
ret i64 %conv
}
81 changes: 81 additions & 0 deletions llvm/test/CodeGen/SystemZ/fp-copysign-02.ll
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Original file line number Diff line number Diff line change
@@ -0,0 +1,81 @@
; Test f128 copysign operations on z14.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s

declare float @copysignf(float, float) readnone
declare double @copysign(double, double) readnone
; FIXME: not really the correct prototype for SystemZ.
declare fp128 @copysignl(fp128, fp128) readnone

; Test f32 copies in which the sign comes from an f128.
define float @f1(float %a, fp128 *%bptr) {
; CHECK-LABEL: f1:
; CHECK: vl %v[[REG:[0-9]+]], 0(%r2)
; CHECK: cpsdr %f0, %f[[REG]], %f0
; CHECK: br %r14
%bl = load volatile fp128, fp128 *%bptr
%b = fptrunc fp128 %bl to float
%res = call float @copysignf(float %a, float %b) readnone
ret float %res
}

; Test f64 copies in which the sign comes from an f128.
define double @f2(double %a, fp128 *%bptr) {
; CHECK-LABEL: f2:
; CHECK: vl %v[[REG:[0-9]+]], 0(%r2)
; CHECK: cpsdr %f0, %f[[REG]], %f0
; CHECK: br %r14
%bl = load volatile fp128, fp128 *%bptr
%b = fptrunc fp128 %bl to double
%res = call double @copysign(double %a, double %b) readnone
ret double %res
}

; Test f128 copies in which the sign comes from an f32.
define void @f7(fp128 *%cptr, fp128 *%aptr, float %bf) {
; CHECK-LABEL: f7:
; CHECK: vl [[REG1:%v[0-7]+]], 0(%r3)
; CHECK: tmlh
; CHECK: wflnxb [[REG1]], [[REG1]]
; CHECK: wflpxb [[REG1]], [[REG1]]
; CHECK: vst [[REG1]], 0(%r2)
; CHECK: br %r14
%a = load volatile fp128, fp128 *%aptr
%b = fpext float %bf to fp128
%c = call fp128 @copysignl(fp128 %a, fp128 %b) readnone
store fp128 %c, fp128 *%cptr
ret void
}

; As above, but the sign comes from an f64.
define void @f8(fp128 *%cptr, fp128 *%aptr, double %bd) {
; CHECK-LABEL: f8:
; CHECK: vl [[REG1:%v[0-7]+]], 0(%r3)
; CHECK: tmhh
; CHECK: wflnxb [[REG1]], [[REG1]]
; CHECK: wflpxb [[REG1]], [[REG1]]
; CHECK: vst [[REG1]], 0(%r2)
; CHECK: br %r14
%a = load volatile fp128, fp128 *%aptr
%b = fpext double %bd to fp128
%c = call fp128 @copysignl(fp128 %a, fp128 %b) readnone
store fp128 %c, fp128 *%cptr
ret void
}

; As above, but the sign comes from an f128.
define void @f9(fp128 *%cptr, fp128 *%aptr, fp128 *%bptr) {
; CHECK-LABEL: f9:
; CHECK: vl [[REG1:%v[0-7]+]], 0(%r3)
; CHECK: vl [[REG2:%v[0-7]+]], 0(%r4)
; CHECK: tm
; CHECK: wflnxb [[REG1]], [[REG1]]
; CHECK: wflpxb [[REG1]], [[REG1]]
; CHECK: vst [[REG1]], 0(%r2)
; CHECK: br %r14
%a = load volatile fp128, fp128 *%aptr
%b = load volatile fp128, fp128 *%bptr
%c = call fp128 @copysignl(fp128 %a, fp128 %b) readnone
store fp128 %c, fp128 *%cptr
ret void
}
17 changes: 17 additions & 0 deletions llvm/test/CodeGen/SystemZ/fp-div-04.ll
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@@ -0,0 +1,17 @@
; Test 128-bit floating-point division on z14.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s

define void @f1(fp128 *%ptr1, fp128 *%ptr2) {
; CHECK-LABEL: f1:
; CHECK-DAG: vl [[REG1:%v[0-9]+]], 0(%r2)
; CHECK-DAG: vl [[REG2:%v[0-9]+]], 0(%r3)
; CHECK: wfdxb [[RES:%v[0-9]+]], [[REG1]], [[REG2]]
; CHECK: vst [[RES]], 0(%r2)
; CHECK: br %r14
%f1 = load fp128, fp128 *%ptr1
%f2 = load fp128, fp128 *%ptr2
%sum = fdiv fp128 %f1, %f2
store fp128 %sum, fp128 *%ptr1
ret void
}
46 changes: 46 additions & 0 deletions llvm/test/CodeGen/SystemZ/fp-move-13.ll
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Original file line number Diff line number Diff line change
@@ -0,0 +1,46 @@
; Test f128 moves on z14.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s

; VR-to-VR moves. Since f128s are passed by reference,
; we need to force a copy by other means.
define void @f1(fp128 *%x) {
; CHECK-LABEL: f1:
; CHECK: vlr
; CHECK: vleig
; CHECK: br %r14
%val = load volatile fp128 , fp128 *%x
%t1 = bitcast fp128 %val to <2 x i64>
%t2 = insertelement <2 x i64> %t1, i64 0, i32 0
%res = bitcast <2 x i64> %t2 to fp128
store volatile fp128 %res, fp128 *%x
store volatile fp128 %val, fp128 *%x
ret void
}

; Test 128-bit moves from GPRs to VRs. i128 isn't a legitimate type,
; so this goes through memory.
define void @f2(fp128 *%a, i128 *%b) {
; CHECK-LABEL: f2:
; CHECK: lg
; CHECK: lg
; CHECK: stg
; CHECK: stg
; CHECK: br %r14
%val = load i128 , i128 *%b
%res = bitcast i128 %val to fp128
store fp128 %res, fp128 *%a
ret void
}

; Test 128-bit moves from VRs to GPRs, with the same restriction as f2.
define void @f3(fp128 *%a, i128 *%b) {
; CHECK-LABEL: f3:
; CHECK: vl
; CHECK: vst
%val = load fp128 , fp128 *%a
%res = bitcast fp128 %val to i128
store i128 %res, i128 *%b
ret void
}

32 changes: 32 additions & 0 deletions llvm/test/CodeGen/SystemZ/fp-mul-11.ll
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Original file line number Diff line number Diff line change
@@ -0,0 +1,32 @@
; Test 128-bit floating-point multiplication on z14.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s

define void @f1(fp128 *%ptr1, fp128 *%ptr2) {
; CHECK-LABEL: f1:
; CHECK-DAG: vl [[REG1:%v[0-9]+]], 0(%r2)
; CHECK-DAG: vl [[REG2:%v[0-9]+]], 0(%r3)
; CHECK: wfmxb [[RES:%v[0-9]+]], [[REG1]], [[REG2]]
; CHECK: vst [[RES]], 0(%r2)
; CHECK: br %r14
%f1 = load fp128, fp128 *%ptr1
%f2 = load fp128, fp128 *%ptr2
%sum = fmul fp128 %f1, %f2
store fp128 %sum, fp128 *%ptr1
ret void
}

define void @f2(double %f1, double %f2, fp128 *%dst) {
; CHECK-LABEL: f2:
; CHECK-DAG: wflld [[REG1:%v[0-9]+]], %f0
; CHECK-DAG: wflld [[REG2:%v[0-9]+]], %f2
; CHECK: wfmxb [[RES:%v[0-9]+]], [[REG1]], [[REG2]]
; CHECK: vst [[RES]], 0(%r2)
; CHECK: br %r14
%f1x = fpext double %f1 to fp128
%f2x = fpext double %f2 to fp128
%res = fmul fp128 %f1x, %f2x
store fp128 %res, fp128 *%dst
ret void
}

72 changes: 72 additions & 0 deletions llvm/test/CodeGen/SystemZ/fp-mul-12.ll
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@@ -0,0 +1,72 @@
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s

declare fp128 @llvm.fma.f128(fp128 %f1, fp128 %f2, fp128 %f3)

define void @f1(fp128 *%ptr1, fp128 *%ptr2, fp128 *%ptr3, fp128 *%dst) {
; CHECK-LABEL: f1:
; CHECK-DAG: vl [[REG1:%v[0-9]+]], 0(%r2)
; CHECK-DAG: vl [[REG2:%v[0-9]+]], 0(%r3)
; CHECK-DAG: vl [[REG3:%v[0-9]+]], 0(%r4)
; CHECK: wfmaxb [[RES:%v[0-9]+]], [[REG1]], [[REG2]], [[REG3]]
; CHECK: vst [[RES]], 0(%r5)
; CHECK: br %r14
%f1 = load fp128, fp128 *%ptr1
%f2 = load fp128, fp128 *%ptr2
%f3 = load fp128, fp128 *%ptr3
%res = call fp128 @llvm.fma.f128 (fp128 %f1, fp128 %f2, fp128 %f3)
store fp128 %res, fp128 *%dst
ret void
}

define void @f2(fp128 *%ptr1, fp128 *%ptr2, fp128 *%ptr3, fp128 *%dst) {
; CHECK-LABEL: f2:
; CHECK-DAG: vl [[REG1:%v[0-9]+]], 0(%r2)
; CHECK-DAG: vl [[REG2:%v[0-9]+]], 0(%r3)
; CHECK-DAG: vl [[REG3:%v[0-9]+]], 0(%r4)
; CHECK: wfmsxb [[RES:%v[0-9]+]], [[REG1]], [[REG2]], [[REG3]]
; CHECK: vst [[RES]], 0(%r5)
; CHECK: br %r14
%f1 = load fp128, fp128 *%ptr1
%f2 = load fp128, fp128 *%ptr2
%f3 = load fp128, fp128 *%ptr3
%neg = fsub fp128 0xL00000000000000008000000000000000, %f3
%res = call fp128 @llvm.fma.f128 (fp128 %f1, fp128 %f2, fp128 %neg)
store fp128 %res, fp128 *%dst
ret void
}

define void @f3(fp128 *%ptr1, fp128 *%ptr2, fp128 *%ptr3, fp128 *%dst) {
; CHECK-LABEL: f3:
; CHECK-DAG: vl [[REG1:%v[0-9]+]], 0(%r2)
; CHECK-DAG: vl [[REG2:%v[0-9]+]], 0(%r3)
; CHECK-DAG: vl [[REG3:%v[0-9]+]], 0(%r4)
; CHECK: wfnmaxb [[RES:%v[0-9]+]], [[REG1]], [[REG2]], [[REG3]]
; CHECK: vst [[RES]], 0(%r5)
; CHECK: br %r14
%f1 = load fp128, fp128 *%ptr1
%f2 = load fp128, fp128 *%ptr2
%f3 = load fp128, fp128 *%ptr3
%res = call fp128 @llvm.fma.f128 (fp128 %f1, fp128 %f2, fp128 %f3)
%negres = fsub fp128 0xL00000000000000008000000000000000, %res
store fp128 %negres, fp128 *%dst
ret void
}

define void @f4(fp128 *%ptr1, fp128 *%ptr2, fp128 *%ptr3, fp128 *%dst) {
; CHECK-LABEL: f4:
; CHECK-DAG: vl [[REG1:%v[0-9]+]], 0(%r2)
; CHECK-DAG: vl [[REG2:%v[0-9]+]], 0(%r3)
; CHECK-DAG: vl [[REG3:%v[0-9]+]], 0(%r4)
; CHECK: wfnmsxb [[RES:%v[0-9]+]], [[REG1]], [[REG2]], [[REG3]]
; CHECK: vst [[RES]], 0(%r5)
; CHECK: br %r14
%f1 = load fp128, fp128 *%ptr1
%f2 = load fp128, fp128 *%ptr2
%f3 = load fp128, fp128 *%ptr3
%neg = fsub fp128 0xL00000000000000008000000000000000, %f3
%res = call fp128 @llvm.fma.f128 (fp128 %f1, fp128 %f2, fp128 %neg)
%negres = fsub fp128 0xL00000000000000008000000000000000, %res
store fp128 %negres, fp128 *%dst
ret void
}

7 changes: 5 additions & 2 deletions llvm/test/CodeGen/SystemZ/fp-neg-02.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -25,8 +25,11 @@ define double @f2(double %f) {
; processing so that using FPRs is unequivocally better.
define void @f3(fp128 *%ptr, fp128 *%ptr2) {
; CHECK-LABEL: f3:
; CHECK: lcxbr
; CHECK: dxbr
; CHECK-DAG: vl [[REG1:%v[0-9]+]], 0(%r2)
; CHECK-DAG: vl [[REG2:%v[0-9]+]], 0(%r3)
; CHECK-DAG: wflcxb [[NEGREG1:%v[0-9]+]], [[REG1]]
; CHECK: wfdxb [[RES:%v[0-9]+]], [[NEGREG1]], [[REG2]]
; CHECK: vst [[RES]], 0(%r2)
; CHECK: br %r14
%orig = load fp128 , fp128 *%ptr
%negzero = fpext float -0.0 to fp128
Expand Down
24 changes: 18 additions & 6 deletions llvm/test/CodeGen/SystemZ/fp-round-03.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -26,7 +26,9 @@ define double @f2(double %f) {
declare fp128 @llvm.rint.f128(fp128 %f)
define void @f3(fp128 *%ptr) {
; CHECK-LABEL: f3:
; CHECK: fixbr %f0, 0, %f0
; CHECK: vl [[REG:%v[0-9]+]], 0(%r2)
; CHECK: wfixb [[RES:%v[0-9]+]], [[REG]], 0, 0
; CHECK: vst [[RES]], 0(%r2)
; CHECK: br %r14
%src = load fp128 , fp128 *%ptr
%res = call fp128 @llvm.rint.f128(fp128 %src)
Expand Down Expand Up @@ -58,7 +60,9 @@ define double @f5(double %f) {
declare fp128 @llvm.nearbyint.f128(fp128 %f)
define void @f6(fp128 *%ptr) {
; CHECK-LABEL: f6:
; CHECK: fixbra %f0, 0, %f0, 4
; CHECK: vl [[REG:%v[0-9]+]], 0(%r2)
; CHECK: wfixb [[RES:%v[0-9]+]], [[REG]], 4, 0
; CHECK: vst [[RES]], 0(%r2)
; CHECK: br %r14
%src = load fp128 , fp128 *%ptr
%res = call fp128 @llvm.nearbyint.f128(fp128 %src)
Expand Down Expand Up @@ -90,7 +94,9 @@ define double @f8(double %f) {
declare fp128 @llvm.floor.f128(fp128 %f)
define void @f9(fp128 *%ptr) {
; CHECK-LABEL: f9:
; CHECK: fixbra %f0, 7, %f0, 4
; CHECK: vl [[REG:%v[0-9]+]], 0(%r2)
; CHECK: wfixb [[RES:%v[0-9]+]], [[REG]], 4, 7
; CHECK: vst [[RES]], 0(%r2)
; CHECK: br %r14
%src = load fp128 , fp128 *%ptr
%res = call fp128 @llvm.floor.f128(fp128 %src)
Expand Down Expand Up @@ -122,7 +128,9 @@ define double @f11(double %f) {
declare fp128 @llvm.ceil.f128(fp128 %f)
define void @f12(fp128 *%ptr) {
; CHECK-LABEL: f12:
; CHECK: fixbra %f0, 6, %f0, 4
; CHECK: vl [[REG:%v[0-9]+]], 0(%r2)
; CHECK: wfixb [[RES:%v[0-9]+]], [[REG]], 4, 6
; CHECK: vst [[RES]], 0(%r2)
; CHECK: br %r14
%src = load fp128 , fp128 *%ptr
%res = call fp128 @llvm.ceil.f128(fp128 %src)
Expand Down Expand Up @@ -154,7 +162,9 @@ define double @f14(double %f) {
declare fp128 @llvm.trunc.f128(fp128 %f)
define void @f15(fp128 *%ptr) {
; CHECK-LABEL: f15:
; CHECK: fixbra %f0, 5, %f0, 4
; CHECK: vl [[REG:%v[0-9]+]], 0(%r2)
; CHECK: wfixb [[RES:%v[0-9]+]], [[REG]], 4, 5
; CHECK: vst [[RES]], 0(%r2)
; CHECK: br %r14
%src = load fp128 , fp128 *%ptr
%res = call fp128 @llvm.trunc.f128(fp128 %src)
Expand Down Expand Up @@ -186,7 +196,9 @@ define double @f17(double %f) {
declare fp128 @llvm.round.f128(fp128 %f)
define void @f18(fp128 *%ptr) {
; CHECK-LABEL: f18:
; CHECK: fixbra %f0, 1, %f0, 4
; CHECK: vl [[REG:%v[0-9]+]], 0(%r2)
; CHECK: wfixb [[RES:%v[0-9]+]], [[REG]], 4, 1
; CHECK: vst [[RES]], 0(%r2)
; CHECK: br %r14
%src = load fp128 , fp128 *%ptr
%res = call fp128 @llvm.round.f128(fp128 %src)
Expand Down
17 changes: 17 additions & 0 deletions llvm/test/CodeGen/SystemZ/fp-sqrt-04.ll
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,17 @@
; Test 128-bit floating-point square root on z14.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s

declare fp128 @llvm.sqrt.f128(fp128 %f)

define void @f1(fp128 *%ptr) {
; CHECK-LABEL: f1:
; CHECK-DAG: vl [[REG:%v[0-9]+]], 0(%r2)
; CHECK: wfsqxb [[RES:%v[0-9]+]], [[REG]]
; CHECK: vst [[RES]], 0(%r2)
; CHECK: br %r14
%f = load fp128, fp128 *%ptr
%res = call fp128 @llvm.sqrt.f128(fp128 %f)
store fp128 %res, fp128 *%ptr
ret void
}
17 changes: 17 additions & 0 deletions llvm/test/CodeGen/SystemZ/fp-sub-04.ll
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,17 @@
; Test 128-bit floating-point subtraction on z14.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s

define void @f1(fp128 *%ptr1, fp128 *%ptr2) {
; CHECK-LABEL: f1:
; CHECK-DAG: vl [[REG1:%v[0-9]+]], 0(%r2)
; CHECK-DAG: vl [[REG2:%v[0-9]+]], 0(%r3)
; CHECK: wfsxb [[RES:%v[0-9]+]], [[REG1]], [[REG2]]
; CHECK: vst [[RES]], 0(%r2)
; CHECK: br %r14
%f1 = load fp128, fp128 *%ptr1
%f2 = load fp128, fp128 *%ptr2
%sum = fsub fp128 %f1, %f2
store fp128 %sum, fp128 *%ptr1
ret void
}
18 changes: 18 additions & 0 deletions llvm/test/CodeGen/SystemZ/tdc-07.ll
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,18 @@
; Test the Test Data Class instruction on z14
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s

declare i32 @llvm.s390.tdc.f128(fp128, i64)

; Check using as i32 - f128
define i32 @f3(fp128 %x) {
; CHECK-LABEL: f3
; CHECK: vl %v0, 0(%r2)
; CHECK: vrepg %v2, %v0, 1
; CHECK: tcxb %f0, 123
; CHECK: ipm %r2
; CHECK: srl %r2, 28
%res = call i32 @llvm.s390.tdc.f128(fp128 %x, i64 123)
ret i32 %res
}

63 changes: 63 additions & 0 deletions llvm/test/CodeGen/SystemZ/vec-max-05.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,9 @@ declare float @fmaxf(float, float)
declare float @llvm.maxnum.f32(float, float)
declare <4 x float> @llvm.maxnum.v4f32(<4 x float>, <4 x float>)

declare fp128 @fmaxl(fp128, fp128)
declare fp128 @llvm.maxnum.f128(fp128, fp128)

; Test the fmax library function.
define double @f1(double %dummy, double %val1, double %val2) {
; CHECK-LABEL: f1:
Expand Down Expand Up @@ -110,3 +113,63 @@ define <4 x float> @f15(<4 x float> %dummy, <4 x float> %val1,
ret <4 x float> %ret
}

; Test the fmaxl library function.
define void @f21(fp128 *%ptr1, fp128 *%ptr2, fp128 *%dst) {
; CHECK-LABEL: f21:
; CHECK-DAG: vl [[REG1:%v[0-9]+]], 0(%r2)
; CHECK-DAG: vl [[REG2:%v[0-9]+]], 0(%r3)
; CHECK: wfmaxxb [[RES:%v[0-9]+]], [[REG1]], [[REG2]], 4
; CHECK: vst [[RES]], 0(%r4)
; CHECK: br %r14
%val1 = load fp128, fp128* %ptr1
%val2 = load fp128, fp128* %ptr2
%res = call fp128 @fmaxl(fp128 %val1, fp128 %val2) readnone
store fp128 %res, fp128* %dst
ret void
}

; Test the f128 maxnum intrinsic.
define void @f22(fp128 *%ptr1, fp128 *%ptr2, fp128 *%dst) {
; CHECK-LABEL: f22:
; CHECK-DAG: vl [[REG1:%v[0-9]+]], 0(%r2)
; CHECK-DAG: vl [[REG2:%v[0-9]+]], 0(%r3)
; CHECK: wfmaxxb [[RES:%v[0-9]+]], [[REG1]], [[REG2]], 4
; CHECK: vst [[RES]], 0(%r4)
; CHECK: br %r14
%val1 = load fp128, fp128* %ptr1
%val2 = load fp128, fp128* %ptr2
%res = call fp128 @llvm.maxnum.f128(fp128 %val1, fp128 %val2)
store fp128 %res, fp128* %dst
ret void
}

; Test a f128 constant compare/select resulting in maxnum.
define void @f23(fp128 *%ptr, fp128 *%dst) {
; CHECK-LABEL: f23:
; CHECK-DAG: vl [[REG1:%v[0-9]+]], 0(%r2)
; CHECK-DAG: vzero [[REG2:%v[0-9]+]]
; CHECK: wfmaxxb [[RES:%v[0-9]+]], [[REG1]], [[REG2]], 4
; CHECK: vst [[RES]], 0(%r3)
; CHECK: br %r14
%val = load fp128, fp128* %ptr
%cmp = fcmp ogt fp128 %val, 0xL00000000000000000000000000000000
%res = select i1 %cmp, fp128 %val, fp128 0xL00000000000000000000000000000000
store fp128 %res, fp128* %dst
ret void
}

; Test a f128 constant compare/select resulting in maxnan.
define void @f24(fp128 *%ptr, fp128 *%dst) {
; CHECK-LABEL: f24:
; CHECK-DAG: vl [[REG1:%v[0-9]+]], 0(%r2)
; CHECK-DAG: vzero [[REG2:%v[0-9]+]]
; CHECK: wfmaxxb [[RES:%v[0-9]+]], [[REG1]], [[REG2]], 1
; CHECK: vst [[RES]], 0(%r3)
; CHECK: br %r14
%val = load fp128, fp128* %ptr
%cmp = fcmp ugt fp128 %val, 0xL00000000000000000000000000000000
%res = select i1 %cmp, fp128 %val, fp128 0xL00000000000000000000000000000000
store fp128 %res, fp128* %dst
ret void
}

63 changes: 63 additions & 0 deletions llvm/test/CodeGen/SystemZ/vec-min-05.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,9 @@ declare float @fminf(float, float)
declare float @llvm.minnum.f32(float, float)
declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>)

declare fp128 @fminl(fp128, fp128)
declare fp128 @llvm.minnum.f128(fp128, fp128)

; Test the fmin library function.
define double @f1(double %dummy, double %val1, double %val2) {
; CHECK-LABEL: f1:
Expand Down Expand Up @@ -110,3 +113,63 @@ define <4 x float> @f15(<4 x float> %dummy, <4 x float> %val1,
ret <4 x float> %ret
}

; Test the fminl library function.
define void @f21(fp128 *%ptr1, fp128 *%ptr2, fp128 *%dst) {
; CHECK-LABEL: f21:
; CHECK-DAG: vl [[REG1:%v[0-9]+]], 0(%r2)
; CHECK-DAG: vl [[REG2:%v[0-9]+]], 0(%r3)
; CHECK: wfminxb [[RES:%v[0-9]+]], [[REG1]], [[REG2]], 4
; CHECK: vst [[RES]], 0(%r4)
; CHECK: br %r14
%val1 = load fp128, fp128* %ptr1
%val2 = load fp128, fp128* %ptr2
%res = call fp128 @fminl(fp128 %val1, fp128 %val2) readnone
store fp128 %res, fp128* %dst
ret void
}

; Test the f128 minnum intrinsic.
define void @f22(fp128 *%ptr1, fp128 *%ptr2, fp128 *%dst) {
; CHECK-LABEL: f22:
; CHECK-DAG: vl [[REG1:%v[0-9]+]], 0(%r2)
; CHECK-DAG: vl [[REG2:%v[0-9]+]], 0(%r3)
; CHECK: wfminxb [[RES:%v[0-9]+]], [[REG1]], [[REG2]], 4
; CHECK: vst [[RES]], 0(%r4)
; CHECK: br %r14
%val1 = load fp128, fp128* %ptr1
%val2 = load fp128, fp128* %ptr2
%res = call fp128 @llvm.minnum.f128(fp128 %val1, fp128 %val2)
store fp128 %res, fp128* %dst
ret void
}

; Test a f128 constant compare/select resulting in minnum.
define void @f23(fp128 *%ptr, fp128 *%dst) {
; CHECK-LABEL: f23:
; CHECK-DAG: vl [[REG1:%v[0-9]+]], 0(%r2)
; CHECK-DAG: vzero [[REG2:%v[0-9]+]]
; CHECK: wfminxb [[RES:%v[0-9]+]], [[REG1]], [[REG2]], 4
; CHECK: vst [[RES]], 0(%r3)
; CHECK: br %r14
%val = load fp128, fp128* %ptr
%cmp = fcmp olt fp128 %val, 0xL00000000000000000000000000000000
%res = select i1 %cmp, fp128 %val, fp128 0xL00000000000000000000000000000000
store fp128 %res, fp128* %dst
ret void
}

; Test a f128 constant compare/select resulting in minnan.
define void @f24(fp128 *%ptr, fp128 *%dst) {
; CHECK-LABEL: f24:
; CHECK-DAG: vl [[REG1:%v[0-9]+]], 0(%r2)
; CHECK-DAG: vzero [[REG2:%v[0-9]+]]
; CHECK: wfminxb [[RES:%v[0-9]+]], [[REG1]], [[REG2]], 1
; CHECK: vst [[RES]], 0(%r3)
; CHECK: br %r14
%val = load fp128, fp128* %ptr
%cmp = fcmp ult fp128 %val, 0xL00000000000000000000000000000000
%res = select i1 %cmp, fp128 %val, fp128 0xL00000000000000000000000000000000
store fp128 %res, fp128* %dst
ret void
}

564 changes: 564 additions & 0 deletions llvm/test/MC/Disassembler/SystemZ/insns-z14.txt
View file

Large diffs are not rendered by default.

99 changes: 99 additions & 0 deletions llvm/test/MC/SystemZ/insn-bad-z13.s
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2738,42 +2738,69 @@

#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfasb %v0, %v0, %v0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfaxb %v0, %v0, %v0

wfasb %v0, %v0, %v0
wfaxb %v0, %v0, %v0

#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfcsb %v0, %v0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfcxb %v0, %v0

wfcsb %v0, %v0
wfcxb %v0, %v0

#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfcesb %v0, %v0, %v0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfcesbs %v0, %v0, %v0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfcexb %v0, %v0, %v0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfcexbs %v0, %v0, %v0

wfcesb %v0, %v0, %v0
wfcesbs %v0, %v0, %v0
wfcexb %v0, %v0, %v0
wfcexbs %v0, %v0, %v0

#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfchsb %v0, %v0, %v0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfchsbs %v0, %v0, %v0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfchxb %v0, %v0, %v0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfchxbs %v0, %v0, %v0

wfchsb %v0, %v0, %v0
wfchsbs %v0, %v0, %v0
wfchxb %v0, %v0, %v0
wfchxbs %v0, %v0, %v0

#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfchesb %v0, %v0, %v0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfchesbs %v0, %v0, %v0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfchexb %v0, %v0, %v0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfchexbs %v0, %v0, %v0

wfchesb %v0, %v0, %v0
wfchesbs %v0, %v0, %v0
wfchexb %v0, %v0, %v0
wfchexbs %v0, %v0, %v0

#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfdsb %v0, %v0, %v0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfdxb %v0, %v0, %v0

wfdsb %v0, %v0, %v0
wfdxb %v0, %v0, %v0

#CHECK: error: invalid operand
#CHECK: wfidb %v0, %v0, 0, -1
Expand All @@ -2791,13 +2818,19 @@

#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfisb %v0, %v0, 0, 0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfixb %v0, %v0, 0, 0

wfisb %v0, %v0, 0, 0
wfixb %v0, %v0, 0, 0

#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfksb %v0, %v0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfkxb %v0, %v0

wfksb %v0, %v0
wfkxb %v0, %v0

#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfkedb %v0, %v0, %v0
Expand All @@ -2807,11 +2840,17 @@
#CHECK: wfkesb %v0, %v0, %v0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfkesbs %v0, %v0, %v0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfkexb %v0, %v0, %v0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfkexbs %v0, %v0, %v0

wfkedb %v0, %v0, %v0
wfkedbs %v0, %v0, %v0
wfkesb %v0, %v0, %v0
wfkesbs %v0, %v0, %v0
wfkexb %v0, %v0, %v0
wfkexbs %v0, %v0, %v0

#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfkhdb %v0, %v0, %v0
Expand All @@ -2821,11 +2860,17 @@
#CHECK: wfkhsb %v0, %v0, %v0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfkhsbs %v0, %v0, %v0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfkhxb %v0, %v0, %v0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfkhxbs %v0, %v0, %v0

wfkhdb %v0, %v0, %v0
wfkhdbs %v0, %v0, %v0
wfkhsb %v0, %v0, %v0
wfkhsbs %v0, %v0, %v0
wfkhxb %v0, %v0, %v0
wfkhxbs %v0, %v0, %v0

#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfkhedb %v0, %v0, %v0
Expand All @@ -2835,92 +2880,143 @@
#CHECK: wfkhesb %v0, %v0, %v0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfkhesbs %v0, %v0, %v0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfkhexb %v0, %v0, %v0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfkhexbs %v0, %v0, %v0

wfkhedb %v0, %v0, %v0
wfkhedbs %v0, %v0, %v0
wfkhesb %v0, %v0, %v0
wfkhesbs %v0, %v0, %v0
wfkhexb %v0, %v0, %v0
wfkhexbs %v0, %v0, %v0

#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfpsosb %v0, %v0, 0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfpsoxb %v0, %v0, 0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wflcsb %v0, %v0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wflcxb %v0, %v0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wflnsb %v0, %v0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wflnxb %v0, %v0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wflpsb %v0, %v0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wflpxb %v0, %v0

wfpsosb %v0, %v0, 0
wfpsoxb %v0, %v0, 0
wflcsb %v0, %v0
wflcxb %v0, %v0
wflnsb %v0, %v0
wflnxb %v0, %v0
wflpsb %v0, %v0
wflpxb %v0, %v0

#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wflls %v0, %v0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wflld %v0, %v0

wflls %v0, %v0
wflld %v0, %v0

#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wflrd %v0, %v0, 0, 0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wflrx %v0, %v0, 0, 0

wflrd %v0, %v0, 0, 0
wflrx %v0, %v0, 0, 0

#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfmaxdb %v0, %v0, %v0, 0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfmaxsb %v0, %v0, %v0, 0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfmaxxb %v0, %v0, %v0, 0

wfmaxdb %v0, %v0, %v0, 0
wfmaxsb %v0, %v0, %v0, 0
wfmaxxb %v0, %v0, %v0, 0

#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfmindb %v0, %v0, %v0, 0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfminsb %v0, %v0, %v0, 0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfminxb %v0, %v0, %v0, 0

wfmindb %v0, %v0, %v0, 0
wfminsb %v0, %v0, %v0, 0
wfminxb %v0, %v0, %v0, 0

#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfmasb %v0, %v0, %v0, %v0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfmaxb %v0, %v0, %v0, %v0

wfmasb %v0, %v0, %v0, %v0
wfmaxb %v0, %v0, %v0, %v0

#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfmsb %v0, %v0, %v0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfmxb %v0, %v0, %v0

wfmsb %v0, %v0, %v0
wfmxb %v0, %v0, %v0

#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfmssb %v0, %v0, %v0, %v0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfmsxb %v0, %v0, %v0, %v0

wfmssb %v0, %v0, %v0, %v0
wfmsxb %v0, %v0, %v0, %v0

#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfnmadb %v0, %v0, %v0, %v0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfnmasb %v0, %v0, %v0, %v0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfnmaxb %v0, %v0, %v0, %v0

wfnmadb %v0, %v0, %v0, %v0
wfnmasb %v0, %v0, %v0, %v0
wfnmaxb %v0, %v0, %v0, %v0

#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfnmsdb %v0, %v0, %v0, %v0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfnmssb %v0, %v0, %v0, %v0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfnmsxb %v0, %v0, %v0, %v0

wfnmsdb %v0, %v0, %v0, %v0
wfnmssb %v0, %v0, %v0, %v0
wfnmsxb %v0, %v0, %v0, %v0

#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfssb %v0, %v0, %v0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfsxb %v0, %v0, %v0

wfssb %v0, %v0, %v0
wfsxb %v0, %v0, %v0

#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfsqsb %v0, %v0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wfsqxb %v0, %v0

wfsqsb %v0, %v0
wfsqxb %v0, %v0

#CHECK: error: invalid operand
#CHECK: wftcidb %v0, %v0, -1
Expand All @@ -2932,8 +3028,11 @@

#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wftcisb %v0, %v0, 0
#CHECK: error: instruction requires: vector-enhancements-1
#CHECK: wftcixb %v0, %v0, 0

wftcisb %v0, %v0, 0
wftcixb %v0, %v0, 0

#CHECK: error: invalid operand
#CHECK: wledb %v0, %v0, 0, -1
Expand Down
52 changes: 52 additions & 0 deletions llvm/test/MC/SystemZ/insn-bad-z14.s
View file
Original file line number Diff line number Diff line change
Expand Up @@ -644,6 +644,20 @@
wfisb %v0, %v0, -1, 0
wfisb %v0, %v0, 16, 0

#CHECK: error: invalid operand
#CHECK: wfixb %v0, %v0, 0, -1
#CHECK: error: invalid operand
#CHECK: wfixb %v0, %v0, 0, 16
#CHECK: error: invalid operand
#CHECK: wfixb %v0, %v0, -1, 0
#CHECK: error: invalid operand
#CHECK: wfixb %v0, %v0, 16, 0

wfixb %v0, %v0, 0, -1
wfixb %v0, %v0, 0, 16
wfixb %v0, %v0, -1, 0
wfixb %v0, %v0, 16, 0

#CHECK: error: invalid operand
#CHECK: wflrd %v0, %v0, 0, -1
#CHECK: error: invalid operand
Expand All @@ -658,6 +672,20 @@
wflrd %v0, %v0, -1, 0
wflrd %v0, %v0, 16, 0

#CHECK: error: invalid operand
#CHECK: wflrx %v0, %v0, 0, -1
#CHECK: error: invalid operand
#CHECK: wflrx %v0, %v0, 0, 16
#CHECK: error: invalid operand
#CHECK: wflrx %v0, %v0, -1, 0
#CHECK: error: invalid operand
#CHECK: wflrx %v0, %v0, 16, 0

wflrx %v0, %v0, 0, -1
wflrx %v0, %v0, 0, 16
wflrx %v0, %v0, -1, 0
wflrx %v0, %v0, 16, 0

#CHECK: error: invalid operand
#CHECK: wfmaxdb %v0, %v0, %v0, -1
#CHECK: error: invalid operand
Expand All @@ -674,6 +702,14 @@
wfmaxsb %v0, %v0, %v0, -1
wfmaxsb %v0, %v0, %v0, 16

#CHECK: error: invalid operand
#CHECK: wfmaxxb %v0, %v0, %v0, -1
#CHECK: error: invalid operand
#CHECK: wfmaxxb %v0, %v0, %v0, 16

wfmaxxb %v0, %v0, %v0, -1
wfmaxxb %v0, %v0, %v0, 16

#CHECK: error: invalid operand
#CHECK: wfmindb %v0, %v0, %v0, -1
#CHECK: error: invalid operand
Expand All @@ -690,6 +726,14 @@
wfminsb %v0, %v0, %v0, -1
wfminsb %v0, %v0, %v0, 16

#CHECK: error: invalid operand
#CHECK: wfminxb %v0, %v0, %v0, -1
#CHECK: error: invalid operand
#CHECK: wfminxb %v0, %v0, %v0, 16

wfminxb %v0, %v0, %v0, -1
wfminxb %v0, %v0, %v0, 16

#CHECK: error: invalid operand
#CHECK: wftcisb %v0, %v0, -1
#CHECK: error: invalid operand
Expand All @@ -698,3 +742,11 @@
wftcisb %v0, %v0, -1
wftcisb %v0, %v0, 4096

#CHECK: error: invalid operand
#CHECK: wftcixb %v0, %v0, -1
#CHECK: error: invalid operand
#CHECK: wftcixb %v0, %v0, 4096

wftcixb %v0, %v0, -1
wftcixb %v0, %v0, 4096

442 changes: 442 additions & 0 deletions llvm/test/MC/SystemZ/insn-good-z14.s
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