32 changes: 15 additions & 17 deletions llvm/test/CodeGen/AArch64/sve-ptest-removal-brk.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -6,8 +6,7 @@
define i32 @brkpa(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
; CHECK-LABEL: brkpa:
; CHECK: // %bb.0:
; CHECK-NEXT: brkpa p1.b, p0/z, p1.b, p2.b
; CHECK-NEXT: ptest p0, p1.b
; CHECK-NEXT: brkpas p0.b, p0/z, p1.b, p2.b
; CHECK-NEXT: cset w0, ne
; CHECK-NEXT: ret
%1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.brkpa.z.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b)
Expand All @@ -31,8 +30,7 @@ define i32 @brkpb(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x
define i32 @brka(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
; CHECK-LABEL: brka:
; CHECK: // %bb.0:
; CHECK-NEXT: brka p1.b, p0/z, p1.b
; CHECK-NEXT: ptest p0, p1.b
; CHECK-NEXT: brkas p0.b, p0/z, p1.b
; CHECK-NEXT: cset w0, ne
; CHECK-NEXT: ret
%1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.brka.z.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a)
Expand All @@ -53,19 +51,6 @@ define i32 @brkb(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
ret i32 %conv
}

define i32 @brkn(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
; CHECK-LABEL: brkn:
; CHECK: // %bb.0:
; CHECK-NEXT: brkn p2.b, p0/z, p1.b, p2.b
; CHECK-NEXT: ptest p0, p2.b
; CHECK-NEXT: cset w0, ne
; CHECK-NEXT: ret
%1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.brkn.z.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b)
%2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %1)
%conv = zext i1 %2 to i32
ret i32 %conv
}

define i32 @brkn_all_active(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
; CHECK-LABEL: brkn_all_active:
; CHECK: // %bb.0:
Expand Down Expand Up @@ -146,6 +131,19 @@ define i32 @brkn_neg(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16
ret i32 %conv
}

define i32 @brkn_neg2(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
; CHECK-LABEL: brkn_neg2:
; CHECK: // %bb.0:
; CHECK-NEXT: brkn p2.b, p0/z, p1.b, p2.b
; CHECK-NEXT: ptest p0, p2.b
; CHECK-NEXT: cset w0, ne
; CHECK-NEXT: ret
%1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.brkn.z.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b)
%2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %1)
%conv = zext i1 %2 to i32
ret i32 %conv
}

declare <vscale x 16 x i1> @llvm.aarch64.sve.brkpa.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
declare <vscale x 16 x i1> @llvm.aarch64.sve.brkpb.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
declare <vscale x 16 x i1> @llvm.aarch64.sve.brka.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>)
Expand Down
21 changes: 7 additions & 14 deletions llvm/test/CodeGen/AArch64/sve-ptest-removal-log.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -7,8 +7,7 @@
define i1 @and(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
; CHECK-LABEL: and:
; CHECK: // %bb.0:
; CHECK-NEXT: and p1.b, p0/z, p1.b, p2.b
; CHECK-NEXT: ptest p0, p1.b
; CHECK-NEXT: ands p0.b, p0/z, p1.b, p2.b
; CHECK-NEXT: cset w0, ne
; CHECK-NEXT: ret
%1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.and.z.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b)
Expand All @@ -19,8 +18,7 @@ define i1 @and(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1>
define i1 @bic(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
; CHECK-LABEL: bic:
; CHECK: // %bb.0:
; CHECK-NEXT: bic p1.b, p0/z, p1.b, p2.b
; CHECK-NEXT: ptest p0, p1.b
; CHECK-NEXT: bics p0.b, p0/z, p1.b, p2.b
; CHECK-NEXT: cset w0, ne
; CHECK-NEXT: ret
%1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.bic.z.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b)
Expand All @@ -31,8 +29,7 @@ define i1 @bic(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1>
define i1 @eor(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
; CHECK-LABEL: eor:
; CHECK: // %bb.0:
; CHECK-NEXT: eor p1.b, p0/z, p1.b, p2.b
; CHECK-NEXT: ptest p0, p1.b
; CHECK-NEXT: eors p0.b, p0/z, p1.b, p2.b
; CHECK-NEXT: cset w0, ne
; CHECK-NEXT: ret
%1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.eor.z.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b)
Expand All @@ -43,8 +40,7 @@ define i1 @eor(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1>
define i1 @nand(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
; CHECK-LABEL: nand:
; CHECK: // %bb.0:
; CHECK-NEXT: nand p1.b, p0/z, p1.b, p2.b
; CHECK-NEXT: ptest p0, p1.b
; CHECK-NEXT: nands p0.b, p0/z, p1.b, p2.b
; CHECK-NEXT: cset w0, ne
; CHECK-NEXT: ret
%1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.nand.z.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b)
Expand All @@ -55,8 +51,7 @@ define i1 @nand(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1
define i1 @nor(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
; CHECK-LABEL: nor:
; CHECK: // %bb.0:
; CHECK-NEXT: nor p1.b, p0/z, p1.b, p2.b
; CHECK-NEXT: ptest p0, p1.b
; CHECK-NEXT: nors p0.b, p0/z, p1.b, p2.b
; CHECK-NEXT: cset w0, ne
; CHECK-NEXT: ret
%1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.nor.z.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b)
Expand All @@ -67,8 +62,7 @@ define i1 @nor(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1>
define i1 @orn(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
; CHECK-LABEL: orn:
; CHECK: // %bb.0:
; CHECK-NEXT: orn p1.b, p0/z, p1.b, p2.b
; CHECK-NEXT: ptest p0, p1.b
; CHECK-NEXT: orns p0.b, p0/z, p1.b, p2.b
; CHECK-NEXT: cset w0, ne
; CHECK-NEXT: ret
%1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.orn.z.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b)
Expand All @@ -79,8 +73,7 @@ define i1 @orn(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1>
define i1 @orr(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
; CHECK-LABEL: orr:
; CHECK: // %bb.0:
; CHECK-NEXT: orr p1.b, p0/z, p1.b, p2.b
; CHECK-NEXT: ptest p0, p1.b
; CHECK-NEXT: orrs p0.b, p0/z, p1.b, p2.b
; CHECK-NEXT: cset w0, ne
; CHECK-NEXT: ret
%1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.orr.z.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b)
Expand Down
3 changes: 1 addition & 2 deletions llvm/test/CodeGen/AArch64/sve-ptest-removal-ptrue.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -4,8 +4,7 @@
define i1 @ptrue() {
; CHECK-LABEL: ptrue:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.b, pow2
; CHECK-NEXT: ptest p0, p0.b
; CHECK-NEXT: ptrues p0.b, pow2
; CHECK-NEXT: cset w0, ne
; CHECK-NEXT: ret
%1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 0)
Expand Down
12 changes: 4 additions & 8 deletions llvm/test/CodeGen/AArch64/sve-split-int-pred-reduce.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -8,8 +8,7 @@ define i1 @andv_nxv32i1(<vscale x 32 x i1> %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p2.b
; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
; CHECK-NEXT: not p0.b, p2/z, p0.b
; CHECK-NEXT: ptest p2, p0.b
; CHECK-NEXT: nots p0.b, p2/z, p0.b
; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: ret
%res = call i1 @llvm.vector.reduce.and.nxv32i1(<vscale x 32 x i1> %a)
Expand All @@ -29,8 +28,7 @@ define i1 @andv_nxv64i1(<vscale x 64 x i1> %a) {
; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: ptrue p4.b
; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
; CHECK-NEXT: not p0.b, p4/z, p0.b
; CHECK-NEXT: ptest p4, p0.b
; CHECK-NEXT: nots p0.b, p4/z, p0.b
; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: addvl sp, sp, #1
Expand Down Expand Up @@ -74,8 +72,7 @@ define i1 @smaxv_nxv32i1(<vscale x 32 x i1> %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p2.b
; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
; CHECK-NEXT: not p0.b, p2/z, p0.b
; CHECK-NEXT: ptest p2, p0.b
; CHECK-NEXT: nots p0.b, p2/z, p0.b
; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: ret
%res = call i1 @llvm.vector.reduce.smax.nxv32i1(<vscale x 32 x i1> %a)
Expand Down Expand Up @@ -115,8 +112,7 @@ define i1 @uminv_nxv32i1(<vscale x 32 x i1> %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p2.b
; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
; CHECK-NEXT: not p0.b, p2/z, p0.b
; CHECK-NEXT: ptest p2, p0.b
; CHECK-NEXT: nots p0.b, p2/z, p0.b
; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: ret
%res = call i1 @llvm.vector.reduce.umin.nxv32i1(<vscale x 32 x i1> %a)
Expand Down
9 changes: 3 additions & 6 deletions llvm/test/CodeGen/AArch64/sve-vecreduce-fold.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -53,8 +53,7 @@ define i1 @reduce_and_insert_subvec_into_ones(<vscale x 4 x i1> %in) {
; CHECK-LABEL: reduce_and_insert_subvec_into_ones:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p1.s
; CHECK-NEXT: not p0.b, p1/z, p0.b
; CHECK-NEXT: ptest p1, p0.b
; CHECK-NEXT: nots p0.b, p1/z, p0.b
; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: ret
%allones.ins = insertelement <vscale x 16 x i1> poison, i1 1, i32 0
Expand All @@ -68,8 +67,7 @@ define i1 @reduce_and_insert_subvec_into_poison(<vscale x 4 x i1> %in) {
; CHECK-LABEL: reduce_and_insert_subvec_into_poison:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p1.s
; CHECK-NEXT: not p0.b, p1/z, p0.b
; CHECK-NEXT: ptest p1, p0.b
; CHECK-NEXT: nots p0.b, p1/z, p0.b
; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: ret
%t = call <vscale x 16 x i1> @llvm.vector.insert.nxv16i1.nxv4i1(<vscale x 16 x i1> poison, <vscale x 4 x i1> %in, i64 0)
Expand All @@ -86,8 +84,7 @@ define i1 @reduce_and_insert_subvec_into_var(<vscale x 4 x i1> %in, <vscale x 16
; CHECK-NEXT: ptrue p2.b
; CHECK-NEXT: uzp1 p0.h, p0.h, p3.h
; CHECK-NEXT: uzp1 p0.b, p0.b, p1.b
; CHECK-NEXT: not p0.b, p2/z, p0.b
; CHECK-NEXT: ptest p2, p0.b
; CHECK-NEXT: nots p0.b, p2/z, p0.b
; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: ret
%t = call <vscale x 16 x i1> @llvm.vector.insert.nxv16i1.nxv4i1(<vscale x 16 x i1> %vec, <vscale x 4 x i1> %in, i64 0)
Expand Down