54 changes: 27 additions & 27 deletions llvm/test/CodeGen/X86/ptest.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -8,9 +8,9 @@ define i32 @veccond128(<4 x i32> %input) {
; SSE2-LABEL: veccond128:
; SSE2: # %bb.0: # %entry
; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: pcmpeqb %xmm0, %xmm1
; SSE2-NEXT: pmovmskb %xmm1, %eax
; SSE2-NEXT: xorl $65535, %eax # imm = 0xFFFF
; SSE2-NEXT: pcmpeqd %xmm0, %xmm1
; SSE2-NEXT: movmskps %xmm1, %eax
; SSE2-NEXT: xorl $15, %eax
; SSE2-NEXT: je .LBB0_2
; SSE2-NEXT: # %bb.1: # %if-true-block
; SSE2-NEXT: xorl %eax, %eax
Expand Down Expand Up @@ -55,9 +55,9 @@ define i32 @veccond256(<8 x i32> %input) {
; SSE2: # %bb.0: # %entry
; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: pcmpeqb %xmm0, %xmm1
; SSE2-NEXT: pmovmskb %xmm1, %eax
; SSE2-NEXT: xorl $65535, %eax # imm = 0xFFFF
; SSE2-NEXT: pcmpeqd %xmm0, %xmm1
; SSE2-NEXT: movmskps %xmm1, %eax
; SSE2-NEXT: xorl $15, %eax
; SSE2-NEXT: je .LBB1_2
; SSE2-NEXT: # %bb.1: # %if-true-block
; SSE2-NEXT: xorl %eax, %eax
Expand Down Expand Up @@ -107,9 +107,9 @@ define i32 @veccond512(<16 x i32> %input) {
; SSE2-NEXT: por %xmm2, %xmm0
; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: pcmpeqb %xmm0, %xmm1
; SSE2-NEXT: pmovmskb %xmm1, %eax
; SSE2-NEXT: xorl $65535, %eax # imm = 0xFFFF
; SSE2-NEXT: pcmpeqd %xmm0, %xmm1
; SSE2-NEXT: movmskps %xmm1, %eax
; SSE2-NEXT: xorl $15, %eax
; SSE2-NEXT: je .LBB2_2
; SSE2-NEXT: # %bb.1: # %if-true-block
; SSE2-NEXT: xorl %eax, %eax
Expand Down Expand Up @@ -173,10 +173,10 @@ define i32 @vectest128(<4 x i32> %input) {
; SSE2-LABEL: vectest128:
; SSE2: # %bb.0:
; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: pcmpeqb %xmm0, %xmm1
; SSE2-NEXT: pmovmskb %xmm1, %ecx
; SSE2-NEXT: pcmpeqd %xmm0, %xmm1
; SSE2-NEXT: movmskps %xmm1, %ecx
; SSE2-NEXT: xorl %eax, %eax
; SSE2-NEXT: xorl $65535, %ecx # imm = 0xFFFF
; SSE2-NEXT: xorl $15, %ecx
; SSE2-NEXT: setne %al
; SSE2-NEXT: retq
;
Expand Down Expand Up @@ -204,10 +204,10 @@ define i32 @vectest256(<8 x i32> %input) {
; SSE2: # %bb.0:
; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: pcmpeqb %xmm0, %xmm1
; SSE2-NEXT: pmovmskb %xmm1, %ecx
; SSE2-NEXT: pcmpeqd %xmm0, %xmm1
; SSE2-NEXT: movmskps %xmm1, %ecx
; SSE2-NEXT: xorl %eax, %eax
; SSE2-NEXT: xorl $65535, %ecx # imm = 0xFFFF
; SSE2-NEXT: xorl $15, %ecx
; SSE2-NEXT: setne %al
; SSE2-NEXT: retq
;
Expand Down Expand Up @@ -239,10 +239,10 @@ define i32 @vectest512(<16 x i32> %input) {
; SSE2-NEXT: por %xmm2, %xmm0
; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: pcmpeqb %xmm0, %xmm1
; SSE2-NEXT: pmovmskb %xmm1, %ecx
; SSE2-NEXT: pcmpeqd %xmm0, %xmm1
; SSE2-NEXT: movmskps %xmm1, %ecx
; SSE2-NEXT: xorl %eax, %eax
; SSE2-NEXT: xorl $65535, %ecx # imm = 0xFFFF
; SSE2-NEXT: xorl $15, %ecx
; SSE2-NEXT: setne %al
; SSE2-NEXT: retq
;
Expand Down Expand Up @@ -284,9 +284,9 @@ define i32 @vecsel128(<4 x i32> %input, i32 %a, i32 %b) {
; SSE2: # %bb.0:
; SSE2-NEXT: movl %edi, %eax
; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: pcmpeqb %xmm0, %xmm1
; SSE2-NEXT: pmovmskb %xmm1, %ecx
; SSE2-NEXT: xorl $65535, %ecx # imm = 0xFFFF
; SSE2-NEXT: pcmpeqd %xmm0, %xmm1
; SSE2-NEXT: movmskps %xmm1, %ecx
; SSE2-NEXT: xorl $15, %ecx
; SSE2-NEXT: cmovel %esi, %eax
; SSE2-NEXT: retq
;
Expand Down Expand Up @@ -315,9 +315,9 @@ define i32 @vecsel256(<8 x i32> %input, i32 %a, i32 %b) {
; SSE2-NEXT: movl %edi, %eax
; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: pcmpeqb %xmm0, %xmm1
; SSE2-NEXT: pmovmskb %xmm1, %ecx
; SSE2-NEXT: xorl $65535, %ecx # imm = 0xFFFF
; SSE2-NEXT: pcmpeqd %xmm0, %xmm1
; SSE2-NEXT: movmskps %xmm1, %ecx
; SSE2-NEXT: xorl $15, %ecx
; SSE2-NEXT: cmovel %esi, %eax
; SSE2-NEXT: retq
;
Expand Down Expand Up @@ -350,9 +350,9 @@ define i32 @vecsel512(<16 x i32> %input, i32 %a, i32 %b) {
; SSE2-NEXT: por %xmm2, %xmm0
; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: pcmpeqb %xmm0, %xmm1
; SSE2-NEXT: pmovmskb %xmm1, %ecx
; SSE2-NEXT: xorl $65535, %ecx # imm = 0xFFFF
; SSE2-NEXT: pcmpeqd %xmm0, %xmm1
; SSE2-NEXT: movmskps %xmm1, %ecx
; SSE2-NEXT: xorl $15, %ecx
; SSE2-NEXT: cmovel %esi, %eax
; SSE2-NEXT: retq
;
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/X86/selectcc-to-shiftand.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -213,8 +213,8 @@ define <16 x i8> @sel_shift_bool_v16i8(<16 x i1> %t) {
define <8 x i16> @sel_shift_bool_v8i16(<8 x i1> %t) {
; ANY-LABEL: sel_shift_bool_v8i16:
; ANY: # %bb.0:
; ANY-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; ANY-NEXT: psllw $7, %xmm0
; ANY-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; ANY-NEXT: retq
%shl= select <8 x i1> %t, <8 x i16> <i16 128, i16 128, i16 128, i16 128, i16 128, i16 128, i16 128, i16 128>, <8 x i16> zeroinitializer
ret <8 x i16> %shl
Expand All @@ -223,8 +223,8 @@ define <8 x i16> @sel_shift_bool_v8i16(<8 x i1> %t) {
define <4 x i32> @sel_shift_bool_v4i32(<4 x i1> %t) {
; ANY-LABEL: sel_shift_bool_v4i32:
; ANY: # %bb.0:
; ANY-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; ANY-NEXT: pslld $6, %xmm0
; ANY-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; ANY-NEXT: retq
%shl = select <4 x i1> %t, <4 x i32> <i32 64, i32 64, i32 64, i32 64>, <4 x i32> zeroinitializer
ret <4 x i32> %shl
Expand All @@ -233,8 +233,8 @@ define <4 x i32> @sel_shift_bool_v4i32(<4 x i1> %t) {
define <2 x i64> @sel_shift_bool_v2i64(<2 x i1> %t) {
; ANY-LABEL: sel_shift_bool_v2i64:
; ANY: # %bb.0:
; ANY-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; ANY-NEXT: psllq $16, %xmm0
; ANY-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; ANY-NEXT: retq
%shl = select <2 x i1> %t, <2 x i64> <i64 65536, i64 65536>, <2 x i64> zeroinitializer
ret <2 x i64> %shl
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/X86/shrink-const.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -7,15 +7,15 @@ define <4 x i32> @sext_vector_constants(<4 x i32> %a0) {
; SSE-LABEL: sext_vector_constants:
; SSE: # %bb.0:
; SSE-NEXT: psrld $9, %xmm0
; SSE-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: pslld $26, %xmm0
; SSE-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: sext_vector_constants:
; AVX: # %bb.0:
; AVX-NEXT: vpsrld $9, %xmm0, %xmm0
; AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vpslld $26, %xmm0, %xmm0
; AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
%1 = lshr <4 x i32> %a0, <i32 9, i32 9, i32 9, i32 9>
%2 = xor <4 x i32> %1, <i32 314523200, i32 -2085372448, i32 144496960, i32 1532773600>
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/X86/vector-fshl-rot-128.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -171,8 +171,8 @@ define <2 x i64> @var_funnnel_v2i64(<2 x i64> %x, <2 x i64> %amt) nounwind {
define <4 x i32> @var_funnnel_v4i32(<4 x i32> %x, <4 x i32> %amt) nounwind {
; SSE2-LABEL: var_funnnel_v4i32:
; SSE2: # %bb.0:
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pslld $23, %xmm1
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: cvttps2dq %xmm1, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
Expand All @@ -191,8 +191,8 @@ define <4 x i32> @var_funnnel_v4i32(<4 x i32> %x, <4 x i32> %amt) nounwind {
; SSE41-LABEL: var_funnnel_v4i32:
; SSE41: # %bb.0:
; SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: pslld $23, %xmm1
; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: cvttps2dq %xmm1, %xmm1
; SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,3,3]
Expand All @@ -208,8 +208,8 @@ define <4 x i32> @var_funnnel_v4i32(<4 x i32> %x, <4 x i32> %amt) nounwind {
; AVX1-LABEL: var_funnnel_v4i32:
; AVX1: # %bb.0:
; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpslld $23, %xmm1, %xmm1
; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vcvttps2dq %xmm1, %xmm1
; AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm1[1,1,3,3]
Expand Down Expand Up @@ -282,8 +282,8 @@ define <4 x i32> @var_funnnel_v4i32(<4 x i32> %x, <4 x i32> %amt) nounwind {
;
; X86-SSE2-LABEL: var_funnnel_v4i32:
; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: pslld $23, %xmm1
; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: cvttps2dq %xmm1, %xmm1
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/X86/vector-fshl-rot-sub128.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -24,8 +24,8 @@ declare <2 x i32> @llvm.fshl.v2i32(<2 x i32>, <2 x i32>, <2 x i32>)
define <2 x i32> @var_funnnel_v2i32(<2 x i32> %x, <2 x i32> %amt) nounwind {
; SSE2-LABEL: var_funnnel_v2i32:
; SSE2: # %bb.0:
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pslld $23, %xmm1
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: cvttps2dq %xmm1, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
Expand All @@ -44,8 +44,8 @@ define <2 x i32> @var_funnnel_v2i32(<2 x i32> %x, <2 x i32> %amt) nounwind {
; SSE41-LABEL: var_funnnel_v2i32:
; SSE41: # %bb.0:
; SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: pslld $23, %xmm1
; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: cvttps2dq %xmm1, %xmm1
; SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,3,3]
Expand All @@ -61,8 +61,8 @@ define <2 x i32> @var_funnnel_v2i32(<2 x i32> %x, <2 x i32> %amt) nounwind {
; AVX1-LABEL: var_funnnel_v2i32:
; AVX1: # %bb.0:
; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpslld $23, %xmm1, %xmm1
; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vcvttps2dq %xmm1, %xmm1
; AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm1[1,1,3,3]
Expand Down Expand Up @@ -135,8 +135,8 @@ define <2 x i32> @var_funnnel_v2i32(<2 x i32> %x, <2 x i32> %amt) nounwind {
;
; X86-SSE2-LABEL: var_funnnel_v2i32:
; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: pslld $23, %xmm1
; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: cvttps2dq %xmm1, %xmm1
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/X86/vector-fshr-rot-128.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -175,8 +175,8 @@ define <4 x i32> @var_funnnel_v4i32(<4 x i32> %x, <4 x i32> %amt) nounwind {
; SSE2: # %bb.0:
; SSE2-NEXT: pxor %xmm2, %xmm2
; SSE2-NEXT: psubd %xmm1, %xmm2
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: pslld $23, %xmm2
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: cvttps2dq %xmm2, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
Expand All @@ -196,8 +196,8 @@ define <4 x i32> @var_funnnel_v4i32(<4 x i32> %x, <4 x i32> %amt) nounwind {
; SSE41: # %bb.0:
; SSE41-NEXT: pxor %xmm2, %xmm2
; SSE41-NEXT: psubd %xmm1, %xmm2
; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE41-NEXT: pslld $23, %xmm2
; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE41-NEXT: cvttps2dq %xmm2, %xmm1
; SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
Expand All @@ -215,8 +215,8 @@ define <4 x i32> @var_funnnel_v4i32(<4 x i32> %x, <4 x i32> %amt) nounwind {
; AVX1: # %bb.0:
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX1-NEXT: vpsubd %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpslld $23, %xmm1, %xmm1
; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vcvttps2dq %xmm1, %xmm1
; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
Expand Down Expand Up @@ -294,8 +294,8 @@ define <4 x i32> @var_funnnel_v4i32(<4 x i32> %x, <4 x i32> %amt) nounwind {
; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pxor %xmm2, %xmm2
; X86-SSE2-NEXT: psubd %xmm1, %xmm2
; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2
; X86-SSE2-NEXT: pslld $23, %xmm2
; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2
; X86-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2
; X86-SSE2-NEXT: cvttps2dq %xmm2, %xmm1
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/X86/vector-fshr-rot-sub128.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -26,8 +26,8 @@ define <2 x i32> @var_funnnel_v2i32(<2 x i32> %x, <2 x i32> %amt) nounwind {
; SSE2: # %bb.0:
; SSE2-NEXT: pxor %xmm2, %xmm2
; SSE2-NEXT: psubd %xmm1, %xmm2
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: pslld $23, %xmm2
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: cvttps2dq %xmm2, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
Expand All @@ -47,8 +47,8 @@ define <2 x i32> @var_funnnel_v2i32(<2 x i32> %x, <2 x i32> %amt) nounwind {
; SSE41: # %bb.0:
; SSE41-NEXT: pxor %xmm2, %xmm2
; SSE41-NEXT: psubd %xmm1, %xmm2
; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE41-NEXT: pslld $23, %xmm2
; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE41-NEXT: cvttps2dq %xmm2, %xmm1
; SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
Expand All @@ -66,8 +66,8 @@ define <2 x i32> @var_funnnel_v2i32(<2 x i32> %x, <2 x i32> %amt) nounwind {
; AVX1: # %bb.0:
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX1-NEXT: vpsubd %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpslld $23, %xmm1, %xmm1
; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vcvttps2dq %xmm1, %xmm1
; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
Expand Down Expand Up @@ -145,8 +145,8 @@ define <2 x i32> @var_funnnel_v2i32(<2 x i32> %x, <2 x i32> %amt) nounwind {
; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pxor %xmm2, %xmm2
; X86-SSE2-NEXT: psubd %xmm1, %xmm2
; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2
; X86-SSE2-NEXT: pslld $23, %xmm2
; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2
; X86-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2
; X86-SSE2-NEXT: cvttps2dq %xmm2, %xmm1
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
Expand Down
60 changes: 30 additions & 30 deletions llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -14,9 +14,9 @@ define i1 @test_v2i64(<2 x i64> %a0) {
; SSE2-LABEL: test_v2i64:
; SSE2: # %bb.0:
; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: pcmpeqb %xmm0, %xmm1
; SSE2-NEXT: pmovmskb %xmm1, %eax
; SSE2-NEXT: xorl $65535, %eax # imm = 0xFFFF
; SSE2-NEXT: pcmpeqd %xmm0, %xmm1
; SSE2-NEXT: movmskps %xmm1, %eax
; SSE2-NEXT: xorl $15, %eax
; SSE2-NEXT: sete %al
; SSE2-NEXT: retq
;
Expand All @@ -41,9 +41,9 @@ define i1 @test_v4i64(<4 x i64> %a0) {
; SSE2: # %bb.0:
; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: pcmpeqb %xmm0, %xmm1
; SSE2-NEXT: pmovmskb %xmm1, %eax
; SSE2-NEXT: xorl $65535, %eax # imm = 0xFFFF
; SSE2-NEXT: pcmpeqd %xmm0, %xmm1
; SSE2-NEXT: movmskps %xmm1, %eax
; SSE2-NEXT: xorl $15, %eax
; SSE2-NEXT: setne %al
; SSE2-NEXT: retq
;
Expand Down Expand Up @@ -72,9 +72,9 @@ define i1 @test_v8i64(<8 x i64> %a0) {
; SSE2-NEXT: por %xmm2, %xmm0
; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: pcmpeqb %xmm0, %xmm1
; SSE2-NEXT: pmovmskb %xmm1, %eax
; SSE2-NEXT: xorl $65535, %eax # imm = 0xFFFF
; SSE2-NEXT: pcmpeqd %xmm0, %xmm1
; SSE2-NEXT: movmskps %xmm1, %eax
; SSE2-NEXT: xorl $15, %eax
; SSE2-NEXT: sete %al
; SSE2-NEXT: retq
;
Expand Down Expand Up @@ -126,9 +126,9 @@ define i1 @test_v16i64(<16 x i64> %a0) {
; SSE2-NEXT: por %xmm2, %xmm0
; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: pcmpeqb %xmm0, %xmm1
; SSE2-NEXT: pmovmskb %xmm1, %eax
; SSE2-NEXT: xorl $65535, %eax # imm = 0xFFFF
; SSE2-NEXT: pcmpeqd %xmm0, %xmm1
; SSE2-NEXT: movmskps %xmm1, %eax
; SSE2-NEXT: xorl $15, %eax
; SSE2-NEXT: setne %al
; SSE2-NEXT: retq
;
Expand Down Expand Up @@ -205,9 +205,9 @@ define i1 @test_v4i32(<4 x i32> %a0) {
; SSE2-LABEL: test_v4i32:
; SSE2: # %bb.0:
; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: pcmpeqb %xmm0, %xmm1
; SSE2-NEXT: pmovmskb %xmm1, %eax
; SSE2-NEXT: xorl $65535, %eax # imm = 0xFFFF
; SSE2-NEXT: pcmpeqd %xmm0, %xmm1
; SSE2-NEXT: movmskps %xmm1, %eax
; SSE2-NEXT: xorl $15, %eax
; SSE2-NEXT: setne %al
; SSE2-NEXT: retq
;
Expand All @@ -232,9 +232,9 @@ define i1 @test_v8i32(<8 x i32> %a0) {
; SSE2: # %bb.0:
; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: pcmpeqb %xmm0, %xmm1
; SSE2-NEXT: pmovmskb %xmm1, %eax
; SSE2-NEXT: xorl $65535, %eax # imm = 0xFFFF
; SSE2-NEXT: pcmpeqd %xmm0, %xmm1
; SSE2-NEXT: movmskps %xmm1, %eax
; SSE2-NEXT: xorl $15, %eax
; SSE2-NEXT: sete %al
; SSE2-NEXT: retq
;
Expand Down Expand Up @@ -263,9 +263,9 @@ define i1 @test_v16i32(<16 x i32> %a0) {
; SSE2-NEXT: por %xmm2, %xmm0
; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: pcmpeqb %xmm0, %xmm1
; SSE2-NEXT: pmovmskb %xmm1, %eax
; SSE2-NEXT: xorl $65535, %eax # imm = 0xFFFF
; SSE2-NEXT: pcmpeqd %xmm0, %xmm1
; SSE2-NEXT: movmskps %xmm1, %eax
; SSE2-NEXT: xorl $15, %eax
; SSE2-NEXT: setne %al
; SSE2-NEXT: retq
;
Expand Down Expand Up @@ -317,9 +317,9 @@ define i1 @test_v32i32(<32 x i32> %a0) {
; SSE2-NEXT: por %xmm2, %xmm0
; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: pcmpeqb %xmm0, %xmm1
; SSE2-NEXT: pmovmskb %xmm1, %eax
; SSE2-NEXT: xorl $65535, %eax # imm = 0xFFFF
; SSE2-NEXT: pcmpeqd %xmm0, %xmm1
; SSE2-NEXT: movmskps %xmm1, %eax
; SSE2-NEXT: xorl $15, %eax
; SSE2-NEXT: sete %al
; SSE2-NEXT: retq
;
Expand Down Expand Up @@ -861,9 +861,9 @@ define i1 @trunc_v2i64(<2 x i64> %a0) {
define i1 @mask_v8i32(<8 x i32> %a0) {
; SSE2-LABEL: mask_v8i32:
; SSE2: # %bb.0:
; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: pmovmskb %xmm0, %eax
; SSE2-NEXT: testl $34952, %eax # imm = 0x8888
; SSE2-NEXT: orps %xmm1, %xmm0
; SSE2-NEXT: movmskps %xmm0, %eax
; SSE2-NEXT: testl %eax, %eax
; SSE2-NEXT: sete %al
; SSE2-NEXT: retq
;
Expand Down Expand Up @@ -1020,9 +1020,9 @@ define zeroext i1 @PR44781(ptr %0) {
; SSE2-NEXT: movdqu (%rdi), %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: pcmpeqb %xmm0, %xmm1
; SSE2-NEXT: pmovmskb %xmm1, %eax
; SSE2-NEXT: xorl $65535, %eax # imm = 0xFFFF
; SSE2-NEXT: pcmpeqd %xmm0, %xmm1
; SSE2-NEXT: movmskps %xmm1, %eax
; SSE2-NEXT: xorl $15, %eax
; SSE2-NEXT: sete %al
; SSE2-NEXT: retq
;
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/X86/vector-rotate-128.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -126,8 +126,8 @@ define <2 x i64> @var_rotate_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
define <4 x i32> @var_rotate_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
; SSE2-LABEL: var_rotate_v4i32:
; SSE2: # %bb.0:
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: pslld $23, %xmm1
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: cvttps2dq %xmm1, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
Expand All @@ -146,8 +146,8 @@ define <4 x i32> @var_rotate_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
; SSE41-LABEL: var_rotate_v4i32:
; SSE41: # %bb.0:
; SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: pslld $23, %xmm1
; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE41-NEXT: cvttps2dq %xmm1, %xmm1
; SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,3,3]
Expand All @@ -163,8 +163,8 @@ define <4 x i32> @var_rotate_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
; AVX1-LABEL: var_rotate_v4i32:
; AVX1: # %bb.0:
; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpslld $23, %xmm1, %xmm1
; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vcvttps2dq %xmm1, %xmm1
; AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm1[1,1,3,3]
Expand Down Expand Up @@ -209,8 +209,8 @@ define <4 x i32> @var_rotate_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
;
; X86-SSE2-LABEL: var_rotate_v4i32:
; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: pslld $23, %xmm1
; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: cvttps2dq %xmm1, %xmm1
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/X86/vector-shuffle-128-v16.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -769,8 +769,8 @@ define <16 x i8> @shuffle_v16i8_02_20_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu(
; SSE2: # %bb.0:
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,1,1]
; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: psrlq $16, %xmm0
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: retq
;
Expand Down
811 changes: 396 additions & 415 deletions llvm/test/CodeGen/X86/vector_splat-const-shift-of-constmasked.ll
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