diff --git a/llvm/test/CodeGen/RISCV/double-convert.ll b/llvm/test/CodeGen/RISCV/double-convert.ll
diff --git a/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll b/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
diff --git a/llvm/test/CodeGen/RISCV/float-convert.ll b/llvm/test/CodeGen/RISCV/float-convert.ll
diff --git a/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll b/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
diff --git a/llvm/test/CodeGen/RISCV/fpclamptosat.ll b/llvm/test/CodeGen/RISCV/fpclamptosat.ll
diff --git a/llvm/test/CodeGen/RISCV/half-convert.ll b/llvm/test/CodeGen/RISCV/half-convert.ll
diff --git a/llvm/test/CodeGen/RISCV/half-round-conv-sat.ll b/llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
diff --git a/llvm/test/CodeGen/RISCV/min-max.ll b/llvm/test/CodeGen/RISCV/min-max.ll
@@ -665,10 +665,9 @@ define signext i32 @smax_i32_pos_constant_trailing_zeros(i32 signext %a) {
 define signext i32 @smin_i32_negone(i32 signext %a) {
 ; NOZBB-LABEL: smin_i32_negone:
 ; NOZBB:       # %bb.0:
-; NOZBB-NEXT:    bltz a0, .LBB26_2
-; NOZBB-NEXT:  # %bb.1:
-; NOZBB-NEXT:    li a0, -1
-; NOZBB-NEXT:  .LBB26_2:
+; NOZBB-NEXT:    slti a1, a0, 0
+; NOZBB-NEXT:    addi a1, a1, -1
+; NOZBB-NEXT:    or a0, a1, a0
 ; NOZBB-NEXT:    ret
 ;
 ; ZBB-LABEL: smin_i32_negone:
@@ -684,49 +683,35 @@ define i64 @smin_i64_negone(i64 %a) {
 ; RV32I-LABEL: smin_i64_negone:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    li a2, -1
-; RV32I-NEXT:    mv a3, a0
-; RV32I-NEXT:    bge a1, a2, .LBB27_4
+; RV32I-NEXT:    beq a1, a2, .LBB27_2
 ; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    bne a1, a2, .LBB27_5
+; RV32I-NEXT:    slti a2, a1, -1
+; RV32I-NEXT:    addi a2, a2, -1
+; RV32I-NEXT:    or a0, a2, a0
 ; RV32I-NEXT:  .LBB27_2:
-; RV32I-NEXT:    bgez a1, .LBB27_6
-; RV32I-NEXT:  .LBB27_3:
-; RV32I-NEXT:    ret
-; RV32I-NEXT:  .LBB27_4:
-; RV32I-NEXT:    li a3, -1
-; RV32I-NEXT:    beq a1, a2, .LBB27_2
-; RV32I-NEXT:  .LBB27_5:
-; RV32I-NEXT:    mv a0, a3
-; RV32I-NEXT:    bltz a1, .LBB27_3
-; RV32I-NEXT:  .LBB27_6:
-; RV32I-NEXT:    li a1, -1
+; RV32I-NEXT:    slti a2, a1, 0
+; RV32I-NEXT:    addi a2, a2, -1
+; RV32I-NEXT:    or a1, a2, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: smin_i64_negone:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    bltz a0, .LBB27_2
-; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    li a0, -1
-; RV64I-NEXT:  .LBB27_2:
+; RV64I-NEXT:    slti a1, a0, 0
+; RV64I-NEXT:    addi a1, a1, -1
+; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV32ZBB-LABEL: smin_i64_negone:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    li a2, -1
-; RV32ZBB-NEXT:    mv a3, a0
-; RV32ZBB-NEXT:    bge a1, a2, .LBB27_3
+; RV32ZBB-NEXT:    beq a1, a2, .LBB27_2
 ; RV32ZBB-NEXT:  # %bb.1:
-; RV32ZBB-NEXT:    bne a1, a2, .LBB27_4
+; RV32ZBB-NEXT:    slti a3, a1, -1
+; RV32ZBB-NEXT:    addi a3, a3, -1
+; RV32ZBB-NEXT:    or a0, a3, a0
 ; RV32ZBB-NEXT:  .LBB27_2:
 ; RV32ZBB-NEXT:    min a1, a1, a2
 ; RV32ZBB-NEXT:    ret
-; RV32ZBB-NEXT:  .LBB27_3:
-; RV32ZBB-NEXT:    li a3, -1
-; RV32ZBB-NEXT:    beq a1, a2, .LBB27_2
-; RV32ZBB-NEXT:  .LBB27_4:
-; RV32ZBB-NEXT:    mv a0, a3
-; RV32ZBB-NEXT:    min a1, a1, a2
-; RV32ZBB-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: smin_i64_negone:
 ; RV64ZBB:       # %bb.0:

diff --git a/llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll b/llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll
@@ -298,32 +298,30 @@ define i32 @not_shl_one_i32(i32 %x) {
 define i64 @not_shl_one_i64(i64 %x) {
 ; RV32I-LABEL: not_shl_one_i64:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi a3, a0, -32
-; RV32I-NEXT:    li a2, 1
-; RV32I-NEXT:    li a1, -1
-; RV32I-NEXT:    bltz a3, .LBB15_2
-; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    sll a0, a2, a3
-; RV32I-NEXT:    not a1, a0
-; RV32I-NEXT:    li a0, -1
-; RV32I-NEXT:    ret
-; RV32I-NEXT:  .LBB15_2:
-; RV32I-NEXT:    sll a0, a2, a0
-; RV32I-NEXT:    not a0, a0
+; RV32I-NEXT:    li a1, 1
+; RV32I-NEXT:    sll a2, a1, a0
+; RV32I-NEXT:    addi a0, a0, -32
+; RV32I-NEXT:    sll a1, a1, a0
+; RV32I-NEXT:    slti a0, a0, 0
+; RV32I-NEXT:    neg a3, a0
+; RV32I-NEXT:    not a1, a1
+; RV32I-NEXT:    or a1, a3, a1
+; RV32I-NEXT:    not a2, a2
+; RV32I-NEXT:    addi a0, a0, -1
+; RV32I-NEXT:    or a0, a0, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBB-ZBKB-LABEL: not_shl_one_i64:
 ; RV32ZBB-ZBKB:       # %bb.0:
-; RV32ZBB-ZBKB-NEXT:    addi a3, a0, -32
+; RV32ZBB-ZBKB-NEXT:    addi a1, a0, -32
 ; RV32ZBB-ZBKB-NEXT:    li a2, -2
-; RV32ZBB-ZBKB-NEXT:    li a1, -1
-; RV32ZBB-ZBKB-NEXT:    bltz a3, .LBB15_2
-; RV32ZBB-ZBKB-NEXT:  # %bb.1:
-; RV32ZBB-ZBKB-NEXT:    rol a1, a2, a3
-; RV32ZBB-ZBKB-NEXT:    li a0, -1
-; RV32ZBB-ZBKB-NEXT:    ret
-; RV32ZBB-ZBKB-NEXT:  .LBB15_2:
+; RV32ZBB-ZBKB-NEXT:    rol a3, a2, a1
+; RV32ZBB-ZBKB-NEXT:    slti a4, a1, 0
+; RV32ZBB-ZBKB-NEXT:    neg a1, a4
+; RV32ZBB-ZBKB-NEXT:    or a1, a1, a3
 ; RV32ZBB-ZBKB-NEXT:    rol a0, a2, a0
+; RV32ZBB-ZBKB-NEXT:    addi a2, a4, -1
+; RV32ZBB-ZBKB-NEXT:    or a0, a2, a0
 ; RV32ZBB-ZBKB-NEXT:    ret
   %1 = shl i64 1, %x
   %2 = xor i64 %1, -1

diff --git a/llvm/test/CodeGen/RISCV/rv64zbb.ll b/llvm/test/CodeGen/RISCV/rv64zbb.ll
@@ -217,27 +217,23 @@ define signext i32 @findLastSet_i32(i32 signext %a) nounwind {
 ; RV64I-NEXT:    lui a1, 4112
 ; RV64I-NEXT:    addiw a1, a1, 257
 ; RV64I-NEXT:    call __muldi3@plt
-; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    li a0, -1
-; RV64I-NEXT:    beqz s0, .LBB3_2
-; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    srliw a0, a1, 24
+; RV64I-NEXT:    srliw a0, a0, 24
 ; RV64I-NEXT:    xori a0, a0, 31
-; RV64I-NEXT:  .LBB3_2:
+; RV64I-NEXT:    snez a1, s0
+; RV64I-NEXT:    addi a1, a1, -1
+; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: findLastSet_i32:
 ; RV64ZBB:       # %bb.0:
-; RV64ZBB-NEXT:    mv a1, a0
-; RV64ZBB-NEXT:    li a0, -1
-; RV64ZBB-NEXT:    beqz a1, .LBB3_2
-; RV64ZBB-NEXT:  # %bb.1:
-; RV64ZBB-NEXT:    clzw a0, a1
-; RV64ZBB-NEXT:    xori a0, a0, 31
-; RV64ZBB-NEXT:  .LBB3_2:
+; RV64ZBB-NEXT:    clzw a1, a0
+; RV64ZBB-NEXT:    xori a1, a1, 31
+; RV64ZBB-NEXT:    snez a0, a0
+; RV64ZBB-NEXT:    addi a0, a0, -1
+; RV64ZBB-NEXT:    or a0, a0, a1
 ; RV64ZBB-NEXT:    ret
   %1 = call i32 @llvm.ctlz.i32(i32 %a, i1 true)
   %2 = xor i32 31, %1
@@ -459,24 +455,20 @@ define signext i32 @findFirstSet_i32(i32 signext %a) nounwind {
 ; RV64I-NEXT:    add a0, a1, a0
 ; RV64I-NEXT:    lbu a1, 0(a0)
 ; RV64I-NEXT:  .LBB8_2:
-; RV64I-NEXT:    li a0, -1
-; RV64I-NEXT:    beqz s0, .LBB8_4
-; RV64I-NEXT:  # %bb.3:
-; RV64I-NEXT:    mv a0, a1
-; RV64I-NEXT:  .LBB8_4:
+; RV64I-NEXT:    snez a0, s0
+; RV64I-NEXT:    addi a0, a0, -1
+; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: findFirstSet_i32:
 ; RV64ZBB:       # %bb.0:
-; RV64ZBB-NEXT:    mv a1, a0
-; RV64ZBB-NEXT:    li a0, -1
-; RV64ZBB-NEXT:    beqz a1, .LBB8_2
-; RV64ZBB-NEXT:  # %bb.1:
-; RV64ZBB-NEXT:    ctzw a0, a1
-; RV64ZBB-NEXT:  .LBB8_2:
+; RV64ZBB-NEXT:    ctzw a1, a0
+; RV64ZBB-NEXT:    snez a0, a0
+; RV64ZBB-NEXT:    addi a0, a0, -1
+; RV64ZBB-NEXT:    or a0, a0, a1
 ; RV64ZBB-NEXT:    ret
   %1 = call i32 @llvm.cttz.i32(i32 %a, i1 true)
   %2 = icmp eq i32 %a, 0

diff --git a/llvm/test/CodeGen/RISCV/uadd_sat.ll b/llvm/test/CodeGen/RISCV/uadd_sat.ll
@@ -13,24 +13,18 @@ declare i64 @llvm.uadd.sat.i64(i64, i64)
 define signext i32 @func(i32 signext %x, i32 signext %y) nounwind {
 ; RV32I-LABEL: func:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    mv a2, a0
 ; RV32I-NEXT:    add a1, a0, a1
-; RV32I-NEXT:    li a0, -1
-; RV32I-NEXT:    bltu a1, a2, .LBB0_2
-; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    mv a0, a1
-; RV32I-NEXT:  .LBB0_2:
+; RV32I-NEXT:    sltu a0, a1, a0
+; RV32I-NEXT:    neg a0, a0
+; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    mv a2, a0
 ; RV64I-NEXT:    addw a1, a0, a1
-; RV64I-NEXT:    li a0, -1
-; RV64I-NEXT:    bltu a1, a2, .LBB0_2
-; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    mv a0, a1
-; RV64I-NEXT:  .LBB0_2:
+; RV64I-NEXT:    sltu a0, a1, a0
+; RV64I-NEXT:    neg a0, a0
+; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV32IZbb-LABEL: func:
@@ -55,49 +49,40 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    add a3, a1, a3
 ; RV32I-NEXT:    add a2, a0, a2
-; RV32I-NEXT:    sltu a4, a2, a0
-; RV32I-NEXT:    add a3, a3, a4
+; RV32I-NEXT:    sltu a0, a2, a0
+; RV32I-NEXT:    add a3, a3, a0
 ; RV32I-NEXT:    beq a3, a1, .LBB1_2
 ; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    sltu a4, a3, a1
+; RV32I-NEXT:    sltu a0, a3, a1
 ; RV32I-NEXT:  .LBB1_2:
-; RV32I-NEXT:    li a0, -1
-; RV32I-NEXT:    li a1, -1
-; RV32I-NEXT:    bnez a4, .LBB1_4
-; RV32I-NEXT:  # %bb.3:
-; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    mv a1, a3
-; RV32I-NEXT:  .LBB1_4:
+; RV32I-NEXT:    seqz a0, a0
+; RV32I-NEXT:    addi a1, a0, -1
+; RV32I-NEXT:    or a0, a1, a2
+; RV32I-NEXT:    or a1, a1, a3
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func2:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    mv a2, a0
 ; RV64I-NEXT:    add a1, a0, a1
-; RV64I-NEXT:    li a0, -1
-; RV64I-NEXT:    bltu a1, a2, .LBB1_2
-; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    mv a0, a1
-; RV64I-NEXT:  .LBB1_2:
+; RV64I-NEXT:    sltu a0, a1, a0
+; RV64I-NEXT:    neg a0, a0
+; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV32IZbb-LABEL: func2:
 ; RV32IZbb:       # %bb.0:
 ; RV32IZbb-NEXT:    add a3, a1, a3
 ; RV32IZbb-NEXT:    add a2, a0, a2
-; RV32IZbb-NEXT:    sltu a4, a2, a0
-; RV32IZbb-NEXT:    add a3, a3, a4
+; RV32IZbb-NEXT:    sltu a0, a2, a0
+; RV32IZbb-NEXT:    add a3, a3, a0
 ; RV32IZbb-NEXT:    beq a3, a1, .LBB1_2
 ; RV32IZbb-NEXT:  # %bb.1:
-; RV32IZbb-NEXT:    sltu a4, a3, a1
+; RV32IZbb-NEXT:    sltu a0, a3, a1
 ; RV32IZbb-NEXT:  .LBB1_2:
-; RV32IZbb-NEXT:    li a0, -1
-; RV32IZbb-NEXT:    li a1, -1
-; RV32IZbb-NEXT:    bnez a4, .LBB1_4
-; RV32IZbb-NEXT:  # %bb.3:
-; RV32IZbb-NEXT:    mv a0, a2
-; RV32IZbb-NEXT:    mv a1, a3
-; RV32IZbb-NEXT:  .LBB1_4:
+; RV32IZbb-NEXT:    seqz a0, a0
+; RV32IZbb-NEXT:    addi a1, a0, -1
+; RV32IZbb-NEXT:    or a0, a1, a2
+; RV32IZbb-NEXT:    or a1, a1, a3
 ; RV32IZbb-NEXT:    ret
 ;
 ; RV64IZbb-LABEL: func2:

diff --git a/llvm/test/CodeGen/RISCV/uadd_sat_plus.ll b/llvm/test/CodeGen/RISCV/uadd_sat_plus.ll
@@ -13,26 +13,21 @@ declare i64 @llvm.uadd.sat.i64(i64, i64)
 define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
 ; RV32I-LABEL: func32:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    mv a3, a0
-; RV32I-NEXT:    mul a0, a1, a2
-; RV32I-NEXT:    add a1, a3, a0
-; RV32I-NEXT:    li a0, -1
-; RV32I-NEXT:    bltu a1, a3, .LBB0_2
-; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    mv a0, a1
-; RV32I-NEXT:  .LBB0_2:
+; RV32I-NEXT:    mul a1, a1, a2
+; RV32I-NEXT:    add a1, a0, a1
+; RV32I-NEXT:    sltu a0, a1, a0
+; RV32I-NEXT:    neg a0, a0
+; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func32:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    mulw a1, a1, a2
 ; RV64I-NEXT:    addw a1, a0, a1
-; RV64I-NEXT:    sext.w a2, a0
-; RV64I-NEXT:    li a0, -1
-; RV64I-NEXT:    bltu a1, a2, .LBB0_2
-; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    mv a0, a1
-; RV64I-NEXT:  .LBB0_2:
+; RV64I-NEXT:    sext.w a0, a0
+; RV64I-NEXT:    sltu a0, a1, a0
+; RV64I-NEXT:    neg a0, a0
+; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV32IZbb-LABEL: func32:
@@ -61,49 +56,40 @@ define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    add a3, a1, a5
 ; RV32I-NEXT:    add a2, a0, a4
-; RV32I-NEXT:    sltu a4, a2, a0
-; RV32I-NEXT:    add a3, a3, a4
+; RV32I-NEXT:    sltu a0, a2, a0
+; RV32I-NEXT:    add a3, a3, a0
 ; RV32I-NEXT:    beq a3, a1, .LBB1_2
 ; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    sltu a4, a3, a1
+; RV32I-NEXT:    sltu a0, a3, a1
 ; RV32I-NEXT:  .LBB1_2:
-; RV32I-NEXT:    li a0, -1
-; RV32I-NEXT:    li a1, -1
-; RV32I-NEXT:    bnez a4, .LBB1_4
-; RV32I-NEXT:  # %bb.3:
-; RV32I-NEXT:    mv a0, a2
-; RV32I-NEXT:    mv a1, a3
-; RV32I-NEXT:  .LBB1_4:
+; RV32I-NEXT:    seqz a0, a0
+; RV32I-NEXT:    addi a1, a0, -1
+; RV32I-NEXT:    or a0, a1, a2
+; RV32I-NEXT:    or a1, a1, a3
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func64:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    add a2, a0, a2
-; RV64I-NEXT:    li a0, -1
-; RV64I-NEXT:    bltu a2, a1, .LBB1_2
-; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    mv a0, a2
-; RV64I-NEXT:  .LBB1_2:
+; RV64I-NEXT:    add a1, a0, a2
+; RV64I-NEXT:    sltu a0, a1, a0
+; RV64I-NEXT:    neg a0, a0
+; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV32IZbb-LABEL: func64:
 ; RV32IZbb:       # %bb.0:
 ; RV32IZbb-NEXT:    add a3, a1, a5
 ; RV32IZbb-NEXT:    add a2, a0, a4
-; RV32IZbb-NEXT:    sltu a4, a2, a0
-; RV32IZbb-NEXT:    add a3, a3, a4
+; RV32IZbb-NEXT:    sltu a0, a2, a0
+; RV32IZbb-NEXT:    add a3, a3, a0
 ; RV32IZbb-NEXT:    beq a3, a1, .LBB1_2
 ; RV32IZbb-NEXT:  # %bb.1:
-; RV32IZbb-NEXT:    sltu a4, a3, a1
+; RV32IZbb-NEXT:    sltu a0, a3, a1
 ; RV32IZbb-NEXT:  .LBB1_2:
-; RV32IZbb-NEXT:    li a0, -1
-; RV32IZbb-NEXT:    li a1, -1
-; RV32IZbb-NEXT:    bnez a4, .LBB1_4
-; RV32IZbb-NEXT:  # %bb.3:
-; RV32IZbb-NEXT:    mv a0, a2
-; RV32IZbb-NEXT:    mv a1, a3
-; RV32IZbb-NEXT:  .LBB1_4:
+; RV32IZbb-NEXT:    seqz a0, a0
+; RV32IZbb-NEXT:    addi a1, a0, -1
+; RV32IZbb-NEXT:    or a0, a1, a2
+; RV32IZbb-NEXT:    or a1, a1, a3
 ; RV32IZbb-NEXT:    ret
 ;
 ; RV64IZbb-LABEL: func64: