79 changes: 0 additions & 79 deletions llvm/test/CodeGen/AArch64/dag-combine-setcc.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -128,82 +128,3 @@ define i1 @combine_setcc_ne_vecreduce_or_v64i1(<64 x i8> %a) {
%cmp2 = icmp ne i64 %cast, zeroinitializer
ret i1 %cmp2
}

define i1 @combine_setcc_eq0_conjunction_xor_or(ptr %a, ptr %b) {
; CHECK-LABEL: combine_setcc_eq0_conjunction_xor_or:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp x8, x9, [x0]
; CHECK-NEXT: ldp x10, x11, [x1]
; CHECK-NEXT: cmp x8, x10
; CHECK-NEXT: ccmp x9, x11, #0, eq
; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: ret
%bcmp = tail call i32 @bcmp(ptr dereferenceable(16) %a, ptr dereferenceable(16) %b, i64 16)
%cmp = icmp eq i32 %bcmp, 0
ret i1 %cmp
}

define i1 @combine_setcc_ne0_conjunction_xor_or(ptr %a, ptr %b) {
; CHECK-LABEL: combine_setcc_ne0_conjunction_xor_or:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp x8, x9, [x0]
; CHECK-NEXT: ldp x10, x11, [x1]
; CHECK-NEXT: cmp x8, x10
; CHECK-NEXT: ccmp x9, x11, #0, eq
; CHECK-NEXT: cset w0, ne
; CHECK-NEXT: ret
%bcmp = tail call i32 @bcmp(ptr dereferenceable(16) %a, ptr dereferenceable(16) %b, i64 16)
%cmp = icmp ne i32 %bcmp, 0
ret i1 %cmp
}

; Doesn't increase the number of instructions, where the LHS has multiple uses
define i32 @combine_setcc_multiuse(i32 %0, i32 %1, i32 %2, i32 %3) {
; CHECK-LABEL: combine_setcc_multiuse:
; CHECK: // %bb.0:
; CHECK-NEXT: eor w8, w1, w0
; CHECK-NEXT: eor w9, w3, w2
; CHECK-NEXT: orr w8, w9, w8
; CHECK-NEXT: cbz w8, .LBB10_2
; CHECK-NEXT: // %bb.1:
; CHECK-NEXT: mov w0, w8
; CHECK-NEXT: b use
; CHECK-NEXT: .LBB10_2:
; CHECK-NEXT: ret
%5 = xor i32 %1, %0
%6 = xor i32 %3, %2
%7 = or i32 %6, %5
%8 = icmp eq i32 %7, 0
br i1 %8, label %11, label %9

9: ; preds = %4
%10 = tail call i32 @use(i32 %7) #2
br label %11

11: ; preds = %4, %9
%12 = phi i32 [ %10, %9 ], [ %0, %4 ]
ret i32 %12
}

; There may be issues with the CMP/CCMP with the scheduling of instructions
; that ISel will create out of the DAG
define i32 @combine_setcc_glue(i128 noundef %x, i128 noundef %y) {
; CHECK-LABEL: combine_setcc_glue:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: cmp x0, x2
; CHECK-NEXT: ccmp x1, x3, #0, eq
; CHECK-NEXT: ccmp x0, x2, #4, ne
; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: ret
entry:
%cmp3 = icmp eq i128 %x, %y
%conv = trunc i128 %x to i64
%conv1 = trunc i128 %y to i64
%cmp = icmp eq i64 %conv, %conv1
%or7 = or i1 %cmp3, %cmp
%or = zext i1 %or7 to i32
ret i32 %or
}

declare i32 @bcmp(ptr nocapture, ptr nocapture, i64)
declare i32 @use(i32 noundef)
26 changes: 16 additions & 10 deletions llvm/test/CodeGen/AArch64/i128-cmp.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -6,8 +6,10 @@ declare void @call()
define i1 @cmp_i128_eq(i128 %a, i128 %b) {
; CHECK-LABEL: cmp_i128_eq:
; CHECK: // %bb.0:
; CHECK-NEXT: cmp x0, x2
; CHECK-NEXT: ccmp x1, x3, #0, eq
; CHECK-NEXT: eor x8, x1, x3
; CHECK-NEXT: eor x9, x0, x2
; CHECK-NEXT: orr x8, x9, x8
; CHECK-NEXT: cmp x8, #0
; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: ret
%cmp = icmp eq i128 %a, %b
Expand All @@ -17,8 +19,10 @@ define i1 @cmp_i128_eq(i128 %a, i128 %b) {
define i1 @cmp_i128_ne(i128 %a, i128 %b) {
; CHECK-LABEL: cmp_i128_ne:
; CHECK: // %bb.0:
; CHECK-NEXT: cmp x0, x2
; CHECK-NEXT: ccmp x1, x3, #0, eq
; CHECK-NEXT: eor x8, x1, x3
; CHECK-NEXT: eor x9, x0, x2
; CHECK-NEXT: orr x8, x9, x8
; CHECK-NEXT: cmp x8, #0
; CHECK-NEXT: cset w0, ne
; CHECK-NEXT: ret
%cmp = icmp ne i128 %a, %b
Expand Down Expand Up @@ -116,9 +120,10 @@ define i1 @cmp_i128_sle(i128 %a, i128 %b) {
define void @br_on_cmp_i128_eq(i128 %a, i128 %b) nounwind {
; CHECK-LABEL: br_on_cmp_i128_eq:
; CHECK: // %bb.0:
; CHECK-NEXT: cmp x0, x2
; CHECK-NEXT: ccmp x1, x3, #0, eq
; CHECK-NEXT: b.ne .LBB10_2
; CHECK-NEXT: eor x8, x1, x3
; CHECK-NEXT: eor x9, x0, x2
; CHECK-NEXT: orr x8, x9, x8
; CHECK-NEXT: cbnz x8, .LBB10_2
; CHECK-NEXT: // %bb.1: // %call
; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: bl call
Expand All @@ -137,9 +142,10 @@ exit:
define void @br_on_cmp_i128_ne(i128 %a, i128 %b) nounwind {
; CHECK-LABEL: br_on_cmp_i128_ne:
; CHECK: // %bb.0:
; CHECK-NEXT: cmp x0, x2
; CHECK-NEXT: ccmp x1, x3, #0, eq
; CHECK-NEXT: b.eq .LBB11_2
; CHECK-NEXT: eor x8, x1, x3
; CHECK-NEXT: eor x9, x0, x2
; CHECK-NEXT: orr x8, x9, x8
; CHECK-NEXT: cbz x8, .LBB11_2
; CHECK-NEXT: // %bb.1: // %call
; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: bl call
Expand Down
8 changes: 5 additions & 3 deletions llvm/test/CodeGen/AArch64/umulo-128-legalisation-lowering.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -68,10 +68,12 @@ define i128 @__muloti4(i128 %0, i128 %1, i32* nocapture nonnull writeonly align
; AARCH-NEXT: adds x11, x12, x11
; AARCH-NEXT: adc x12, x13, x14
; AARCH-NEXT: adds x10, x11, x10
; AARCH-NEXT: asr x11, x1, #63
; AARCH-NEXT: adc x9, x12, x9
; AARCH-NEXT: cmp x10, x11
; AARCH-NEXT: ccmp x9, x11, #0, eq
; AARCH-NEXT: asr x11, x1, #63
; AARCH-NEXT: eor x9, x9, x11
; AARCH-NEXT: eor x10, x10, x11
; AARCH-NEXT: orr x9, x10, x9
; AARCH-NEXT: cmp x9, #0
; AARCH-NEXT: cset w9, ne
; AARCH-NEXT: tbz x8, #63, .LBB1_2
; AARCH-NEXT: // %bb.1: // %Entry
Expand Down