99 changes: 81 additions & 18 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,27 @@

---

name: zext_sgpr_s1_to_sgpr_s16
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $sgpr0
; GCN-LABEL: name: zext_sgpr_s1_to_sgpr_s16
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 1, implicit-def $scc
; GCN-NEXT: [[S_SEXT_I32_I16_:%[0-9]+]]:sreg_32 = S_SEXT_I32_I16 [[S_AND_B32_]]
; GCN-NEXT: $sgpr0 = COPY [[S_SEXT_I32_I16_]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s1) = G_TRUNC %0
%2:sgpr(s16) = G_ZEXT %1
%3:sgpr(s32) = G_SEXT %2
$sgpr0 = COPY %3
...

---

name: zext_sgpr_s1_to_sgpr_s32
legalized: true
regBankSelected: true
Expand All @@ -12,8 +33,8 @@ body: |
; GCN-LABEL: name: zext_sgpr_s1_to_sgpr_s32
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 1, implicit-def $scc
; GCN: $sgpr0 = COPY [[S_AND_B32_]]
; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 1, implicit-def $scc
; GCN-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s1) = G_TRUNC %0
%2:sgpr(s32) = G_ZEXT %1
Expand All @@ -31,10 +52,10 @@ body: |
; GCN-LABEL: name: zext_sgpr_s1_to_sgpr_s64
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
; GCN: [[S_BFE_U64_:%[0-9]+]]:sreg_64 = S_BFE_U64 [[REG_SEQUENCE]], 65536, implicit-def $scc
; GCN: $sgpr0_sgpr1 = COPY [[S_BFE_U64_]]
; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
; GCN-NEXT: [[S_BFE_U64_:%[0-9]+]]:sreg_64 = S_BFE_U64 [[REG_SEQUENCE]], 65536, implicit-def $scc
; GCN-NEXT: $sgpr0_sgpr1 = COPY [[S_BFE_U64_]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s1) = G_TRUNC %0
%2:sgpr(s64) = G_ZEXT %1
Expand All @@ -52,8 +73,8 @@ body: |
; GCN-LABEL: name: zext_sgpr_s16_to_sgpr_s32
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[S_BFE_U32_:%[0-9]+]]:sreg_32 = S_BFE_U32 [[COPY]], 1048576, implicit-def $scc
; GCN: $sgpr0 = COPY [[S_BFE_U32_]]
; GCN-NEXT: [[S_BFE_U32_:%[0-9]+]]:sreg_32 = S_BFE_U32 [[COPY]], 1048576, implicit-def $scc
; GCN-NEXT: $sgpr0 = COPY [[S_BFE_U32_]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s16) = G_TRUNC %0
%2:sgpr(s32) = G_ZEXT %1
Expand All @@ -72,17 +93,38 @@ body: |
; GCN-LABEL: name: zext_sgpr_s16_to_sgpr_s64
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
; GCN: [[S_BFE_U64_:%[0-9]+]]:sreg_64 = S_BFE_U64 [[REG_SEQUENCE]], 1048576, implicit-def $scc
; GCN: $sgpr0_sgpr1 = COPY [[S_BFE_U64_]]
; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
; GCN-NEXT: [[S_BFE_U64_:%[0-9]+]]:sreg_64 = S_BFE_U64 [[REG_SEQUENCE]], 1048576, implicit-def $scc
; GCN-NEXT: $sgpr0_sgpr1 = COPY [[S_BFE_U64_]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s16) = G_TRUNC %0
%2:sgpr(s64) = G_ZEXT %1
$sgpr0_sgpr1 = COPY %2
...

---

name: zext_sgpr_s32_to_sgpr_s64
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $sgpr0
; GCN-LABEL: name: zext_sgpr_s32_to_sgpr_s64
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
; GCN-NEXT: [[S_BFE_U64_:%[0-9]+]]:sreg_64 = S_BFE_U64 [[REG_SEQUENCE]], 2097152, implicit-def $scc
; GCN-NEXT: $sgpr0_sgpr1 = COPY [[S_BFE_U64_]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s64) = G_ZEXT %0
$sgpr0_sgpr1 = COPY %1
...

# ---

# name: zext_vcc_s1_to_vgpr_s32
Expand All @@ -100,6 +142,27 @@ body: |

---

name: zext_vgpr_s1_to_vgpr_s16
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0
; GCN-LABEL: name: zext_vgpr_s1_to_vgpr_s16
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
; GCN-NEXT: [[V_BFE_I32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_I32_e64 [[V_AND_B32_e32_]], 0, 16, implicit $exec
; GCN-NEXT: $vgpr0 = COPY [[V_BFE_I32_e64_]]
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s1) = G_TRUNC %0
%2:vgpr(s16) = G_ZEXT %1
%3:vgpr(s32) = G_SEXT %2
$vgpr0 = COPY %3
...

---

name: zext_vgpr_s1_to_vgpr_s32
legalized: true
regBankSelected: true
Expand All @@ -109,8 +172,8 @@ body: |
; GCN-LABEL: name: zext_vgpr_s1_to_vgpr_s32
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
; GCN: $vgpr0 = COPY [[V_AND_B32_e32_]]
; GCN-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
; GCN-NEXT: $vgpr0 = COPY [[V_AND_B32_e32_]]
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s1) = G_TRUNC %0
%2:vgpr(s32) = G_ZEXT %1
Expand All @@ -128,8 +191,8 @@ body: |
; GCN-LABEL: name: zext_vgpr_s16_to_vgpr_s32
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[V_BFE_U32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_U32_e64 [[COPY]], 0, 16, implicit $exec
; GCN: $vgpr0 = COPY [[V_BFE_U32_e64_]]
; GCN-NEXT: [[V_BFE_U32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_U32_e64 [[COPY]], 0, 16, implicit $exec
; GCN-NEXT: $vgpr0 = COPY [[V_BFE_U32_e64_]]
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s16) = G_TRUNC %0
%2:vgpr(s32) = G_ZEXT %1
Expand All @@ -148,8 +211,8 @@ body: |
; GCN-LABEL: name: zext_sgpr_reg_class_s1_to_sgpr_s32
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 1, implicit-def $scc
; GCN: $sgpr0 = COPY [[S_AND_B32_]]
; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 1, implicit-def $scc
; GCN-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
%0:sgpr(s32) = COPY $sgpr0
%1:sreg_32(s1) = G_TRUNC %0
%2:sgpr(s32) = G_ZEXT %1
Expand Down