104 changes: 104 additions & 0 deletions llvm/test/CodeGen/AArch64/copyprop.mir
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@@ -0,0 +1,104 @@
# RUN: llc -mtriple=aarch64-linux-gnu -run-pass machine-cp -o - %s | FileCheck %s
# Tests for MachineCopyPropagation copy forwarding.
---
# Simple forwarding.
# CHECK-LABEL: name: test1
# CHECK: $x0 = SUBXri $x0, 1, 0
name: test1
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
renamable $x1 = COPY $x0
$x0 = SUBXri renamable $x1, 1, 0
...
---
# Don't forward if not renamable.
# CHECK-LABEL: name: test2
# CHECK: $x0 = SUBXri $x1, 1, 0
name: test2
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
$x1 = COPY $x0
$x0 = SUBXri $x1, 1, 0
...
---
# Don't forward reserved non-constant reg values.
# CHECK-LABEL: name: test4
# CHECK: $x0 = SUBXri renamable $x1, 1, 0
name: test4
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
$sp = SUBXri $sp, 16, 0
renamable $x1 = COPY $sp
$x0 = SUBXri renamable $x1, 1, 0
$sp = ADDXri $sp, 16, 0
...
---
# Don't violate opcode constraints when forwarding.
# CHECK-LABEL: name: test5
# CHECK: $x0 = SUBXri renamable $x1, 1, 0
name: test5
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
renamable $x1 = COPY $xzr
$x0 = SUBXri renamable $x1, 1, 0
...
---
# Test cross-class COPY forwarding.
# CHECK-LABEL: name: test6
# CHECK: $x2 = COPY $x0
name: test6
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
renamable $d1 = COPY $x0
$x2 = COPY renamable $d1
RET_ReallyLR implicit $x2
...
---
# Don't forward if there are overlapping implicit operands.
# CHECK-LABEL: name: test7
# CHECK: $w0 = SUBWri killed renamable $w1, 1, 0
name: test7
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0
renamable $w1 = COPY $w0
$w0 = SUBWri killed renamable $w1, 1, 0, implicit killed $x1
...
---
# Check that kill flags are cleared.
# CHECK-LABEL: name: test8
# CHECK: $x2 = ADDXri $x0, 1, 0
# CHECK: $x0 = SUBXri $x0, 1, 0
name: test8
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
renamable $x1 = COPY $x0
$x2 = ADDXri killed $x0, 1, 0
$x0 = SUBXri renamable $x1, 1, 0
...
---
# Don't forward if value is clobbered.
# CHECK-LABEL: name: test9
# CHECK: $x2 = SUBXri renamable $x1, 1, 0
name: test9
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
renamable $x1 = COPY $x0
$x0 = ADDXri $x0, 1, 0
$x2 = SUBXri renamable $x1, 1, 0
...
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AArch64/f16-instructions.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -489,7 +489,7 @@ else:

; CHECK-COMMON-LABEL: test_phi:
; CHECK-COMMON: mov x[[PTR:[0-9]+]], x0
; CHECK-COMMON: ldr h[[AB:[0-9]+]], [x[[PTR]]]
; CHECK-COMMON: ldr h[[AB:[0-9]+]], [x0]
; CHECK-COMMON: [[LOOP:LBB[0-9_]+]]:
; CHECK-COMMON: mov.16b v[[R:[0-9]+]], v[[AB]]
; CHECK-COMMON: ldr h[[AB]], [x[[PTR]]]
Expand Down
5 changes: 4 additions & 1 deletion llvm/test/CodeGen/AArch64/flags-multiuse.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -17,6 +17,9 @@ define i32 @test_multiflag(i32 %n, i32 %m, i32 %o) {
%val = zext i1 %test to i32
; CHECK: cset {{[xw][0-9]+}}, ne

; CHECK: mov [[RHSCOPY:w[0-9]+]], [[RHS]]
; CHECK: mov [[LHSCOPY:w[0-9]+]], [[LHS]]

store i32 %val, i32* @var

call void @bar()
Expand All @@ -25,7 +28,7 @@ define i32 @test_multiflag(i32 %n, i32 %m, i32 %o) {
; Currently, the comparison is emitted again. An MSR/MRS pair would also be
; acceptable, but assuming the call preserves NZCV is not.
br i1 %test, label %iftrue, label %iffalse
; CHECK: cmp [[LHS]], [[RHS]]
; CHECK: cmp [[LHSCOPY]], [[RHSCOPY]]
; CHECK: b.eq

iftrue:
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AArch64/ldst-opt.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -1671,7 +1671,7 @@ entry:
; CHECK-LABEL: bug34674:
; CHECK: // %entry
; CHECK-NEXT: mov [[ZREG:x[0-9]+]], xzr
; CHECK-DAG: stp [[ZREG]], [[ZREG]], [x0]
; CHECK-DAG: stp xzr, xzr, [x0]
; CHECK-DAG: add x{{[0-9]+}}, [[ZREG]], #1
define i64 @bug34674(<2 x i64>* %p) {
entry:
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AArch64/merge-store-dependency.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@ entry:
; A53: mov [[DATA:w[0-9]+]], w1
; A53: str q{{[0-9]+}}, {{.*}}
; A53: str q{{[0-9]+}}, {{.*}}
; A53: str [[DATA]], {{.*}}
; A53: str w1, {{.*}}

%0 = bitcast %struct1* %fde to i8*
tail call void @llvm.memset.p0i8.i64(i8* align 8 %0, i8 0, i64 40, i1 false)
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AArch64/neg-imm.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -7,8 +7,8 @@ declare void @foo(i32)
define void @test(i32 %px) {
; CHECK_LABEL: test:
; CHECK_LABEL: %entry
; CHECK: subs
; CHECK-NEXT: csel
; CHECK: subs [[REG0:w[0-9]+]],
; CHECK: csel {{w[0-9]+}}, wzr, [[REG0]]
entry:
%sub = add nsw i32 %px, -1
%cmp = icmp slt i32 %px, 1
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/AArch64/swifterror.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -41,7 +41,7 @@ define float @caller(i8* %error_ref) {
; CHECK-APPLE: mov x21, xzr
; CHECK-APPLE: bl {{.*}}foo
; CHECK-APPLE: mov x0, x21
; CHECK-APPLE: cbnz x0
; CHECK-APPLE: cbnz x21
; Access part of the error object and save it to error_ref
; CHECK-APPLE: ldrb [[CODE:w[0-9]+]], [x0, #8]
; CHECK-APPLE: strb [[CODE]], [{{.*}}[[ID]]]
Expand Down Expand Up @@ -264,7 +264,7 @@ define float @caller3(i8* %error_ref) {
; CHECK-APPLE: mov x21, xzr
; CHECK-APPLE: bl {{.*}}foo_sret
; CHECK-APPLE: mov x0, x21
; CHECK-APPLE: cbnz x0
; CHECK-APPLE: cbnz x21
; Access part of the error object and save it to error_ref
; CHECK-APPLE: ldrb [[CODE:w[0-9]+]], [x0, #8]
; CHECK-APPLE: strb [[CODE]], [{{.*}}[[ID]]]
Expand Down Expand Up @@ -358,7 +358,7 @@ define float @caller4(i8* %error_ref) {
; CHECK-APPLE: mov x21, xzr
; CHECK-APPLE: bl {{.*}}foo_vararg
; CHECK-APPLE: mov x0, x21
; CHECK-APPLE: cbnz x0
; CHECK-APPLE: cbnz x21
; Access part of the error object and save it to error_ref
; CHECK-APPLE: ldrb [[CODE:w[0-9]+]], [x0, #8]
; CHECK-APPLE: strb [[CODE]], [{{.*}}[[ID]]]
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -547,16 +547,16 @@ define void @func_use_every_sgpr_input_call_use_workgroup_id_xyz() #1 {
; GCN: s_mov_b32 s5, s32
; GCN: s_add_u32 s32, s32, 0x300

; GCN-DAG: s_mov_b32 [[SAVE_X:s[0-9]+]], s14
; GCN-DAG: s_mov_b32 [[SAVE_Y:s[0-9]+]], s15
; GCN-DAG: s_mov_b32 [[SAVE_Z:s[0-9]+]], s16
; GCN-DAG: s_mov_b32 [[SAVE_X:s[0-57-9][0-9]*]], s14
; GCN-DAG: s_mov_b32 [[SAVE_Y:s[0-68-9][0-9]*]], s15
; GCN-DAG: s_mov_b32 [[SAVE_Z:s[0-79][0-9]*]], s16
; GCN-DAG: s_mov_b64 {{s\[[0-9]+:[0-9]+\]}}, s[6:7]
; GCN-DAG: s_mov_b64 {{s\[[0-9]+:[0-9]+\]}}, s[8:9]
; GCN-DAG: s_mov_b64 {{s\[[0-9]+:[0-9]+\]}}, s[10:11]

; GCN-DAG: s_mov_b32 s6, [[SAVE_X]]
; GCN-DAG: s_mov_b32 s7, [[SAVE_Y]]
; GCN-DAG: s_mov_b32 s8, [[SAVE_Z]]
; GCN-DAG: s_mov_b32 s6, s14
; GCN-DAG: s_mov_b32 s7, s15
; GCN-DAG: s_mov_b32 s8, s16
; GCN: s_swappc_b64

; GCN: buffer_store_dword v{{[0-9]+}}, off, s[0:3], s5 offset:4
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/fix-vgpr-copies.mir
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Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
# RUN: llc -march=amdgcn -start-after=greedy -stop-after=si-optimize-exec-masking -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -start-after=greedy -disable-copyprop -stop-after=si-optimize-exec-masking -o - %s | FileCheck %s
# Check that we first do all vector instructions and only then change exec
# CHECK-DAG: COPY $vgpr10_vgpr11
# CHECK-DAG: COPY $vgpr12_vgpr13
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/multilevel-break.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -78,7 +78,7 @@ ENDIF: ; preds = %LOOP

; Uses a copy intsead of an or
; GCN: s_mov_b64 [[COPY:s\[[0-9]+:[0-9]+\]]], [[BREAK_REG]]
; GCN: s_or_b64 [[BREAK_REG]], exec, [[COPY]]
; GCN: s_or_b64 [[BREAK_REG]], exec, [[BREAK_REG]]
define amdgpu_kernel void @multi_if_break_loop(i32 %arg) #0 {
bb:
%id = call i32 @llvm.amdgcn.workitem.id.x()
Expand Down
18 changes: 9 additions & 9 deletions llvm/test/CodeGen/AMDGPU/ret.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -2,10 +2,10 @@
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s

; GCN-LABEL: {{^}}vgpr:
; GCN: v_mov_b32_e32 v1, v0
; GCN-DAG: v_add_f32_e32 v0, 1.0, v1
; GCN-DAG: exp mrt0 v1, v1, v1, v1 done vm
; GCN-DAG: v_mov_b32_e32 v1, v0
; GCN-DAG: exp mrt0 v0, v0, v0, v0 done vm
; GCN: s_waitcnt expcnt(0)
; GCN: v_add_f32_e32 v0, 1.0, v1
; GCN-NOT: s_endpgm
define amdgpu_vs { float, float } @vgpr([9 x <16 x i8>] addrspace(4)* byval %arg, i32 inreg %arg1, i32 inreg %arg2, float %arg3) #0 {
bb:
Expand Down Expand Up @@ -179,7 +179,7 @@ bb:

; GCN-LABEL: {{^}}sgpr:
; GCN: s_mov_b32 s2, s3
; GCN: s_add_i32 s0, s2, 2
; GCN: s_add_i32 s0, s3, 2
; GCN-NOT: s_endpgm
define amdgpu_vs { i32, i32, i32 } @sgpr([9 x <16 x i8>] addrspace(4)* byval %arg, i32 inreg %arg1, i32 inreg %arg2, float %arg3) #0 {
bb:
Expand All @@ -204,13 +204,13 @@ bb:
}

; GCN-LABEL: {{^}}both:
; GCN: v_mov_b32_e32 v1, v0
; GCN-DAG: exp mrt0 v1, v1, v1, v1 done vm
; GCN-DAG: v_add_f32_e32 v0, 1.0, v1
; GCN-DAG: s_add_i32 s0, s3, 2
; GCN-DAG: exp mrt0 v0, v0, v0, v0 done vm
; GCN-DAG: v_mov_b32_e32 v1, v0
; GCN-DAG: s_mov_b32 s1, s2
; GCN: s_mov_b32 s2, s3
; GCN: s_waitcnt expcnt(0)
; GCN: v_add_f32_e32 v0, 1.0, v1
; GCN-DAG: s_add_i32 s0, s3, 2
; GCN-DAG: s_mov_b32 s2, s3
; GCN-NOT: s_endpgm
define amdgpu_vs { float, i32, float, i32, i32 } @both([9 x <16 x i8>] addrspace(4)* byval %arg, i32 inreg %arg1, i32 inreg %arg2, float %arg3) #0 {
bb:
Expand Down
6 changes: 4 additions & 2 deletions llvm/test/CodeGen/ARM/atomic-op.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -287,7 +287,8 @@ define i32 @test_cmpxchg_fail_order(i32 *%addr, i32 %desired, i32 %new) {

%pair = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst monotonic
%oldval = extractvalue { i32, i1 } %pair, 0
; CHECK-ARMV7: ldrex [[OLDVAL:r[0-9]+]], [r[[ADDR:[0-9]+]]]
; CHECK-ARMV7: mov r[[ADDR:[0-9]+]], r0
; CHECK-ARMV7: ldrex [[OLDVAL:r[0-9]+]], [r0]
; CHECK-ARMV7: cmp [[OLDVAL]], r1
; CHECK-ARMV7: bne [[FAIL_BB:\.?LBB[0-9]+_[0-9]+]]
; CHECK-ARMV7: dmb ish
Expand All @@ -305,7 +306,8 @@ define i32 @test_cmpxchg_fail_order(i32 *%addr, i32 %desired, i32 %new) {
; CHECK-ARMV7: dmb ish
; CHECK-ARMV7: bx lr

; CHECK-T2: ldrex [[OLDVAL:r[0-9]+]], [r[[ADDR:[0-9]+]]]
; CHECK-T2: mov r[[ADDR:[0-9]+]], r0
; CHECK-T2: ldrex [[OLDVAL:r[0-9]+]], [r0]
; CHECK-T2: cmp [[OLDVAL]], r1
; CHECK-T2: bne [[FAIL_BB:\.?LBB.*]]
; CHECK-T2: dmb ish
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/ARM/intrinsics-overflow.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -39,7 +39,7 @@ define i32 @sadd_overflow(i32 %a, i32 %b) #0 {
; ARM: mov pc, lr

; THUMBV6: mov r[[R2:[0-9]+]], r[[R0:[0-9]+]]
; THUMBV6: adds r[[R3:[0-9]+]], r[[R2]], r[[R1:[0-9]+]]
; THUMBV6: adds r[[R3:[0-9]+]], r[[R0]], r[[R1:[0-9]+]]
; THUMBV6: movs r[[R0]], #0
; THUMBV6: movs r[[R1]], #1
; THUMBV6: cmp r[[R3]], r[[R2]]
Expand Down
9 changes: 4 additions & 5 deletions llvm/test/CodeGen/ARM/swifterror.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -40,7 +40,7 @@ define float @caller(i8* %error_ref) {
; CHECK-APPLE-DAG: mov r8, #0
; CHECK-APPLE: bl {{.*}}foo
; CHECK-APPLE: mov r0, r8
; CHECK-APPLE: cmp r0, #0
; CHECK-APPLE: cmp r8, #0
; Access part of the error object and save it to error_ref
; CHECK-APPLE: ldrbeq [[CODE:r[0-9]+]], [r0, #8]
; CHECK-APPLE: strbeq [[CODE]], [{{.*}}[[ID]]]
Expand Down Expand Up @@ -181,8 +181,7 @@ define float @foo_loop(%swift_error** swifterror %error_ptr_ref, i32 %cc, float
; CHECK-APPLE: beq
; CHECK-APPLE: mov r0, #16
; CHECK-APPLE: malloc
; CHECK-APPLE: mov r8, r0
; CHECK-APPLE: strb r{{.*}}, [r8, #8]
; CHECK-APPLE: strb r{{.*}}, [r0, #8]
; CHECK-APPLE: ble

; CHECK-O0-LABEL: foo_loop:
Expand Down Expand Up @@ -266,7 +265,7 @@ define float @caller3(i8* %error_ref) {
; CHECK-APPLE: mov r8, #0
; CHECK-APPLE: bl {{.*}}foo_sret
; CHECK-APPLE: mov r0, r8
; CHECK-APPLE: cmp r0, #0
; CHECK-APPLE: cmp r8, #0
; Access part of the error object and save it to error_ref
; CHECK-APPLE: ldrbeq [[CODE:r[0-9]+]], [r0, #8]
; CHECK-APPLE: strbeq [[CODE]], [{{.*}}[[ID]]]
Expand Down Expand Up @@ -347,7 +346,7 @@ define float @caller4(i8* %error_ref) {
; CHECK-APPLE: mov r8, #0
; CHECK-APPLE: bl {{.*}}foo_vararg
; CHECK-APPLE: mov r0, r8
; CHECK-APPLE: cmp r0, #0
; CHECK-APPLE: cmp r8, #0
; Access part of the error object and save it to error_ref
; CHECK-APPLE: ldrbeq [[CODE:r[0-9]+]], [r0, #8]
; CHECK-APPLE: strbeq [[CODE]], [{{.*}}[[ID]]]
Expand Down
30 changes: 13 additions & 17 deletions llvm/test/CodeGen/Mips/analyzebranch.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -10,12 +10,11 @@
define double @foo(double %a, double %b) nounwind readnone {
; MIPS32-LABEL: foo:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: mov.d $f0, $f12
; MIPS32-NEXT: mtc1 $zero, $f2
; MIPS32-NEXT: mtc1 $zero, $f3
; MIPS32-NEXT: c.ule.d $f0, $f2
; MIPS32-NEXT: c.ule.d $f12, $f2
; MIPS32-NEXT: bc1f $BB0_2
; MIPS32-NEXT: nop
; MIPS32-NEXT: mov.d $f0, $f12
; MIPS32-NEXT: # %bb.1: # %if.else
; MIPS32-NEXT: mtc1 $zero, $f0
; MIPS32-NEXT: mtc1 $zero, $f1
Expand All @@ -34,7 +33,7 @@ define double @foo(double %a, double %b) nounwind readnone {
; MIPS32R2-NEXT: mov.d $f0, $f12
; MIPS32R2-NEXT: mtc1 $zero, $f2
; MIPS32R2-NEXT: mthc1 $zero, $f2
; MIPS32R2-NEXT: c.ule.d $f0, $f2
; MIPS32R2-NEXT: c.ule.d $f12, $f2
; MIPS32R2-NEXT: bc1f $BB0_2
; MIPS32R2-NEXT: nop
; MIPS32R2-NEXT: # %bb.1: # %if.else
Expand All @@ -55,7 +54,7 @@ define double @foo(double %a, double %b) nounwind readnone {
; MIPS32r6-NEXT: mov.d $f0, $f12
; MIPS32r6-NEXT: mtc1 $zero, $f1
; MIPS32r6-NEXT: mthc1 $zero, $f1
; MIPS32r6-NEXT: cmp.lt.d $f1, $f1, $f0
; MIPS32r6-NEXT: cmp.lt.d $f1, $f1, $f12
; MIPS32r6-NEXT: mfc1 $1, $f1
; MIPS32r6-NEXT: andi $1, $1, 1
; MIPS32r6-NEXT: bnezc $1, $BB0_2
Expand All @@ -74,11 +73,10 @@ define double @foo(double %a, double %b) nounwind readnone {
;
; MIPS4-LABEL: foo:
; MIPS4: # %bb.0: # %entry
; MIPS4-NEXT: mov.d $f0, $f12
; MIPS4-NEXT: dmtc1 $zero, $f1
; MIPS4-NEXT: c.ule.d $f0, $f1
; MIPS4-NEXT: c.ule.d $f12, $f1
; MIPS4-NEXT: bc1f .LBB0_2
; MIPS4-NEXT: nop
; MIPS4-NEXT: mov.d $f0, $f12
; MIPS4-NEXT: # %bb.1: # %if.else
; MIPS4-NEXT: dmtc1 $zero, $f0
; MIPS4-NEXT: c.ule.d $f13, $f0
Expand All @@ -93,11 +91,10 @@ define double @foo(double %a, double %b) nounwind readnone {
;
; MIPS64-LABEL: foo:
; MIPS64: # %bb.0: # %entry
; MIPS64-NEXT: mov.d $f0, $f12
; MIPS64-NEXT: dmtc1 $zero, $f1
; MIPS64-NEXT: c.ule.d $f0, $f1
; MIPS64-NEXT: c.ule.d $f12, $f1
; MIPS64-NEXT: bc1f .LBB0_2
; MIPS64-NEXT: nop
; MIPS64-NEXT: mov.d $f0, $f12
; MIPS64-NEXT: # %bb.1: # %if.else
; MIPS64-NEXT: dmtc1 $zero, $f0
; MIPS64-NEXT: c.ule.d $f13, $f0
Expand All @@ -112,11 +109,10 @@ define double @foo(double %a, double %b) nounwind readnone {
;
; MIPS64R2-LABEL: foo:
; MIPS64R2: # %bb.0: # %entry
; MIPS64R2-NEXT: mov.d $f0, $f12
; MIPS64R2-NEXT: dmtc1 $zero, $f1
; MIPS64R2-NEXT: c.ule.d $f0, $f1
; MIPS64R2-NEXT: c.ule.d $f12, $f1
; MIPS64R2-NEXT: bc1f .LBB0_2
; MIPS64R2-NEXT: nop
; MIPS64R2-NEXT: mov.d $f0, $f12
; MIPS64R2-NEXT: # %bb.1: # %if.else
; MIPS64R2-NEXT: dmtc1 $zero, $f0
; MIPS64R2-NEXT: c.ule.d $f13, $f0
Expand All @@ -131,12 +127,12 @@ define double @foo(double %a, double %b) nounwind readnone {
;
; MIPS64R6-LABEL: foo:
; MIPS64R6: # %bb.0: # %entry
; MIPS64R6-NEXT: mov.d $f0, $f12
; MIPS64R6-NEXT: dmtc1 $zero, $f1
; MIPS64R6-NEXT: cmp.lt.d $f1, $f1, $f0
; MIPS64R6-NEXT: cmp.lt.d $f1, $f1, $f12
; MIPS64R6-NEXT: mfc1 $1, $f1
; MIPS64R6-NEXT: andi $1, $1, 1
; MIPS64R6-NEXT: bnezc $1, .LBB0_2
; MIPS64R6-NEXT: bnez $1, .LBB0_2
; MIPS64R6-NEXT: mov.d $f0, $f12
; MIPS64R6-NEXT: # %bb.1: # %if.else
; MIPS64R6-NEXT: dmtc1 $zero, $f0
; MIPS64R6-NEXT: cmp.ule.d $f1, $f13, $f0
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Mips/llvm-ir/ashr.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -800,7 +800,7 @@ define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) {
; MMR3-NEXT: sw $5, 36($sp) # 4-byte Folded Spill
; MMR3-NEXT: sw $4, 8($sp) # 4-byte Folded Spill
; MMR3-NEXT: lw $16, 76($sp)
; MMR3-NEXT: srlv $4, $8, $16
; MMR3-NEXT: srlv $4, $7, $16
; MMR3-NEXT: not16 $3, $16
; MMR3-NEXT: sw $3, 24($sp) # 4-byte Folded Spill
; MMR3-NEXT: sll16 $2, $6, 1
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/Mips/llvm-ir/lshr.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -828,7 +828,7 @@ define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) {
; MMR3-NEXT: move $17, $5
; MMR3-NEXT: sw $4, 8($sp) # 4-byte Folded Spill
; MMR3-NEXT: lw $16, 76($sp)
; MMR3-NEXT: srlv $7, $8, $16
; MMR3-NEXT: srlv $7, $7, $16
; MMR3-NEXT: not16 $3, $16
; MMR3-NEXT: sw $3, 24($sp) # 4-byte Folded Spill
; MMR3-NEXT: sll16 $2, $6, 1
Expand Down Expand Up @@ -919,14 +919,14 @@ define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) {
; MMR6-NEXT: not16 $5, $3
; MMR6-NEXT: sw $5, 12($sp) # 4-byte Folded Spill
; MMR6-NEXT: move $17, $6
; MMR6-NEXT: sw $17, 16($sp) # 4-byte Folded Spill
; MMR6-NEXT: sll16 $6, $17, 1
; MMR6-NEXT: sw $6, 16($sp) # 4-byte Folded Spill
; MMR6-NEXT: sll16 $6, $6, 1
; MMR6-NEXT: sllv $6, $6, $5
; MMR6-NEXT: or $8, $6, $2
; MMR6-NEXT: addiu $5, $3, -64
; MMR6-NEXT: srlv $9, $7, $5
; MMR6-NEXT: move $6, $4
; MMR6-NEXT: sll16 $2, $6, 1
; MMR6-NEXT: sll16 $2, $4, 1
; MMR6-NEXT: sw $2, 8($sp) # 4-byte Folded Spill
; MMR6-NEXT: not16 $16, $5
; MMR6-NEXT: sllv $10, $2, $16
Expand All @@ -948,7 +948,7 @@ define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) {
; MMR6-NEXT: selnez $11, $12, $4
; MMR6-NEXT: sllv $12, $6, $2
; MMR6-NEXT: move $7, $6
; MMR6-NEXT: sw $7, 4($sp) # 4-byte Folded Spill
; MMR6-NEXT: sw $6, 4($sp) # 4-byte Folded Spill
; MMR6-NEXT: not16 $2, $2
; MMR6-NEXT: srl16 $6, $17, 1
; MMR6-NEXT: srlv $2, $6, $2
Expand Down
108 changes: 48 additions & 60 deletions llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -201,10 +201,9 @@ entry:
define double @tst_select_fcmp_olt_double(double %x, double %y) {
; M2-LABEL: tst_select_fcmp_olt_double:
; M2: # %bb.0: # %entry
; M2-NEXT: mov.d $f0, $f12
; M2-NEXT: c.olt.d $f0, $f14
; M2-NEXT: c.olt.d $f12, $f14
; M2-NEXT: bc1t $BB2_2
; M2-NEXT: nop
; M2-NEXT: mov.d $f0, $f12
; M2-NEXT: # %bb.1: # %entry
; M2-NEXT: mov.d $f0, $f14
; M2-NEXT: $BB2_2: # %entry
Expand All @@ -214,14 +213,14 @@ define double @tst_select_fcmp_olt_double(double %x, double %y) {
; CMOV32R1-LABEL: tst_select_fcmp_olt_double:
; CMOV32R1: # %bb.0: # %entry
; CMOV32R1-NEXT: mov.d $f0, $f14
; CMOV32R1-NEXT: c.olt.d $f12, $f0
; CMOV32R1-NEXT: c.olt.d $f12, $f14
; CMOV32R1-NEXT: jr $ra
; CMOV32R1-NEXT: movt.d $f0, $f12, $fcc0
;
; CMOV32R2-LABEL: tst_select_fcmp_olt_double:
; CMOV32R2: # %bb.0: # %entry
; CMOV32R2-NEXT: mov.d $f0, $f14
; CMOV32R2-NEXT: c.olt.d $f12, $f0
; CMOV32R2-NEXT: c.olt.d $f12, $f14
; CMOV32R2-NEXT: jr $ra
; CMOV32R2-NEXT: movt.d $f0, $f12, $fcc0
;
Expand All @@ -235,10 +234,9 @@ define double @tst_select_fcmp_olt_double(double %x, double %y) {
;
; M3-LABEL: tst_select_fcmp_olt_double:
; M3: # %bb.0: # %entry
; M3-NEXT: mov.d $f0, $f12
; M3-NEXT: c.olt.d $f0, $f13
; M3-NEXT: c.olt.d $f12, $f13
; M3-NEXT: bc1t .LBB2_2
; M3-NEXT: nop
; M3-NEXT: mov.d $f0, $f12
; M3-NEXT: # %bb.1: # %entry
; M3-NEXT: mov.d $f0, $f13
; M3-NEXT: .LBB2_2: # %entry
Expand All @@ -248,7 +246,7 @@ define double @tst_select_fcmp_olt_double(double %x, double %y) {
; CMOV64-LABEL: tst_select_fcmp_olt_double:
; CMOV64: # %bb.0: # %entry
; CMOV64-NEXT: mov.d $f0, $f13
; CMOV64-NEXT: c.olt.d $f12, $f0
; CMOV64-NEXT: c.olt.d $f12, $f13
; CMOV64-NEXT: jr $ra
; CMOV64-NEXT: movt.d $f0, $f12, $fcc0
;
Expand All @@ -263,7 +261,7 @@ define double @tst_select_fcmp_olt_double(double %x, double %y) {
; MM32R3-LABEL: tst_select_fcmp_olt_double:
; MM32R3: # %bb.0: # %entry
; MM32R3-NEXT: mov.d $f0, $f14
; MM32R3-NEXT: c.olt.d $f12, $f0
; MM32R3-NEXT: c.olt.d $f12, $f14
; MM32R3-NEXT: jr $ra
; MM32R3-NEXT: movt.d $f0, $f12, $fcc0
;
Expand All @@ -283,10 +281,9 @@ entry:
define double @tst_select_fcmp_ole_double(double %x, double %y) {
; M2-LABEL: tst_select_fcmp_ole_double:
; M2: # %bb.0: # %entry
; M2-NEXT: mov.d $f0, $f12
; M2-NEXT: c.ole.d $f0, $f14
; M2-NEXT: c.ole.d $f12, $f14
; M2-NEXT: bc1t $BB3_2
; M2-NEXT: nop
; M2-NEXT: mov.d $f0, $f12
; M2-NEXT: # %bb.1: # %entry
; M2-NEXT: mov.d $f0, $f14
; M2-NEXT: $BB3_2: # %entry
Expand All @@ -296,14 +293,14 @@ define double @tst_select_fcmp_ole_double(double %x, double %y) {
; CMOV32R1-LABEL: tst_select_fcmp_ole_double:
; CMOV32R1: # %bb.0: # %entry
; CMOV32R1-NEXT: mov.d $f0, $f14
; CMOV32R1-NEXT: c.ole.d $f12, $f0
; CMOV32R1-NEXT: c.ole.d $f12, $f14
; CMOV32R1-NEXT: jr $ra
; CMOV32R1-NEXT: movt.d $f0, $f12, $fcc0
;
; CMOV32R2-LABEL: tst_select_fcmp_ole_double:
; CMOV32R2: # %bb.0: # %entry
; CMOV32R2-NEXT: mov.d $f0, $f14
; CMOV32R2-NEXT: c.ole.d $f12, $f0
; CMOV32R2-NEXT: c.ole.d $f12, $f14
; CMOV32R2-NEXT: jr $ra
; CMOV32R2-NEXT: movt.d $f0, $f12, $fcc0
;
Expand All @@ -317,10 +314,9 @@ define double @tst_select_fcmp_ole_double(double %x, double %y) {
;
; M3-LABEL: tst_select_fcmp_ole_double:
; M3: # %bb.0: # %entry
; M3-NEXT: mov.d $f0, $f12
; M3-NEXT: c.ole.d $f0, $f13
; M3-NEXT: c.ole.d $f12, $f13
; M3-NEXT: bc1t .LBB3_2
; M3-NEXT: nop
; M3-NEXT: mov.d $f0, $f12
; M3-NEXT: # %bb.1: # %entry
; M3-NEXT: mov.d $f0, $f13
; M3-NEXT: .LBB3_2: # %entry
Expand All @@ -330,7 +326,7 @@ define double @tst_select_fcmp_ole_double(double %x, double %y) {
; CMOV64-LABEL: tst_select_fcmp_ole_double:
; CMOV64: # %bb.0: # %entry
; CMOV64-NEXT: mov.d $f0, $f13
; CMOV64-NEXT: c.ole.d $f12, $f0
; CMOV64-NEXT: c.ole.d $f12, $f13
; CMOV64-NEXT: jr $ra
; CMOV64-NEXT: movt.d $f0, $f12, $fcc0
;
Expand All @@ -345,7 +341,7 @@ define double @tst_select_fcmp_ole_double(double %x, double %y) {
; MM32R3-LABEL: tst_select_fcmp_ole_double:
; MM32R3: # %bb.0: # %entry
; MM32R3-NEXT: mov.d $f0, $f14
; MM32R3-NEXT: c.ole.d $f12, $f0
; MM32R3-NEXT: c.ole.d $f12, $f14
; MM32R3-NEXT: jr $ra
; MM32R3-NEXT: movt.d $f0, $f12, $fcc0
;
Expand All @@ -365,10 +361,9 @@ entry:
define double @tst_select_fcmp_ogt_double(double %x, double %y) {
; M2-LABEL: tst_select_fcmp_ogt_double:
; M2: # %bb.0: # %entry
; M2-NEXT: mov.d $f0, $f12
; M2-NEXT: c.ule.d $f0, $f14
; M2-NEXT: c.ule.d $f12, $f14
; M2-NEXT: bc1f $BB4_2
; M2-NEXT: nop
; M2-NEXT: mov.d $f0, $f12
; M2-NEXT: # %bb.1: # %entry
; M2-NEXT: mov.d $f0, $f14
; M2-NEXT: $BB4_2: # %entry
Expand All @@ -378,14 +373,14 @@ define double @tst_select_fcmp_ogt_double(double %x, double %y) {
; CMOV32R1-LABEL: tst_select_fcmp_ogt_double:
; CMOV32R1: # %bb.0: # %entry
; CMOV32R1-NEXT: mov.d $f0, $f14
; CMOV32R1-NEXT: c.ule.d $f12, $f0
; CMOV32R1-NEXT: c.ule.d $f12, $f14
; CMOV32R1-NEXT: jr $ra
; CMOV32R1-NEXT: movf.d $f0, $f12, $fcc0
;
; CMOV32R2-LABEL: tst_select_fcmp_ogt_double:
; CMOV32R2: # %bb.0: # %entry
; CMOV32R2-NEXT: mov.d $f0, $f14
; CMOV32R2-NEXT: c.ule.d $f12, $f0
; CMOV32R2-NEXT: c.ule.d $f12, $f14
; CMOV32R2-NEXT: jr $ra
; CMOV32R2-NEXT: movf.d $f0, $f12, $fcc0
;
Expand All @@ -399,10 +394,9 @@ define double @tst_select_fcmp_ogt_double(double %x, double %y) {
;
; M3-LABEL: tst_select_fcmp_ogt_double:
; M3: # %bb.0: # %entry
; M3-NEXT: mov.d $f0, $f12
; M3-NEXT: c.ule.d $f0, $f13
; M3-NEXT: c.ule.d $f12, $f13
; M3-NEXT: bc1f .LBB4_2
; M3-NEXT: nop
; M3-NEXT: mov.d $f0, $f12
; M3-NEXT: # %bb.1: # %entry
; M3-NEXT: mov.d $f0, $f13
; M3-NEXT: .LBB4_2: # %entry
Expand All @@ -412,7 +406,7 @@ define double @tst_select_fcmp_ogt_double(double %x, double %y) {
; CMOV64-LABEL: tst_select_fcmp_ogt_double:
; CMOV64: # %bb.0: # %entry
; CMOV64-NEXT: mov.d $f0, $f13
; CMOV64-NEXT: c.ule.d $f12, $f0
; CMOV64-NEXT: c.ule.d $f12, $f13
; CMOV64-NEXT: jr $ra
; CMOV64-NEXT: movf.d $f0, $f12, $fcc0
;
Expand All @@ -427,7 +421,7 @@ define double @tst_select_fcmp_ogt_double(double %x, double %y) {
; MM32R3-LABEL: tst_select_fcmp_ogt_double:
; MM32R3: # %bb.0: # %entry
; MM32R3-NEXT: mov.d $f0, $f14
; MM32R3-NEXT: c.ule.d $f12, $f0
; MM32R3-NEXT: c.ule.d $f12, $f14
; MM32R3-NEXT: jr $ra
; MM32R3-NEXT: movf.d $f0, $f12, $fcc0
;
Expand All @@ -447,10 +441,9 @@ entry:
define double @tst_select_fcmp_oge_double(double %x, double %y) {
; M2-LABEL: tst_select_fcmp_oge_double:
; M2: # %bb.0: # %entry
; M2-NEXT: mov.d $f0, $f12
; M2-NEXT: c.ult.d $f0, $f14
; M2-NEXT: c.ult.d $f12, $f14
; M2-NEXT: bc1f $BB5_2
; M2-NEXT: nop
; M2-NEXT: mov.d $f0, $f12
; M2-NEXT: # %bb.1: # %entry
; M2-NEXT: mov.d $f0, $f14
; M2-NEXT: $BB5_2: # %entry
Expand All @@ -460,14 +453,14 @@ define double @tst_select_fcmp_oge_double(double %x, double %y) {
; CMOV32R1-LABEL: tst_select_fcmp_oge_double:
; CMOV32R1: # %bb.0: # %entry
; CMOV32R1-NEXT: mov.d $f0, $f14
; CMOV32R1-NEXT: c.ult.d $f12, $f0
; CMOV32R1-NEXT: c.ult.d $f12, $f14
; CMOV32R1-NEXT: jr $ra
; CMOV32R1-NEXT: movf.d $f0, $f12, $fcc0
;
; CMOV32R2-LABEL: tst_select_fcmp_oge_double:
; CMOV32R2: # %bb.0: # %entry
; CMOV32R2-NEXT: mov.d $f0, $f14
; CMOV32R2-NEXT: c.ult.d $f12, $f0
; CMOV32R2-NEXT: c.ult.d $f12, $f14
; CMOV32R2-NEXT: jr $ra
; CMOV32R2-NEXT: movf.d $f0, $f12, $fcc0
;
Expand All @@ -481,10 +474,9 @@ define double @tst_select_fcmp_oge_double(double %x, double %y) {
;
; M3-LABEL: tst_select_fcmp_oge_double:
; M3: # %bb.0: # %entry
; M3-NEXT: mov.d $f0, $f12
; M3-NEXT: c.ult.d $f0, $f13
; M3-NEXT: c.ult.d $f12, $f13
; M3-NEXT: bc1f .LBB5_2
; M3-NEXT: nop
; M3-NEXT: mov.d $f0, $f12
; M3-NEXT: # %bb.1: # %entry
; M3-NEXT: mov.d $f0, $f13
; M3-NEXT: .LBB5_2: # %entry
Expand All @@ -494,7 +486,7 @@ define double @tst_select_fcmp_oge_double(double %x, double %y) {
; CMOV64-LABEL: tst_select_fcmp_oge_double:
; CMOV64: # %bb.0: # %entry
; CMOV64-NEXT: mov.d $f0, $f13
; CMOV64-NEXT: c.ult.d $f12, $f0
; CMOV64-NEXT: c.ult.d $f12, $f13
; CMOV64-NEXT: jr $ra
; CMOV64-NEXT: movf.d $f0, $f12, $fcc0
;
Expand All @@ -509,7 +501,7 @@ define double @tst_select_fcmp_oge_double(double %x, double %y) {
; MM32R3-LABEL: tst_select_fcmp_oge_double:
; MM32R3: # %bb.0: # %entry
; MM32R3-NEXT: mov.d $f0, $f14
; MM32R3-NEXT: c.ult.d $f12, $f0
; MM32R3-NEXT: c.ult.d $f12, $f14
; MM32R3-NEXT: jr $ra
; MM32R3-NEXT: movf.d $f0, $f12, $fcc0
;
Expand All @@ -529,10 +521,9 @@ entry:
define double @tst_select_fcmp_oeq_double(double %x, double %y) {
; M2-LABEL: tst_select_fcmp_oeq_double:
; M2: # %bb.0: # %entry
; M2-NEXT: mov.d $f0, $f12
; M2-NEXT: c.eq.d $f0, $f14
; M2-NEXT: c.eq.d $f12, $f14
; M2-NEXT: bc1t $BB6_2
; M2-NEXT: nop
; M2-NEXT: mov.d $f0, $f12
; M2-NEXT: # %bb.1: # %entry
; M2-NEXT: mov.d $f0, $f14
; M2-NEXT: $BB6_2: # %entry
Expand All @@ -542,14 +533,14 @@ define double @tst_select_fcmp_oeq_double(double %x, double %y) {
; CMOV32R1-LABEL: tst_select_fcmp_oeq_double:
; CMOV32R1: # %bb.0: # %entry
; CMOV32R1-NEXT: mov.d $f0, $f14
; CMOV32R1-NEXT: c.eq.d $f12, $f0
; CMOV32R1-NEXT: c.eq.d $f12, $f14
; CMOV32R1-NEXT: jr $ra
; CMOV32R1-NEXT: movt.d $f0, $f12, $fcc0
;
; CMOV32R2-LABEL: tst_select_fcmp_oeq_double:
; CMOV32R2: # %bb.0: # %entry
; CMOV32R2-NEXT: mov.d $f0, $f14
; CMOV32R2-NEXT: c.eq.d $f12, $f0
; CMOV32R2-NEXT: c.eq.d $f12, $f14
; CMOV32R2-NEXT: jr $ra
; CMOV32R2-NEXT: movt.d $f0, $f12, $fcc0
;
Expand All @@ -563,10 +554,9 @@ define double @tst_select_fcmp_oeq_double(double %x, double %y) {
;
; M3-LABEL: tst_select_fcmp_oeq_double:
; M3: # %bb.0: # %entry
; M3-NEXT: mov.d $f0, $f12
; M3-NEXT: c.eq.d $f0, $f13
; M3-NEXT: c.eq.d $f12, $f13
; M3-NEXT: bc1t .LBB6_2
; M3-NEXT: nop
; M3-NEXT: mov.d $f0, $f12
; M3-NEXT: # %bb.1: # %entry
; M3-NEXT: mov.d $f0, $f13
; M3-NEXT: .LBB6_2: # %entry
Expand All @@ -576,7 +566,7 @@ define double @tst_select_fcmp_oeq_double(double %x, double %y) {
; CMOV64-LABEL: tst_select_fcmp_oeq_double:
; CMOV64: # %bb.0: # %entry
; CMOV64-NEXT: mov.d $f0, $f13
; CMOV64-NEXT: c.eq.d $f12, $f0
; CMOV64-NEXT: c.eq.d $f12, $f13
; CMOV64-NEXT: jr $ra
; CMOV64-NEXT: movt.d $f0, $f12, $fcc0
;
Expand All @@ -591,7 +581,7 @@ define double @tst_select_fcmp_oeq_double(double %x, double %y) {
; MM32R3-LABEL: tst_select_fcmp_oeq_double:
; MM32R3: # %bb.0: # %entry
; MM32R3-NEXT: mov.d $f0, $f14
; MM32R3-NEXT: c.eq.d $f12, $f0
; MM32R3-NEXT: c.eq.d $f12, $f14
; MM32R3-NEXT: jr $ra
; MM32R3-NEXT: movt.d $f0, $f12, $fcc0
;
Expand All @@ -611,10 +601,9 @@ entry:
define double @tst_select_fcmp_one_double(double %x, double %y) {
; M2-LABEL: tst_select_fcmp_one_double:
; M2: # %bb.0: # %entry
; M2-NEXT: mov.d $f0, $f12
; M2-NEXT: c.ueq.d $f0, $f14
; M2-NEXT: c.ueq.d $f12, $f14
; M2-NEXT: bc1f $BB7_2
; M2-NEXT: nop
; M2-NEXT: mov.d $f0, $f12
; M2-NEXT: # %bb.1: # %entry
; M2-NEXT: mov.d $f0, $f14
; M2-NEXT: $BB7_2: # %entry
Expand All @@ -624,14 +613,14 @@ define double @tst_select_fcmp_one_double(double %x, double %y) {
; CMOV32R1-LABEL: tst_select_fcmp_one_double:
; CMOV32R1: # %bb.0: # %entry
; CMOV32R1-NEXT: mov.d $f0, $f14
; CMOV32R1-NEXT: c.ueq.d $f12, $f0
; CMOV32R1-NEXT: c.ueq.d $f12, $f14
; CMOV32R1-NEXT: jr $ra
; CMOV32R1-NEXT: movf.d $f0, $f12, $fcc0
;
; CMOV32R2-LABEL: tst_select_fcmp_one_double:
; CMOV32R2: # %bb.0: # %entry
; CMOV32R2-NEXT: mov.d $f0, $f14
; CMOV32R2-NEXT: c.ueq.d $f12, $f0
; CMOV32R2-NEXT: c.ueq.d $f12, $f14
; CMOV32R2-NEXT: jr $ra
; CMOV32R2-NEXT: movf.d $f0, $f12, $fcc0
;
Expand All @@ -646,10 +635,9 @@ define double @tst_select_fcmp_one_double(double %x, double %y) {
;
; M3-LABEL: tst_select_fcmp_one_double:
; M3: # %bb.0: # %entry
; M3-NEXT: mov.d $f0, $f12
; M3-NEXT: c.ueq.d $f0, $f13
; M3-NEXT: c.ueq.d $f12, $f13
; M3-NEXT: bc1f .LBB7_2
; M3-NEXT: nop
; M3-NEXT: mov.d $f0, $f12
; M3-NEXT: # %bb.1: # %entry
; M3-NEXT: mov.d $f0, $f13
; M3-NEXT: .LBB7_2: # %entry
Expand All @@ -659,7 +647,7 @@ define double @tst_select_fcmp_one_double(double %x, double %y) {
; CMOV64-LABEL: tst_select_fcmp_one_double:
; CMOV64: # %bb.0: # %entry
; CMOV64-NEXT: mov.d $f0, $f13
; CMOV64-NEXT: c.ueq.d $f12, $f0
; CMOV64-NEXT: c.ueq.d $f12, $f13
; CMOV64-NEXT: jr $ra
; CMOV64-NEXT: movf.d $f0, $f12, $fcc0
;
Expand All @@ -675,7 +663,7 @@ define double @tst_select_fcmp_one_double(double %x, double %y) {
; MM32R3-LABEL: tst_select_fcmp_one_double:
; MM32R3: # %bb.0: # %entry
; MM32R3-NEXT: mov.d $f0, $f14
; MM32R3-NEXT: c.ueq.d $f12, $f0
; MM32R3-NEXT: c.ueq.d $f12, $f14
; MM32R3-NEXT: jr $ra
; MM32R3-NEXT: movf.d $f0, $f12, $fcc0
;
Expand Down
108 changes: 48 additions & 60 deletions llvm/test/CodeGen/Mips/llvm-ir/select-flt.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -188,10 +188,9 @@ entry:
define float @tst_select_fcmp_olt_float(float %x, float %y) {
; M2-LABEL: tst_select_fcmp_olt_float:
; M2: # %bb.0: # %entry
; M2-NEXT: mov.s $f0, $f12
; M2-NEXT: c.olt.s $f0, $f14
; M2-NEXT: c.olt.s $f12, $f14
; M2-NEXT: bc1t $BB2_2
; M2-NEXT: nop
; M2-NEXT: mov.s $f0, $f12
; M2-NEXT: # %bb.1: # %entry
; M2-NEXT: mov.s $f0, $f14
; M2-NEXT: $BB2_2: # %entry
Expand All @@ -201,14 +200,14 @@ define float @tst_select_fcmp_olt_float(float %x, float %y) {
; CMOV32R1-LABEL: tst_select_fcmp_olt_float:
; CMOV32R1: # %bb.0: # %entry
; CMOV32R1-NEXT: mov.s $f0, $f14
; CMOV32R1-NEXT: c.olt.s $f12, $f0
; CMOV32R1-NEXT: c.olt.s $f12, $f14
; CMOV32R1-NEXT: jr $ra
; CMOV32R1-NEXT: movt.s $f0, $f12, $fcc0
;
; CMOV32R2-LABEL: tst_select_fcmp_olt_float:
; CMOV32R2: # %bb.0: # %entry
; CMOV32R2-NEXT: mov.s $f0, $f14
; CMOV32R2-NEXT: c.olt.s $f12, $f0
; CMOV32R2-NEXT: c.olt.s $f12, $f14
; CMOV32R2-NEXT: jr $ra
; CMOV32R2-NEXT: movt.s $f0, $f12, $fcc0
;
Expand All @@ -220,10 +219,9 @@ define float @tst_select_fcmp_olt_float(float %x, float %y) {
;
; M3-LABEL: tst_select_fcmp_olt_float:
; M3: # %bb.0: # %entry
; M3-NEXT: mov.s $f0, $f12
; M3-NEXT: c.olt.s $f0, $f13
; M3-NEXT: c.olt.s $f12, $f13
; M3-NEXT: bc1t .LBB2_2
; M3-NEXT: nop
; M3-NEXT: mov.s $f0, $f12
; M3-NEXT: # %bb.1: # %entry
; M3-NEXT: mov.s $f0, $f13
; M3-NEXT: .LBB2_2: # %entry
Expand All @@ -233,7 +231,7 @@ define float @tst_select_fcmp_olt_float(float %x, float %y) {
; CMOV64-LABEL: tst_select_fcmp_olt_float:
; CMOV64: # %bb.0: # %entry
; CMOV64-NEXT: mov.s $f0, $f13
; CMOV64-NEXT: c.olt.s $f12, $f0
; CMOV64-NEXT: c.olt.s $f12, $f13
; CMOV64-NEXT: jr $ra
; CMOV64-NEXT: movt.s $f0, $f12, $fcc0
;
Expand All @@ -246,7 +244,7 @@ define float @tst_select_fcmp_olt_float(float %x, float %y) {
; MM32R3-LABEL: tst_select_fcmp_olt_float:
; MM32R3: # %bb.0: # %entry
; MM32R3-NEXT: mov.s $f0, $f14
; MM32R3-NEXT: c.olt.s $f12, $f0
; MM32R3-NEXT: c.olt.s $f12, $f14
; MM32R3-NEXT: jr $ra
; MM32R3-NEXT: movt.s $f0, $f12, $fcc0
;
Expand All @@ -264,10 +262,9 @@ entry:
define float @tst_select_fcmp_ole_float(float %x, float %y) {
; M2-LABEL: tst_select_fcmp_ole_float:
; M2: # %bb.0: # %entry
; M2-NEXT: mov.s $f0, $f12
; M2-NEXT: c.ole.s $f0, $f14
; M2-NEXT: c.ole.s $f12, $f14
; M2-NEXT: bc1t $BB3_2
; M2-NEXT: nop
; M2-NEXT: mov.s $f0, $f12
; M2-NEXT: # %bb.1: # %entry
; M2-NEXT: mov.s $f0, $f14
; M2-NEXT: $BB3_2: # %entry
Expand All @@ -277,14 +274,14 @@ define float @tst_select_fcmp_ole_float(float %x, float %y) {
; CMOV32R1-LABEL: tst_select_fcmp_ole_float:
; CMOV32R1: # %bb.0: # %entry
; CMOV32R1-NEXT: mov.s $f0, $f14
; CMOV32R1-NEXT: c.ole.s $f12, $f0
; CMOV32R1-NEXT: c.ole.s $f12, $f14
; CMOV32R1-NEXT: jr $ra
; CMOV32R1-NEXT: movt.s $f0, $f12, $fcc0
;
; CMOV32R2-LABEL: tst_select_fcmp_ole_float:
; CMOV32R2: # %bb.0: # %entry
; CMOV32R2-NEXT: mov.s $f0, $f14
; CMOV32R2-NEXT: c.ole.s $f12, $f0
; CMOV32R2-NEXT: c.ole.s $f12, $f14
; CMOV32R2-NEXT: jr $ra
; CMOV32R2-NEXT: movt.s $f0, $f12, $fcc0
;
Expand All @@ -296,10 +293,9 @@ define float @tst_select_fcmp_ole_float(float %x, float %y) {
;
; M3-LABEL: tst_select_fcmp_ole_float:
; M3: # %bb.0: # %entry
; M3-NEXT: mov.s $f0, $f12
; M3-NEXT: c.ole.s $f0, $f13
; M3-NEXT: c.ole.s $f12, $f13
; M3-NEXT: bc1t .LBB3_2
; M3-NEXT: nop
; M3-NEXT: mov.s $f0, $f12
; M3-NEXT: # %bb.1: # %entry
; M3-NEXT: mov.s $f0, $f13
; M3-NEXT: .LBB3_2: # %entry
Expand All @@ -309,7 +305,7 @@ define float @tst_select_fcmp_ole_float(float %x, float %y) {
; CMOV64-LABEL: tst_select_fcmp_ole_float:
; CMOV64: # %bb.0: # %entry
; CMOV64-NEXT: mov.s $f0, $f13
; CMOV64-NEXT: c.ole.s $f12, $f0
; CMOV64-NEXT: c.ole.s $f12, $f13
; CMOV64-NEXT: jr $ra
; CMOV64-NEXT: movt.s $f0, $f12, $fcc0
;
Expand All @@ -322,7 +318,7 @@ define float @tst_select_fcmp_ole_float(float %x, float %y) {
; MM32R3-LABEL: tst_select_fcmp_ole_float:
; MM32R3: # %bb.0: # %entry
; MM32R3-NEXT: mov.s $f0, $f14
; MM32R3-NEXT: c.ole.s $f12, $f0
; MM32R3-NEXT: c.ole.s $f12, $f14
; MM32R3-NEXT: jr $ra
; MM32R3-NEXT: movt.s $f0, $f12, $fcc0
;
Expand All @@ -340,10 +336,9 @@ entry:
define float @tst_select_fcmp_ogt_float(float %x, float %y) {
; M2-LABEL: tst_select_fcmp_ogt_float:
; M2: # %bb.0: # %entry
; M2-NEXT: mov.s $f0, $f12
; M2-NEXT: c.ule.s $f0, $f14
; M2-NEXT: c.ule.s $f12, $f14
; M2-NEXT: bc1f $BB4_2
; M2-NEXT: nop
; M2-NEXT: mov.s $f0, $f12
; M2-NEXT: # %bb.1: # %entry
; M2-NEXT: mov.s $f0, $f14
; M2-NEXT: $BB4_2: # %entry
Expand All @@ -353,14 +348,14 @@ define float @tst_select_fcmp_ogt_float(float %x, float %y) {
; CMOV32R1-LABEL: tst_select_fcmp_ogt_float:
; CMOV32R1: # %bb.0: # %entry
; CMOV32R1-NEXT: mov.s $f0, $f14
; CMOV32R1-NEXT: c.ule.s $f12, $f0
; CMOV32R1-NEXT: c.ule.s $f12, $f14
; CMOV32R1-NEXT: jr $ra
; CMOV32R1-NEXT: movf.s $f0, $f12, $fcc0
;
; CMOV32R2-LABEL: tst_select_fcmp_ogt_float:
; CMOV32R2: # %bb.0: # %entry
; CMOV32R2-NEXT: mov.s $f0, $f14
; CMOV32R2-NEXT: c.ule.s $f12, $f0
; CMOV32R2-NEXT: c.ule.s $f12, $f14
; CMOV32R2-NEXT: jr $ra
; CMOV32R2-NEXT: movf.s $f0, $f12, $fcc0
;
Expand All @@ -372,10 +367,9 @@ define float @tst_select_fcmp_ogt_float(float %x, float %y) {
;
; M3-LABEL: tst_select_fcmp_ogt_float:
; M3: # %bb.0: # %entry
; M3-NEXT: mov.s $f0, $f12
; M3-NEXT: c.ule.s $f0, $f13
; M3-NEXT: c.ule.s $f12, $f13
; M3-NEXT: bc1f .LBB4_2
; M3-NEXT: nop
; M3-NEXT: mov.s $f0, $f12
; M3-NEXT: # %bb.1: # %entry
; M3-NEXT: mov.s $f0, $f13
; M3-NEXT: .LBB4_2: # %entry
Expand All @@ -385,7 +379,7 @@ define float @tst_select_fcmp_ogt_float(float %x, float %y) {
; CMOV64-LABEL: tst_select_fcmp_ogt_float:
; CMOV64: # %bb.0: # %entry
; CMOV64-NEXT: mov.s $f0, $f13
; CMOV64-NEXT: c.ule.s $f12, $f0
; CMOV64-NEXT: c.ule.s $f12, $f13
; CMOV64-NEXT: jr $ra
; CMOV64-NEXT: movf.s $f0, $f12, $fcc0
;
Expand All @@ -398,7 +392,7 @@ define float @tst_select_fcmp_ogt_float(float %x, float %y) {
; MM32R3-LABEL: tst_select_fcmp_ogt_float:
; MM32R3: # %bb.0: # %entry
; MM32R3-NEXT: mov.s $f0, $f14
; MM32R3-NEXT: c.ule.s $f12, $f0
; MM32R3-NEXT: c.ule.s $f12, $f14
; MM32R3-NEXT: jr $ra
; MM32R3-NEXT: movf.s $f0, $f12, $fcc0
;
Expand All @@ -416,10 +410,9 @@ entry:
define float @tst_select_fcmp_oge_float(float %x, float %y) {
; M2-LABEL: tst_select_fcmp_oge_float:
; M2: # %bb.0: # %entry
; M2-NEXT: mov.s $f0, $f12
; M2-NEXT: c.ult.s $f0, $f14
; M2-NEXT: c.ult.s $f12, $f14
; M2-NEXT: bc1f $BB5_2
; M2-NEXT: nop
; M2-NEXT: mov.s $f0, $f12
; M2-NEXT: # %bb.1: # %entry
; M2-NEXT: mov.s $f0, $f14
; M2-NEXT: $BB5_2: # %entry
Expand All @@ -429,14 +422,14 @@ define float @tst_select_fcmp_oge_float(float %x, float %y) {
; CMOV32R1-LABEL: tst_select_fcmp_oge_float:
; CMOV32R1: # %bb.0: # %entry
; CMOV32R1-NEXT: mov.s $f0, $f14
; CMOV32R1-NEXT: c.ult.s $f12, $f0
; CMOV32R1-NEXT: c.ult.s $f12, $f14
; CMOV32R1-NEXT: jr $ra
; CMOV32R1-NEXT: movf.s $f0, $f12, $fcc0
;
; CMOV32R2-LABEL: tst_select_fcmp_oge_float:
; CMOV32R2: # %bb.0: # %entry
; CMOV32R2-NEXT: mov.s $f0, $f14
; CMOV32R2-NEXT: c.ult.s $f12, $f0
; CMOV32R2-NEXT: c.ult.s $f12, $f14
; CMOV32R2-NEXT: jr $ra
; CMOV32R2-NEXT: movf.s $f0, $f12, $fcc0
;
Expand All @@ -448,10 +441,9 @@ define float @tst_select_fcmp_oge_float(float %x, float %y) {
;
; M3-LABEL: tst_select_fcmp_oge_float:
; M3: # %bb.0: # %entry
; M3-NEXT: mov.s $f0, $f12
; M3-NEXT: c.ult.s $f0, $f13
; M3-NEXT: c.ult.s $f12, $f13
; M3-NEXT: bc1f .LBB5_2
; M3-NEXT: nop
; M3-NEXT: mov.s $f0, $f12
; M3-NEXT: # %bb.1: # %entry
; M3-NEXT: mov.s $f0, $f13
; M3-NEXT: .LBB5_2: # %entry
Expand All @@ -461,7 +453,7 @@ define float @tst_select_fcmp_oge_float(float %x, float %y) {
; CMOV64-LABEL: tst_select_fcmp_oge_float:
; CMOV64: # %bb.0: # %entry
; CMOV64-NEXT: mov.s $f0, $f13
; CMOV64-NEXT: c.ult.s $f12, $f0
; CMOV64-NEXT: c.ult.s $f12, $f13
; CMOV64-NEXT: jr $ra
; CMOV64-NEXT: movf.s $f0, $f12, $fcc0
;
Expand All @@ -474,7 +466,7 @@ define float @tst_select_fcmp_oge_float(float %x, float %y) {
; MM32R3-LABEL: tst_select_fcmp_oge_float:
; MM32R3: # %bb.0: # %entry
; MM32R3-NEXT: mov.s $f0, $f14
; MM32R3-NEXT: c.ult.s $f12, $f0
; MM32R3-NEXT: c.ult.s $f12, $f14
; MM32R3-NEXT: jr $ra
; MM32R3-NEXT: movf.s $f0, $f12, $fcc0
;
Expand All @@ -492,10 +484,9 @@ entry:
define float @tst_select_fcmp_oeq_float(float %x, float %y) {
; M2-LABEL: tst_select_fcmp_oeq_float:
; M2: # %bb.0: # %entry
; M2-NEXT: mov.s $f0, $f12
; M2-NEXT: c.eq.s $f0, $f14
; M2-NEXT: c.eq.s $f12, $f14
; M2-NEXT: bc1t $BB6_2
; M2-NEXT: nop
; M2-NEXT: mov.s $f0, $f12
; M2-NEXT: # %bb.1: # %entry
; M2-NEXT: mov.s $f0, $f14
; M2-NEXT: $BB6_2: # %entry
Expand All @@ -505,14 +496,14 @@ define float @tst_select_fcmp_oeq_float(float %x, float %y) {
; CMOV32R1-LABEL: tst_select_fcmp_oeq_float:
; CMOV32R1: # %bb.0: # %entry
; CMOV32R1-NEXT: mov.s $f0, $f14
; CMOV32R1-NEXT: c.eq.s $f12, $f0
; CMOV32R1-NEXT: c.eq.s $f12, $f14
; CMOV32R1-NEXT: jr $ra
; CMOV32R1-NEXT: movt.s $f0, $f12, $fcc0
;
; CMOV32R2-LABEL: tst_select_fcmp_oeq_float:
; CMOV32R2: # %bb.0: # %entry
; CMOV32R2-NEXT: mov.s $f0, $f14
; CMOV32R2-NEXT: c.eq.s $f12, $f0
; CMOV32R2-NEXT: c.eq.s $f12, $f14
; CMOV32R2-NEXT: jr $ra
; CMOV32R2-NEXT: movt.s $f0, $f12, $fcc0
;
Expand All @@ -524,10 +515,9 @@ define float @tst_select_fcmp_oeq_float(float %x, float %y) {
;
; M3-LABEL: tst_select_fcmp_oeq_float:
; M3: # %bb.0: # %entry
; M3-NEXT: mov.s $f0, $f12
; M3-NEXT: c.eq.s $f0, $f13
; M3-NEXT: c.eq.s $f12, $f13
; M3-NEXT: bc1t .LBB6_2
; M3-NEXT: nop
; M3-NEXT: mov.s $f0, $f12
; M3-NEXT: # %bb.1: # %entry
; M3-NEXT: mov.s $f0, $f13
; M3-NEXT: .LBB6_2: # %entry
Expand All @@ -537,7 +527,7 @@ define float @tst_select_fcmp_oeq_float(float %x, float %y) {
; CMOV64-LABEL: tst_select_fcmp_oeq_float:
; CMOV64: # %bb.0: # %entry
; CMOV64-NEXT: mov.s $f0, $f13
; CMOV64-NEXT: c.eq.s $f12, $f0
; CMOV64-NEXT: c.eq.s $f12, $f13
; CMOV64-NEXT: jr $ra
; CMOV64-NEXT: movt.s $f0, $f12, $fcc0
;
Expand All @@ -550,7 +540,7 @@ define float @tst_select_fcmp_oeq_float(float %x, float %y) {
; MM32R3-LABEL: tst_select_fcmp_oeq_float:
; MM32R3: # %bb.0: # %entry
; MM32R3-NEXT: mov.s $f0, $f14
; MM32R3-NEXT: c.eq.s $f12, $f0
; MM32R3-NEXT: c.eq.s $f12, $f14
; MM32R3-NEXT: jr $ra
; MM32R3-NEXT: movt.s $f0, $f12, $fcc0
;
Expand All @@ -568,10 +558,9 @@ entry:
define float @tst_select_fcmp_one_float(float %x, float %y) {
; M2-LABEL: tst_select_fcmp_one_float:
; M2: # %bb.0: # %entry
; M2-NEXT: mov.s $f0, $f12
; M2-NEXT: c.ueq.s $f0, $f14
; M2-NEXT: c.ueq.s $f12, $f14
; M2-NEXT: bc1f $BB7_2
; M2-NEXT: nop
; M2-NEXT: mov.s $f0, $f12
; M2-NEXT: # %bb.1: # %entry
; M2-NEXT: mov.s $f0, $f14
; M2-NEXT: $BB7_2: # %entry
Expand All @@ -581,14 +570,14 @@ define float @tst_select_fcmp_one_float(float %x, float %y) {
; CMOV32R1-LABEL: tst_select_fcmp_one_float:
; CMOV32R1: # %bb.0: # %entry
; CMOV32R1-NEXT: mov.s $f0, $f14
; CMOV32R1-NEXT: c.ueq.s $f12, $f0
; CMOV32R1-NEXT: c.ueq.s $f12, $f14
; CMOV32R1-NEXT: jr $ra
; CMOV32R1-NEXT: movf.s $f0, $f12, $fcc0
;
; CMOV32R2-LABEL: tst_select_fcmp_one_float:
; CMOV32R2: # %bb.0: # %entry
; CMOV32R2-NEXT: mov.s $f0, $f14
; CMOV32R2-NEXT: c.ueq.s $f12, $f0
; CMOV32R2-NEXT: c.ueq.s $f12, $f14
; CMOV32R2-NEXT: jr $ra
; CMOV32R2-NEXT: movf.s $f0, $f12, $fcc0
;
Expand All @@ -603,10 +592,9 @@ define float @tst_select_fcmp_one_float(float %x, float %y) {
;
; M3-LABEL: tst_select_fcmp_one_float:
; M3: # %bb.0: # %entry
; M3-NEXT: mov.s $f0, $f12
; M3-NEXT: c.ueq.s $f0, $f13
; M3-NEXT: c.ueq.s $f12, $f13
; M3-NEXT: bc1f .LBB7_2
; M3-NEXT: nop
; M3-NEXT: mov.s $f0, $f12
; M3-NEXT: # %bb.1: # %entry
; M3-NEXT: mov.s $f0, $f13
; M3-NEXT: .LBB7_2: # %entry
Expand All @@ -616,7 +604,7 @@ define float @tst_select_fcmp_one_float(float %x, float %y) {
; CMOV64-LABEL: tst_select_fcmp_one_float:
; CMOV64: # %bb.0: # %entry
; CMOV64-NEXT: mov.s $f0, $f13
; CMOV64-NEXT: c.ueq.s $f12, $f0
; CMOV64-NEXT: c.ueq.s $f12, $f13
; CMOV64-NEXT: jr $ra
; CMOV64-NEXT: movf.s $f0, $f12, $fcc0
;
Expand All @@ -632,7 +620,7 @@ define float @tst_select_fcmp_one_float(float %x, float %y) {
; MM32R3-LABEL: tst_select_fcmp_one_float:
; MM32R3: # %bb.0: # %entry
; MM32R3-NEXT: mov.s $f0, $f14
; MM32R3-NEXT: c.ueq.s $f12, $f0
; MM32R3-NEXT: c.ueq.s $f12, $f14
; MM32R3-NEXT: jr $ra
; MM32R3-NEXT: movf.s $f0, $f12, $fcc0
;
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/Mips/llvm-ir/shl.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -857,7 +857,7 @@ define signext i128 @shl_i128(i128 signext %a, i128 signext %b) {
; MMR3-NEXT: sw $5, 32($sp) # 4-byte Folded Spill
; MMR3-NEXT: move $1, $4
; MMR3-NEXT: lw $16, 76($sp)
; MMR3-NEXT: sllv $2, $1, $16
; MMR3-NEXT: sllv $2, $4, $16
; MMR3-NEXT: not16 $4, $16
; MMR3-NEXT: sw $4, 24($sp) # 4-byte Folded Spill
; MMR3-NEXT: srl16 $3, $5, 1
Expand Down Expand Up @@ -945,7 +945,7 @@ define signext i128 @shl_i128(i128 signext %a, i128 signext %b) {
; MMR6-NEXT: .cfi_offset 16, -8
; MMR6-NEXT: move $11, $4
; MMR6-NEXT: lw $3, 44($sp)
; MMR6-NEXT: sllv $1, $11, $3
; MMR6-NEXT: sllv $1, $4, $3
; MMR6-NEXT: not16 $2, $3
; MMR6-NEXT: sw $2, 4($sp) # 4-byte Folded Spill
; MMR6-NEXT: srl16 $16, $5, 1
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Mips/llvm-ir/sub.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -163,7 +163,7 @@ entry:
; MMR3: subu16 $5, $[[T19]], $[[T20]]

; MMR6: move $[[T0:[0-9]+]], $7
; MMR6: sw $[[T0]], 8($sp)
; MMR6: sw $7, 8($sp)
; MMR6: move $[[T1:[0-9]+]], $5
; MMR6: sw $4, 12($sp)
; MMR6: lw $[[T2:[0-9]+]], 48($sp)
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Mips/o32_cc_byval.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -193,7 +193,7 @@ define void @f4(float %f, %struct.S3* nocapture byval %s3, %struct.S1* nocapture
; CHECK-NEXT: move $4, $7
; CHECK-NEXT: sw $5, 52($sp)
; CHECK-NEXT: sw $6, 56($sp)
; CHECK-NEXT: sw $4, 60($sp)
; CHECK-NEXT: sw $7, 60($sp)
; CHECK-NEXT: lw $1, 80($sp)
; CHECK-NEXT: lb $2, 52($sp)
; CHECK-NEXT: addiu $3, $zero, 4
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/PowerPC/MCSE-caller-preserved-reg.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -20,9 +20,9 @@ define noalias i8* @_ZN2CC3funEv(%class.CC* %this) {
; CHECK-NEXT: .cfi_def_cfa_offset 48
; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: .cfi_offset r30, -16
; CHECK-NEXT: ld 12, 0(3)
; CHECK-NEXT: std 30, 32(1)
; CHECK-NEXT: mr 30, 3
; CHECK-NEXT: ld 12, 0(30)
; CHECK-NEXT: std 2, 24(1)
; CHECK-NEXT: mtctr 12
; CHECK-NEXT: bctrl
Expand Down
3 changes: 2 additions & 1 deletion llvm/test/CodeGen/PowerPC/fma-mutate.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,8 @@ define double @foo3(double %a) nounwind {
ret double %r

; CHECK: @foo3
; CHECK: xsnmsubadp [[REG:[0-9]+]], {{[0-9]+}}, [[REG]]
; CHECK: fmr [[REG:[0-9]+]], [[REG2:[0-9]+]]
; CHECK: xsnmsubadp [[REG]], {{[0-9]+}}, [[REG2]]
; CHECK: xsmaddmdp
; CHECK: xsmaddadp
}
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/PowerPC/gpr-vsr-spill.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -16,8 +16,8 @@ if.end: ; preds = %if.then, %entry
ret i32 %e.0
; CHECK: @foo
; CHECK: mr [[NEWREG:[0-9]+]], 3
; CHECK: mr [[REG1:[0-9]+]], 4
; CHECK: mtvsrd [[NEWREG2:[0-9]+]], 4
; CHECK: mffprd [[REG1:[0-9]+]], [[NEWREG2]]
; CHECK: add {{[0-9]+}}, [[NEWREG]], [[REG1]]
; CHECK: mffprd [[REG2:[0-9]+]], [[NEWREG2]]
; CHECK: add {{[0-9]+}}, [[REG2]], [[NEWREG]]
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/PowerPC/licm-remat.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -20,8 +20,8 @@ declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture r
define linkonce_odr void @ZN6snappyDecompressor_(%"class.snappy::SnappyDecompressor"* %this, %"class.snappy::SnappyIOVecWriter"* %writer) {
; CHECK-LABEL: ZN6snappyDecompressor_:
; CHECK: # %bb.0: # %entry
; CHECK: addis 3, 2, _ZN6snappy8internalL8wordmaskE@toc@ha
; CHECK-DAG: addi 25, 3, _ZN6snappy8internalL8wordmaskE@toc@l
; CHECK: addis 23, 2, _ZN6snappy8internalL8wordmaskE@toc@ha
; CHECK-DAG: addi 25, 23, _ZN6snappy8internalL8wordmaskE@toc@l
; CHECK-DAG: addis 5, 2, _ZN6snappy8internalL10char_tableE@toc@ha
; CHECK-DAG: addi 24, 5, _ZN6snappy8internalL10char_tableE@toc@l
; CHECK: b .LBB0_2
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/PowerPC/opt-li-add-to-addi.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@

define i64 @testOptimizeLiAddToAddi(i64 %a) {
; CHECK-LABEL: testOptimizeLiAddToAddi:
; CHECK: addi 3, 30, 2444
; CHECK: addi 3, 3, 2444
; CHECK: bl callv
; CHECK: addi 3, 30, 234
; CHECK: bl call
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/PowerPC/tail-dup-layout.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,7 @@ target triple = "powerpc64le-grtev4-linux-gnu"
;CHECK-LABEL: straight_test:
; test1 may have been merged with entry
;CHECK: mr [[TAGREG:[0-9]+]], 3
;CHECK: andi. {{[0-9]+}}, [[TAGREG]], 1
;CHECK: andi. {{[0-9]+}}, [[TAGREG:[0-9]+]], 1
;CHECK-NEXT: bc 12, 1, .[[OPT1LABEL:[_0-9A-Za-z]+]]
;CHECK-NEXT: # %test2
;CHECK-NEXT: rlwinm. {{[0-9]+}}, [[TAGREG]], 0, 30, 30
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/SPARC/32abi.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -148,9 +148,9 @@ define double @floatarg(double %a0, ; %i0,%i1
; HARD-NEXT: std %o0, [%sp+96]
; HARD-NEXT: st %o1, [%sp+92]
; HARD-NEXT: mov %i0, %o2
; HARD-NEXT: mov %o0, %o3
; HARD-NEXT: mov %i1, %o3
; HARD-NEXT: mov %o1, %o4
; HARD-NEXT: mov %o0, %o5
; HARD-NEXT: mov %i1, %o5
; HARD-NEXT: call floatarg
; HARD: std %f0, [%i4]
; SOFT: st %i0, [%sp+104]
Expand Down
5 changes: 3 additions & 2 deletions llvm/test/CodeGen/SPARC/atomics.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -235,8 +235,9 @@ entry:

; CHECK-LABEL: test_load_add_i32
; CHECK: membar
; CHECK: add [[V:%[gilo][0-7]]], %o1, [[U:%[gilo][0-7]]]
; CHECK: cas [%o0], [[V]], [[U]]
; CHECK: mov [[U:%[gilo][0-7]]], [[V:%[gilo][0-7]]]
; CHECK: add [[U:%[gilo][0-7]]], %o1, [[V2:%[gilo][0-7]]]
; CHECK: cas [%o0], [[V]], [[V2]]
; CHECK: membar
define zeroext i32 @test_load_add_i32(i32* %p, i32 zeroext %v) {
entry:
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/SystemZ/vec-sub-01.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -46,12 +46,12 @@ define <4 x float> @f5(<4 x float> %val1, <4 x float> %val2) {
; CHECK-LABEL: f5:
; CHECK-DAG: vlr %v[[A1:[0-5]]], %v24
; CHECK-DAG: vlr %v[[A2:[0-5]]], %v26
; CHECK-DAG: vrepf %v[[B1:[0-5]]], %v[[A1]], 1
; CHECK-DAG: vrepf %v[[B2:[0-5]]], %v[[A2]], 1
; CHECK-DAG: vrepf %v[[C1:[0-5]]], %v[[A1]], 2
; CHECK-DAG: vrepf %v[[C2:[0-5]]], %v[[A2]], 2
; CHECK-DAG: vrepf %v[[D1:[0-5]]], %v[[A1]], 3
; CHECK-DAG: vrepf %v[[D2:[0-5]]], %v[[A2]], 3
; CHECK-DAG: vrepf %v[[B1:[0-5]]], %v24, 1
; CHECK-DAG: vrepf %v[[B2:[0-5]]], %v26, 1
; CHECK-DAG: vrepf %v[[C1:[0-5]]], %v24, 2
; CHECK-DAG: vrepf %v[[C2:[0-5]]], %v26, 2
; CHECK-DAG: vrepf %v[[D1:[0-5]]], %v24, 3
; CHECK-DAG: vrepf %v[[D2:[0-5]]], %v26, 3
; CHECK-DAG: sebr %f[[A1]], %f[[A2]]
; CHECK-DAG: sebr %f[[B1]], %f[[B2]]
; CHECK-DAG: sebr %f[[C1]], %f[[C2]]
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/Thumb/pr35836.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -37,13 +37,13 @@ while.body:
; CHECK: adds r3, r0, r1
; CHECK: push {r5}
; CHECK: pop {r1}
; CHECK: adcs r1, r1
; CHECK: adcs r1, r5
; CHECK: ldr r0, [sp, #12] @ 4-byte Reload
; CHECK: ldr r2, [sp, #8] @ 4-byte Reload
; CHECK: adds r2, r0, r2
; CHECK: push {r5}
; CHECK: pop {r4}
; CHECK: adcs r4, r4
; CHECK: adcs r4, r5
; CHECK: adds r0, r2, r5
; CHECK: push {r3}
; CHECK: pop {r0}
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Thumb/thumb-shrink-wrapping.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -598,7 +598,7 @@ declare void @abort() #0
define i32 @b_to_bx(i32 %value) {
; CHECK-LABEL: b_to_bx:
; DISABLE: push {r7, lr}
; CHECK: cmp r1, #49
; CHECK: cmp r0, #49
; CHECK-NEXT: bgt [[ELSE_LABEL:LBB[0-9_]+]]
; ENABLE: push {r7, lr}

Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/X86/2006-03-01-InstrSchedBug.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@ define i32 @f(i32 %a, i32 %b) {
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movl %ecx, %edx
; CHECK-NEXT: imull %edx, %edx
; CHECK-NEXT: imull %ecx, %edx
; CHECK-NEXT: imull %eax, %ecx
; CHECK-NEXT: imull %eax, %eax
; CHECK-NEXT: addl %edx, %eax
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/X86/arg-copy-elide.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -106,7 +106,7 @@ entry:
; CHECK-DAG: movl %edx, %[[r1:[^ ]*]]
; CHECK-DAG: movl 8(%ebp), %[[r2:[^ ]*]]
; CHECK-DAG: movl %[[r2]], 4(%esp)
; CHECK-DAG: movl %[[r1]], (%esp)
; CHECK-DAG: movl %edx, (%esp)
; CHECK: movl %esp, %[[reg:[^ ]*]]
; CHECK: pushl %[[reg]]
; CHECK: calll _addrof_i64
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/X86/avg.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -2222,7 +2222,7 @@ define void @not_avg_v16i8_wide_constants(<16 x i8>* %a, <16 x i8>* %b) nounwind
; SSE2-NEXT: movq %rax, %xmm11
; SSE2-NEXT: movq -{{[0-9]+}}(%rsp), %rax # 8-byte Reload
; SSE2-NEXT: movq %rbp, %rcx
; SSE2-NEXT: shrdq $1, %rcx, %rax
; SSE2-NEXT: shrdq $1, %rbp, %rax
; SSE2-NEXT: pslldq {{.*#+}} xmm13 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm13[0,1,2]
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm15 = xmm15[0],xmm8[0]
; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255]
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/X86/avx-load-store.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -12,11 +12,11 @@ define void @test_256_load(double* nocapture %d, float* nocapture %f, <4 x i64>*
; CHECK-NEXT: movq %rdx, %r14
; CHECK-NEXT: movq %rsi, %r15
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: vmovaps (%rbx), %ymm0
; CHECK-NEXT: vmovaps (%rdi), %ymm0
; CHECK-NEXT: vmovups %ymm0, {{[0-9]+}}(%rsp) # 32-byte Spill
; CHECK-NEXT: vmovaps (%r15), %ymm1
; CHECK-NEXT: vmovaps (%rsi), %ymm1
; CHECK-NEXT: vmovups %ymm1, {{[0-9]+}}(%rsp) # 32-byte Spill
; CHECK-NEXT: vmovaps (%r14), %ymm2
; CHECK-NEXT: vmovaps (%rdx), %ymm2
; CHECK-NEXT: vmovups %ymm2, (%rsp) # 32-byte Spill
; CHECK-NEXT: callq dummy
; CHECK-NEXT: vmovups {{[0-9]+}}(%rsp), %ymm0 # 32-byte Reload
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/X86/avx512-bugfix-25270.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -9,10 +9,10 @@ define void @bar__512(<16 x i32>* %var) #0 {
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: subq $112, %rsp
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: vmovups (%rbx), %zmm0
; CHECK-NEXT: vmovups (%rdi), %zmm0
; CHECK-NEXT: vmovups %zmm0, (%rsp) ## 64-byte Spill
; CHECK-NEXT: vbroadcastss {{.*}}(%rip), %zmm1
; CHECK-NEXT: vmovaps %zmm1, (%rbx)
; CHECK-NEXT: vmovaps %zmm1, (%rdi)
; CHECK-NEXT: callq _Print__512
; CHECK-NEXT: vmovups (%rsp), %zmm0 ## 64-byte Reload
; CHECK-NEXT: callq _Print__512
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/X86/avx512-calling-conv.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -355,7 +355,7 @@ define i32 @test12(i32 %a1, i32 %a2, i32 %b1) {
; KNL_X32-NEXT: movl %edi, (%esp)
; KNL_X32-NEXT: calll _test11
; KNL_X32-NEXT: movl %eax, %ebx
; KNL_X32-NEXT: movzbl %bl, %eax
; KNL_X32-NEXT: movzbl %al, %eax
; KNL_X32-NEXT: movl %eax, {{[0-9]+}}(%esp)
; KNL_X32-NEXT: movl %esi, {{[0-9]+}}(%esp)
; KNL_X32-NEXT: movl %edi, (%esp)
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/X86/avx512-intel-ocl.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -148,7 +148,7 @@ define <16 x float> @testf16_regs(<16 x float> %a, <16 x float> %b) nounwind {
; X64-NEXT: andq $-64, %rsp
; X64-NEXT: subq $128, %rsp
; X64-NEXT: vmovaps %zmm1, %zmm16
; X64-NEXT: vaddps %zmm16, %zmm0, %zmm0
; X64-NEXT: vaddps %zmm1, %zmm0, %zmm0
; X64-NEXT: movq %rsp, %rdi
; X64-NEXT: callq _func_float16_ptr
; X64-NEXT: vaddps %zmm16, %zmm0, %zmm0
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/X86/avx512-regcall-NoMask.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -650,7 +650,7 @@ define x86_regcallcc <4 x i32> @test_CallargRet128Vector(<4 x i32> %a) {
; X32-NEXT: subl $24, %esp
; X32-NEXT: vmovups %xmm4, (%esp) # 16-byte Spill
; X32-NEXT: vmovdqa %xmm0, %xmm4
; X32-NEXT: vmovdqa %xmm4, %xmm1
; X32-NEXT: vmovdqa %xmm0, %xmm1
; X32-NEXT: calll _test_argRet128Vector
; X32-NEXT: vmovdqa32 %xmm4, %xmm0 {%k1}
; X32-NEXT: vmovups (%esp), %xmm4 # 16-byte Reload
Expand All @@ -668,7 +668,7 @@ define x86_regcallcc <4 x i32> @test_CallargRet128Vector(<4 x i32> %a) {
; WIN64-NEXT: .seh_savexmm 8, 0
; WIN64-NEXT: .seh_endprologue
; WIN64-NEXT: vmovdqa %xmm0, %xmm8
; WIN64-NEXT: vmovdqa %xmm8, %xmm1
; WIN64-NEXT: vmovdqa %xmm0, %xmm1
; WIN64-NEXT: callq test_argRet128Vector
; WIN64-NEXT: vmovdqa32 %xmm8, %xmm0 {%k1}
; WIN64-NEXT: vmovaps (%rsp), %xmm8 # 16-byte Reload
Expand All @@ -689,7 +689,7 @@ define x86_regcallcc <4 x i32> @test_CallargRet128Vector(<4 x i32> %a) {
; LINUXOSX64-NEXT: .cfi_offset %rsp, -16
; LINUXOSX64-NEXT: .cfi_offset %xmm8, -32
; LINUXOSX64-NEXT: vmovdqa %xmm0, %xmm8
; LINUXOSX64-NEXT: vmovdqa %xmm8, %xmm1
; LINUXOSX64-NEXT: vmovdqa %xmm0, %xmm1
; LINUXOSX64-NEXT: callq test_argRet128Vector
; LINUXOSX64-NEXT: vmovdqa32 %xmm8, %xmm0 {%k1}
; LINUXOSX64-NEXT: vmovaps (%rsp), %xmm8 # 16-byte Reload
Expand Down Expand Up @@ -908,12 +908,12 @@ define x86_regcallcc i32 @testi32_inp(i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a
; X32-NEXT: subl $20, %esp
; X32-NEXT: movl %esi, {{[0-9]+}}(%esp) # 4-byte Spill
; X32-NEXT: movl %edi, %esi
; X32-NEXT: movl %esi, {{[0-9]+}}(%esp) # 4-byte Spill
; X32-NEXT: movl %edi, {{[0-9]+}}(%esp) # 4-byte Spill
; X32-NEXT: movl %edx, %ebx
; X32-NEXT: movl %ebx, (%esp) # 4-byte Spill
; X32-NEXT: movl %edx, (%esp) # 4-byte Spill
; X32-NEXT: movl %ecx, {{[0-9]+}}(%esp) # 4-byte Spill
; X32-NEXT: movl %eax, %edx
; X32-NEXT: movl %edx, {{[0-9]+}}(%esp) # 4-byte Spill
; X32-NEXT: movl %eax, {{[0-9]+}}(%esp) # 4-byte Spill
; X32-NEXT: subl %ecx, %edx
; X32-NEXT: movl {{[0-9]+}}(%esp), %edi
; X32-NEXT: movl %edi, %ebp
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/X86/buildvec-insertvec.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -38,7 +38,7 @@ define <4 x float> @test_negative_zero_1(<4 x float> %A) {
; SSE2-LABEL: test_negative_zero_1:
; SSE2: # %bb.0: # %entry
; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE2-NEXT: xorps %xmm2, %xmm2
; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/X86/combine-fcopysign.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -197,8 +197,8 @@ define <4 x double> @combine_vec_fcopysign_fpext_sgn(<4 x double> %x, <4 x float
; SSE-NEXT: cvtss2sd %xmm2, %xmm4
; SSE-NEXT: movshdup {{.*#+}} xmm5 = xmm2[1,1,3,3]
; SSE-NEXT: movaps %xmm2, %xmm6
; SSE-NEXT: movhlps {{.*#+}} xmm6 = xmm6[1,1]
; SSE-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,1,2,3]
; SSE-NEXT: movhlps {{.*#+}} xmm6 = xmm2[1],xmm6[1]
; SSE-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,1],xmm2[2,3]
; SSE-NEXT: movaps {{.*#+}} xmm7
; SSE-NEXT: movaps %xmm0, %xmm2
; SSE-NEXT: andps %xmm7, %xmm2
Expand All @@ -213,7 +213,7 @@ define <4 x double> @combine_vec_fcopysign_fpext_sgn(<4 x double> %x, <4 x float
; SSE-NEXT: orps %xmm0, %xmm4
; SSE-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm4[0]
; SSE-NEXT: movaps %xmm1, %xmm0
; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm1[1],xmm0[1]
; SSE-NEXT: andps %xmm7, %xmm0
; SSE-NEXT: cvtss2sd %xmm3, %xmm3
; SSE-NEXT: andps %xmm8, %xmm3
Expand Down Expand Up @@ -260,7 +260,7 @@ define <4 x float> @combine_vec_fcopysign_fptrunc_sgn(<4 x float> %x, <4 x doubl
; SSE-NEXT: orps %xmm6, %xmm1
; SSE-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE-NEXT: movaps %xmm3, %xmm1
; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm3[1],xmm1[1]
; SSE-NEXT: andps %xmm5, %xmm1
; SSE-NEXT: xorps %xmm6, %xmm6
; SSE-NEXT: cvtsd2ss %xmm2, %xmm6
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/X86/combine-shl.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -188,7 +188,7 @@ define <8 x i32> @combine_vec_shl_ext_shl0(<8 x i16> %x) {
; SSE-LABEL: combine_vec_shl_ext_shl0:
; SSE: # %bb.0:
; SSE-NEXT: movdqa %xmm0, %xmm1
; SSE-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero
; SSE-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
; SSE-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
; SSE-NEXT: pslld $20, %xmm1
; SSE-NEXT: pslld $20, %xmm0
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/X86/complex-fastmath.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,7 @@ define <2 x float> @complex_square_f32(<2 x float>) #0 {
; SSE: # %bb.0:
; SSE-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE-NEXT: movaps %xmm0, %xmm2
; SSE-NEXT: addss %xmm2, %xmm2
; SSE-NEXT: addss %xmm0, %xmm2
; SSE-NEXT: mulss %xmm1, %xmm2
; SSE-NEXT: mulss %xmm0, %xmm0
; SSE-NEXT: mulss %xmm1, %xmm1
Expand Down Expand Up @@ -58,9 +58,9 @@ define <2 x double> @complex_square_f64(<2 x double>) #0 {
; SSE-LABEL: complex_square_f64:
; SSE: # %bb.0:
; SSE-NEXT: movaps %xmm0, %xmm1
; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-NEXT: movaps %xmm0, %xmm2
; SSE-NEXT: addsd %xmm2, %xmm2
; SSE-NEXT: addsd %xmm0, %xmm2
; SSE-NEXT: mulsd %xmm1, %xmm2
; SSE-NEXT: mulsd %xmm0, %xmm0
; SSE-NEXT: mulsd %xmm1, %xmm1
Expand Down Expand Up @@ -161,9 +161,9 @@ define <2 x double> @complex_mul_f64(<2 x double>, <2 x double>) #0 {
; SSE-LABEL: complex_mul_f64:
; SSE: # %bb.0:
; SSE-NEXT: movaps %xmm0, %xmm2
; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm2[1,1]
; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]
; SSE-NEXT: movaps %xmm1, %xmm3
; SSE-NEXT: movhlps {{.*#+}} xmm3 = xmm3[1,1]
; SSE-NEXT: movhlps {{.*#+}} xmm3 = xmm1[1],xmm3[1]
; SSE-NEXT: movaps %xmm3, %xmm4
; SSE-NEXT: mulsd %xmm0, %xmm4
; SSE-NEXT: mulsd %xmm1, %xmm0
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/X86/divide-by-constant.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -312,7 +312,7 @@ define i64 @PR23590(i64 %x) nounwind {
; X64: # %bb.0: # %entry
; X64-NEXT: movq %rdi, %rcx
; X64-NEXT: movabsq $6120523590596543007, %rdx # imm = 0x54F077C718E7C21F
; X64-NEXT: movq %rcx, %rax
; X64-NEXT: movq %rdi, %rax
; X64-NEXT: mulq %rdx
; X64-NEXT: shrq $12, %rdx
; X64-NEXT: imulq $12345, %rdx, %rax # imm = 0x3039
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/X86/fmaxnum.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@ declare <8 x double> @llvm.maxnum.v8f64(<8 x double>, <8 x double>)

; CHECK-LABEL: @test_fmaxf
; SSE: movaps %xmm0, %xmm2
; SSE-NEXT: cmpunordss %xmm2, %xmm2
; SSE-NEXT: cmpunordss %xmm0, %xmm2
; SSE-NEXT: movaps %xmm2, %xmm3
; SSE-NEXT: andps %xmm1, %xmm3
; SSE-NEXT: maxss %xmm0, %xmm1
Expand Down Expand Up @@ -47,7 +47,7 @@ define float @test_fmaxf_minsize(float %x, float %y) minsize {

; CHECK-LABEL: @test_fmax
; SSE: movapd %xmm0, %xmm2
; SSE-NEXT: cmpunordsd %xmm2, %xmm2
; SSE-NEXT: cmpunordsd %xmm0, %xmm2
; SSE-NEXT: movapd %xmm2, %xmm3
; SSE-NEXT: andpd %xmm1, %xmm3
; SSE-NEXT: maxsd %xmm0, %xmm1
Expand All @@ -74,7 +74,7 @@ define x86_fp80 @test_fmaxl(x86_fp80 %x, x86_fp80 %y) {

; CHECK-LABEL: @test_intrinsic_fmaxf
; SSE: movaps %xmm0, %xmm2
; SSE-NEXT: cmpunordss %xmm2, %xmm2
; SSE-NEXT: cmpunordss %xmm0, %xmm2
; SSE-NEXT: movaps %xmm2, %xmm3
; SSE-NEXT: andps %xmm1, %xmm3
; SSE-NEXT: maxss %xmm0, %xmm1
Expand All @@ -95,7 +95,7 @@ define float @test_intrinsic_fmaxf(float %x, float %y) {

; CHECK-LABEL: @test_intrinsic_fmax
; SSE: movapd %xmm0, %xmm2
; SSE-NEXT: cmpunordsd %xmm2, %xmm2
; SSE-NEXT: cmpunordsd %xmm0, %xmm2
; SSE-NEXT: movapd %xmm2, %xmm3
; SSE-NEXT: andpd %xmm1, %xmm3
; SSE-NEXT: maxsd %xmm0, %xmm1
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/X86/fmf-flags.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@ define float @fast_fmuladd_opts(float %a , float %b , float %c) {
; X64-LABEL: fast_fmuladd_opts:
; X64: # %bb.0:
; X64-NEXT: movaps %xmm0, %xmm1
; X64-NEXT: addss %xmm1, %xmm1
; X64-NEXT: addss %xmm0, %xmm1
; X64-NEXT: addss %xmm0, %xmm1
; X64-NEXT: movaps %xmm1, %xmm0
; X64-NEXT: retq
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/X86/fminnum.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@ declare <8 x double> @llvm.minnum.v8f64(<8 x double>, <8 x double>)

; CHECK-LABEL: @test_fminf
; SSE: movaps %xmm0, %xmm2
; SSE-NEXT: cmpunordss %xmm2, %xmm2
; SSE-NEXT: cmpunordss %xmm0, %xmm2
; SSE-NEXT: movaps %xmm2, %xmm3
; SSE-NEXT: andps %xmm1, %xmm3
; SSE-NEXT: minss %xmm0, %xmm1
Expand All @@ -40,7 +40,7 @@ define float @test_fminf(float %x, float %y) {

; CHECK-LABEL: @test_fmin
; SSE: movapd %xmm0, %xmm2
; SSE-NEXT: cmpunordsd %xmm2, %xmm2
; SSE-NEXT: cmpunordsd %xmm0, %xmm2
; SSE-NEXT: movapd %xmm2, %xmm3
; SSE-NEXT: andpd %xmm1, %xmm3
; SSE-NEXT: minsd %xmm0, %xmm1
Expand All @@ -67,7 +67,7 @@ define x86_fp80 @test_fminl(x86_fp80 %x, x86_fp80 %y) {

; CHECK-LABEL: @test_intrinsic_fminf
; SSE: movaps %xmm0, %xmm2
; SSE-NEXT: cmpunordss %xmm2, %xmm2
; SSE-NEXT: cmpunordss %xmm0, %xmm2
; SSE-NEXT: movaps %xmm2, %xmm3
; SSE-NEXT: andps %xmm1, %xmm3
; SSE-NEXT: minss %xmm0, %xmm1
Expand All @@ -87,7 +87,7 @@ define float @test_intrinsic_fminf(float %x, float %y) {

; CHECK-LABEL: @test_intrinsic_fmin
; SSE: movapd %xmm0, %xmm2
; SSE-NEXT: cmpunordsd %xmm2, %xmm2
; SSE-NEXT: cmpunordsd %xmm0, %xmm2
; SSE-NEXT: movapd %xmm2, %xmm3
; SSE-NEXT: andpd %xmm1, %xmm3
; SSE-NEXT: minsd %xmm0, %xmm1
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/X86/fp128-i128.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -227,7 +227,7 @@ define fp128 @TestI128_4(fp128 %x) #0 {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subq $40, %rsp
; CHECK-NEXT: movaps %xmm0, %xmm1
; CHECK-NEXT: movaps %xmm1, {{[0-9]+}}(%rsp)
; CHECK-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
; CHECK-NEXT: movq %rax, {{[0-9]+}}(%rsp)
; CHECK-NEXT: movq $0, (%rsp)
Expand Down Expand Up @@ -275,7 +275,7 @@ define fp128 @acosl(fp128 %x) #0 {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subq $40, %rsp
; CHECK-NEXT: movaps %xmm0, %xmm1
; CHECK-NEXT: movaps %xmm1, {{[0-9]+}}(%rsp)
; CHECK-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
; CHECK-NEXT: movq %rax, {{[0-9]+}}(%rsp)
; CHECK-NEXT: movq $0, (%rsp)
Expand Down
6 changes: 2 additions & 4 deletions llvm/test/CodeGen/X86/h-registers-1.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -32,8 +32,7 @@ define i64 @foo(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f, i64 %g, i64 %h)
; CHECK-NEXT: movzbl %ah, %eax
; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %ebx
; CHECK-NEXT: movzbl %bh, %edi
; CHECK-NEXT: movq %r10, %r8
; CHECK-NEXT: addq %r8, %rsi
; CHECK-NEXT: addq %r10, %rsi
; CHECK-NEXT: addq %r11, %rdx
; CHECK-NEXT: addq %rsi, %rdx
; CHECK-NEXT: addq %rbp, %rcx
Expand Down Expand Up @@ -68,8 +67,7 @@ define i64 @foo(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f, i64 %g, i64 %h)
; GNUX32-NEXT: movzbl %ah, %eax
; GNUX32-NEXT: movl {{[0-9]+}}(%esp), %ebx
; GNUX32-NEXT: movzbl %bh, %edi
; GNUX32-NEXT: movq %r10, %r8
; GNUX32-NEXT: addq %r8, %rsi
; GNUX32-NEXT: addq %r10, %rsi
; GNUX32-NEXT: addq %r11, %rdx
; GNUX32-NEXT: addq %rsi, %rdx
; GNUX32-NEXT: addq %rbp, %rcx
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/X86/haddsub-2.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -896,16 +896,16 @@ define <4 x float> @not_a_hsub_2(<4 x float> %A, <4 x float> %B) {
; SSE-LABEL: not_a_hsub_2:
; SSE: # %bb.0:
; SSE-NEXT: movaps %xmm0, %xmm2
; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm2[1,1]
; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]
; SSE-NEXT: movaps %xmm0, %xmm3
; SSE-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,1,2,3]
; SSE-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,1],xmm0[2,3]
; SSE-NEXT: subss %xmm3, %xmm2
; SSE-NEXT: movshdup {{.*#+}} xmm3 = xmm0[1,1,3,3]
; SSE-NEXT: subss %xmm3, %xmm0
; SSE-NEXT: movaps %xmm1, %xmm3
; SSE-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,1,2,3]
; SSE-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,1],xmm1[2,3]
; SSE-NEXT: movaps %xmm1, %xmm4
; SSE-NEXT: movhlps {{.*#+}} xmm4 = xmm4[1,1]
; SSE-NEXT: movhlps {{.*#+}} xmm4 = xmm1[1],xmm4[1]
; SSE-NEXT: subss %xmm4, %xmm3
; SSE-NEXT: movshdup {{.*#+}} xmm4 = xmm1[1,1,3,3]
; SSE-NEXT: subss %xmm4, %xmm1
Expand Down Expand Up @@ -953,10 +953,10 @@ define <2 x double> @not_a_hsub_3(<2 x double> %A, <2 x double> %B) {
; SSE-LABEL: not_a_hsub_3:
; SSE: # %bb.0:
; SSE-NEXT: movaps %xmm1, %xmm2
; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm2[1,1]
; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm1[1],xmm2[1]
; SSE-NEXT: subsd %xmm2, %xmm1
; SSE-NEXT: movaps %xmm0, %xmm2
; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm2[1,1]
; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]
; SSE-NEXT: subsd %xmm0, %xmm2
; SSE-NEXT: unpcklpd {{.*#+}} xmm2 = xmm2[0],xmm1[0]
; SSE-NEXT: movapd %xmm2, %xmm0
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/X86/haddsub-3.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,10 +7,10 @@ define float @pr26491(<4 x float> %a0) {
; SSE2-LABEL: pr26491:
; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,3,3]
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[3,3]
; SSE2-NEXT: addps %xmm0, %xmm1
; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm1[1],xmm0[1]
; SSE2-NEXT: addss %xmm1, %xmm0
; SSE2-NEXT: retq
;
Expand All @@ -19,7 +19,7 @@ define float @pr26491(<4 x float> %a0) {
; SSSE3-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSSE3-NEXT: addps %xmm0, %xmm1
; SSSE3-NEXT: movaps %xmm1, %xmm0
; SSSE3-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSSE3-NEXT: movhlps {{.*#+}} xmm0 = xmm1[1],xmm0[1]
; SSSE3-NEXT: addss %xmm1, %xmm0
; SSSE3-NEXT: retq
;
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/X86/haddsub-undef.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -103,7 +103,7 @@ define <2 x double> @test5_undef(<2 x double> %a, <2 x double> %b) {
; SSE-LABEL: test5_undef:
; SSE: # %bb.0:
; SSE-NEXT: movaps %xmm0, %xmm1
; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm0[1],xmm1[1]
; SSE-NEXT: addsd %xmm0, %xmm1
; SSE-NEXT: movapd %xmm1, %xmm0
; SSE-NEXT: retq
Expand Down Expand Up @@ -168,7 +168,7 @@ define <4 x float> @test8_undef(<4 x float> %a, <4 x float> %b) {
; SSE-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE-NEXT: addss %xmm0, %xmm1
; SSE-NEXT: movaps %xmm0, %xmm2
; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm2[1,1]
; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm0[1],xmm2[1]
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1,2,3]
; SSE-NEXT: addss %xmm2, %xmm0
; SSE-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/X86/half.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -386,7 +386,7 @@ define <4 x float> @test_extend32_vec4(<4 x half>* %p) #0 {
; CHECK-LIBCALL-NEXT: pushq %rbx
; CHECK-LIBCALL-NEXT: subq $48, %rsp
; CHECK-LIBCALL-NEXT: movq %rdi, %rbx
; CHECK-LIBCALL-NEXT: movzwl (%rbx), %edi
; CHECK-LIBCALL-NEXT: movzwl (%rdi), %edi
; CHECK-LIBCALL-NEXT: callq __gnu_h2f_ieee
; CHECK-LIBCALL-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp) # 16-byte Spill
; CHECK-LIBCALL-NEXT: movzwl 2(%rbx), %edi
Expand Down Expand Up @@ -472,7 +472,7 @@ define <4 x double> @test_extend64_vec4(<4 x half>* %p) #0 {
; CHECK-LIBCALL-NEXT: pushq %rbx
; CHECK-LIBCALL-NEXT: subq $16, %rsp
; CHECK-LIBCALL-NEXT: movq %rdi, %rbx
; CHECK-LIBCALL-NEXT: movzwl 4(%rbx), %edi
; CHECK-LIBCALL-NEXT: movzwl 4(%rdi), %edi
; CHECK-LIBCALL-NEXT: callq __gnu_h2f_ieee
; CHECK-LIBCALL-NEXT: movss %xmm0, {{[0-9]+}}(%rsp) # 4-byte Spill
; CHECK-LIBCALL-NEXT: movzwl 6(%rbx), %edi
Expand Down Expand Up @@ -657,7 +657,7 @@ define void @test_trunc32_vec4(<4 x float> %a, <4 x half>* %p) #0 {
; CHECK-I686-NEXT: movaps %xmm0, {{[0-9]+}}(%esp) # 16-byte Spill
; CHECK-I686-NEXT: movl {{[0-9]+}}(%esp), %ebp
; CHECK-I686-NEXT: movaps %xmm0, %xmm1
; CHECK-I686-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,2,3]
; CHECK-I686-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[2,3]
; CHECK-I686-NEXT: movss %xmm1, (%esp)
; CHECK-I686-NEXT: calll __gnu_f2h_ieee
; CHECK-I686-NEXT: movw %ax, %si
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/X86/horizontal-reduce-smax.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -40,7 +40,7 @@ define i64 @test_reduce_v2i64(<2 x i64> %a0) {
; X86-SSE42-LABEL: test_reduce_v2i64:
; X86-SSE42: ## %bb.0:
; X86-SSE42-NEXT: movdqa %xmm0, %xmm1
; X86-SSE42-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,0,1]
; X86-SSE42-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,0,1]
; X86-SSE42-NEXT: pcmpgtq %xmm2, %xmm0
; X86-SSE42-NEXT: blendvpd %xmm0, %xmm1, %xmm2
; X86-SSE42-NEXT: movd %xmm2, %eax
Expand Down Expand Up @@ -80,7 +80,7 @@ define i64 @test_reduce_v2i64(<2 x i64> %a0) {
; X64-SSE42-LABEL: test_reduce_v2i64:
; X64-SSE42: ## %bb.0:
; X64-SSE42-NEXT: movdqa %xmm0, %xmm1
; X64-SSE42-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,0,1]
; X64-SSE42-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,0,1]
; X64-SSE42-NEXT: pcmpgtq %xmm2, %xmm0
; X64-SSE42-NEXT: blendvpd %xmm0, %xmm1, %xmm2
; X64-SSE42-NEXT: movq %xmm2, %rax
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/X86/horizontal-reduce-smin.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -40,7 +40,7 @@ define i64 @test_reduce_v2i64(<2 x i64> %a0) {
; X86-SSE42-LABEL: test_reduce_v2i64:
; X86-SSE42: ## %bb.0:
; X86-SSE42-NEXT: movdqa %xmm0, %xmm1
; X86-SSE42-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,0,1]
; X86-SSE42-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,0,1]
; X86-SSE42-NEXT: movdqa %xmm2, %xmm0
; X86-SSE42-NEXT: pcmpgtq %xmm1, %xmm0
; X86-SSE42-NEXT: blendvpd %xmm0, %xmm1, %xmm2
Expand Down Expand Up @@ -81,7 +81,7 @@ define i64 @test_reduce_v2i64(<2 x i64> %a0) {
; X64-SSE42-LABEL: test_reduce_v2i64:
; X64-SSE42: ## %bb.0:
; X64-SSE42-NEXT: movdqa %xmm0, %xmm1
; X64-SSE42-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,0,1]
; X64-SSE42-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,0,1]
; X64-SSE42-NEXT: movdqa %xmm2, %xmm0
; X64-SSE42-NEXT: pcmpgtq %xmm1, %xmm0
; X64-SSE42-NEXT: blendvpd %xmm0, %xmm1, %xmm2
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/X86/horizontal-reduce-umax.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -40,7 +40,7 @@ define i64 @test_reduce_v2i64(<2 x i64> %a0) {
; X86-SSE42-LABEL: test_reduce_v2i64:
; X86-SSE42: ## %bb.0:
; X86-SSE42-NEXT: movdqa %xmm0, %xmm1
; X86-SSE42-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,0,1]
; X86-SSE42-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,0,1]
; X86-SSE42-NEXT: movdqa {{.*#+}} xmm3 = [0,2147483648,0,2147483648]
; X86-SSE42-NEXT: pxor %xmm3, %xmm0
; X86-SSE42-NEXT: pxor %xmm2, %xmm3
Expand Down Expand Up @@ -86,7 +86,7 @@ define i64 @test_reduce_v2i64(<2 x i64> %a0) {
; X64-SSE42-LABEL: test_reduce_v2i64:
; X64-SSE42: ## %bb.0:
; X64-SSE42-NEXT: movdqa %xmm0, %xmm1
; X64-SSE42-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,0,1]
; X64-SSE42-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,0,1]
; X64-SSE42-NEXT: movdqa {{.*#+}} xmm3 = [9223372036854775808,9223372036854775808]
; X64-SSE42-NEXT: pxor %xmm3, %xmm0
; X64-SSE42-NEXT: pxor %xmm2, %xmm3
Expand Down Expand Up @@ -1693,7 +1693,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) {
; X86-SSE2-NEXT: pxor %xmm4, %xmm1
; X86-SSE2-NEXT: pmaxsw %xmm3, %xmm1
; X86-SSE2-NEXT: movdqa %xmm4, %xmm2
; X86-SSE2-NEXT: pxor %xmm2, %xmm2
; X86-SSE2-NEXT: pxor %xmm4, %xmm2
; X86-SSE2-NEXT: pxor %xmm2, %xmm1
; X86-SSE2-NEXT: pxor %xmm0, %xmm2
; X86-SSE2-NEXT: pmaxsw %xmm1, %xmm2
Expand Down Expand Up @@ -1771,7 +1771,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) {
; X64-SSE2-NEXT: pxor %xmm4, %xmm1
; X64-SSE2-NEXT: pmaxsw %xmm3, %xmm1
; X64-SSE2-NEXT: movdqa %xmm4, %xmm2
; X64-SSE2-NEXT: pxor %xmm2, %xmm2
; X64-SSE2-NEXT: pxor %xmm4, %xmm2
; X64-SSE2-NEXT: pxor %xmm2, %xmm1
; X64-SSE2-NEXT: pxor %xmm0, %xmm2
; X64-SSE2-NEXT: pmaxsw %xmm1, %xmm2
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/X86/horizontal-reduce-umin.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -40,7 +40,7 @@ define i64 @test_reduce_v2i64(<2 x i64> %a0) {
; X86-SSE42-LABEL: test_reduce_v2i64:
; X86-SSE42: ## %bb.0:
; X86-SSE42-NEXT: movdqa %xmm0, %xmm1
; X86-SSE42-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,0,1]
; X86-SSE42-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,0,1]
; X86-SSE42-NEXT: movdqa {{.*#+}} xmm0 = [0,2147483648,0,2147483648]
; X86-SSE42-NEXT: movdqa %xmm1, %xmm3
; X86-SSE42-NEXT: pxor %xmm0, %xmm3
Expand Down Expand Up @@ -87,7 +87,7 @@ define i64 @test_reduce_v2i64(<2 x i64> %a0) {
; X64-SSE42-LABEL: test_reduce_v2i64:
; X64-SSE42: ## %bb.0:
; X64-SSE42-NEXT: movdqa %xmm0, %xmm1
; X64-SSE42-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,0,1]
; X64-SSE42-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,0,1]
; X64-SSE42-NEXT: movdqa {{.*#+}} xmm0 = [9223372036854775808,9223372036854775808]
; X64-SSE42-NEXT: movdqa %xmm1, %xmm3
; X64-SSE42-NEXT: pxor %xmm0, %xmm3
Expand Down Expand Up @@ -444,7 +444,7 @@ define i64 @test_reduce_v4i64(<4 x i64> %a0) {
; X86-SSE42: ## %bb.0:
; X86-SSE42-NEXT: movdqa %xmm0, %xmm2
; X86-SSE42-NEXT: movdqa {{.*#+}} xmm3 = [0,2147483648,0,2147483648]
; X86-SSE42-NEXT: movdqa %xmm2, %xmm4
; X86-SSE42-NEXT: movdqa %xmm0, %xmm4
; X86-SSE42-NEXT: pxor %xmm3, %xmm4
; X86-SSE42-NEXT: movdqa %xmm1, %xmm0
; X86-SSE42-NEXT: pxor %xmm3, %xmm0
Expand Down Expand Up @@ -543,7 +543,7 @@ define i64 @test_reduce_v4i64(<4 x i64> %a0) {
; X64-SSE42: ## %bb.0:
; X64-SSE42-NEXT: movdqa %xmm0, %xmm2
; X64-SSE42-NEXT: movdqa {{.*#+}} xmm3 = [9223372036854775808,9223372036854775808]
; X64-SSE42-NEXT: movdqa %xmm2, %xmm4
; X64-SSE42-NEXT: movdqa %xmm0, %xmm4
; X64-SSE42-NEXT: pxor %xmm3, %xmm4
; X64-SSE42-NEXT: movdqa %xmm1, %xmm0
; X64-SSE42-NEXT: pxor %xmm3, %xmm0
Expand Down Expand Up @@ -1597,7 +1597,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) {
; X86-SSE2-NEXT: pxor %xmm4, %xmm1
; X86-SSE2-NEXT: pminsw %xmm3, %xmm1
; X86-SSE2-NEXT: movdqa %xmm4, %xmm2
; X86-SSE2-NEXT: pxor %xmm2, %xmm2
; X86-SSE2-NEXT: pxor %xmm4, %xmm2
; X86-SSE2-NEXT: pxor %xmm2, %xmm1
; X86-SSE2-NEXT: pxor %xmm0, %xmm2
; X86-SSE2-NEXT: pminsw %xmm1, %xmm2
Expand Down Expand Up @@ -1666,7 +1666,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) {
; X64-SSE2-NEXT: pxor %xmm4, %xmm1
; X64-SSE2-NEXT: pminsw %xmm3, %xmm1
; X64-SSE2-NEXT: movdqa %xmm4, %xmm2
; X64-SSE2-NEXT: pxor %xmm2, %xmm2
; X64-SSE2-NEXT: pxor %xmm4, %xmm2
; X64-SSE2-NEXT: pxor %xmm2, %xmm1
; X64-SSE2-NEXT: pxor %xmm0, %xmm2
; X64-SSE2-NEXT: pminsw %xmm1, %xmm2
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/X86/i128-mul.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -145,8 +145,8 @@ define i64 @mul1(i64 %n, i64* nocapture %z, i64* nocapture %x, i64 %y) nounwind
; X86-NOBMI-NEXT: movl %eax, {{[0-9]+}}(%esp) # 4-byte Spill
; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NOBMI-NEXT: movl %eax, %ecx
; X86-NOBMI-NEXT: movl (%ecx,%ebx,8), %ebp
; X86-NOBMI-NEXT: movl 4(%ecx,%ebx,8), %esi
; X86-NOBMI-NEXT: movl (%eax,%ebx,8), %ebp
; X86-NOBMI-NEXT: movl 4(%eax,%ebx,8), %esi
; X86-NOBMI-NEXT: movl %esi, {{[0-9]+}}(%esp) # 4-byte Spill
; X86-NOBMI-NEXT: movl %ebp, %eax
; X86-NOBMI-NEXT: movl %ebp, {{[0-9]+}}(%esp) # 4-byte Spill
Expand Down Expand Up @@ -245,7 +245,7 @@ define i64 @mul1(i64 %n, i64* nocapture %z, i64* nocapture %x, i64 %y) nounwind
; X86-BMI-NEXT: movl %ecx, %edx
; X86-BMI-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BMI-NEXT: movl %eax, %esi
; X86-BMI-NEXT: mulxl %esi, %eax, %ebp
; X86-BMI-NEXT: mulxl %eax, %eax, %ebp
; X86-BMI-NEXT: movl %eax, {{[0-9]+}}(%esp) # 4-byte Spill
; X86-BMI-NEXT: movl %ebx, %edx
; X86-BMI-NEXT: mulxl %esi, %eax, %esi
Expand Down
1 change: 1 addition & 0 deletions llvm/test/CodeGen/X86/inline-asm-fpstack.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -161,6 +161,7 @@ define void @testPR4459(x86_fp80 %a) {
; CHECK-NEXT: fstpt (%esp)
; CHECK-NEXT: calll _ceil
; CHECK-NEXT: fld %st(0)
; CHECK-NEXT: fxch %st(1)
; CHECK-NEXT: ## InlineAsm Start
; CHECK-NEXT: fistpl %st(0)
; CHECK-NEXT: ## InlineAsm End
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/X86/ipra-local-linkage.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,7 @@ define void @bar(i32 %X) {
call void @foo()
; CHECK-LABEL: bar:
; CHECK: callq foo
; CHECK-NEXT: movl %eax, %r15d
; CHECK-NEXT: movl %edi, %r15d
call void asm sideeffect "movl $0, %r12d", "{r15}~{r12}"(i32 %X)
ret void
}
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/X86/legalize-shift.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@ define void @PR36250() {
; X86-NEXT: roll %ecx
; X86-NEXT: addl %eax, %eax
; X86-NEXT: movl %ecx, %edx
; X86-NEXT: orl %edx, %edx
; X86-NEXT: orl %ecx, %edx
; X86-NEXT: orl %ecx, %edx
; X86-NEXT: orl %eax, %edx
; X86-NEXT: orl %ecx, %edx
Expand All @@ -24,7 +24,7 @@ define void @PR36250() {
; X64-NEXT: rolq %rcx
; X64-NEXT: addq %rax, %rax
; X64-NEXT: movq %rcx, %rdx
; X64-NEXT: orq %rdx, %rdx
; X64-NEXT: orq %rcx, %rdx
; X64-NEXT: orq %rax, %rdx
; X64-NEXT: orq %rcx, %rdx
; X64-NEXT: sete (%rax)
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/X86/localescape.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -27,7 +27,7 @@ define void @print_framealloc_from_fp(i8* %fp) {

; X64-LABEL: print_framealloc_from_fp:
; X64: movq %rcx, %[[parent_fp:[a-z]+]]
; X64: movl .Lalloc_func$frame_escape_0(%[[parent_fp]]), %edx
; X64: movl .Lalloc_func$frame_escape_0(%rcx), %edx
; X64: leaq {{.*}}(%rip), %[[str:[a-z]+]]
; X64: movq %[[str]], %rcx
; X64: callq printf
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/X86/machine-cp.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@ define i32 @t1(i32 %a, i32 %b) nounwind {
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: movl %esi, %edx
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: testl %edx, %edx
; CHECK-NEXT: testl %esi, %esi
; CHECK-NEXT: je LBB0_1
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB0_2: ## %while.body
Expand Down Expand Up @@ -59,7 +59,7 @@ define i32 @t3(i64 %a, i64 %b) nounwind {
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: movq %rsi, %rdx
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: testq %rdx, %rdx
; CHECK-NEXT: testq %rsi, %rsi
; CHECK-NEXT: je LBB2_1
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB2_2: ## %while.body
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/X86/mmx-arith.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -580,7 +580,7 @@ define <1 x i64> @test3(<1 x i64>* %a, <1 x i64>* %b, i32 %count) nounwind {
; X32-NEXT: # =>This Inner Loop Header: Depth=1
; X32-NEXT: movl 8(%ebp), %ecx
; X32-NEXT: movl %ecx, %esi
; X32-NEXT: movl (%esi,%ebx,8), %ecx
; X32-NEXT: movl (%ecx,%ebx,8), %ecx
; X32-NEXT: movl 4(%esi,%ebx,8), %esi
; X32-NEXT: movl 12(%ebp), %edi
; X32-NEXT: addl (%edi,%ebx,8), %ecx
Expand Down
165 changes: 78 additions & 87 deletions llvm/test/CodeGen/X86/mul-i1024.ll
View file

Large diffs are not rendered by default.

10 changes: 5 additions & 5 deletions llvm/test/CodeGen/X86/mul-i256.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -44,7 +44,7 @@ define void @test(i256* %a, i256* %b, i256* %out) #0 {
; X32-NEXT: movl %edi, %eax
; X32-NEXT: mull %ecx
; X32-NEXT: movl %ecx, %edi
; X32-NEXT: movl %edi, {{[0-9]+}}(%esp) # 4-byte Spill
; X32-NEXT: movl %ecx, {{[0-9]+}}(%esp) # 4-byte Spill
; X32-NEXT: movl %edx, %ecx
; X32-NEXT: addl %ebx, %eax
; X32-NEXT: movl %eax, {{[0-9]+}}(%esp) # 4-byte Spill
Expand All @@ -62,9 +62,9 @@ define void @test(i256* %a, i256* %b, i256* %out) #0 {
; X32-NEXT: movl %ecx, %eax
; X32-NEXT: mull %edx
; X32-NEXT: movl %edx, %ebp
; X32-NEXT: movl %ebp, {{[0-9]+}}(%esp) # 4-byte Spill
; X32-NEXT: movl %edx, {{[0-9]+}}(%esp) # 4-byte Spill
; X32-NEXT: movl %eax, %esi
; X32-NEXT: movl %esi, (%esp) # 4-byte Spill
; X32-NEXT: movl %eax, (%esp) # 4-byte Spill
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax # 4-byte Reload
; X32-NEXT: xorl %edx, %edx
; X32-NEXT: mull %edx
Expand Down Expand Up @@ -127,7 +127,7 @@ define void @test(i256* %a, i256* %b, i256* %out) #0 {
; X32-NEXT: adcl $0, {{[0-9]+}}(%esp) # 4-byte Folded Spill
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movl %eax, %ecx
; X32-NEXT: movl 8(%ecx), %ebx
; X32-NEXT: movl 8(%eax), %ebx
; X32-NEXT: movl %esi, %eax
; X32-NEXT: movl %esi, %edi
; X32-NEXT: mull %ebx
Expand Down Expand Up @@ -156,7 +156,7 @@ define void @test(i256* %a, i256* %b, i256* %out) #0 {
; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax # 1-byte Folded Reload
; X32-NEXT: adcl %eax, %esi
; X32-NEXT: movl %ebx, %edi
; X32-NEXT: movl %edi, %eax
; X32-NEXT: movl %ebx, %eax
; X32-NEXT: xorl %ecx, %ecx
; X32-NEXT: mull %ecx
; X32-NEXT: movl %edx, {{[0-9]+}}(%esp) # 4-byte Spill
Expand Down
45 changes: 22 additions & 23 deletions llvm/test/CodeGen/X86/mul-i512.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -31,7 +31,7 @@ define void @test_512(i512* %a, i512* %b, i512* %out) nounwind {
; X32-NEXT: movl %edi, (%esp) # 4-byte Spill
; X32-NEXT: adcl %ecx, %ebx
; X32-NEXT: movl %ecx, %edi
; X32-NEXT: movl %edi, {{[0-9]+}}(%esp) # 4-byte Spill
; X32-NEXT: movl %ecx, {{[0-9]+}}(%esp) # 4-byte Spill
; X32-NEXT: setb %cl
; X32-NEXT: addl %eax, %ebx
; X32-NEXT: movzbl %cl, %ecx
Expand All @@ -55,7 +55,7 @@ define void @test_512(i512* %a, i512* %b, i512* %out) nounwind {
; X32-NEXT: mull %ebx
; X32-NEXT: movl %eax, %ebp
; X32-NEXT: movl %edx, %edi
; X32-NEXT: movl %edi, {{[0-9]+}}(%esp) # 4-byte Spill
; X32-NEXT: movl %edx, {{[0-9]+}}(%esp) # 4-byte Spill
; X32-NEXT: movl 4(%ecx), %eax
; X32-NEXT: movl %eax, {{[0-9]+}}(%esp) # 4-byte Spill
; X32-NEXT: movl %ecx, %esi
Expand Down Expand Up @@ -92,14 +92,13 @@ define void @test_512(i512* %a, i512* %b, i512* %out) nounwind {
; X32-NEXT: adcl %edi, %eax
; X32-NEXT: movl %eax, {{[0-9]+}}(%esp) # 4-byte Spill
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movl %ecx, %eax
; X32-NEXT: movl (%eax), %eax
; X32-NEXT: movl (%ecx), %eax
; X32-NEXT: movl %eax, {{[0-9]+}}(%esp) # 4-byte Spill
; X32-NEXT: xorl %ebp, %ebp
; X32-NEXT: mull %ebp
; X32-NEXT: movl %edx, %ebx
; X32-NEXT: movl %eax, %ecx
; X32-NEXT: movl %ecx, %edx
; X32-NEXT: movl %eax, %edx
; X32-NEXT: addl %esi, %edx
; X32-NEXT: movl %esi, {{[0-9]+}}(%esp) # 4-byte Spill
; X32-NEXT: movl %ebx, %eax
Expand All @@ -113,7 +112,7 @@ define void @test_512(i512* %a, i512* %b, i512* %out) nounwind {
; X32-NEXT: movl %edx, {{[0-9]+}}(%esp) # 4-byte Spill
; X32-NEXT: movl %ecx, %edi
; X32-NEXT: movl %ecx, %ebp
; X32-NEXT: movl %ebp, {{[0-9]+}}(%esp) # 4-byte Spill
; X32-NEXT: movl %ecx, {{[0-9]+}}(%esp) # 4-byte Spill
; X32-NEXT: addl %eax, %edi
; X32-NEXT: movl %ebx, %eax
; X32-NEXT: adcl %edx, %eax
Expand Down Expand Up @@ -143,7 +142,7 @@ define void @test_512(i512* %a, i512* %b, i512* %out) nounwind {
; X32-NEXT: movl %esi, {{[0-9]+}}(%esp) # 4-byte Spill
; X32-NEXT: adcl %ebx, %ecx
; X32-NEXT: movl %ebx, %esi
; X32-NEXT: movl %esi, {{[0-9]+}}(%esp) # 4-byte Spill
; X32-NEXT: movl %ebx, {{[0-9]+}}(%esp) # 4-byte Spill
; X32-NEXT: setb %bl
; X32-NEXT: addl %eax, %ecx
; X32-NEXT: movzbl %bl, %ebx
Expand Down Expand Up @@ -278,7 +277,7 @@ define void @test_512(i512* %a, i512* %b, i512* %out) nounwind {
; X32-NEXT: adcl %ebx, %ecx
; X32-NEXT: setb {{[0-9]+}}(%esp) # 1-byte Folded Spill
; X32-NEXT: movl %edi, %ebp
; X32-NEXT: movl %ebp, %eax
; X32-NEXT: movl %edi, %eax
; X32-NEXT: mull %esi
; X32-NEXT: movl %edx, %edi
; X32-NEXT: movl %eax, %ebx
Expand Down Expand Up @@ -433,7 +432,7 @@ define void @test_512(i512* %a, i512* %b, i512* %out) nounwind {
; X32-NEXT: adcl %edi, %ecx
; X32-NEXT: setb {{[0-9]+}}(%esp) # 1-byte Folded Spill
; X32-NEXT: movl %ebx, %edi
; X32-NEXT: movl %edi, %eax
; X32-NEXT: movl %ebx, %eax
; X32-NEXT: mull %esi
; X32-NEXT: movl %eax, %ebp
; X32-NEXT: addl %ecx, %ebp
Expand Down Expand Up @@ -899,7 +898,7 @@ define void @test_512(i512* %a, i512* %b, i512* %out) nounwind {
; X32-NEXT: movl %ecx, %eax
; X32-NEXT: mull %esi
; X32-NEXT: movl %esi, %ecx
; X32-NEXT: movl %ecx, {{[0-9]+}}(%esp) # 4-byte Spill
; X32-NEXT: movl %esi, {{[0-9]+}}(%esp) # 4-byte Spill
; X32-NEXT: movl %edx, %esi
; X32-NEXT: addl %ebx, %eax
; X32-NEXT: movl %eax, {{[0-9]+}}(%esp) # 4-byte Spill
Expand Down Expand Up @@ -929,7 +928,7 @@ define void @test_512(i512* %a, i512* %b, i512* %out) nounwind {
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx # 4-byte Reload
; X32-NEXT: movl %ecx, %eax
; X32-NEXT: movl %ebx, %esi
; X32-NEXT: mull %esi
; X32-NEXT: mull %ebx
; X32-NEXT: movl %edx, %edi
; X32-NEXT: movl %eax, {{[0-9]+}}(%esp) # 4-byte Spill
; X32-NEXT: movl {{[0-9]+}}(%esp), %ebx # 4-byte Reload
Expand Down Expand Up @@ -1077,7 +1076,7 @@ define void @test_512(i512* %a, i512* %b, i512* %out) nounwind {
; X32-NEXT: addl %esi, %edx
; X32-NEXT: movl {{[0-9]+}}(%esp), %esi # 4-byte Reload
; X32-NEXT: movl %edi, %eax
; X32-NEXT: imull %eax, %esi
; X32-NEXT: imull %edi, %esi
; X32-NEXT: addl %edx, %esi
; X32-NEXT: addl {{[0-9]+}}(%esp), %ecx # 4-byte Folded Reload
; X32-NEXT: movl %ecx, {{[0-9]+}}(%esp) # 4-byte Spill
Expand Down Expand Up @@ -1177,7 +1176,7 @@ define void @test_512(i512* %a, i512* %b, i512* %out) nounwind {
; X32-NEXT: movl %edx, {{[0-9]+}}(%esp) # 4-byte Spill
; X32-NEXT: movl {{[0-9]+}}(%esp), %esi
; X32-NEXT: movl %esi, %ecx
; X32-NEXT: movl 40(%ecx), %ebx
; X32-NEXT: movl 40(%esi), %ebx
; X32-NEXT: movl %ebx, %eax
; X32-NEXT: movl %ebx, {{[0-9]+}}(%esp) # 4-byte Spill
; X32-NEXT: movl {{[0-9]+}}(%esp), %esi # 4-byte Reload
Expand Down Expand Up @@ -1374,7 +1373,7 @@ define void @test_512(i512* %a, i512* %b, i512* %out) nounwind {
; X32-NEXT: addl %edi, %edx
; X32-NEXT: movl 60(%ebx), %ebx
; X32-NEXT: movl %ecx, %eax
; X32-NEXT: imull %eax, %ebx
; X32-NEXT: imull %ecx, %ebx
; X32-NEXT: addl %edx, %ebx
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx # 4-byte Reload
; X32-NEXT: addl %ecx, {{[0-9]+}}(%esp) # 4-byte Folded Spill
Expand Down Expand Up @@ -1546,7 +1545,7 @@ define void @test_512(i512* %a, i512* %b, i512* %out) nounwind {
; X64-NEXT: movq 8(%rsi), %rbp
; X64-NEXT: movq %r15, %rax
; X64-NEXT: movq %rdx, %rsi
; X64-NEXT: mulq %rsi
; X64-NEXT: mulq %rdx
; X64-NEXT: movq %rdx, %r9
; X64-NEXT: movq %rax, %r8
; X64-NEXT: movq %r11, %rax
Expand All @@ -1569,23 +1568,23 @@ define void @test_512(i512* %a, i512* %b, i512* %out) nounwind {
; X64-NEXT: movq %r11, %rax
; X64-NEXT: mulq %rbp
; X64-NEXT: movq %rbp, %r14
; X64-NEXT: movq %r14, -{{[0-9]+}}(%rsp) # 8-byte Spill
; X64-NEXT: movq %rbp, -{{[0-9]+}}(%rsp) # 8-byte Spill
; X64-NEXT: movq %rdx, %rsi
; X64-NEXT: movq %rax, %rbp
; X64-NEXT: addq %rcx, %rbp
; X64-NEXT: adcq %rbx, %rsi
; X64-NEXT: xorl %ecx, %ecx
; X64-NEXT: movq %r10, %rbx
; X64-NEXT: movq %rbx, -{{[0-9]+}}(%rsp) # 8-byte Spill
; X64-NEXT: movq %rbx, %rax
; X64-NEXT: movq %r10, -{{[0-9]+}}(%rsp) # 8-byte Spill
; X64-NEXT: movq %r10, %rax
; X64-NEXT: mulq %rcx
; X64-NEXT: movq %rdx, %r13
; X64-NEXT: movq %rax, %r10
; X64-NEXT: movq %r15, %rax
; X64-NEXT: mulq %rcx
; X64-NEXT: movq %rdx, -{{[0-9]+}}(%rsp) # 8-byte Spill
; X64-NEXT: movq %rax, %r15
; X64-NEXT: movq %r15, -{{[0-9]+}}(%rsp) # 8-byte Spill
; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill
; X64-NEXT: addq %r10, %r15
; X64-NEXT: adcq %r13, %rdx
; X64-NEXT: addq %rbp, %r15
Expand Down Expand Up @@ -1624,8 +1623,8 @@ define void @test_512(i512* %a, i512* %b, i512* %out) nounwind {
; X64-NEXT: mulq %rdx
; X64-NEXT: movq %rdx, %r14
; X64-NEXT: movq %rax, %r11
; X64-NEXT: addq %r11, %r10
; X64-NEXT: adcq %r14, %r13
; X64-NEXT: addq %rax, %r10
; X64-NEXT: adcq %rdx, %r13
; X64-NEXT: addq %rbp, %r10
; X64-NEXT: adcq %rsi, %r13
; X64-NEXT: addq %r8, %r10
Expand All @@ -1637,7 +1636,7 @@ define void @test_512(i512* %a, i512* %b, i512* %out) nounwind {
; X64-NEXT: movq 16(%rsi), %r8
; X64-NEXT: movq %rcx, %rax
; X64-NEXT: movq %rcx, %r9
; X64-NEXT: movq %r9, -{{[0-9]+}}(%rsp) # 8-byte Spill
; X64-NEXT: movq %rcx, -{{[0-9]+}}(%rsp) # 8-byte Spill
; X64-NEXT: mulq %r8
; X64-NEXT: movq %rdx, %rdi
; X64-NEXT: movq %rax, %r12
Expand Down Expand Up @@ -1668,7 +1667,7 @@ define void @test_512(i512* %a, i512* %b, i512* %out) nounwind {
; X64-NEXT: mulq %rcx
; X64-NEXT: movq %rdx, -{{[0-9]+}}(%rsp) # 8-byte Spill
; X64-NEXT: movq %rax, %rbp
; X64-NEXT: addq %rbp, %r11
; X64-NEXT: addq %rax, %r11
; X64-NEXT: adcq %rdx, %r14
; X64-NEXT: addq %r9, %r11
; X64-NEXT: adcq %rbx, %r14
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/X86/mul128.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@ define i128 @foo(i128 %t, i128 %u) {
; X64-NEXT: movq %rdx, %r8
; X64-NEXT: imulq %rdi, %rcx
; X64-NEXT: movq %rdi, %rax
; X64-NEXT: mulq %r8
; X64-NEXT: mulq %rdx
; X64-NEXT: addq %rcx, %rdx
; X64-NEXT: imulq %r8, %rsi
; X64-NEXT: addq %rsi, %rdx
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/X86/mulvi32.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -234,7 +234,7 @@ define <4 x i64> @_mul4xi32toi64b(<4 x i32>, <4 x i32>) {
; SSE-LABEL: _mul4xi32toi64b:
; SSE: # %bb.0:
; SSE-NEXT: movdqa %xmm0, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,3,3]
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
; SSE-NEXT: pmuludq %xmm1, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; SSE-NEXT: pmuludq %xmm0, %xmm1
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/X86/musttail-varargs.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -209,9 +209,9 @@ define void @f_thunk(i8* %this, ...) {
; WINDOWS-NEXT: movq %r8, %rdi
; WINDOWS-NEXT: movq %rdx, %rbx
; WINDOWS-NEXT: movq %rcx, %rbp
; WINDOWS-NEXT: movq %rsi, {{[0-9]+}}(%rsp)
; WINDOWS-NEXT: movq %rdi, {{[0-9]+}}(%rsp)
; WINDOWS-NEXT: movq %rbx, {{[0-9]+}}(%rsp)
; WINDOWS-NEXT: movq %r9, {{[0-9]+}}(%rsp)
; WINDOWS-NEXT: movq %r8, {{[0-9]+}}(%rsp)
; WINDOWS-NEXT: movq %rdx, {{[0-9]+}}(%rsp)
; WINDOWS-NEXT: leaq {{[0-9]+}}(%rsp), %rax
; WINDOWS-NEXT: movq %rax, {{[0-9]+}}(%rsp)
; WINDOWS-NEXT: callq get_f
Expand Down
48 changes: 24 additions & 24 deletions llvm/test/CodeGen/X86/pmul.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@ define <16 x i8> @mul_v16i8c(<16 x i8> %i) nounwind {
; SSE2-LABEL: mul_v16i8c:
; SSE2: # %bb.0: # %entry
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; SSE2-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15]
; SSE2-NEXT: psraw $8, %xmm1
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [117,117,117,117,117,117,117,117]
; SSE2-NEXT: pmullw %xmm2, %xmm1
Expand Down Expand Up @@ -143,10 +143,10 @@ define <16 x i8> @mul_v16i8(<16 x i8> %i, <16 x i8> %j) nounwind {
; SSE2-LABEL: mul_v16i8:
; SSE2: # %bb.0: # %entry
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]
; SSE2-NEXT: psraw $8, %xmm2
; SSE2-NEXT: movdqa %xmm0, %xmm3
; SSE2-NEXT: punpckhbw {{.*#+}} xmm3 = xmm3[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; SSE2-NEXT: punpckhbw {{.*#+}} xmm3 = xmm3[8],xmm0[8],xmm3[9],xmm0[9],xmm3[10],xmm0[10],xmm3[11],xmm0[11],xmm3[12],xmm0[12],xmm3[13],xmm0[13],xmm3[14],xmm0[14],xmm3[15],xmm0[15]
; SSE2-NEXT: psraw $8, %xmm3
; SSE2-NEXT: pmullw %xmm2, %xmm3
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255]
Expand Down Expand Up @@ -386,7 +386,7 @@ define <32 x i8> @mul_v32i8c(<32 x i8> %i) nounwind {
; SSE2-LABEL: mul_v32i8c:
; SSE2: # %bb.0: # %entry
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm0[8],xmm2[9],xmm0[9],xmm2[10],xmm0[10],xmm2[11],xmm0[11],xmm2[12],xmm0[12],xmm2[13],xmm0[13],xmm2[14],xmm0[14],xmm2[15],xmm0[15]
; SSE2-NEXT: psraw $8, %xmm2
; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [117,117,117,117,117,117,117,117]
; SSE2-NEXT: pmullw %xmm3, %xmm2
Expand All @@ -398,7 +398,7 @@ define <32 x i8> @mul_v32i8c(<32 x i8> %i) nounwind {
; SSE2-NEXT: pand %xmm4, %xmm0
; SSE2-NEXT: packuswb %xmm2, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]
; SSE2-NEXT: psraw $8, %xmm2
; SSE2-NEXT: pmullw %xmm3, %xmm2
; SSE2-NEXT: pand %xmm4, %xmm2
Expand Down Expand Up @@ -567,10 +567,10 @@ define <32 x i8> @mul_v32i8(<32 x i8> %i, <32 x i8> %j) nounwind {
; SSE2-LABEL: mul_v32i8:
; SSE2: # %bb.0: # %entry
; SSE2-NEXT: movdqa %xmm2, %xmm4
; SSE2-NEXT: punpckhbw {{.*#+}} xmm4 = xmm4[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; SSE2-NEXT: punpckhbw {{.*#+}} xmm4 = xmm4[8],xmm2[8],xmm4[9],xmm2[9],xmm4[10],xmm2[10],xmm4[11],xmm2[11],xmm4[12],xmm2[12],xmm4[13],xmm2[13],xmm4[14],xmm2[14],xmm4[15],xmm2[15]
; SSE2-NEXT: psraw $8, %xmm4
; SSE2-NEXT: movdqa %xmm0, %xmm5
; SSE2-NEXT: punpckhbw {{.*#+}} xmm5 = xmm5[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; SSE2-NEXT: punpckhbw {{.*#+}} xmm5 = xmm5[8],xmm0[8],xmm5[9],xmm0[9],xmm5[10],xmm0[10],xmm5[11],xmm0[11],xmm5[12],xmm0[12],xmm5[13],xmm0[13],xmm5[14],xmm0[14],xmm5[15],xmm0[15]
; SSE2-NEXT: psraw $8, %xmm5
; SSE2-NEXT: pmullw %xmm4, %xmm5
; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [255,255,255,255,255,255,255,255]
Expand All @@ -583,10 +583,10 @@ define <32 x i8> @mul_v32i8(<32 x i8> %i, <32 x i8> %j) nounwind {
; SSE2-NEXT: pand %xmm4, %xmm0
; SSE2-NEXT: packuswb %xmm5, %xmm0
; SSE2-NEXT: movdqa %xmm3, %xmm2
; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm3[8],xmm2[9],xmm3[9],xmm2[10],xmm3[10],xmm2[11],xmm3[11],xmm2[12],xmm3[12],xmm2[13],xmm3[13],xmm2[14],xmm3[14],xmm2[15],xmm3[15]
; SSE2-NEXT: psraw $8, %xmm2
; SSE2-NEXT: movdqa %xmm1, %xmm5
; SSE2-NEXT: punpckhbw {{.*#+}} xmm5 = xmm5[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; SSE2-NEXT: punpckhbw {{.*#+}} xmm5 = xmm5[8],xmm1[8],xmm5[9],xmm1[9],xmm5[10],xmm1[10],xmm5[11],xmm1[11],xmm5[12],xmm1[12],xmm5[13],xmm1[13],xmm5[14],xmm1[14],xmm5[15],xmm1[15]
; SSE2-NEXT: psraw $8, %xmm5
; SSE2-NEXT: pmullw %xmm2, %xmm5
; SSE2-NEXT: pand %xmm4, %xmm5
Expand Down Expand Up @@ -774,7 +774,7 @@ define <64 x i8> @mul_v64i8c(<64 x i8> %i) nounwind {
; SSE2-LABEL: mul_v64i8c:
; SSE2: # %bb.0: # %entry
; SSE2-NEXT: movdqa %xmm0, %xmm6
; SSE2-NEXT: punpckhbw {{.*#+}} xmm6 = xmm6[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; SSE2-NEXT: punpckhbw {{.*#+}} xmm6 = xmm6[8],xmm0[8],xmm6[9],xmm0[9],xmm6[10],xmm0[10],xmm6[11],xmm0[11],xmm6[12],xmm0[12],xmm6[13],xmm0[13],xmm6[14],xmm0[14],xmm6[15],xmm0[15]
; SSE2-NEXT: psraw $8, %xmm6
; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [117,117,117,117,117,117,117,117]
; SSE2-NEXT: pmullw %xmm4, %xmm6
Expand All @@ -786,7 +786,7 @@ define <64 x i8> @mul_v64i8c(<64 x i8> %i) nounwind {
; SSE2-NEXT: pand %xmm5, %xmm0
; SSE2-NEXT: packuswb %xmm6, %xmm0
; SSE2-NEXT: movdqa %xmm1, %xmm6
; SSE2-NEXT: punpckhbw {{.*#+}} xmm6 = xmm6[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; SSE2-NEXT: punpckhbw {{.*#+}} xmm6 = xmm6[8],xmm1[8],xmm6[9],xmm1[9],xmm6[10],xmm1[10],xmm6[11],xmm1[11],xmm6[12],xmm1[12],xmm6[13],xmm1[13],xmm6[14],xmm1[14],xmm6[15],xmm1[15]
; SSE2-NEXT: psraw $8, %xmm6
; SSE2-NEXT: pmullw %xmm4, %xmm6
; SSE2-NEXT: pand %xmm5, %xmm6
Expand All @@ -796,7 +796,7 @@ define <64 x i8> @mul_v64i8c(<64 x i8> %i) nounwind {
; SSE2-NEXT: pand %xmm5, %xmm1
; SSE2-NEXT: packuswb %xmm6, %xmm1
; SSE2-NEXT: movdqa %xmm2, %xmm6
; SSE2-NEXT: punpckhbw {{.*#+}} xmm6 = xmm6[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; SSE2-NEXT: punpckhbw {{.*#+}} xmm6 = xmm6[8],xmm2[8],xmm6[9],xmm2[9],xmm6[10],xmm2[10],xmm6[11],xmm2[11],xmm6[12],xmm2[12],xmm6[13],xmm2[13],xmm6[14],xmm2[14],xmm6[15],xmm2[15]
; SSE2-NEXT: psraw $8, %xmm6
; SSE2-NEXT: pmullw %xmm4, %xmm6
; SSE2-NEXT: pand %xmm5, %xmm6
Expand All @@ -806,7 +806,7 @@ define <64 x i8> @mul_v64i8c(<64 x i8> %i) nounwind {
; SSE2-NEXT: pand %xmm5, %xmm2
; SSE2-NEXT: packuswb %xmm6, %xmm2
; SSE2-NEXT: movdqa %xmm3, %xmm6
; SSE2-NEXT: punpckhbw {{.*#+}} xmm6 = xmm6[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; SSE2-NEXT: punpckhbw {{.*#+}} xmm6 = xmm6[8],xmm3[8],xmm6[9],xmm3[9],xmm6[10],xmm3[10],xmm6[11],xmm3[11],xmm6[12],xmm3[12],xmm6[13],xmm3[13],xmm6[14],xmm3[14],xmm6[15],xmm3[15]
; SSE2-NEXT: psraw $8, %xmm6
; SSE2-NEXT: pmullw %xmm4, %xmm6
; SSE2-NEXT: pand %xmm5, %xmm6
Expand All @@ -821,7 +821,7 @@ define <64 x i8> @mul_v64i8c(<64 x i8> %i) nounwind {
; SSE41: # %bb.0: # %entry
; SSE41-NEXT: movdqa %xmm1, %xmm4
; SSE41-NEXT: movdqa %xmm0, %xmm1
; SSE41-NEXT: pmovsxbw %xmm1, %xmm0
; SSE41-NEXT: pmovsxbw %xmm0, %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm6 = [117,117,117,117,117,117,117,117]
; SSE41-NEXT: pmullw %xmm6, %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm7 = [255,255,255,255,255,255,255,255]
Expand Down Expand Up @@ -939,10 +939,10 @@ define <64 x i8> @mul_v64i8(<64 x i8> %i, <64 x i8> %j) nounwind {
; SSE2-LABEL: mul_v64i8:
; SSE2: # %bb.0: # %entry
; SSE2-NEXT: movdqa %xmm4, %xmm8
; SSE2-NEXT: punpckhbw {{.*#+}} xmm8 = xmm8[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; SSE2-NEXT: punpckhbw {{.*#+}} xmm8 = xmm8[8],xmm4[8],xmm8[9],xmm4[9],xmm8[10],xmm4[10],xmm8[11],xmm4[11],xmm8[12],xmm4[12],xmm8[13],xmm4[13],xmm8[14],xmm4[14],xmm8[15],xmm4[15]
; SSE2-NEXT: psraw $8, %xmm8
; SSE2-NEXT: movdqa %xmm0, %xmm9
; SSE2-NEXT: punpckhbw {{.*#+}} xmm9 = xmm9[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; SSE2-NEXT: punpckhbw {{.*#+}} xmm9 = xmm9[8],xmm0[8],xmm9[9],xmm0[9],xmm9[10],xmm0[10],xmm9[11],xmm0[11],xmm9[12],xmm0[12],xmm9[13],xmm0[13],xmm9[14],xmm0[14],xmm9[15],xmm0[15]
; SSE2-NEXT: psraw $8, %xmm9
; SSE2-NEXT: pmullw %xmm8, %xmm9
; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [255,255,255,255,255,255,255,255]
Expand All @@ -955,10 +955,10 @@ define <64 x i8> @mul_v64i8(<64 x i8> %i, <64 x i8> %j) nounwind {
; SSE2-NEXT: pand %xmm8, %xmm0
; SSE2-NEXT: packuswb %xmm9, %xmm0
; SSE2-NEXT: movdqa %xmm5, %xmm9
; SSE2-NEXT: punpckhbw {{.*#+}} xmm9 = xmm9[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; SSE2-NEXT: punpckhbw {{.*#+}} xmm9 = xmm9[8],xmm5[8],xmm9[9],xmm5[9],xmm9[10],xmm5[10],xmm9[11],xmm5[11],xmm9[12],xmm5[12],xmm9[13],xmm5[13],xmm9[14],xmm5[14],xmm9[15],xmm5[15]
; SSE2-NEXT: psraw $8, %xmm9
; SSE2-NEXT: movdqa %xmm1, %xmm4
; SSE2-NEXT: punpckhbw {{.*#+}} xmm4 = xmm4[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; SSE2-NEXT: punpckhbw {{.*#+}} xmm4 = xmm4[8],xmm1[8],xmm4[9],xmm1[9],xmm4[10],xmm1[10],xmm4[11],xmm1[11],xmm4[12],xmm1[12],xmm4[13],xmm1[13],xmm4[14],xmm1[14],xmm4[15],xmm1[15]
; SSE2-NEXT: psraw $8, %xmm4
; SSE2-NEXT: pmullw %xmm9, %xmm4
; SSE2-NEXT: pand %xmm8, %xmm4
Expand All @@ -970,10 +970,10 @@ define <64 x i8> @mul_v64i8(<64 x i8> %i, <64 x i8> %j) nounwind {
; SSE2-NEXT: pand %xmm8, %xmm1
; SSE2-NEXT: packuswb %xmm4, %xmm1
; SSE2-NEXT: movdqa %xmm6, %xmm4
; SSE2-NEXT: punpckhbw {{.*#+}} xmm4 = xmm4[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; SSE2-NEXT: punpckhbw {{.*#+}} xmm4 = xmm4[8],xmm6[8],xmm4[9],xmm6[9],xmm4[10],xmm6[10],xmm4[11],xmm6[11],xmm4[12],xmm6[12],xmm4[13],xmm6[13],xmm4[14],xmm6[14],xmm4[15],xmm6[15]
; SSE2-NEXT: psraw $8, %xmm4
; SSE2-NEXT: movdqa %xmm2, %xmm5
; SSE2-NEXT: punpckhbw {{.*#+}} xmm5 = xmm5[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; SSE2-NEXT: punpckhbw {{.*#+}} xmm5 = xmm5[8],xmm2[8],xmm5[9],xmm2[9],xmm5[10],xmm2[10],xmm5[11],xmm2[11],xmm5[12],xmm2[12],xmm5[13],xmm2[13],xmm5[14],xmm2[14],xmm5[15],xmm2[15]
; SSE2-NEXT: psraw $8, %xmm5
; SSE2-NEXT: pmullw %xmm4, %xmm5
; SSE2-NEXT: pand %xmm8, %xmm5
Expand All @@ -985,10 +985,10 @@ define <64 x i8> @mul_v64i8(<64 x i8> %i, <64 x i8> %j) nounwind {
; SSE2-NEXT: pand %xmm8, %xmm2
; SSE2-NEXT: packuswb %xmm5, %xmm2
; SSE2-NEXT: movdqa %xmm7, %xmm4
; SSE2-NEXT: punpckhbw {{.*#+}} xmm4 = xmm4[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; SSE2-NEXT: punpckhbw {{.*#+}} xmm4 = xmm4[8],xmm7[8],xmm4[9],xmm7[9],xmm4[10],xmm7[10],xmm4[11],xmm7[11],xmm4[12],xmm7[12],xmm4[13],xmm7[13],xmm4[14],xmm7[14],xmm4[15],xmm7[15]
; SSE2-NEXT: psraw $8, %xmm4
; SSE2-NEXT: movdqa %xmm3, %xmm5
; SSE2-NEXT: punpckhbw {{.*#+}} xmm5 = xmm5[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; SSE2-NEXT: punpckhbw {{.*#+}} xmm5 = xmm5[8],xmm3[8],xmm5[9],xmm3[9],xmm5[10],xmm3[10],xmm5[11],xmm3[11],xmm5[12],xmm3[12],xmm5[13],xmm3[13],xmm5[14],xmm3[14],xmm5[15],xmm3[15]
; SSE2-NEXT: psraw $8, %xmm5
; SSE2-NEXT: pmullw %xmm4, %xmm5
; SSE2-NEXT: pand %xmm8, %xmm5
Expand All @@ -1006,7 +1006,7 @@ define <64 x i8> @mul_v64i8(<64 x i8> %i, <64 x i8> %j) nounwind {
; SSE41-NEXT: movdqa %xmm1, %xmm8
; SSE41-NEXT: movdqa %xmm0, %xmm1
; SSE41-NEXT: pmovsxbw %xmm4, %xmm9
; SSE41-NEXT: pmovsxbw %xmm1, %xmm0
; SSE41-NEXT: pmovsxbw %xmm0, %xmm0
; SSE41-NEXT: pmullw %xmm9, %xmm0
; SSE41-NEXT: movdqa {{.*#+}} xmm9 = [255,255,255,255,255,255,255,255]
; SSE41-NEXT: pand %xmm9, %xmm0
Expand Down Expand Up @@ -1383,7 +1383,7 @@ define <8 x i64> @mul_v8i64_sext(<8 x i16> %val1, <8 x i32> %val2) {
; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm1, %xmm4
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: punpckhwd {{.*#+}} xmm9 = xmm9[4],xmm1[4],xmm9[5],xmm1[5],xmm9[6],xmm1[6],xmm9[7],xmm1[7]
; SSE2-NEXT: punpckhwd {{.*#+}} xmm9 = xmm9[4],xmm0[4],xmm9[5],xmm0[5],xmm9[6],xmm0[6],xmm9[7],xmm0[7]
; SSE2-NEXT: movdqa %xmm9, %xmm0
; SSE2-NEXT: psrad $31, %xmm0
; SSE2-NEXT: psrad $16, %xmm9
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/X86/powi.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@ define double @pow_wrapper(double %a) nounwind readonly ssp noredzone {
; CHECK-LABEL: pow_wrapper:
; CHECK: # %bb.0:
; CHECK-NEXT: movapd %xmm0, %xmm1
; CHECK-NEXT: mulsd %xmm1, %xmm1
; CHECK-NEXT: mulsd %xmm0, %xmm1
; CHECK-NEXT: mulsd %xmm1, %xmm0
; CHECK-NEXT: mulsd %xmm1, %xmm1
; CHECK-NEXT: mulsd %xmm1, %xmm0
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/X86/pr11334.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,7 @@ define <3 x double> @v3f2d_ext_vec(<3 x float> %v1) nounwind {
; SSE-NEXT: cvtps2pd %xmm0, %xmm0
; SSE-NEXT: movlps %xmm0, -{{[0-9]+}}(%rsp)
; SSE-NEXT: movaps %xmm2, %xmm1
; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]
; SSE-NEXT: fldl -{{[0-9]+}}(%rsp)
; SSE-NEXT: movaps %xmm2, %xmm0
; SSE-NEXT: retq
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/X86/pr29112.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -49,13 +49,13 @@ define <4 x float> @bar(<4 x float>* %a1p, <4 x float>* %a2p, <4 x float> %a3, <
; CHECK-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm12[0]
; CHECK-NEXT: vaddps %xmm3, %xmm2, %xmm2
; CHECK-NEXT: vmovaps %xmm15, %xmm1
; CHECK-NEXT: vmovaps %xmm1, {{[0-9]+}}(%rsp) # 16-byte Spill
; CHECK-NEXT: vaddps %xmm0, %xmm1, %xmm9
; CHECK-NEXT: vmovaps %xmm15, {{[0-9]+}}(%rsp) # 16-byte Spill
; CHECK-NEXT: vaddps %xmm0, %xmm15, %xmm9
; CHECK-NEXT: vaddps %xmm14, %xmm10, %xmm0
; CHECK-NEXT: vaddps %xmm1, %xmm1, %xmm8
; CHECK-NEXT: vaddps %xmm15, %xmm15, %xmm8
; CHECK-NEXT: vaddps %xmm11, %xmm3, %xmm3
; CHECK-NEXT: vaddps %xmm0, %xmm3, %xmm0
; CHECK-NEXT: vaddps %xmm0, %xmm1, %xmm0
; CHECK-NEXT: vaddps %xmm0, %xmm15, %xmm0
; CHECK-NEXT: vmovaps %xmm8, {{[0-9]+}}(%rsp)
; CHECK-NEXT: vmovaps %xmm9, (%rsp)
; CHECK-NEXT: vmovaps {{[0-9]+}}(%rsp), %xmm3 # 16-byte Reload
Expand Down
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